54FCT574LMQB [NSC]
Octal D-Type Flip-Flop with TRI-STATE Outputs; 八路D型触发器具有三态输出
| 型号： | 54FCT574LMQB |
| 厂家： | 
National Semiconductor |
| 描述： | Octal D-Type Flip-Flop with TRI-STATE Outputs |
| 文件： | 总7页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1999
54FCT574
Octal D-Type Flip-Flop with TRI-STATE® Outputs
General Description
The ’FCT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE). The
Features
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’FCT374
information presented to the
D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.
The device is functionally identical to the ’FCT374 except for
the pinouts.
n TRI-STATE outputs for bus-oriented applications
n Output sink capability of 32 mA, source capability of
12 mA
n TTL input and output level compatible
n CMOS power consumption
n Standard Microcircuit Drawing (SMD) 5962-8951301
Ordering Code
Military
54FCT574DMQB
54FCT574FMQB
54FCT574LMQB
Package Number
J20A
Package Description
20-Lead Ceramic Dual-In-Line
W20A
20-Lead Cerpack
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Descriptions
Pin Assignment for DIP and Flatpak
Pin
Names
D0–D7
CP
Description
Data Inputs
Clock Pulse Input
(Active Rising Edge)
TRI-STATE Output Enable
Input (Active LOW)
TRI-STATE Outputs
OE
O0–O7
DS100966-1
Pin Assignment
for LCC
DS100966-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100966
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Functional Description
Inputs
CP
Internal Outputs
Function
The ’FCT574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold times require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
OE
H
H
H
L
D
H
L
Q
NC
L
O
Z
H or L
N
Hold
Load
Load
Z
N
H
L
H
Z
N
L
L
Data Available
L
N
H
L
H
H
Data Available
L
H or L
H or L
NC
NC
NC
NC
No Change in Data
No Change in Data
L
H
=
=
=
=
=
H
L
X
Z
N
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW-to-HIGH Transition
Function Table
Inputs
Internal Outputs
Function
=
NC No Change
OE
CP
D
Q
O
H
H or L
L
NC
Z
Hold
Logic Diagram
DS100966-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
−500 mA
DC Latchup Source Current
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Storage Temperature
−65˚C to +150˚C
−55˚C to +125˚C
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
−55˚C to +175˚C
−0.5V to +7.0V
−55˚C to +125˚C
+4.5V to +5.5V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
Supply Voltage
−0.5V to +7.0V
Military
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Any Output in
the Disabled or Power-Off State
in the HIGH State
−0.5V to 5.5V
−0.5V to VCC
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
FCT574
Units
VCC
Conditions
Min
Max
VIH
Input HIGH Voltage
2.0
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
=
IIN −18 mA
VCD
VOH
Input Clamp Diode Voltage
−1.2
V
Min
Min
Min
Min
Min
Max
=
IOH −300 µA
Output HIGH
Voltage
54FCT
54FCT
54FCT
54FCT
4.3
2.4
V
=
IOH −12 mA
V
=
VOL
0.2
0.5
5
V
IOL 300 µA
Output LOW Voltage
Input HIGH Current
V
IOL = 32mA
=
VIN 2.7V (Note 3)
IIH
µA
=
VIN VCC
5
=
VIN 0.5V (Note 3)
IIL
Input LOW Current
−5
−5
10
−10
µA
Max
=
VIN 0.0V
= =
0 − 5.5V VOUT 2.7V; OE 2.0V
IOZH
IOZL
IOS
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Power Supply Current
µA
µA
=
=
0 − 5.5V VOUT 0.5V; OE 2.0V
=
−60
mA
mA
Max
Max
VOUT 0.0V
ICCQ
1.5
VIN = 0.2V or VIN = 5.3V, fI =
0MHz
∆ICC
Power Supply Current
2.0
6.0
mA
mA
Max
Max
VIN = 3.4V
=
ICCT
Additional
ICC/Input
VI VCC − 2.1V or VIN = GND, fCP
= 10MHz, Outputs open, OE =
GND, one bit toggling at fI = 5MHz,
50% duty cycle
=
VI 5.3V or VCC = 0.2V, fCP =
5.5
mA
Max
Max
10MHz, Outputs open, OE = GND,
one bit toggling at fI = 5MHz, 50%
duty cycle
ICCD
Dynamic ICC
No Load
0.40
mA/
Outputs Open, OE = GND, One bit
MHz
toggling, 50% duty cycle, VIN
5.3V or VIN = 0.2V
=
Note 3: Guaranteed, but not tested.
3
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AC Electrical Characteristics
54FCT
TA −55˚C to +125˚C
Fig.
No.
=
=
Symbol
Parameter
VCC 4.5V to 5.5V
Units
=
CL 50 pF
Min
2.0
2.0
1.5
1.5
1.5
1.5
Max
11.0
11.0
14.0
14.0
8.0
tPLH
Propagation Delay
ns
ns
ns
Figure 4
Figure 6
Figure 6
tPHL
tPZH
tPZL
tPHZ
tPLZ
CP to On
Output Enable Time
Output Disable Time
8.0
AC Operating Requirements
54FCT
=
TA −55˚C to +125˚C
Fig.
No.
=
Symbol
Parameter
VCC 4.5V to 5.5V
Units
=
CL 50 pF
Min
3.5
3.5
2.0
2.0
7.0
7.0
Max
ts(H)
Setup Time, HIGH
or LOW Dn to CP
Hold Time, HIGH
or LOW Dn to CP
Pulse Width, CP,
HIGH or LOW
ns
ns
ns
Figure 7
Figure 7
Figure 5
ts(L)
th(H)
th(L)
tw(H)
tw(L)
Capacitance
Symbol
Parameter
Typ
Units
Conditions
=
TA 25˚C
=
VCC 0V
CIN
COUT (Note 4)
Input Capacitance
Output Capacitance
5.0
9.0
pF
pF
=
VCC 5.0V
=
C is measured at frequency f 1 MHz, per MIL-STD-883B, Method 3012.
OUT
Note 4:
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4
AC Loading
DS100966-4
DS100966-6
*Includes jig and probe capacitance
=
FIGURE 2. VM 1.5V
FIGURE 1. Standard AC Test Load
Input Pulse Requirements
Amplitude Rep. Rate
3.0V 1 MHz
tw
tr
tf
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100966-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100966-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100966-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100966-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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