54FCT273DMQB [NSC]
Octal D-Type Flip-Flop; 八D型触发器
| 型号： | 54FCT273DMQB |
| 厂家： | 
National Semiconductor |
| 描述： | Octal D-Type Flip-Flop |
| 文件： | 总8页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54FCT273
Octal D-Type Flip-Flop
General Description
Features
n Eight edge-triggered D flip-flops
n Buffered common clock
The ’FCT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
n Buffered, asynchronous Master Reset
n See ’FCT377 for clock enable version
n See ’FCT373 for transparent latch version
n See ’FCT374 for TRI-STATE® version
n Output sink capability of 32 mA, source capability of
12 mA
n TTL input and output level compatible
n CMOS power consumption
n Standard Microcircuit Drawing (SMD) 5962-8765601
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The de-
vice is useful for applications where the true output only is re-
quired and the Clock and Master Reset are common to all
storage elements.
Ordering Code
Military
Package
Number
Package Description
54FCT273DMQB
54FCT273FMQB
54FCT273LMQB
J20A
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
W20A
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Assignment for DIP
and Flatpack
Pin Assignment
for LCC
DS100956-2
DS100956-1
Pin
Names
D0–D7
MR
Description
Data Inputs
Master Reset
(Active LOW)
CP
Clock Pulse Input
(Active Rising Edge)
Data Outputs
Q0–Q7
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100956
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=
=
H
h
HIGH Voltage Level steady state
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock tran-
Truth Table
sition
=
L
I
LOW Voltage Level steady state
Mode Select-Function Table
=
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock tran-
sition
=
Operating Mode
Inputs
Output
X
N
Immaterial
=
LOW-to-HIGH clock transition
MR
L
CP
X
Dn
X
h
Qn
L
Reset (Clear)
Load “1”
H
N
H
L
Load “0”
H
N
l
Logic Diagram
DS100956-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
−500 mA
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup
VCC + 4.5V
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
−65˚C to +150˚C
−55˚C to +125˚C
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
−55˚C to +175˚C
VCC Pin Potential to
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
−55˚C to +125˚C
+4.5V to +5.5V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Supply Voltage
−30 mA to +5.0 mA
Military
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Power-Off State
−0.5V to +4.75V
−0.5V to VCC
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
in the HIGH State
DC Electrical Characteristics
Symbol
Parameter
FCT240
Conditions
Units
VCC
Min Max
2.0
VIH
Input HIGH Voltage
V
V
Recognized HIGH Signal
Recognized LOW Signal
VIL
Input LOW Voltage
0.8
=
IIN −18 mA
VCD
VOH
Input Clamp Diode Voltage
−1.2
4.3
V
Min
Min
Min
Min
Min
Max
Max
Max
Max
Max
=
IOH −300 uA
Output HIGH
Voltage
54FCT
54FCT
54FCT
54FCT
V
=
IOH −12 mA
2.4
V
=
IOL 300 µA
VOL
Output LOW
Voltage
0.2
V
=
IOL 32 mA
0.5
V
=
VIN 5.5V
IIH
Input HIGH Current
5
µA
µA
mA
mA
mA
=
VIN 0.0V
IIL
Input LOW Current
−5
=
IOS
Output Short-Circuit Current
Power Supply Current
Power Supply Current
Total Power Supply Current
−60
1.5
VOUT 0.0V
ICCQ
∆ICC
ICCT
VIN = 0.2V or VIN = 5.3V
VIN = 3.4V
2.0
=
VIN 3.4V or VIN = GND, OE =
6.0
4.0
mA
mA
Max
GND, fI = 10Mhz, outputs open,
one bit toggling - 50% duty cycle
=
VIN 5.3V or VIN = 0.2V,OE =
Max
Max
GND, fI = 10Mhz, outputs open,
one bit toggling - 50% duty cycle
=
ICCD
Dynamic ICC
Outputs Open,OE GND, One Bit
0.25 mA/MHz
Toggling, 50% Duty Cycle
AC Electrical Characteristics
Symbol
Parameter
54FCT
Units
Fig. No.
=
TA −55˚C to +125˚C
=
VCC 4.5V to 5.5V
=
CL 50 pF
Min
2.0
2.0
2.0
Max
15.0
15.0
15.0
tPLH
tPHL
tPHL
Propagation Delay
CP to On
ns
ns
Figures 2, 5
Figures 2, 5
Propagation Delay
MR to On
3
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AC Operating Requirements
54FCT
TA −55˚C to +125˚C
=
=
Symbol
Parameter
VCC 4.5V to 5.5V
Units
Fig. No.
=
CL 50 pF
Min
3.5
3.5
2.5
2.5
7.0
7.0
7.0
Max
ts(H)
Setup Time, HIGH
or LOW Dn to CP
Hold Time, HIGH
or LOW Dn to CP
Pulse Width, CP,
HIGH or LOW
ns
ns
ns
ns
ns
Figure 6
Figure 6
Figure 2
Figure 2
Figure 6
ts(L)
th(H)
th(L)
tw(H)
tw(L)
tw(L)
Master Reset Pulse
Width, LOW
tREC
Recovery Time
MR to CP
5.0
Capacitance
Symbol
Parameter
Max
Units
Conditions
=
TA 25˚C
=
VCC 0V
CIN
OUT (Note 3)
Input Capacitance
Output Capacitance
10
12
pF
pF
=
VCC 5.0V
C
=
C is measured at frequency f 1 MHz, per MIL-STD-833B, Method 3012.
OUT
Note 3:
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4
AC Loading
DS100956-4
DS100956-6
*Includes jig and probe capacitance
=
FIGURE 3. VM 1.5V
FIGURE 1. Standard AC Test Load
Input Pulse Requirements
Amplitude Rep. Rate
3.0V 1 MHz
tw
tr
2.5 ns
tf
500 ns
2.5 ns
FIGURE 4. Test Input Signal Requirements
DS100956-5
FIGURE 2. Propagation Delay,
Pulse Width Waveforms
DS100956-8
FIGURE 5. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100956-9
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
5
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line (D)
NS Package Number J20A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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