54ACTQ543DMQBD [NSC]
Quiet Series Octal Registered Transceiver with TRI-STATE Outputs; 宁静系列八路寄存收发器具有三态输出
| 型号： | 54ACTQ543DMQBD |
| 厂家： | 
National Semiconductor |
| 描述： | Quiet Series Octal Registered Transceiver with TRI-STATE Outputs |
| 文件： | 总10页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54ACTQ543
Quiet Series Octal Registered Transceiver with
TRI-STATE® Outputs
General Description
Features
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
The ACTQ543 is a non-inverting octal transceiver containing
two sets of D-type registers for temporary storage of data
flowing in either direction. Separate Latch Enable and Out-
put Enable inputs are provided for each register to permit in-
dependent input and output control in either direction of data
flow.
n 8-bit octal latched transceiver
n Separate controls for data flow in each direction
n Back-to-back registers for storage
n Outputs source/sink 24 mA
The ACTQ utilizes NSC Quiet Series technology to guaran-
tee quiet output switching and improved dynamic threshold
n 4 kV minimum ESD immunity
™
™
performance. FACT Quiet Series features GTO output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Ordering Code
Military
Package
Number
J24A
Package Description
54ACTQ543DMQB
54ACTQ543FMQB
54ACTQ543LMQB
24-Lead Ceramic Dual-In-Line
24-Lead Cerpack
W24C
E28A
24-Lead Ceramic Leadless
Chip Carrier, Type C
Logic Symbols
IEEE/IEC
DS100233-1
DS100233-4
™
GTO is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
™
FACT Quiet Series is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100233
www.national.com
Connection Diagrams
Pin Names
OEAB
OEBA
CEAB
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or
Pin Assignment for
DIP and Flatpak
CEBA
LEAB
LEBA
A0–A7
B-to-A TRI-STATE Outputs
B0–B7
B-to-A Data Inputs or
A-to-B TRI-STATE Outputs
Functional Description
The ACTQ543 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from A0–A7 or take data
from B0–B7, as indicated in the Data I/O Control Table. With
CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subse-
quent LOW-to-HIGH transition of the LEAB signal puts the A
latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the TRI-STATE B output buffers are active and reflect the
data present at the output of the A latches. Control of data
flow from B to A is similar, but using the CEBA, LEBA and
OEBA inputs.
DS100233-2
Pin Assignment
for LCC
Data I/O Control Table
Inputs
Latch Status Output Buffers
DS100233-3
CEAB LEAB OEAB
H
X
L
X
H
L
X
X
X
H
L
Latched
Latched
Transparent
—
High Z
—
—
X
L
X
X
High Z
Driving
—
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using CEBA,
LEBA and OEBA
www.national.com
2
Logic Diagram
DS100233-8
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
DC Latch-up Source or
Sink Current
±
300 mA
175˚C
Junction Temperature (TJ)
CDIP
Supply Voltage (VCC
)
−0.5V to +7.0V
Recommended Operating
Conditions
Supply Voltage VCC
’ACTQ
DC Input Diode Current (IIK
)
=
VI −0.5V
−20 mA
+20 mA
=
VI VCC + 0.5V
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
4.5V to 5.5V
0V to VCC
0V to VCC
DC Output Diode Current (IOK
)
Input Voltage (VI)
=
VO −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
=
VO VCC + 0.5V
Operating Temperature (TA) (Note 2)
54ACTQ
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
Note 2: All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from −40˚C to +125˚C.
DC Characteristics for ’ACTQ Family Devices
54ACTQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 3)
=
VIN VIL or VIH
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
IOH = −24 mA
IOH = −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 3)
=
VIN VIL or VIH
4.5
5.5
5.5
0.50
0.50
V
IOL = 24 mA
IOL = 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum I/O
1.0
µA
µA
VI VCC, GND
±
IOZT
5.5
10
V(OE)
V
IL, VIH
=
=
Leakage Current
Maximum ICC/Input
VO VCC, GND
=
VI VCC − 2.1V
ICCT
IOLD
5.5
5.5
1.6
mA
mA
=
VOLD 1.65V Max
Minimum Dynamic
Output Current
(Note 4)
=
VOHD 3.85V Min
IOHD
ICC
5.5
5.5
−50
mA
µA
=
Maximum Quiescent
Supply Current
160.0
VIN VCC
or GND (Note 5)
www.national.com
4
DC Characteristics for ’ACTQ Family Devices (Continued)
54ACTQ
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
1.5
VOLP
Quiet Output
5.0
5.0
V
V
(Notes 6, 7)
Maximum Dynamic VOL
Quiet Output
VOLV
−1.2
(Notes 6, 7)
Minimum Dynamic VOL
Note 3: Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACTQ 25˚C is identical to 74ACTQ 25˚C.
Note 5:
I
CC
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). (n−1) Data Inputs are driven 0V to 3V, one output GND.
Note 8: Max number of Data Inputs (n) switching. (n–1) Inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (V ), 0V to threshold (V ),
@
ILD IHD
=
f
1 MHz.
AC Electrical Characteristics
54ACTQ
=
TA −55˚C
Fig.
No.
VCC
(V)
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 9)
Min
Max
tPLH
tPHL
Propagation Delay
Transparent Mode
5.0
5.0
5.0
5.0
2.0
9.5
ns
ns
ns
ns
Figure 4
Figure 4
An to Bn or Bn to An
Propagation Delay
tPLH
tPHL
LEBA, LEAB
2.0
1.5
1.5
11.0
13.0
9.0
to An, Bn
tPZH
tPZL
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
Figure 6
Figure 6
tPHZ
tPLZ
±
Note 9: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACTQ
=
TA −55˚C
Symbol
Parameter
to +125˚C
Units
Fig.
No.
VCC
(V)
=
CL 50 pF
(Note 10)
Guaranteed
Minimum
3.0
ts
Setup Time, HIGH or LOW
An or Bn to LEBA or LEAB
Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
Latch Enable
5.0
5.0
5.0
ns
ns
ns
Figure 7
Figure 7
Figure 5
th
1.5
4.0
tw
Pulse Width, LOW
±
Note 10: Voltage Range 5.0 is 5.0V 0.5V
5
www.national.com
Capacitance
Symbol
Parameter
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
Input Capacitance
Power Dissipation
Capacitance
=
VCC 5.0V
CPD
70.0
pF
AC Loading
AC Waveforms
DS100233-12
FIGURE 4. Propagation Delay Waveforms for Inverting
and Non-Inverting Functions
DS100233-10
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100233-13
DS100233-11
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 2. Test Input Signal Levels
Amplitude
Rep. Rate
tw
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100233-14
FIGURE 6. TRI-STATE Output High and Low Enable
and Disable Time
www.national.com
6
AC Waveforms (Continued)
DS100233-15
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
7
www.national.com
8
Physical Dimensions inches (millimeters) unless otherwise noted
28-Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
24-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J24F
9
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Ceramic Flatpak (F)
NS Package Number W24C
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
National Semiconductor
Europe
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
Email: sea.support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明