54ACT823 [NSC]
9-Bit D Flip-Flop; 9位D触发器
| 型号： | 54ACT823 |
| 厂家： | 
National Semiconductor |
| 描述： | 9-Bit D Flip-Flop |
| 文件： | 总8页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54ACT823
9-Bit D Flip-Flop
TRI-STATE outputs for bus interfacing
Inputs and outputs are on opposite sides
ACT823 has TTL-compatible inputs
General Description
The ACT823 is a 9-bit buffered register. It features Clock En-
able and Clear which are ideal for parity bus interfacing in
high performance microprogramming systems. The ACT823
offers noninverting outputs and is fully compatible with
AMD’s Am29823.
Standard Microcircuit Drawing (SMD) 5962-9161001
Features
Outputs source/sink 24 mA
Ordering Code
Order Number
54ACT823DMQB
54ACT823FMQB
54ACT823LMQB
Package Number
J24A
Package Description
24-Lead Ceramic Dual-in-line
W24C
24-Lead Cerpack
E28A
28-Lead Ceramic Leadless Chip Carrier, Type C
Logic Symbols
IEEE/IEC
DS100253-1
DS100253-2
Pin Names
Description
D0–D8
O0–O8
OE
Data Inputs
Data Outputs
Output Enable
Clear
CLR
CP
Clock Input
Clock Enable
EN
™
FACT is a trademark of Fairchild Semiconductor Corporation.
™
TRI-STATE is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100253
www.national.com
Connection Diagrams
Pin Assignment for DIP
and Cerpack
DS100253-3
Pin Assignment
for LCC
DS100253-4
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2
Functional Description
The ACT823 consists of nine D-type edge-triggered
flip-flops. These have TRI-STATE outputs for bus systems
organized with inputs and outputs on opposite sides. The
buffered clock (CP) and buffered Output Enable (OE) are
common to all flip-flops. The flip-flops will store the state of
their individual D inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH CP transition. With OE
LOW, the contents of the flip-flops are available at the out-
puts. When OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops. In addition to the Clock and Output En-
able pins, there are Clear (CLR) and Clock Enable (EN) pins.
These devices are ideal for parity bus interfacing in high per-
formance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the EN
is HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
Internal
Output
Function
OE
H
H
H
L
CLR
X
EN
L
CP
N
N
X
D
L
Q
L
O
Z
High Z
X
L
H
X
X
X
X
L
H
Z
High Z
Clear
Clear
Hold
L
X
X
H
H
L
L
Z
L
X
L
L
H
L
H
X
NC
NC
L
Z
H
X
NC
Z
Hold
H
H
L
H
N
N
N
N
Load
Load
Load
Load
H
L
H
L
H
Z
H
L
L
L
L
H
L
H
H
H
=
=
=
=
=
H
L
X
Z
N
HIGH Voltage Level
LOW Voltage Level
Immaterial
High Impedance
LOW-to-HIGH Transition
=
NC No Change
Logic Diagram
DS100253-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature (TJ)
CDIP
175˚C
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to 7.0V
DC Input Diode Current (IIK
)
Supply Voltage (VCC
)
=
VI −0.5V
−20 mA
+20 mA
ACT
4.5V to 5.5V
0V to VCC
0V to VCC
=
VI VCC + 0.5V
Input Voltage (VI)
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Output Voltage (VO
)
DC Output Diode Current (IOK
)
Operating Temperature (TA)
54ACT
=
VO −0.5V
−20 mA
+20 mA
−55˚C to +125˚C
=
VO VCC + 0.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
DC Output Voltage (VO
)
−0.5V to VCC + 0.5V
DC Output Source or Sink Current
(IO
VIN from 0.8V to 2.0V
±
±
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
)
50 mA
Storage Temperature (TSTG
)
−65˚C to +150˚C
™
mend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics
=
Symbol
Parameter
VCC
(V)
4.5
5.5
4.5
4.5
4.5
TA
Units
Conditions
−55˚C to +125˚C
=
VIH
Minimum High Level
Input Voltage
2.0
2.0
0.8
0.8
3.7
V
V
VOUT 0.1V
or VCC −0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC −0.1V
=
IOH −24 mA
VOH
VOL
IIN
Minimum High Level
Output Voltage
V
V
=
Maximum Low Level
Output Voltage
4.5
0.5
IOL 24 mA
Maximum Input
Leakage Current
=
±
5.5
5.5
1.0
µA
µA
VI VCC, GND
=
±
IOZ
Maximum TRI-STATE
Current
10.0
VI VIL, VIH
=
VO VCC, GND
=
VI VCC −2.1V
ICCT
IOLD
Maximum ICC/Input
5.5
5.5
1.6
50
mA
mA
=
VOLD 1.65V Max
(Note 3) Minimum
Dynamic Output
Current
=
VOHD 3.85V Min
IOHD
ICC
5.5
5.5
−50
160
mA
µA
=
Maximum Quiescent
Supply Current
VIN VCC
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics
=
Symbol
Parameter
VCC
(V)
TA −55˚C to +125˚C
Units
=
CL 50 pF
(Note 4)
Min
Max
fmax
Maximum Clock
Frequency
5.0
5.0
95
MHz
ns
tPLH
Propagation Delay
CP to On
1.0
12.0
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4
AC Electrical Characteristics (Continued)
=
Symbol
Parameter
VCC
(V)
TA −55˚C to +125˚C
Units
=
CL 50 pF
(Note 4)
Min
Max
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
Propagation Delay
CP to On
5.0
5.0
5.0
5.0
5.0
5.0
1.0
12.0
ns
ns
ns
ns
ns
ns
Propagation Delay
CLR to On
1.0
1.0
1.0
1.0
1.0
18.0
11.5
12.0
13.5
12.0
Output Enable Time
OE to On
Output Enable Time
OE to On
Output Disable Time
OE to On
Output Disable Time
OE to On
±
Note 4: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
=
Symbol
Parameter
VCC(V)
TA −55˚C to +125˚C
Units
=
(Note 5)
CL 50 pF
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
D to CP
5.0
5.0
5.0
5.0
5.0
4.0
ns
ns
ns
ns
ns
th
ts
th
tw
Hold Time, HIGH or LOW
Dn to CP
3.0
4.0
3.0
6.0
Setup Time, HIGH or LOW
EN to CP
Hold Time, HIGH or LOW
EN to CP
CP Pulse Width
HIGH or LOW
tw
CLR Pulse Width, LOW
CLR to CP
5.0
5.0
7.5
4.5
ns
ns
trec
Recovery Time
±
Note 5: Voltage Range 5.0 is 5.0V 0.5V
5
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Capacitance
Symbol
Parameter
Max
Units
Conditions
VCC OPEN
=
CIN
Input Capacitance
4.5
pF
CPD
Power Dissipation
Capacitance
=
VCC 5.0V
4.4
pF
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6
Physical Dimensions inches (millimeters) unless otherwise noted
24 Lead Ceramic Dual-in-line
Package Number J24A
24 Lead Cerpack
Package Number W24C
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
28 Lead Ceramic Leadless Chip Carrier
Package Number E28A
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2. A critical component in any component of a life support
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