54ACT323L [NSC]
8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins; 8位通用移位/存储寄存器与同步复位和通用I / O引脚
| 型号： | 54ACT323L |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins |
| 文件： | 总8页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1998
54ACT323
8-Bit Universal Shift/Storage Register with Synchronous
Reset and Common I/O Pins
n Common parallel I/O for reduced pin count
General Description
n Additional serial inputs and outputs for expansion
The ’ACT323 is an 8-bit universal shift/storage register with
n Four operating modes: shift left, shift right, load and
TRI-STATE® outputs. Parallel load inputs and flip-flop out-
store
puts are multiplexed to minimize pin count. Separate serial
inputs and outputs are provided for Q0 and Q7 to allow easy
cascading. Four operation modes are possible: hold (store),
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n TTL-compatible inputs
shift left, shift right and parallel load.
n Standard Military Drawing (SMD)
— ’ACT323: 5962-91607
Features
n ICC and IOZ reduced by 50%
Logic Symbols
DS100328-1
DS100328-5
Pin Name
CP
Description
Clock Pulse Input
DS0
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
DS7
S0, S1
SR
Synchronous Reset Input
TRI-STATE Output Enable Inputs
Multiplexed Parallel Data Inputs or
TRI-STATE Parallel Data Outputs
Serial Outputs
OE1, OE2
I/O0–I/O7
Q0, Q7
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100328
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Connection Diagrams
Functional Description
The ’ACT323 contains eight edge-triggered D-type flip-flops
and the interstage logic necessary to perform synchronous
reset, shift left, shift right, parallel load and hold operations.
The type of operation is determined by S0 and S1 as shown
in the Mode Select Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7 are
also brought out on other pins for expansion in serial shifting
of longer words.
Pin Assignment for
DIP and Flatpak
A LOW signal on SR overrides the Select inputs and allows
the flip-flops to be reset by the next rising edge of CP. All
other state changes are also initiated by the LOW-to-HIGH
CP transition. Inputs can change when the clock is in either
state provided only that the recommended setup and hold
times, relative to the rising edge of CP, are observed.
DS100328-2
A HIGH signal on either OE1 or OE2 disables the TRI-STATE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, load, hold and reset operations can
still occur. The TRI-STATE buffers are also disabled by HIGH
signals on both S0 and S1 in preparation for a parallel load
operation.
Pin Assignment
for LCC
Mode Select Table
Inputs
Response
SR S1 S0 CP
N
N
N
N
X
=
Synchronous Reset; Q0–Q7 LOW
L
X
H
L
X
H
H
L
→
Parallel Load; I/On Qn
H
H
H
H
→
→
Shift Right; DS0 Q0, Q0 Q1, etc.
→
→
DS100328-3
H
L
Shift Left; DS7 Q7, Q7 Q6, etc.
L
Hold
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
N =
LOW-to-HIGH Clock Transition
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2
Logic Diagram
DS100328-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature (TJ)
CDIP
175˚C
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
)
Supply Voltage (VCC
)
=
VI −0.5V
−20 mA
+20 mA
’ACT
4.5V to 5.5V
0V to VCC
0V to VCC
=
VI VCC + 0.5V
Input Voltage (VI)
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Output Voltage (VO
)
DC Output Diode Current (IOK
)
Operating Temperature (TA)
54ACT
=
VO −0.5V
−20 mA
+20 mA
−55˚C to +125˚C
=
VO VCC + 0.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
DC Output Voltage (VO
DC Output Source or
)
−0.5V to VCC + 0.5V
VIN from 0.8V to 2.0V
±
±
Sink Current (IO
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
DC VCC or Ground Current
Per Output Pin (ICC or IGND
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
)
50 mA
Storage Temperature (TSTG
)
−65˚C to +150˚C
™
mend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 2)
=
VIN VIL or VIH
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
IOH = −24 mA
IOH = −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 2)
=
VIN VIL or VIH
4.5
5.5
5.5
0.50
0.50
V
IOL = −24 mA
IOL = −24 mA
=
±
IIN
Maximum Input
1.0
µA
µA
VI VCC, GND
Leakage Current
Maximum I/O
=
±
IOZT
5.5
5.5
VI/O VCC or GND
=
VIN VIH, VIL
Leakage Current
Maximum ICC/Input
Minimum Dynamic Output
Current (Note 3)
Maximum Quiescent
Supply Current
=
VI VCC − 2.1V
ICCT
IOLD
IOHD
ICC
5.5
5.5
5.5
5.5
1.6
mA
mA
mA
µA
=
VOLD 1.65V Max
50
=
VOHD 3.85V Min
−50
80.0
=
VIN VCC or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
I for 54ACT is identical to 74ACT 25˚C.
CC
Note 4:
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4
AC Electrical Characteristics
54ACT
=
VCC
(V)
TA −55˚C
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 5)
Min
70
Max
16.5
17.0
16.5
18.0
fmax
tPLH
Maximum Input Frequency
Propagation Delay
CP to Q0 or Q7
5.0
5.0
MHz
ns
1.0
tPHL
tPLH
tPHL
Propagation Delay
CP to Q0 or Q7
5.0
5.0
5.0
1.0
1.0
1.0
ns
ns
ns
Propagation Delay
CP to I/On
Propagation Delay
CP to I/On
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
Output Enable Time
Output Disable Time
Output Disable Time
5.0
5.0
5.0
5.0
1.0
1.0
1.0
1.0
15.5
15.5
15.5
15.0
ns
ns
ns
ns
±
Note 5: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACT
=
TA −55˚C
Symbol
Parameter
VCC
(V)
to +125˚C
Units
=
CL 50 pF
=
(Note 6)
VCC +5.0V
Guaranteed Minimum
ts
th
ts
th
ts
th
tw
Setup Time, HIGH or LOW
S0 or S1 to CP
5.0
5.0
5.0
5.0
5.0
5.0
5.0
6.0
ns
ns
ns
ns
ns
ns
ns
Hold Time, HIGH or LOW
S0 or S1 to CP
2.0
4.5
2.0
3.0
1.5
5.0
Setup Time, HIGH or LOW
I/On, DS0, DS7 to CP
Hold Time, HIGH or LOW
I/On, DS0, DS7 to CP
Setup Time, HIGH or LOW
SR to CP
Hold Time, HIGH or LOW
SR to CP
CP Pulse Width
HIGH or LOW
±
Note 6: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
CIN
CPD
Parameter
Typ
Units
pF
Conditions
=
VCC OPEN
Input Capacitance
4.5
=
VCC 5.0V
Power Dissipation Capacitance
170
pF
5
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6
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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