54ACT161 [NSC]
Synchronous Presettable Binary Counter; 同步可预置二进制计数器
| 型号： | 54ACT161 |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous Presettable Binary Counter |
| 文件： | 总12页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1998
54AC161 • 54ACT161
Synchronous Presettable Binary Counter
n Synchronous counting and loading
General Description
n High-speed synchronous expansion
n Typical count rate of 125 MHz
n Outputs source/sink 24 mA
n ’ACT161 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC161: 5962-89561
The ’AC/’ACT161 are high-speed synchronous modulo-16
binary counters. They are synchronously presettable for ap-
plication in programmable dividers and have two types of
Count Enable inputs plus a Terminal Count output for versa-
tility in forming synchronous multistage counters. The ’AC/
’ACT161 has an asynchronous Master Reset input that over-
rides all other inputs and forces the outputs LOW.
— ’ACT161: 5962-91722
Features
n ICC reduced by 50%
Logic Symbols
Pin Names
CEP
Description
Count Enable Parallel Input
CET
CP
Count Enable Trickle Input
Clock Pulse Input
MR
Asynchronous Master Reset Input
Parallel Data Inputs
P0–P3
PE
Parallel Enable Inputs
Flip-Flop Outputs
Q0–Q3
TC
Terminal Count Output
DS100274-1
IEEE/IEC
DS100274-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
™
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100274
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The Terminal Count (TC) output is HIGH when CET is HIGH
and counter is in state 15. To implement synchronous multi-
stage counters, the TC outputs can be used with the CEP
and CET inputs in two different ways.
Connection Diagrams
Pin Assignment
for DIP and Flatpak
Figure 1 shows the connections for simple ripple carry, in
which the clock period must be longer than the CP to TC de-
lay of the first stage, plus the cumulative CET to TC delays of
the intermediate stages, plus the CET to CP setup time of
the last stage. This total delay plus setup time sets the upper
limit on clock frequency. For faster clock rates, the carry loo-
kahead connections shown in Figure 2 are recommended. In
this scheme the ripple delay through the intermediate stages
commences with the same clock that causes the first stage
to tick over from max to min in the Up mode, or min to max
in the Down mode, to start its final cycle. Since this final
cycle requires 16 clocks to complete, there is plenty of time
for the ripple to progress through the intermediate stages.
The critical timing that limits the clock period is the CP to TC
delay of the first stage plus the CEP to CP setup time of the
last stage. The TC output is subject to decoding spikes due
to internal race conditions and is therefore not recom-
DS100274-3
Pin Assignment
for LCC
mended for use as
a clock or asynchronous reset for
flip-flops, registers or counters.
=
Logic Equations: Count Enable CEP • CET • PE
=
TC Q0 • Q1 • Q2 • Q3 • CET
Mode Select Table
PE
CET
CEP
Action on the Rising
N
Clock Edge (
Reset (Clear)
)
X
L
X
X
H
L
X
X
H
X
L
→
Load (Pn Qn)
DS100274-4
H
H
H
Count (Increment)
No Change (Hold)
No Change (Hold)
Functional Description
X
The ’AC/’ACT161 count in modulo-16 binary sequence.
From state 15 (HHHH) they increment to state 0 (LLLL). The
clock inputs of all flip-flops are driven in parallel through a
clock buffer. Thus all changes of the Q outputs (except due
to Master Reset of the ’161) occur as a result of, and syn-
chronous with, the LOW-to-HIGH transition of the CP input
signal. The circuits have four fundamental modes of opera-
tion, in order of precedence: asynchronous reset, parallel
load, count-up and hold. Five control inputs — Master Reset,
Parallel Enable (PE), Count Enable Parallel (CEP) and
Count Enable Trickle (CET) — determine the mode of opera-
tion, as shown in the Mode Select Table. A LOW signal on
MR overrides all other inputs and asynchronously forces all
outputs LOW. A LOW signal on PE overrides counting and
allows information on the Parallel Data (Pn) inputs to be
loaded into the flip-flops on the next rising edge of CP. With
PE and MR HIGH, CEP and CET permit counting when both
are HIGH. Conversely, a LOW signal on either CEP or CET
inhibits counting.
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
State Diagram
The ’AC/’ACT161 use D-type edge-triggered flip-flops and
changing the PE, CEP and CET inputs when the CP is in ei-
ther state does not cause errors, provided that the recom-
mended setup and hold times, with respect to the rising edge
of CP, are observed.
DS100274-5
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2
State Diagram (Continued)
DS100274-8
FIGURE 1. Multistage Counter with Ripple Carry
DS100274-9
FIGURE 2. Multistage Counter with Lookahead Carry
3
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Block Diagram
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4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
Output Voltage (VO
)
0V to VCC
=
VI VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
−55˚C to +125˚C
125 mV/ns
DC Output Diode Current (IOK
)
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO −0.5V
−20 mA
+20 mA
=
VO VCC + 0.5V
% to 70% of V
VIN from 30
CC
DC Output Voltage (VO
DC Output Source
)
−0.5V to VCC + 0.5V
@
VCC 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
±
±
or Sink Current (IO
)
50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
VIN from 0.8V to 2.0V
)
50 mA
@
VCC 4.5V, 5.5V
125 mV/ns
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
175˚C
™
mend operation of FACT circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 2)
=
VIN VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
IOH = −12 mA
IOH = −24 mA
IOH = −24 mA
V
V
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 2)
=
VIN VIL or VIH
3.0
4.5
5.5
5.5
0.5
0.5
0.5
IOL = 12 mA
IOL = 24 mA
IOL = 24 mA
V
=
±
IIN
Maximum Input
Leakage Current
1.0
µA
VI VCC, GND
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 3)
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
160
=
VIN VCC
Maximum Quiescent
5
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DC Characteristics for ’AC Family Devices (Continued)
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
Note 4:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54AC 25˚C is identical to 74AC 25˚C.
CC
DC Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High Level
Input Voltage (Note 7)
Maximum Low Level
Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
3.0
3.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
(Note 5)
=
VIN VIL or 3.0V
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
IOH = −24 mA
IOH = −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 5)
=
VIN VIL or VIH
4.5
5.5
5.5
0.50
0.50
V
IOL = 24 mA
IOL = 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum
1.0
µA
mA
VI VCC, GND
=
VI VCC − 2.1V
ICCT
5.5
1.6
I
CC/Input
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
160
=
Maximum Quiescent
Supply Current
VIN VCC
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: For dynamic operation, a V level between 2.0 and 3.0V may be recognized by this device as a high logic level input. For static operation, a V ≥ 2.0V will
IH
IH
be recognized by this device as a high logic level input. Users are cautioned to verify that this will not affect their system.
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6
AC Electrical Characteristics
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 8)
Min
Max
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
Maximum Count
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
55
80
MHz
ns
Frequency
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay
CP to TC
1.0
1.0
1.0
1.0
3.0
3.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
14.0
10.0
14.0
10.0
18.0
13.0
17.5
13.0
13.0
8.5
ns
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
13.5
10.5
14.5
10.5
18.5
14.0
ns
Propagation Delay
MR to Qn
ns
Propagation Delay
MR to TC
ns
±
Note 8: Voltage Range 3.3 is 3.3V 0.3V
±
Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54AC
=
VCC
TA −55˚C
Fig.
No.
Symbol
Parameter
(V)
to +125˚C
Units
=
CL 50 pF
(Note 9)
Guaranteed Minimum
ts
Setup Time, HIGH or LOW
Pn to CP
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
16.0
10.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
th
ts
Hold Time, HIGH or LOW
Pn to CP
1.5
Setup Time, HIGH or LOW
PE to CP
15.0
10.5
−1.0
0.0
th
ts
Hold Time, HIGH or LOW
PE to CP
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Clock Pulse Width
(Load) HIGH or LOW
Clock Pulse Width
(Count) HIGH or LOW
MR Pulse Width,
7.5
5.5
th
tw
tw
tw
2.0
2.0
5.0
5.0
5.0
5.0
5.0
LOW
5.0
7
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AC Operating Requirements (Continued)
54AC
=
VCC
TA −55˚C
Fig.
No.
Symbol
Parameter
(V)
to +125˚C
Units
=
(Note 9)
CL 50 pF
Guaranteed Minimum
trec
Recovery Time
MR to CP
1.5
2.0
ns
±
Note 9: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
54ACT
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note 10)
CL 50 pF
Min
Max
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
Maximum Count
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
85
MHz
ns
Frequency
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay CP to Qn
(PE Input HIGH or LOW)
Propagation Delay
CP to TC
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
10.5
10.5
14.0
12.5
9.5
ns
ns
Propagation Delay
CP to TC
ns
Propagation Delay
CET to TC
ns
Propagation Delay
CET to TC
9.5
ns
Propagation Delay
MR to Qn
10.0
11.5
ns
Propagation Delay
MR to TC
ns
±
Note 10: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACT
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note
11)
Guaranteed Minimum
ts
th
ts
Setup Time, HIGH or LOW
Pn to CP
5.0
5.0
5.0
13.0
ns
ns
ns
Hold Time, HIGH or LOW
Pn to CP
0
Setup Time, HIGH or LOW
PE to CP
11.0
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8
AC Operating Requirements (Continued)
54ACT
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note
11)
CL 50 pF
Guaranteed Minimum
th
ts
Hold Time, HIGH or LOW
PE to CP
5.0
5.0
5.0
5.0
5.0
0
ns
ns
ns
ns
ns
Setup Time, HIGH or LOW
CEP or CET to CP
Hold Time, HIGH or LOW
CEP or CET to CP
Clock Pulse Width,
(Load) HIGH or LOW
Clock Pulse Width,
(Count) HIGH or LOW
MR Pulse Width, LOW
Recovery Time
7.0
0.5
5.0
5.0
th
tw
tw
tw
5.0
5.0
6.5
0.5
ns
ns
trec
MR to CP
±
Note 11: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
CIN
CPD
Parameter
Typ
4.5
Units
Conditions
=
VCC OPEN
Input Capacitance
pF
pF
=
VCC 5.0V
Power Dissipation Capacitance
45.0
9
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10
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
11
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Tel: 1-800-272-9959
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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