54ACT112_09 [NSC]
Dual JK Negative Edge-Triggered Flip-Flop; 双JK负边沿触发触发器
| 型号： | 54ACT112_09 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual JK Negative Edge-Triggered Flip-Flop |
| 文件： | 总8页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OBSOLETE
July 20, 2009
54ACT112
Dual JK Negative Edge-Triggered Flip-Flop
LOW input to SD sets Q to HIGH level
General Description
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
The 'ACT112 contains two independent, high-speed JK flip-
flops with Direct Set and Clear inputs. Synchronous state
changes are initiated by the falling edge of the clock. Trigger-
ing occurs at a voltage level of the clock and is not directly
related to the transition time. The J and K inputs can change
when the clock is in either state without affecting the flip-flop,
provided that they are in the desired state during the recom-
mended setup and hold times relative to the falling edge of
the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW signals
on SD and CD force both Q and Q HIGH.
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Features
'ACT112 has TTL-compatible inputs
■
■
■
Outputs source/si24 mA
Standard Microcuit awing (SMD) 5962-8995001
Asynchronous Inputs:
Connection Diagrams
Pin Dptions
PNames
Description
Pin Assigment for
DIP and Flatpack
J, K1, 2
Data Inputs
CP1
Clock Pulse Inputs
(Active Falling Edge)
CD1, CD2
Direct Clear Inputs (Active LOW)
1, S
Direct Set Inputs (Active LOW)
Outputs
Q1Q1, Q2
100976
Pin Assigment
for LCC
10097605
FACT™ is a trademark of Fairchild Semiconductor
© 2009 National Semiconductor Corporation
100976
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100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36
Logic Symbols
IEEE/IEC
10097601
10097604
10097602
Truth Table
Inp
CP
Outputs
SD
D
J
K
Q
Q
L
H
L
X
X
X
h
l
X
X
X
h
h
l
H
L
L
H
L
X
H
H
H
H
M
M
M
M
Q0
L
Q0
H
h
l
H
L
l
Q0
Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage Level
X = Immaterial
M = HIGH-to-LOW Clock Transition
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
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Logic Diagram
(One Half Shown)
10097606
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
0V to VCC
Input Voltage (VI)
Supply Voltage (VCC
)
−0.5V to +7.0V
Output Voltage (VO)
DC Input Diode Current (IIK)
VI = −0.5V
Operating Temperature (TA)
−55°C to +125°C
125 mV/ns
−20 mA
+20 mA
−0.5V to VCC + 0.5V
Minimum Input Edge Rate (ΔV/Δt)
VIN from 0.8V to 2.0V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK
VO = −0.5V
VCC @ 4.5V, 5.5V
)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT™ circuits outside databook specifications.
−20 mA
+20 mA
−0.5V to VCC +0.5V
VO = VCC + O.5
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
±50 mA
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65°C to +150°C
175°C
DC Characteristics for 'ACT Family Devic
Symbol
Parameter
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.
TA = −55°C to +
Units
Conditions
aranteed Limits
VIH
VIL
Minimum High Level
Input Voltage
2.0
0.8
0.8
4.4
5.4
VOUT = 0.1V
V
V
V
or VCC − 0.1V
VOUT = 0.1V
or VCC − 0.1V
Maximum Low Level
Input Voltage
VOH
Minimum High Level
Output Voltage
IOUT = −50 μA
VIN = VIL or VIH
IOH = −24 mA
IOH = −24 mA
(Note 2)
5.5
3.70
4.70
V
V
V
VOL
Maximum Low Level
Output Voltage
0.1
0.1
IOUT = 50 μA
VIN = VIL or VIH
IOL = 24 MA
4.5
5.5
0.5
0.5
IOL = 24 mA
(Note 2)
IIN
Maximum Input Leakagnt
Maximum ICC/Input
VI = VCC, GND
VI = VCC − 2.1V
VOLD = 1.65V Max
VOHD = 3.85V Min
VIN = VCC or GND
5.5
5.5
5.5
5.5
± 1.0
1.6
μA
mA
mA
mA
ICCT
IOLD
IOHD
ICC
Minimum Dynamic
50
Output Current(Note 3)
−50
Maximum Quiescent Supply
Current
5.5
80.0
μA
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
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100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36
AC Electrical Characteristics for 'ACT Family Devices
Symbol
Parameter
VCC
TA = −55°C to +125°C
Units
Fig. No.
(V)
CL = 50 pF
(Note 4)
5.0
Min
Max
fmax
tPLH
tPHL
tPLH
tPHL
Maximum Clock
80
1.0
1.0
1.0
1.0
MHz
ns
Frequency
Propagation Delay
CPn to Qn or Qn
5.0
5.0
5.0
5.0
14.0
14.0
13.5
13.5
Propagation Delay
CPn to Qn or Qn
ns
Propagation Delay
CDn or SDn to Qn or Qn
Propagation Delay
CDn or SDn to Qn or Qn
ns
ns
Note 4: Voltage Range 5.0 is 5.0V ±0.5V
AC Operating Requirements:
Symbol
Parameter
VCC
(V)
TA = to +125°C
CL = 5
Units
Fig. No.
(Note 5)
5.0
aranteed Minum
8.0
tS
Setup Time, HIGH or LOW
Jn or Kn to CPn
ns
ns
ns
ns
tH
Hold Time, HIGH or LOW
Jn or Kn to CPn
5.0
5.0
5.
.5
5.0
3.0
tW
Pulse Width
CPn or CDn or SDn
Recovery Time
trec
CDn or SDn to CPn
Note 5: Voltage Range 5.0 is 5.0V ±0.5V
Capacitance
Symbol
Parameter
Max
10.0
60
Units
Conditions
CIN
Input Capacitance
Power Dissipati
pF
pF
VCC = OPEN
VCC = 5.0V
CPD
5
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100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Ceramic Dne
Package Number J
16-Lead Cerpack
Package Number W16A
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20-Lead Ceramic Leas p Carrier
PackaNumb0A
7
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