30130-23_技术文档

April 2000

Geode™ GXm Processor

Integrated x86 Solution with MMX Support

General Description

The National Semiconductor^®Geode™ GXm processor

is an advanced 32-bit x86 compatible processor offering

high performance, fully accelerated 2D graphics, a 64-bit

synchronous DRAM controller and a PCI bus controller,

all on a single chip that is compatible with Intel’s MMX

technology.

graphics accelerator provides pixel processing and ren-

dering functions.

A separate on-chip video buffer enables >30 fps MPEG1

video playback when used together with the CS5530 I/O

companion chip. Graphics and system memory accesses

are supported by a tightly-coupled synchronous DRAM

(SDRAM) memory controller. This tightly coupled memory

subsystem eliminates the need for an external L2 cache.

The GXm processor core is a proven design that offers

competitive CPU performance. It has integer and floating

point execution units that are based on sixth-generation

technology. The integer core contains a single, six-stage

execution pipeline and offers advanced features such as

operand forwarding, branch target buffers, and extensive

write buffering. A 16 KB write-back L1 cache is accessed

in a unique fashion that eliminates pipeline stalls to fetch

operands that hit in the cache.

The GXm processor includes Virtual System Architec-

ture^®(VSA™ technology) enabling XpressGRAPHICS

and XpressAUDIO subsystems as well as generic emula-

tion capabilities. Software handler routines for the Xpress-

GRAPHICS and XpressAUDIO subsystems can be

included in the BIOS and provide compatible VGA and 16-

bit industry standard audio emulation. XpressAUDIO tech-

nology eliminates much of the hardware traditionally asso-

ciated with audio functions.

In addition to the advanced CPU features, the GXm pro-

cessor integrates a host of functions which are typically

implemented with external components. A full-function

Geode™ GXm Processor Internal Block Diagram

Write-Back

Cache Unit

Integer

Unit

FPU

MMU

C-Bus

Internal Bus Interface Unit

X-Bus

Graphics

Pipeline

Memory

Controller

Display

Controller

PCI

Controller

Integrated

Functions

PCI Bus

SDRAM Port

CS5530

(CRT/LCD TFT)

National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.

Geode and VSA are trademarks of National Semiconductor Corporation.

For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.

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Features

General Features

2D Graphics Accelerator

Packaged in:

— 352-Terminal Ball Grid Array (BGA) or

— 320-Pin Staggered Pin Grid Array (SPGA)

Graphics pipeline performance significantly increased

over previous generations by pipelining burst

reads/writes

0.35-micron four layer metal CMOS process

Split rail design (3.3V I/O and 2.9V core)

Accelerates BitBLTs, line draw, text

Supports all 256 raster operations

Supports transparent BLTs

32-Bit x86 Processor

Runs at core clock frequency

Full VGA and VESA mode support

Supports the MMX instruction set extension for the

acceleration of multimedia applications

Speeds offered up to 266 MHz

16 KB unified L1 cache

Special "Driver level” instructions utilize internal

scratchpad for enhanced performance

Integrated Floating Point Unit (FPU)

Display Controller

Re-entrant System Management Mode (SMM)

enhanced for VSA

Video Generator (VG) improves memory efficiency for

display refresh with SDRAM

Supports a separate MPEG1 video buffer and data

path to enable video acceleration in the CS5530

PCI Controller

Fixed, rotating, hybrid, or ping-pong arbitration

Internal palette RAM for use with the CS5530

Supports up to three PCI bus masters

Direct interface to CS5530 for CRT and TFT flat panel

support which eliminates need for external RAMDAC

Synchronous CPU and PCI bus clock frequency

Hardware frame buffer compressor/decompressor

Hardware cursor

Supports concurrency between PCI master and L1

cache

Supports up to 1280x1024x8 bpp and 1024x768x16

bpp

Power Management

Designed to support CS5530 power management

architecture

XpressRAM Subsystem

CPU only Suspend or full 3V Suspend supported:

— Clocks to CPU core stopped for CPU Suspend

— All on-chip clocks stopped for 3V Suspend

— Suspend refresh supported for 3V Suspend

Memory control/interface directly from CPU

64-Bit wide memory bus

Support for:

— Two 168-pin unbuffered DIMMs

— Up to 16 open banks simultaneously

— Single or 16-byte reads (burst length of two)

Virtual Systems Architecture Technology

Architecture allows OS independent (software) virtual-

ization of hardware functions

Provides compatible high performance legacy VGA

core functionality

Note: GUI (Graphical User Interface) graphics accel-

eration is pure hardware.

Provides 16-bit XpressAUDIO subsystem

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Revision 3.1

Table of Contents

1.0 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.1

1.2

1.3

1.4

INTEGER UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

FLOATING POINT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WRITE-BACK CACHE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

MEMORY MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.4.1

Internal Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5

INTEGRATED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.5.1

1.5.2

1.5.3

1.5.4

Graphics Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

XpressRAM Memory Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.6

GEODE GXM/CS5530 SYSTEM DESIGNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.0 Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1

2.2

PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memory Controller Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Video Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Power, Ground, and No Connect Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Internal Test and Measurement Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.3

2.4

SUBSYSTEM SIGNAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

POWER PLANES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.0 Processor Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.1

3.2

CORE PROCESSOR INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

INSTRUCTION SET OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.2.1

Lock Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3

3.4

REGISTER SETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.3.1

3.3.2

3.3.3

3.3.4

Application Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

System Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Model Specific Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

ADDRESS SPACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.4.1

3.4.2

I/O Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.5

3.6

3.7

OFFSET, SEGMENT, AND PAGING MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

OFFSET MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

DESCRIPTORS AND SEGMENT MECHANISMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.7.1

3.7.2

3.7.3

3.7.4

3.7.5

Real and Virtual 8086 Mode Segment Mechanisms . . . . . . . . . . . . . . . . . . . . . . . 62

Segment Mechanism in Protective Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

GDTR and LDTR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Descriptor Bit Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Gate Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.8

3.9

MULTITASKING AND TASK STATE SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

PAGING MECHANISM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Revision 3.1

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Table of Contents (Continued)

3.10 INTERRUPTS AND EXCEPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.10.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.10.2 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.10.3 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.10.4 Interrupt and Exception Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.10.5 Exceptions in Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.10.6 Error Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.11 SYSTEM MANAGEMENT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.11.1 SMM Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.11.2 SMM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.11.3 The SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11.4 SMM Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11.5 SMM Memory Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.11.6 SMM Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.11.7 SMM Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.11.8 SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.11.9 SMI Service Routine Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.12 SHUTDOWN AND HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13 PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13.1 Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13.2 I/O Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.13.3 Privilege Level Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.13.4 Initialization and Transition to Protected Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.14 VIRTUAL 8086 MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.14.1 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.14.2 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.14.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.14.4 Entering and Leaving Virtual 8086 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

3.15 FLOATING POINT UNIT OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.15.1 FPU (Floating Point Unit) Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.15.2 FPU Tag Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.15.3 FPU Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.15.4 FPU Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

4.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.1

INTEGRATED FUNCTIONS PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . 92

4.1.1

4.1.2

4.1.3

4.1.4

4.1.5

4.1.6

Graphics Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Graphics Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

L1 Cache Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Display Driver Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

CPU_READ/CPU_WRITE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

4.2

INTERNAL BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.2.1

4.2.2

4.2.3

4.2.4

4.2.5

FPU Error Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

A20M Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

SMI Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

640 KB to 1 MB Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Internal Bus Interface Unit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

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Table of Contents (Continued)

4.3

MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

Memory Array Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Memory Organizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

SDRAM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Memory Controller Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Memory Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

SDRAM Interface Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

4.4

4.5

GRAPHICS PIPELINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

4.4.1

4.4.2

4.4.3

4.4.4

4.4.5

4.4.6

BitBLT/Vector Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Master/Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Source Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Raster Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Graphics Pipeline Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

DISPLAY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.5.1

4.5.2

4.5.3

4.5.4

4.5.5

4.5.6

4.5.7

4.5.8

4.5.9

Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Compression Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Motion Video Acceleration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Hardware Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Display Timing Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Dither and Frame-Rate Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Graphics Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Display Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

4.5.10 Memory Organization Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

4.5.11 Timing Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

4.5.12 Cursor Position Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

4.5.13 Color Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

4.5.14 Palette Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

4.5.15 CS5530 Display Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

PCI CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

4.6

4.6.1

4.6.2

4.6.3

4.6.4

4.6.5

4.6.6

4.6.7

4.6.8

X-Bus PCI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

X-Bus PCI Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

PCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Generating Configuration Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

Generating Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

PCI Configuration Space Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

PCI Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

PCI Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

5.0 Virtual Subsystem Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.1

VIRTUAL VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

5.1.1 Traditional VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

GXM VIRTUAL VGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

Datapath Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

Video Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

GXm VGA Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

VGA Video BIOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

Virtual VGA Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

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Table of Contents (Continued)

6.0 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

6.1

6.2

6.3

6.4

6.5

APM SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

CPU SUSPEND COMMAND REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

SUSPEND MODULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

3-VOLT SUSPEND MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

SUSPEND MODE AND BUS CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.5.1

6.5.2

6.5.3

6.5.4

Initiating Suspend with SUSP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Initiating Suspend with HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

Responding to a PCI Access During Suspend Mode . . . . . . . . . . . . . . . . . . . . . . 177

Stopping the Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.6

6.7

GXM PROCESSOR SERIAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

6.6.1 Serial Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

POWER MANAGEMENT REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

7.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.1

7.2

PART NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

Power/Ground Connections and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Power Sequencing the Core and I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

NC-Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

7.3

7.4

7.5

7.6

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

8.0 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

8.1

THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

8.1.1 Heatsink Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

MECHANICAL PACKAGE OUTLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

8.2

9.0 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

9.1

GENERAL INSTRUCTION SET FORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

Prefix (Optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

Opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

mod and r/m Byte (Memory Addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

reg Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

s-i-b Byte (Scale, Indexing, Base) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

9.2

CPUID INSTRUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

9.2.1

9.2.2

Standard CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

Extended CPUID Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

9.3

9.4

9.5

9.6

PROCESSOR CORE INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

FPU INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

MMX INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

NATIONAL SEMICONDUCTOR EXTENDED MMX INSTRUCTION SET . . . . . . . . . . . . . 234

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Table of Contents (Continued)

Appendix A Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

A.1

A.2

ORDER INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

DATA BOOK REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

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1.0 Architecture Overview

The National Semiconductor Geode GXm processor is

an x86-compatible 32-bit microprocessor. The decoupled

load/store unit (within the memory management unit)

allows multiple instructions in a single clock cycle. Other

features include single-cycle execution, single-cycle

instruction decode, 16 KB write-back cache, and clock

rates up to 266 MHz. These features are made possible

by the use of advanced-process technologies and super-

pipelining.

The instruction fetch pipeline stage generates, from the

on-chip cache, continuous high-speed instruction

stream for use by the processor. Up to 128 bits of code

are read during a single clock cycle.

a

Branch prediction logic within the prefetch unit generates

a predicted target address for unconditional or conditional

branch instructions. When

a branch instruction is

detected, the instruction fetch stage starts loading instruc-

tions at the predicted address within a single clock cycle.

Up to 48 bytes of code are queued prior to the instruction

decode stage.

The GXm processor has low power consumption at all

clock frequencies. Where additional power savings are

required, designers can make use of Suspend mode, Stop

Clock capability, and System Management Mode (SMM).

The instruction decode stage evaluates the code stream

provided by the instruction fetch stage and determines the

number of bytes in each instruction and the instruction

type. Instructions are processed and decoded at a maxi-

mum rate of one instruction per clock.

The GXm processor is divided into major functional blocks

(as shown in Figure 1-1):

•

Integer Unit

Floating Point Unit (FPU)

Write-Back Cache Unit

Memory Management Unit (MMU)

Internal Bus Interface Unit

Integrated Functions

The address calculation function is super-pipelined and

contains two stages, AC1 and AC2. If the instruction

refers to a memory operand, AC1 calculates a linear

memory address for the instruction.

The AC2 stage performs any required memory manage-

ment functions, cache accesses, and register file

accesses. If a floating point instruction is detected by

AC2, the instruction is sent to the floating point unit for

processing.

Instructions are executed in the integer unit and in the

floating point unit. The cache unit stores the most recently

used data and instructions and provides fast access to

this information for the integer and floating point units.

The execution stage, under control of microcode, exe-

cutes instructions using the operands provided by the

address calculation stage.

1.1 INTEGER UNIT

The integer unit consists of:

•

Instruction Buffer

Instruction Fetch

Instruction Decoder and Execution

Write-back, the last stage of the integer unit, updates the

register file within the integer unit or writes to the

load/store unit within the memory management unit.

The superpipelined integer unit fetches, decodes, and

executes x86 instructions through the use of a six-stage

integer pipeline.

Write-Back

Cache Unit

Integer

FPU

MMU

Unit

C-Bus

Internal Bus Interface Unit

X-Bus

Graphics

Pipeline

Memory

Controller

Display

Controller

PCI

Controller

Integrated

Functions

PCI Bus

SDRAM Port

CS5530

(CRT/LCD TFT)

Figure 1-1. Internal Block Diagram

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8

Revision 3.1

Architecture Overview (Continued)

1.2 FLOATING POINT UNIT

The FPU (Floating Point Unit) interfaces to the integer unit

and the cache unit through a 64-bit bus. The FPU is x87-

instruction-set compatible and adheres to the IEEE-754

standard. Because almost all applications that contain

FPU instructions also contain integer instructions, the

GXm processor’s FPU achieves high performance by

completing integer and FPU operations in parallel.

other pending X-Bus memory requests to the SDRAM

controller before completing.

In addition, the internal bus interface unit provides config-

uration control for up to 20 different regions within system

memory with separate controls for read access, write

access, cacheability, and PCI access.

1.5 INTEGRATED FUNCTIONS

FPU instructions are dispatched to the pipeline within the

integer unit. The address calculation stage of the pipeline

checks for memory management exceptions and

accesses memory operands for use by the FPU. Once the

instructions and operands have been provided to the FPU,

the FPU completes instruction execution independently of

the integer unit.

The GXm processor integrates the following functions tra-

ditionally implemented using external devices:

•

High-performance 2D graphics accelerator

Separate CRT and TFT data paths from the display

controller

•

SDRAM memory controller

PCI bridge

1.3 WRITE-BACK CACHE UNIT

The 16 KB write-back unified cache is a data/instruction

cache and is configured as four-way set associative. The

cache stores up to 16 KB of code and data in 1024 cache

lines.

The processor has also been enhanced to support

National Semiconductor’s proprietary Virtual System

Architecture (VSA) implementation.

The GXm processor implements a Unified Memory Archi-

tecture (UMA). By using National Semiconductor’s Dis-

play Compression Technology (DCT), the performance

degradation inherent in traditional UMA systems is elimi-

nated.

The GXm processor provides the ability to allocate a por-

tion of the L1 cache as a scratchpad, which is used to

accelerate the Virtual Systems Architecture algorithms as

well as for some graphics operations.

1.4 MEMORY MANAGEMENT UNIT

1.5.1 Graphics Accelerator

The memory management unit (MMU) translates the lin-

ear address supplied by the integer unit into a physical

address to be used by the cache unit and the internal bus

interface unit. Memory management procedures are x86-

compatible, adhering to standard paging mechanisms.

The graphics accelerator is a full-featured GUI (Graphical

User Interface) accelerator. The graphics pipeline imple-

ments a bitBLT engine for frame buffer bitBLTs and rect-

angular fills. Additional instructions in the integer unit may

be processed, as the bitBLT engine assists the CPU in the

bitBLT operations that take place between system mem-

ory and the frame buffer. This combination of hardware

and software is used by the display driver to provide very

fast transfers in both directions between system memory

and the frame buffer. The bitBLT engine also draws ran-

domly-oriented vectors, and scanlines for polygon fill. All

of the pipeline operations described in the following list

can be applied to any bitBLT operation.

The MMU also contains a load/store unit that is responsi-

ble for scheduling cache and external memory accesses.

The load/store unit incorporates two performance-

enhancing features:

•

Load-store reordering that gives priority to memory

reads required by the integer unit over writes to

external memory.

•

Pattern Memory. Render with 8x8 dither, 8x8 mono-

chrome, or 8x1 color pattern.

•

Memory-read bypassing that eliminates unnecessary

memory reads by using valid data from the execution

unit.

Color Expansion. Expand monochrome bitmaps to

full-depth 8- or 16-bit colors.

1.4.1 Internal Bus Interface Unit

The internal bus interface unit provides a bridge from the

GXm processor to the integrated system functions (i.e.,

memory subsystem, display controller, graphics pipeline)

and the PCI bus interface.

Transparency. Suppresses drawing of background

pixels for transparent text.

Raster Operations. Boolean operation combines

source, destination, and pattern bitmaps.

When external memory access is required, the physical

address is calculated by the memory management unit

and then passed to the internal bus interface unit, which

translates the cycle to an X-Bus cycle (the X-Bus is a

National Semiconductor proprietary internal bus which

provides a common interface for all of the system mod-

ules). The X-Bus memory cycle now is arbitrated between

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Architecture Overview (Continued)

1.5.2 Display Controller

The memory controller handles multiple requests for

memory data from the GXm processor, the graphics

accelerator and the display controller. The memory con-

troller contains extensive buffering logic that helps mini-

mize contention for memory bandwidth between graphics

and CPU requests. The memory controller cooperates

with the internal bus controller to determine the cacheabil-

ity of all memory references.

The display port is a direct interface to the CS5530 which

drives a TFT flat panel display, LCD panel, or a CRT dis-

play.

The display controller (video generator) retrieves image

data from the frame buffer region of memory, performs a

color-look-up if required, inserts the cursor overlay into

the pixel stream, generates display timing, and formats

the pixel data for output to a variety of display devices.

The display controller contains Display Compression

Technology (DCT) that allows the GXm processor to

refresh the display from a compressed copy of the frame

buffer. DCT typically decreases the screen-refresh band-

width requirement by a factor of 15 to 20, further minimiz-

ing bandwidth contention.

1.5.4 PCI Controller

The GXm processor incorporates a full-function PCI inter-

face module that includes the PCI arbiter. All accesses to

external I/O devices are sent over the PCI bus, although

most memory accesses are serviced by the SDRAM con-

troller. The Internal Bus Interface Unit contains address

mapping logic that determines if memory accesses are

targeted for the SDRAM or for the PCI bus.

1.5.3 XpressRAM Memory Subsystem

The memory controller drives a 64-bit SDRAM port

directly. The SDRAM memory array contains both the

main system memory and the graphics frame buffer. Up to

four module banks of SDRAM are supported. Each mod-

ule bank will have two or four component banks depend-

ing on the memory size and organization. The maximum

configuration is four module banks with four component

banks providing a total of 16 open banks. The maximum

memory size is 1 GB.

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10

Revision 3.1

Architecture Overview (Continued)

1.6 GEODE GXM/CS5530 SYSTEM DESIGNS

The GXm Integrated Subsystem with MMX support con-

sists of two chips, the GXm Processor and the CS5530

I/O companion. The subsystem provides high perfor-

mance using 32-bit x86 processing. The two chips inte-

grate video, audio and memory interface functions

normally performed by external hardware.

management, and AT compatibility logic. In addition, the

newer CS5530 provides an Ultra DMA/33 interface,

MPEG2 assist, and AC97 Version 2.0 compliant audio.

Figure 1-2 shows a basic block system diagram (refer to

Figure 2-4 on page 34 for detailed subsystem intercon-

nection signals). It includes the National Semiconductor

CS9210 Dual-Scan Flat Panel Display Controller for

designs that need to interface to a DSTN panel (instead of

TFT panel).

As described in separate manuals, the CS5530 enables

the full features of the GXm processor with MMX support.

These features include full VGA and VESA video, 16-bit

stereo sound, IDE interface, ISA interface, SMM power

MD[63:0]

SDRAM

Port

YUV Port

(Video)

SDRAM

Geode™ GXm

Processor

Clocks

Serial

Packet

RGB Port

(Graphics)

CRT

USB

(2 Ports)

PCI Interface

System

Clocks

PCI Bus

TFT

Panel

Speakers

Graphics Data

Video Data

Analog RGB

CD

ROM

Audio

Geode™ CS5530

I/O Companion

AC97

Codec

Digital RGB (to TFT or DSTN Panel)

IDE Control

Geode™

CS9210

DSTN

Micro-

phone

Super

I/O

IDE

Devices

BIOS

14.31818

MHz Crystal

Controller

GPIO

ISA Bus

DC-DC & Battery

DSTN Panel

Figure 1-2. Geode™ GXm/CS5530 System Block Diagram

Revision 3.1

11

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Architecture Overview (Continued)

The CS9210 converts the digital RGB output of the

CS5530 I/O companion chip to the digital output suitable

for driving a dual-scan color STN (DSTN) flat panel LCD.

It connects to the digital RGB output of a GXm processor

or 55x0 and drives the graphics data onto a dual-scan flat

panel LCD. It can drive all standard dual-scan color STN

flat panels up to 1024x768 resolution. Figure 1-3 shows

an example of a CS9210 interface in a typical GXm Inte-

grated Subsystem.

Pixel Data

18

Pixel Port

(Control & Data)

13

16

Address Control

DRAM Data

24

4

DRAM-A

256Kx16 Bit

Geode™

CS5530

I/O

Geode™

CS9210

DSTN

Geode™ GXm

Processor

13

16

Address Control

DRAM Data

Serial

Configuration

DRAM-B

256Kx16 Bit

Controller

Companion

Panel Control

Panel Data

6

DSTN

LCD

24

Figure 1-3. CS9210 Interface System Diagram

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12

Revision 3.1

Table 2-1. Pin Type Definitions

Mnemonic Definition

Standard input pin.

2.0 Signal Definitions

This section describes the external interface of the Geode

GXm processor. Figure 2-1 shows the signals organized

by their functional interface groups (internal test and elec-

trical pins are not shown).

I

I/O

O

Bidirectional pin.

Totem-pole output.

2.1 PIN ASSIGNMENTS

The tables in this section use several common abbrevia-

tions. Table 2-1 lists the mnemonics and their meanings.

OD

Open-drain output structure that allows

multiple devices to share the pin in a

wired-OR configuration

PU

Pull-up resistor

Figure 2-2 on page 14 shows the pin assignment for the

352 BGA with Tables 2-2 and 2-3 listing the pin assign-

ments sorted by pin number and alphabetically by signal

name, respectively.

PD

Pull-down resistor

s/t/s

Sustained tri-state, an active-low tri-state

signal owned and driven by one and only

one agent at a time. The agent that

Figure 2-3 on page 19 shows the pin assignment for the

320 SPGA with Tables 2-4 and 2-5 listing the pin assign-

ments sorted by pin number and alphabetically by signal

name, respectively.

drives an s/t/s pin low must drive it high

for at least one clock before letting it float.

A new agent cannot start driving an s/t/s

signal any sooner than one clock after

the previous owner lets it float. A pull-up

resistor is required to sustain the inactive

state until another agent drives it, and

must be provided by the central resource.

In Section 2.2 “Signal Descriptions” starting on Page 24 a

description of each signal is provided within its associated

functional group.

Following the signal descriptions, information regarding

subsystem signal connections and split power planes and

decoupling is provided.

VCC (PWR) Power pin.

VSS (GND) Ground pin

#

The "#" symbol at the end of a signal

name indicates that the active, or

.

asserted state occurs when the signal is

at a low voltage level. When "#" is not

present after the signal name, the signal

is asserted when at a high voltage level.

SYSCLK

CLKMODE[2:0]

RESET

MD[63:0]

MA[12:0]

BA[1:0]

System

Interface

Signals

INTR

IRQ13

SMI#

RASA#, RASB#

CASA#, CASB#

CS[3:0]#

WEA#, WEB#

DQM[7:0]

CKEA, CKEB

SDCLK[3:0]

SDCLK_IN

SDCLK_OUT

Memory

Controller

Interface

Signals

SUSP#

SUSPA#

SERIALP

Geode™ GXm

Processor

AD[31:0]

C/BE[3:0]#

PAR

PCLK

FRAME#

IRDY#

VID_CLK

DCLK

TRDY#

STOP#

LOCK#

DEVSEL#

PERR#

CRT_HSYNC

CRT_VSYNC

FP_HSYNC

FP_VSYNC

ENA_DISP

VID_RDY

PCI

Interface

Signals

Video

Interface

Signals

SERR#

REQ[2:0]#

GNT[2:0]#

VID_VAL

VID_DATA[7:0]

PIXEL[17:0]

Figure 2-1. Functional Block Diagram

Revision 3.1

13

www.national.com

Signal Definitions (Continued)

Index Corner

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

A

B

A

VSS VSS AD27 AD24 AD21 AD16 VCC2 FRAM#DEVS# VCC3 PERR# AD15 VSS AD11 CBE0# AD6 VCC2 AD4 AD2 VCC3 AD0 AD1 TEST2 MD2 VSS VSS

VSS VSS AD28 AD25 AD22 AD18 VCC2 CBE2# TRDY# VCC3 LOCK# PAR AD14 AD12 AD9 AD7 VCC2 INTR AD3 VCC3 TEST1 TEST3 MD1 MD33 VSS VSS

B

C

AD29 AD31 AD30 AD26 AD23 AD19 VCC2 AD17 IRDY# VCC3 STOP#SERR# CBE1# AD13 AD10 AD8 VCC2 AD5 SMI# VCC3 TEST0 IRQ13 MD32 MD34 MD3 MD35

D

GNT0# TDI REQ2# VSS CBE3# VSS VCC2 VSS VSS VCC3 VSS VSS VSS VSS VSS VSS VCC2 VSS VSS VCC3 VSS MD0

VSS MD4 MD36 TDN

MD6 TDP MD5 MD37

VSS MD38 MD7 MD39

VCC3 VCC3 VCC3 VCC3

E

GNT2#SUSPA#REQ0# AD20

TD0 GNT1# TEST VSS

VCC3 VCC3 VCC3 VCC3

F

G

H

TMS SUSP#REQ1# VSS

FPVSY TCLK RESET VSS

VCC2 VCC2 VCC2 VCC2

CKM1 FPHSYSERLP VSS

VSS MD8 MD40 MD9

VSS MD41 MD10 MD42

VCC2 VCC2 VCC2 VCC2

VSS MD11 MD43 MD12

J

K

L

M

N

M

N

CKM2 VIDVAL CKM0 VSS

VSS MD44 MD13 MD45

VSS MD14 MD46 MD15

Geode™ GXm

VSS PIX1 PIX0 VSS

P

Processor

VIDCLK PIX3 PIX2 VSS

VSS MD47 CASA#SYSCLK

VSS WEB# WEA# CASB#

R

PIX4 PIX5 PIX6 VSS

T

352 BGA - Top View

PIX7 PIX8 PIX9 VSS

VSS DQM0 DQM4 DQM1

VCC3 VCC3 VCC3 VCC3

VSS DQM5 CS2# CS0#

VSS RASA#RASB# MA0

VCC2 VCC2 VCC2 VCC2

VSS MA1 MA2 MA3

MA4 MA5 MA6 MA7

U

VCC3 VCC3 VCC3 VCC3

PIX10 PIX11 PIX12 VSS

PIX13 CRTHS PIX14 VSS

VCC2 VCC2 VCC2 VCC2

PIX15 PIX16 CRTVS VSS

DCLK PIX17 VDAT6 VDAT7

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

PCLK FLT# VDAT4 VSS VOLDET VSS VCC2 VSS VSS VCC3 VSS VSS VSS VSS VSS VSS VCC2 VSS VSS VCC3 VSS DQM6 VSS MA8 MA9 MA10

VRDY VDAT5 VDAT3 VDAT0 EDISP MD63 VCC2 MD62 MD29 VCC3 MD59 MD26 MD56 MD55 MD22 CKEB VCC2 MD51 MD18 VCC3 MD48 DQM3 CS1# MA11 BA0

BA1

VSS VSS VDAT2 SCLK3 SCLK1RWCLK VCC2 SCKIN MD61 VCC3 MD28 MD58 MD25 MD24 MD54 MD21 VCC2 MD20 MD50 VCC3 MD17 DQM7 CS3# MA12 VSS VSS

VSS VSS VDAT1 SCLK0 SCLK2 MD31 VCC2SCKOUTMD30 VCC3 MD60 MD27 MD57 VSS MD23 MD53 VCC2 MD52 MD19 VCC3 MD49 MD16 DQM2 CKEA VSS VSS

21

22

23

24

25

26

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Note: Signal names have been abbreviated in this figure due to space constraints.

= GND terminal

= PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)

Figure 2-2. 352 BGA Pin Assignment Diagram

For order information refer to Section A.1 “Order Information” on page 236.

www.national.com

14

Revision 3.1

Signal Definitions (Continued)

Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number

No. Signal Name

A1 VSS

A2 VSS

B23 MD1

B24 MD33

B25 VSS

B26 VSS

C1 AD29

C2 AD31

C3 AD30

C4 AD26

C5 AD23

C6 AD19

C7 VCC2

C8 AD17

C9 IRDY#

C10 VCC3

C11 STOP#

C12 SERR#

C13 C/BE1#

C14 AD13

C15 AD10

C16 AD8

C17 VCC2

C18 AD5

C19 SMI#

C20 VCC3

C21 TEST0

C22 IRQ13

C23 MD32

C24 MD34

C25 MD3

C26 MD35

D1 GNT0#

D2 TDI

D19 VSS

D20 VCC3

D21 VSS

D22 MD0

D23 VSS

D24 MD4

D25 MD36

D26 TDN

E1 GNT2#

E2 SUSPA#

E3 REQ0#

E4 AD20

E23 MD6

E24 TDP

E25 MD5

E26 MD37

F1 TDO

K1 VCC2

K2 VCC2

T1 PIXEL7

T2 PIXEL8

T3 PIXEL9

T4 VSS

A3 AD27

A4 AD24

A5 AD21

A6 AD16

A7 VCC2

A8 FRAME#

A9 DEVSEL#

A10 VCC3

A11 PERR#

A12 AD15

A13 VSS

A14 AD11

A15 C/BE0#

A16 AD6

A17 VCC2

A18 AD4

A19 AD2

A20 VCC3

A21 AD0

A22 AD1

A23 TEST2

A24 MD2

A25 VSS

A26 VSS

B1 VSS

K3 VCC2

K4 VCC2

K23 VCC2

K24 VCC2

K25 VCC2

K26 VCC2

L1 CLKMODE1

L2 FP_HSYNC

L3 SERIALP

L4 VSS

T23 VSS

T24 DQM0

T25 DQM4

T26 DQM1

U1 VCC3

U2 VCC3

U3 VCC3

U4 VCC3

L23 VSS

U23 VCC3

U24 VCC3

U25 VCC3

U26 VCC3

V1 PIXEL10

V2 PIXEL11

V3 PIXEL12

V4 VSS

L24 MD11

L25 MD43

L26 MD12

M1 CLKMODE2

M2 VID_VAL

M3 CLKMODE0

M4 VSS

F2 GNT1#

F3 TEST

F4 VSS

F23 VSS

F24 MD38

F25 MD7

F26 MD39

G1 VCC3

G2 VCC3

G3 VCC3

G4 VCC3

G23 VCC3

G24 VCC3

G25 VCC3

G26 VCC3

H1 TMS

M23 VSS

V23 VSS

M24 MD44

M25 MD13

M26 MD45

N1 VSS

V24 DQM5

V25 CS2#

V26 CS0#

W1 PIXEL13

W2 CRT_HSYNC

W3 PIXEL14

W4 VSS

N2 PIXEL1

N3 PIXEL0

N4 VSS

B2 VSS

B3 AD28

B4 AD25

B5 AD22

B6 AD18

B7 VCC2

B8 C/BE2#

B9 TRDY#

B10 VCC3

B11 LOCK#

B12 PAR

B13 AD14

B14 AD12

B15 AD9

B16 AD7

B17 VCC2

B18 INTR

B19 AD3

B20 VCC3

B21 TEST1

B22 TEST3

N23 VSS

W23 VSS

N24 MD14

N25 MD46

N26 MD15

P1 VID_CLK

P2 PIXEL3

P3 PIXEL2

P4 VSS

W24 RASA#

W25 RASB#

W26 MA0

D3 REQ2#

D4 VSS

Y1 VCC2

H2 SUSP#

H3 REQ1#

H4 VSS

Y2 VCC2

D5 C/BE3#

D6 VSS

Y3 VCC2

Y4 VCC2

D7 VCC2

D8 VSS

H23 VSS

H24 MD8

H25 MD40

H26 MD9

J1 FP_VSYNC

J2 TCLK

P23 VSS

Y23 VCC2

Y24 VCC2

Y25 VCC2

Y26 VCC2

AA1 PIXEL15

AA2 PIXEL16

AA3 CRT_VSYNC

AA4 VSS

P24 MD47

P25 CASA#

P26 SYSCLK

R1 PIXEL4

R2 PIXEL5

R3 PIXEL6

R4 VSS

D9 VSS

D10 VCC3

D11 VSS

D12 VSS

D13 VSS

D14 VSS

D15 VSS

D16 VSS

D17 VCC2

D18 VSS

J3 RESET

J4 VSS

J23 VSS

R23 VSS

AA23 VSS

AA24 MA1

AA25 MA2

AA26 MA3

J24 MD41

J25 MD10

J26 MD42

R24 WEB#

R25 WEA#

R26 CASB#

Revision 3.1

15

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Signal Definitions (Continued)

Table 2-2. 352 BGA Pin Assignments - Sorted by Pin Number (Continued)

No. Signal Name

AB1 DCLK

AB2 PIXEL17

AB3 VID_DATA6

AB4 VID_DATA7

AB23 MA4

AB24 MA5

AB25 MA6

AB26 MA7

AC1 PCLK

AC2 FLT#

AC16 VSS

AD13 MD56

AD14 MD55

AD15 MD22

AD16 CKEB

AD17 VCC2

AD18 MD51

AD19 MD18

AD20 VCC3

AD21 MD48

AD22 DQM3

AD23 CS1#

AD24 MA11

AD25 BA0

AE10 VCC3

AE11 MD28

AE12 MD58

AE13 MD25

AE14 MD24

AE15 MD54

AE16 MD21

AE17 VCC2

AE18 MD20

AE19 MD50

AE20 VCC3

AE21 MD17

AE22 DQM7

AE23 CS3#

AE24 MA12

AE25 VSS

AF7 VCC2

AF8 SDCLK_OUT

AF9 MD30

AC17 VCC2

AC18 VSS

AC19 VSS

AF10 VCC3

AF11 MD60

AF12 MD27

AF13 MD57

AF14 VSS

AC20 VCC3

AC21 VSS

AC22 DQM6

AC23 VSS

AC24 MA8

AF15 MD23

AF16 MD53

AF17 VCC2

AF18 MD52

AF19 MD19

AF20 VCC3

AF21 MD49

AF22 MD16

AF23 DQM2

AF24 CKEA

AF25 VSS

AC25 MA9

AC3 VID_DATA4

AC4 VSS

AC26 MA10

AD1 VID_RDY

AD2 VID_DATA5

AD3 VID_DATA3

AD4 VID_DATA0

AD5 ENA_DISP

AD6 MD63

AC5 VOLDET

AC6 VSS

AD26 BA1

AC7 VCC2

AC8 VSS

AE1 VSS

AE2 VSS

AC9 VSS

AE3 VID_DATA2

AE4 SDCLK3

AE5 SDCLK1

AE6 RW_CLK

AE7 VCC2

AE26 VSS

AC10 VCC3

AC11 VSS

AC12 VSS

AC13 VSS

AC14 VSS

AC15 VSS

AD7 VCC2

AF1 VSS

AD8 MD62

AF2 VSS

AD9 MD29

AF3 VID_DATA1

AF4 SDCLK0

AF5 SDCLK2

AF6 MD31

AF26 VSS

AD10 VCC3

AD11 MD59

AD12 MD26

AE8 SDCLK_IN

AE9 MD61

www.national.com

16

Revision 3.1

Signal Definitions (Continued)

Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name

Signal Name Type

Pin No.

Signal Name Type

Pin No.

Signal Name Type

Pin No.

Signal Name Type

Pin No.

AD0

I/O

O

A21

A22

A19

B19

A18

C18

A16

B16

C16

B15

C15

A14

B14

C14

B13

A12

A6

DQM0

DQM1

DQM2

DQM3

DQM4

DQM5

DQM6

DQM7

ENA_DISP

FLT#

O

T24

T26

MD20

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

MD32

MD33

MD34

MD35

MD36

MD37

MD38

MD39

MD40

MD41

MD42

MD43

MD44

MD45

MD46

MD47

MD48

MD49

MD50

MD51

MD52

MD53

MD54

MD55

MD56

MD57

MD58

MD59

MD60

MD61

MD62

MD63

PAR

I/O

O

AE18

AE16

AD15

AF15

AE14

AE13

AD12

AF12

AE11

AD9

AF9

PIXEL6

PIXEL7

PIXEL8

PIXEL9

PIXEL10

PIXEL11

PIXEL12

PIXEL13

PIXEL14

PIXEL15

PIXEL16

PIXEL17

RASA#

RASB#

REQ0#

REQ1#

REQ2#

RESET

RW_CLK

SDCLK_IN

SDCLK_OUT

SDCLK0

SDCLK1

SDCLK2

SDCLK3

SERIALP

SERR#

SMI#

O

I

R3

T1

AD1

AD2

O

AF23

AD22

T25

T2

AD3

O

T3

AD4

O

V1

AD5

O

V24

V2

AD6

O

AC22

AE22

AD5

AC2

L2

V3

AD7

O

W1

AD8

O

W3

AD9

I

AA1

AA2

AB2

W24

W25

E3 (PU)

H3 (PU)

D3 (PU)

J3

AD10

FP_HSYNC

FP_VSYNC

FRAME#

GNT0#

GNT1#

GNT2#

INTR

O

AD11

O

J1

AF6

AD12

s/t/s

O

A8 (PU)

D1

C23

AD13

B24

AD14

O

F2

C24

AD15

O

E1

C26

I

AD16

I

B18

D25

I

AD17

C8

IRDY#

IRQ13

LOCK#

MA0

s/t/s

O

C9 (PU)

C22

E26

I

AD18

B6

F24

O

I

AE6

AE8

AF8

AF4

AE5

AF5

AE4

L3

AD19

C6

s/t/s

O

B11 (PU)

W26

AA24

AA25

AA26

AB23

AB24

AB25

AB26

AC24

AC25

AC26

AD24

AE24

D22

F26

AD20

E4

H25

O

OD

I

AD21

A5

MA1

O

J24

AD22

B5

MA2

O

J26

AD23

C5

MA3

O

L25

AD24

A4

MA4

O

M24

M26

N25

AD25

B4

MA5

O

AD26

C4

MA6

O

C12 (PU)

C19

AD27

A3

MA7

O

P24

AD28

B3

MA8

O

AD21

AF21

AE19

AD18

AF18

AF16

AE15

AD14

AD13

AF13

AE12

AD11

AF11

AE9

AD8

AD6

B12

STOP#

SUSP#

SUSPA#

SYSCLK

TCLK

s/t/s C11 (PU)

AD29

C1

MA9

O

I

O

H2 (PU)

E2

AD30

C3

MA10

MA11

MA12

MD0

O

AD31

C2

O

I

P26

BA0

AD25

AD26

P25

R26

A15

C13

B8

O

I

J2 (PU)

D2 (PU)

D26

BA1

O

I/O

TDI

I

CASA#

CASB#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

CKEA

CKEB

CLKMODE0

CLKMODE1

CLKMODE2

CRT_HSYNC

CRT_VSYNC

CS0#

O

MD1

B23

TDN

O

MD2

A24

TDO

O

F1

I/O

O

MD3

C25

TDP

O

E24

MD4

D24

TEST

I

F3 (PD)

C21

MD5

E25

TEST0

TEST1

TEST2

TEST3

TMS

O

D5

MD6

E23

O

B21

AF24

AD16

M3

MD7

F25

O

A23

O

MD8

H24

O

B22

I

MD9

H26

I

H1 (PU)

B9 (PU)

A7

I

L1

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

J25

TRDY#

VCC2

s/t/s

PWR

I

M1

L24

O

W2

L26

PCLK

PERR#

PIXEL0

PIXEL1

PIXEL2

PIXEL3

PIXEL4

PIXEL5

AC1

A11 (PU)

N3

VCC2

A17

O

AA3

V26

AD23

V25

AE23

AB1

A9 (PU)

M25

N24

s/t/s

O

VCC2

B7

O

VCC2

B17

CS1#

O

N26

O

N2

VCC2

C7

CS2#

O

AF22

AE21

AD19

AF19

O

P3

VCC2

C17

CS3#

O

P2

VCC2

D7

DCLK

DEVSEL#

I

O

R1

VCC2

D17

s/t/s

O

R2

VCC2

K1

Revision 3.1

17

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Signal Definitions (Continued)

Table 2-3. 352 BGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)

Signal Name Type

Pin No.

Signal Name Type

Pin No.

Signal Name Type

Pin No.

Signal Name Type

Pin No.

VCC2

VCC3

PWR

K2

K3

VCC3

PWR

O

G25

G26

U1

VSS

GND

B25

B26

D4

VSS

WEA#

WEB#

GND

O

W4

VCC3

W23

AA4

K4

VCC3

K23

K24

K25

K26

Y1

VCC3

U2

D6

AA23

AC4

VCC3

U3

D8

VCC3

U4

D9

AC6

VCC3

U23

U24

U25

U26

AC10

AC20

AD10

AD20

AE10

AE20

AF10

AF20

P1

D11

D12

D13

D14

D15

D16

D18

D19

D21

D23

F4

AC8

VCC3

AC9

Y2

VCC3

AC11

AC12

AC13

AC14

AC15

AC16

AC18

AC19

AC21

AC23

AE1

Y3

VCC3

Y4

VCC3

Y23

Y24

Y25

Y26

AC7

AC17

AD7

AD17

AE7

AE17

AF7

AF17

A10

A20

B10

B20

C10

C20

D10

D20

G1

VCC3

F23

H4

VID_CLK

VID_DATA0

VID_DATA1

VID_DATA2

VID_DATA3

VID_DATA4

VID_DATA5

VID_DATA6

VID_DATA7

VID_RDY

VID_VAL

VOLDET

VSS

O

AD4

AF3

AE3

AD3

AC3

AD2

AB3

AB4

AD1

M2

H23

J4

AE2

O

AE25

AE26

AF1

O

J23

L4

O

L23

M4

AF2

O

AF14

AF25

AF26

R25

O

M23

N1

O

I

N4

O

N23

P4

O

R24

O

AC5

A1

Note: PU/PD indicates pin is

internally connected to

a 20-kohm pull-up/-

GND

P23

R4

VSS

A2

down resistor.

G2

VSS

A13

A25

A26

B1

R23

T4

G3

VSS

G4

VSS

T23

V4

G23

G24

VSS

B2

V23

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18

Revision 3.1

Signal Definitions (Continued)

Index Corner

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

A

B

A

VCC3

AD25

VSS

VCC2

AD16

CBE2#

AD18 FRAME#

AD20 AD17 IRDY#

VCC2 VCC2 VSS DEVSEL# AD15

VCC3

TRDY# LOCK# CBE1#

VSS PAR VCC3

PERR# AD14 AD12

CBE0#

STOP# SERR#

VSS

AD11

AD13

AD10

AD8

VSS

AD5

VCC3

AD4

AD2

AD0

VCC2

VSS

TST0

TST2

IRQ13

MD0 MD32

VCC3

VSS

B

VSS

AD27

AD31 AD26

AD29 AD24

REQ0# REQ2# AD28

GNT0# TDI

CBE3#

AD23

AD22

AD21

AD19

AD9

AD7

AD6

AD3

SMI#

AD1

MD33

MD2

C

VCC3

VCC2

MD1

MD4

VSS

MD34

VCC3

D

AD30

INTR

TST1

TST3

MD3

MD5

MD6

MD35

E

VSS

VCC2

VSS

MD36

TDN

VSS

MD7

F

TDP

G

VSS CLKMODE2 VSS

GNT2# SUSPA#

MD37

H

MD38

J

TDO

VSS

TEST

VCC2

MD39

VCC2

VSS

K

REQ1# GNT1#

MD8

L

VCC2

VCC3

M

RESET SUSP#

MD40

MD9

N

VCC3

FPVSYN

SERIALP VSS

CKMD1 FPHSYN

TMS

VSS

MD41

P

TCK

MD10

MD11

MD44

MD14 MD13

MD15

VCC3

SYSCLK MD47

WEA# WEB# CASA#

DQM0 CASB#

DQM1 VSS

CS2#

CS0#

RASB# RASA#

MD42

MD43

MD12

Q

NC

VSS

R

S

CKMD0 VID_VAL

PIX0

MD45

T

PIX1

PIX3

NC

PIX2

MD46

Geode™ GXm

Processor

U

VSS

PIX6

PIX8

VCC3

VSS

V

VID_CLK

PIX5 PIX4

W

X

W

X

PIX9

320 SPGA - Top View

Y

VSS

PIX7

VSS

DQM4

VCC3

Z

NC

PIX10

DQM5

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

PIX11

PIX12 PIX13

VCC2 VCC2 VCC2

CRTHSYN DCLK

PIX14 VSS VCC2

PIX15 PIX16

VSS PIX17 VSS

CRTVSYN VDAT6

PCLK FLT# VDAT5

VRDY VSS VDAT0 SDCLK0 SDCLK2 SDCLKIN MD29

VCC2 VDAT4 VDAT2 SDCLK1 VCC2 RWCLK SDCLKOUT VSS

VDAT7 VDAT3 ENDIS SDCLK3 MD63 MD30 MD61

MD62 VCC3 MD28

VSS

VCC2

MA2

MA4

MA8

VSS

MA0

MA3

MA6

BA0

VCC2

VSS

MA1

VSS

MA5

MA10

VSS

VCC2

MD31

VSS

MD60

MD27

MD58

MD59 MD25

MD26

MD57

MD56

VCC3

MD24

MD54

VSS

MD22

MD55 MD21

MD23

MD53

MD52

VSS

VCC2

MD50

VCC2

VSS

BA1

MA9

MA7

MD20

MD16

MD49 VCC2

MD48 DQM7

MD17 VCC2 VSS

DQM3

DQM6

DQM2

CS1#

CS3#

VSS

MD19

CKEA

MA11

VCC3

MD51

MD18

MA12 VOLDET

VCC3 VSS

VSS

1

VCC2

3

VDAT1

5

VSS

7

VCC2

9

VSS

CKEB

VCC3

2

4

6

8

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Note: Signal names have been abbreviated in this figure due to space constraints.

= Denotes GND terminal

= Denotes PWR terminal (VCC2 = VCC_CORE; VCC3 = VCC_IO)

Figure 2-3. 320 SPGA Pin Assignment Diagram

For order information refer to Section A.1 “Order Information” on page 236.

Revision 3.1

19

www.national.com

Signal Definitions (Continued)

Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number

No. Signal Name

A3 VCC3

A5 AD25

C25 AD4

C27 AD0

C29 VCC2

C31 IRQ13

C33 MD1

C35 MD34

C37 VCC3

D2 AD30

D4 AD29

D6 AD24

D8 AD22

D10 AD20

D12 AD17

D14 IRDY#

D16 PERR#

D18 AD14

D20 AD12

D22 AD7

D24 INTR

D26 TEST1

D28 TEST3

D30 MD0

D32 MD32

D34 MD3

D36 MD35

E1 REQ0#

E3 REQ2#

E5 AD28

G1 VSS

G3 CLKMODE2

G5 VSS

R34 MD44

R36 MD12

S1 CLKMODE0

S3 VID_VAL

S5 PIXEL0

S33 MD14

S35 MD13

S37 MD45

T2 PIXEL1

T4 PIXEL2

T34 MD15

T36 MD46

U1 VSS

AB2 PIXEL12

AB4 PIXEL13

AB34 RASB#

AB36 RASA#

AC1 VCC2

AC3 VCC2

AC5 VCC2

AC33 VCC2

AC35 VCC2

AC37 VCC2

AD2 CRT_HSYNC

AD4 DCLK

AD34 MA2

AD36 MA0

AE1 PIXEL14

AE3 VSS

A7 VSS

A9 VCC2

A11 AD16

A13 VCC3

A15 STOP#

A17 SERR#

A19 VSS

A21 AD11

A23 AD8

G33 VSS

G35 MD37

G37 VSS

H2 GNT2#

H4 SUSPA#

H34 MD6

H36 MD38

J1 TDO

A25 VCC3

A27 AD2

J3 VSS

J5 TEST

A29 VCC2

A31 VSS

A33 TEST0

A35 VCC3

A37 VSS

B2 VSS

J33 VCC2

J35 VSS

U3 VCC3

U5 VSS

J37 MD7

U33 VSS

K2 REQ1#

K4 GNT1#

K34 MD39

K36 MD8

L1 VCC2

U35 VCC3

U37 VSS

AE5 VCC2

AE33 VCC2

AE35 VSS

V2 PIXEL3

V4 VID_CLK

V34 SYSCLK

V36 MD47

W1 PIXEL6

W3 PIXEL5

W5 PIXEL4

W33 WEA#

W35 WEB#

W37 CASA#

X2 NC

B4 AD27

AE37 MA1

B6 C/BE3#

B8 AD21

AF2 PIXEL15

AF4 PIXEL16

AF34 MA4

L3 VCC2

B10 AD19

B12 C/BE2#

B14 TRDY#

B16 LOCK#

B18 C/BE1#

B20 AD13

B22 AD9

L5 VCC2

L33 VCC2

L35 VCC2

L37 VCC2

M2 RESET

M4 SUSP#

M34 MD40

M36 MD9

N1 VCC3

N3 TMS

AF36 MA3

AG1 VSS

AG3 PIXEL17

AG5 VSS

AG33 VSS

AG35 MA5

AG37 VSS

AH2 CRT_VSYNC

AH4 VID_DATA6

AH32 MA10

AH34 MA8

AH36 MA6

AJ1 PCLK

E7 VSS

B24 AD6

E9 VCC2

E11 VCC2

E13 VSS

E15 DEVSEL#

E17 AD15

E19 VSS

E21 C/BE0#

E23 AD5

X4 PIXEL9

X34 DQM0

X36 CASB#

Y1 PIXEL8

Y3 VSS

B26 AD3

B28 SMI#

B30 AD1

N5 VSS

B32 TEST2

B34 MD33

B36 MD2

C1 VCC3

C3 AD31

C5 AD26

C7 AD23

C9 VCC2

C11 AD18

C13 FRAME#

C15 VSS

C17 PAR

C19 VCC3

C21 AD10

C23 VSS

N33 VSS

N35 MD41

N37 VCC3

P2 FP_VSYNC

P4 TCLK

Y5 PIXEL7

Y33 DQM1

Y35 VSS

AJ3 FTL#

E25 VSS

E27 VCC2

E29 VCC2

E31 VSS

E33 MD4

E35 MD36

E37 TDN

F2 GNT0#

F4 TDI

Y37 DQM4

Z2 NC

AJ5 VID_DATA5

AJ7 VSS

P34 MD10

P36 MD42

Q1 SERIALP

Q3 VSS

Z4 PIXEL10

Z34 CS2#

Z36 DQM5

AA1 VCC3

AA3 PIXEL11

AA5 VSS

AJ9 VCC2

AJ11 MD31

AJ13 VSS

Q5 NC

AJ15 MD60

AJ17 MD57

AJ19 VSS

Q33 MD11

Q35 VSS

Q37 MD43

R2 CLKMODE1

R4 FP_HSYNC

AA33 VSS

AA35 CS0#

AA37 VCC3

AJ21 MD22

AJ23 MD52

AJ25 VSS

F34 MD5

F36 TDP

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20

Revision 3.1

Signal Definitions (Continued)

Table 2-4. 320 SPGA Pin Assignments - Sorted by Pin Number (Continued)

No. Signal Name

AJ27 VCC2

AJ29 VCC2

AJ31 VSS

AK24 MD20

AK26 MD50

AK28 MD16

AK30 DQM3

AK32 CS3#

AK34 VSS

AL21 MD23

AL23 VSS

AM18 MD25

AM20 MD24

AM22 MD53

AM24 MD51

AM26 MD18

AM28 MD48

AM30 DQM7

AM32 DQM2

AM34 MA12

AM36 VOLDET

AN1 VSS

AN15 MD28

AN17 MD26

AN19 VSS

AN21 MD54

AN23 CKEB

AN25 VCC3

AN27 MD17

AN29 VCC2

AN31 VSS

AN33 CS1#

AN35 VCC3

AN37 VSS

AL25 MD19

AL27 MD49

AL29 VCC2

AL31 DQM6

AL33 CKEA

AL35 MA11

AL37 VCC3

AM2 VID_DATA7

AM4 VID_DATA3

AM6 ENA_DISP

AM8 SDCLK3

AM10 MD63

AM12 MD30

AM14 MD61

AM16 MD59

AJ33 BA1

AJ35 MA9

AJ37 MA7

AK2 VID_RDY

AK4 VSS

AK36 BA0

AL1 VCC2

AK6 VID_DATA0

AK8 SDCLK0

AK10 SDCLK2

AK12 SDCLK_IN

AK14 MD29

AK16 MD27

AK18 MD56

AK20 MD55

AK22 MD21

AL3 VID_DATA4

AL5 VID_DATA2

AL7 SDCLK1

AL9 VCC2

AN3 VCC2

AL11 RW_CLK

AL13 SDCLK_OUT

AL15 VSS

AN5 VID_DATA1

AN7 VSS

AN9 VCC2

AL17 MD58

AL19 VCC3

AN11 MD62

AN13 VCC3

Revision 3.1

21

www.national.com

Signal Definitions (Continued)

Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name

Signal Name Type Pin. No.

AD0

I/O

O

C27

B30

A27

B26

C25

E23

B24

D22

A23

B22

C21

A21

D20

B20

D18

E17

A11

D12

C11

B10

D10

B8

DQM0

DQM1

DQM2

DQM3

DQM4

DQM5

DQM6

DQM7

ENA_DISP

FLT#

O

I

X34

Y33

MD20

MD21

MD22

MD23

MD24

MD25

MD26

MD27

MD28

MD29

MD30

MD31

MD32

MD33

MD34

MD35

MD36

MD37

MD38

MD39

MD40

MD41

MD42

MD43

MD44

MD45

MD46

MD47

MD48

MD49

MD50

MD51

MD52

MD53

MD54

MD55

MD56

MD57

MD58

MD59

MD60

MD61

MD62

MD63

NC

I/O

AK24

AK22

AJ21

AL21

AM20

AM18

AN17

AK16

AN15

AK14

AM12

AJ11

D32

PIXEL3

PIXEL4

PIXEL5

PIXEL6

PIXEL7

PIXEL8

PIXEL9

PIXEL10

PIXEL11

PIXEL12

PIXEL13

PIXEL14

PIXEL15

PIXEL16

PIXEL17

RASA#

RASB#

REQ0#

REQ1#

REQ2#

RESET

RW_CLK

SDCLK_IN

SDCLK_OUT

SDCLK0

SDCLK1

SDCLK2

SDCLK3

SERIALP

SERR#

SMI#

O

I

V2

W5

AD1

AD2

AM32

AK30

Y37

W3

AD3

W1

AD4

Y5

AD5

Z36

Y1

AD6

AL31

AM30

AM6

AJ3

X4

AD7

Z4

AD8

AA3

AD9

AB2

AD10

FP_HSYNC

FP_VSYNC

FRAME#

GNT0#

GNT1#

GNT2#

INTR

O

R4

AB4

AD11

P2

AE1

AD12

s/t/s C13 (PU)

AF2

AD13

O

I

F2

K4

B34

AF4

AD14

C35

AG3

AB36

AB34

E1 (PU)

K2 (PU)

E3 (PU)

M2

AD15

H2

D36

AD16

D24

E35

AD17

IRDY#

IRQ13

LOCK#

MA0

s/t/s D14 (PU)

C31

s/t/s B16 (PU)

G35

AD18

O

H36

I

AD19

K34

I

AD20

O

AD36

AE37

AD34

AF36

AF34

AG35

AH36

AJ37

AH34

AJ35

AH32

AL35

AM34

D30

M34

I

AD21

MA1

N35

O

I

AL11

AK12

AL13

AK8

AD22

D8

MA2

O

P36

AD23

C7

MA3

O

Q37

O

OD

I

AD24

D6

MA4

O

R34

AD25

A5

MA5

O

S37

AL7

AD26

C5

MA6

O

T36

AK10

AM8

Q1

AD27

B4

MA7

O

V36

AD28

E5

MA8

O

AM28

AL27

AK26

AM24

AJ23

AM22

AN21

AK20

AK18

AJ17

AL17

AM16

AJ15

AM14

AN11

AM10

Q5

AD29

D4

MA9

O

A17 (PU)

B28

AD30

D2

MA10

MA11

MA12

MD0

O

AD31

C3

O

STOP#

SUSP#

SUSPA#

SYSCLK

TCLK

s/t/s A15 (PU)

BA0

AK36

AJ33

W37

X36

E21

B18

B12

B6

O

I

O

I

M4 (PU)

H4

BA1

O

I/O

CASA#

CASB#

C/BE0#

C/BE1#

C/BE2#

C/BE3#

CKEA

CKEB

CLKMODE0

CLKMODE1

CLKMODE2

CRT_HSYNC

CRT_VSYNC

CS0#

O

MD1

C33

V34

O

MD2

B36

I

P4 (PU)

F4 (PU)

E37

I/O

O

MD3

D34

TDI

I

MD4

E33

TDN

O

I

MD5

F34

TDO

J1

MD6

H34

TDP

F36

AL33

AN23

S1

MD7

J37

TEST

J5 (PD)

A33

O

MD8

K36

TEST0

TEST1

TEST2

TEST3

TMS

O

I

MD9

M36

P34

D26

I

R2

MD10

MD11

MD12

MD13

MD14

MD15

MD16

MD17

MD18

MD19

B32

I

G3

Q33

D28

O

AD2

AH2

AA35

AN33

Z34

AK32

AD4

R36

NC

X2

N3 (PU)

O

S35

NC

Z2

TRDY#

VCC2

s/t/s B14 (PU)

O

S33

PAR

I/O

O

C17

PWR

A9

A29

C9

CS1#

O

T34

PCLK

PERR#

PIXEL0

PIXEL1

PIXEL2

AJ1

VCC2

CS2#

O

AK28

AN27

AM26

AL25

s/t/s D16 (PU)

VCC2

CS3#

O

S5

T2

T4

VCC2

C29

E9

DCLK

DEVSEL#

I

VCC2

s/t/s E15 (PU)

VCC2

E11

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22

Revision 3.1

Signal Definitions (Continued)

Table 2-5. 320 SPGA Pin Assignments - Sorted Alphabetically by Signal Name (Continued)

Signal Name Type Pin. No.

VCC2

VCC3

PWR

E27

E29

J33

VCC3

PWR

O

A35

C1

VSS

GND

A31

A37

B2

VSS

WEA#

WEB#

GND

O

AE35

AG1

VCC3

C19

C37

N1

AG5

L1

VCC3

C15

C23

E7

AG33

AG37

AJ7

L3

VCC3

L5

VCC3

N37

U3

L33

VCC3

E13

E19

E25

E31

G1

AJ13

AJ19

AJ25

AJ31

AK4

L35

VCC3

U35

AA1

AA37

AL19

AL37

AN13

AN25

AN35

V4

L37

VCC3

AC1

AC3

AC5

AC33

AC35

AC37

AE5

AE33

AJ9

VCC3

G5

AK34

AL15

AL23

AN1

VCC3

G33

G37

J3

VCC3

VID_CLK

VID_DATA0

VID_DATA1

VID_DATA2

VID_DATA3

VID_DATA4

VID_DATA5

VID_DATA6

VID_DATA7

VID_RDY

VID_VAL

VOLDET

VSS

J35

N5

AN7

O

AK6

AN5

AL5

AM4

AL3

AJ5

AN19

AN31

AN37

W33

W35

O

N33

Q3

AJ27

AJ29

AL1

AL9

AL29

AN3

AN9

AN29

A3

O

Q35

U1

O

U5

Note: PU/PD indicates pin is

internally connected to

a 20-kohm pull-up/

O

AH4

AM2

AK2

S3

U33

U37

Y3

O

I

down resistor

O

Y35

AA5

AA33

AE3

O

AM36

A7

A13

A25

GND

VSS

A19

Revision 3.1

23

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Signal Definitions (Continued)

2.2 SIGNAL DESCRIPTIONS

2.2.1 System Interface Signals

BGA

SPGA

Signal Name

Pin No. Pin No.

Type

Description

SYSCLK

P26

V34

I

System Clock

System Clock runs synchronously with the PCI bus. The internal

clock of the GXm processor is generated by an internal PLL

which multiplies the SYSCLK input and can run up to eight times

faster. The SYSCLK to core clock multiplier is configured using

the CLKMOD[2:0] inputs.

The SYSCLK input is a fixed frequency which can only be

stopped or varied when the GXm processor is in a full 3V Sus-

pend. (Section 6.4 “3-Volt Suspend Mode” on page 174 for

details regarding this mode.)

CLKMODE[2:0]

M1, L1,

M3

G3, R2,

S1

I

Clock Mode

These signals are used to set the core clock multiplier. The PCI

clock "SYSCLK" is multiplied by the value programmed by CLK-

MODE[2:0] to generate the GXm processor’s core clock.

CLKMODE2 is valid only for GXm processor revision 4.0 and up.

The value read from DIR1 (Device ID Register 1, refer to

page 51) affects the definition of the CLKMODE pins.

If DIR1 = 30h-33h then CLKMODE[1:0]:

00 = SYSCLK multiplied by 4 (Test mode only)

01 = SYSCLK multiplied by 6

10 = SYSCLK multiplied by 7

11 = SYSCLK multiplied by 5

If DIR1 = 34h-4Fh then CLKMODE[1:0]:

00 = SYSCLK multiplied by 4 (Test mode only)

01 = SYSCLK multiplied by 6

10 = SYSCLK multiplied by 7

11 = SYSCLK multiplied by 8

If DIR1 > or = 50h then CLKMODE[2:0]:

000 = SYSCLK multiplied by 4 (Test mode only)

001 = SYSCLK multiplied by 10

010 = SYSCLK multiplied by 9

011 = SYSCLK multiplied by 5

100 = SYSCLK multiplied by 4

101 = SYSCLK multiplied by 6

110 = SYSCLK multiplied by 7

111 = SYSCLK multiplied by 8

RESET

J3

M2

I

Reset

RESET aborts all operations in progress and places the

GXm processor into a reset state. RESET forces the CPU and

peripheral functions to begin executing at a known state. All data

in the on-chip cache is invalidated.

RESET is an asynchronous input but must meet specified setup

and hold times to guarantee recognition at a particular clock

edge. This input is typically generated during the Power-On-

Reset sequence.

Note: Warm Reset does not require an input on the GXm pro-

cessor since the function is virtualized using SMM.

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24

Revision 3.1

Signal Definitions (Continued)

2.2.1 System Interface Signals (Continued)

BGA

SPGA

Signal Name

Pin No. Pin No.

Type

Description

INTR

B18

C22

D24

C31

I

(Maskable) Interrupt Request

INTR is a level-sensitive input that causes the GXm processor to

Suspend execution of the current instruction stream and begin

execution of an interrupt service routine. The INTR input can be

masked through the Flags Register IF bit. (See Table 3-4 on

page 43 for bit definitions.)

IRQ13

O

Interrupt Request Level 13

IRQ13 is asserted if an on-chip floating point error occurs.

When a floating point error occurs, the GXm processor asserts

the IRQ13 pin. The floating point interrupt handler then performs

an OUT instruction to I/O address F0h or F1h. The GXm proces-

sor accepts either of these cycles and clears the IRQ13 pin.

Refer to Section 3.4.1 “I/O Address Space” on page 60 for fur-

ther information on IN/OUT instructions.

SMI#

C19

B28

I

System Management Interrupt

SMI# is a level-sensitive interrupt. SMI# puts the GXm processor

into System Management Mode (SMM).

SUSP#

H2

M4

Suspend Request

(PU)

This signal is used to request that the GXm processor enter Sus-

pend mode. After recognition of an active SUSP# input, the pro-

cessor completes execution of the current instruction, any

pending decoded instructions and associated bus cycles.

SUSP# is ignored following RESET# and is enabled by setting

the SUSP bit in CCR2. (See Table 16 on page 44 for CCR2 bit

definitions.)

Since the GXm processor includes system logic functions as well

as the CPU core, there are special modes designed to support

the different power management states associated with APM,

ACPI, and portable designs. The part can be configured to stop

only the CPU core clocks, or all clocks. When all clocks are

stopped, the external clock can also be stopped. (See Section

6.0 “Power Management” on page 174 for more details regarding

power management states.)

This pin is internally connected to a 20-kohm pull-up resistor.

SUSP# is pulled up when not active.

SUSPA#

E2

H4

O

Suspend Acknowledge

Suspend Acknowledge indicates that the GXm processor has

entered low-power Suspend mode as a result of SUSP# asser-

tion or execution of a HALT instruction. SUSPA# is enabled by

setting the SUSP bit in CCR2. (See Table 16 on page 44 for

CCR2 bit definitions.)

The SYSCLK input may be stopped after SUSPA# has been

asserted to further reduce power consumption if the system is

configured for 3V Suspend mode. (Section 6.4 “3-Volt Suspend

Mode” on page 174 for details regarding this mode.)

SERIALP

L3

Q1

O

Serial Packet

Serial Packet is the single wire serial-transmission signal to the

CS5530 chip. The clock used for this interface is the PCI clock

(SYSCLK). This interface carries packets of miscellaneous infor-

mation to the chipset to be used by the VSA software handlers.

Revision 3.1

25

www.national.com

Signal Definitions (Continued)

2.2.2 PCI Interface Signals

BGA

SPGA

Signal Name

Pin No. Pin No

Type

Description

AD[31:0]

Refer Refer

I/O

Multiplexed Address and Data

toTable toTable

Addresses and data are multiplexed on the same PCI pins. A bus

transaction consists of an address phase in the cycle in which

FRAME# is asserted followed by one or more data phases. Dur-

ing the address phase, AD[31:0] contain a physical 32-bit

address. For I/O, this is a byte address, for configuration and

memory it is a DWORD address. During data phases, AD[7:0]

contain the least significant byte (LSB) and AD[31:24] contain

the most significant byte (MSB). Write data is stable and valid

when IRDY# is asserted and read data is stable and valid when

TRDY# is asserted. Data is transferred during those SYSCLKS

where both IRDY# and TRDY# are asserted.

2-3

2-5

C/BE[3:0]#

D5,

B8,

C13,

A15

B6,

B12,

B18,

E21

I/O

Multiplexed Command and Byte Enables

Bus command and byte enables are multiplexed on the same

PCI pins. During the address phase of a transaction when

FRAME# is active, C/BE[3:0]# define the bus command. During

the data phase C/BE[3:0]# are used as byte enables. The byte

enables are valid for the entire data phase and determine which

byte lanes carry meaningful data. C/BE0# applies to byte 0

(LSB) and C/BE3# applies to byte 3 (MSB).

The command encoding and types are listed below.

0000 = Interrupt Acknowledge

0001 = Special Cycle

0010 = I/O Read

0011 = I/O Write

0100 = Reserved

0101 = Reserved

0110 = Memory Read

0111 = Memory Write

1000 = Reserved

1001 = Reserved

1010 = Configuration Read

1011 = Configuration Write

1100 = Memory Read Multiple

1101 = Dual Address Cycle (Reserved)

1110 = Memory Read Line

1111 = Memory Write and Invalidate

PAR

B12

C17

I/O

Parity

Parity generation is required by all PCI agents: the master drives

PAR for address and write-data phases, the target drives PAR for

read-data phases. Parity is even across AD[31:0] and

C/BE[3:0]#.

For address phases, PAR is stable and valid one SYSCLK after

the address phase. It has the same timing as AD[31:0] but

delayed by one SYSCLK.

For data phases, PAR is stable and valid one SYSCLK after

either IRDY# is asserted on a write transaction or after TRDY# is

asserted on a read transaction. Once PAR is valid, it remains

valid until one SYSCLK after the completion of the data phase.

(Also see PERR#.)

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26

Revision 3.1

Signal Definitions (Continued)

2.2.2 PCI Interface Signals (Continued)

BGA

SPGA

Signal Name

Pin No. Pin No

Type

Description

Frame

FRAME#

A8

C13

s/t/s

(PU)

Cycle Frame is driven by the current master to indicate the

beginning and duration of an access. FRAME# is asserted to

indicate a bus transaction is beginning. While FRAME# is

asserted, data transfers continue. When FRAME# is deasserted,

the transaction is in the final data phase.

This pin is internally connected to a 20-kohm pull-up resistor.

IRDY#

TRDY#

STOP#

C9

(PU)

D14

(PU)

s/t/s

Initiator Ready

Initiator Ready is asserted to indicate that the bus master is able

to complete the current data phase of the transaction. IRDY# is

used in conjunction with TRDY#. A data phase is completed on

any SYSCLK in which both IRDY# and TRDY# are sampled

asserted. During a write, IRDY# indicates valid data is present

on AD[31:0]. During a read, it indicates the master is prepared to

accept data. Wait cycles are inserted until both IRDY# and

TRDY# are asserted together.

This pin is internally connected to a 20-kohm pull-up resistor.

B9

(PU)

B14

(PU)

Target Ready

TRDY# is asserted to indicate that the target agent is able to

complete the current data phase of the transaction. TRDY# is

used in conjunction with IRDY#. A data phase is complete on any

SYSCLK in which both TRDY# and IRDY# are sampled

asserted. During a read, TRDY# indicates that valid data is

present on AD[31:0]. During a write, it indicates the target is pre-

pared to accept data. Wait cycles are inserted until both IRDY#

and TRDY# are asserted together.

This pin is internally connected to a 20-kohm pull-up resistor.

C11

A15

Target Stop

(PU)

STOP# is asserted to indicate that the current target is request-

ing the master to stop the current transaction. This signal is used

with DEVSEL# to indicate retry, disconnect or target abort. If

STOP# is sampled active while a master, FRAME# will be deas-

serted and the cycle stopped within three SYSCLK cycles. As an

input, STOP# can be asserted in the following cases. 1) If a PCI

master tries to access memory that has been locked by another

master. This condition is detected if FRAME# and LOCK# are

asserted during an address phase. 2) STOP# will also be

asserted if the PCI write buffers are full or if a previously buffered

cycle has not completed. 3) Finally, STOP# can be asserted on

read cycles that cross cache line boundaries. This is conditional

based upon the programming of bit 1 in PCI Control Function 2

Register. (See Table 4-37 on page 156 for programming details.)

This pin is internally connected to a 20-kohm pull-up resistor.

Revision 3.1

27

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Signal Definitions (Continued)

2.2.2 PCI Interface Signals (Continued)

BGA

SPGA

Signal Name

Pin No. Pin No

Type

Description

LOCK#

B11

B16

s/t/s

Lock Operation

(PU)

LOCK# indicates an atomic operation that may require multiple

transactions to complete. When LOCK# is asserted, nonexclu-

sive transactions may proceed to an address that is not currently

locked (at least 16 bytes must be locked). A grant to start a trans-

action on PCI does not guarantee control of LOCK#. Control of

LOCK# is obtained under it own protocol in conjunction with

GNT#. It is possible for different agents to use PCI while a single

master retains ownership of LOCK#. The arbiter can implement

a complete system lock. In this mode, if LOCK# is active, no

other master can gain access to the system until the LOCK# is

deasserted.

This pin is internally connected to a 20-kohm pull-up resistor.

DEVSEL#

A9

E15

s/t/s

Device Select

(PU)

DEVSEL# indicates that the driving device has decoded its

address as the target of the current access. As an input,

DEVSEL# indicates whether any device on the bus has been

selected. DEVSEL# will also be driven by any agent that has the

ability to accept cycles on a subtractive decode basis. As a mas-

ter, if no DEVSEL# is detected within and up to the subtractive

decode clock, a master abort cycle will result expect for special

cycles which do not expect a DEVSEL# returned.

This pin is internally connected to a 20-kohm pull-up resistor.

PERR#

A11

D16

s/t/s

Parity Error

(PU)

PERR# is used for reporting of data parity errors during all PCI

transactions except a Special Cycle. The PERR# line is driven

two SYSCLKs after the data in which the error was detected.

This is one SYSCLK after the PAR that is attached to the data.

The minimum duration of PERR# is one SYSCLK for each data

phase in which a data parity error is detected. PERR# must be

driven high for one SYSCLK before being in TRI-STATE mode. A

target asserts PERR# on write cycles if it has claimed the cycle

with DEVSEL#. The master asserts PERR# on read cycles.

This pin is internally connected to a 20-kohm pull-up resistor.

SERR#

C12

A17

OD

System Error

(PU)

System Error may be asserted by any agent for reporting errors

other than PCI parity. The intent is to have the PCI central agent

assert NMI to the processor. When the Parity Enable bit is set in

the Memory Controller Configuration register, SERR# will be

asserted upon detecting a parity error on read operations from

DRAM.

REQ[2:0]#

D3,

H3,

E3

E3,

K2,

E1

I

Request Lines

Request indicates to the arbiter that an agent desires use of the

bus. Each master has its own REQ# line. REQ# priorities are

based on the arbitration scheme chosen.

(PU)

Each of these pins are internally connected to a 20-kohm pull-up

resistor.

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28

Revision 3.1

Signal Definitions (Continued)

2.2.2 PCI Interface Signals (Continued)

BGA

SPGA

Signal Name

Pin No. Pin No

Type

Description

Grant Lines

GNT[2:0]#

E1,

F2,

D1

H2,

K4,

F2

O

Grant indicates to the requesting master that it has been granted

access to the bus. Each master has its own GNT# line. GNT#

can be pulled away at any time a higher REQ# is received or if

the master does not begin a cycle within a minimum period of

time (16 SYSCLKs).

2.2.3 Memory Controller Interface Signals

BGA SPGA

Signal Name

Pin No. Pin No.

Type

Description

Note: The memory controller interface supports two types of memory configurations: SDRAM modules on the sys-

tem board and JEDEC DIMM connectors. Refer to Section 4.3 “Memory Controller” on page 103 for detailed

information regarding signal connections.

MD[63:0]

Refer

I/O

Memory Data Bus

toTable toTable

The data bus lines driven to/from system memory.

2-3

2-5

MA[12:0]

Refer

O

Memory Address Bus

toTable toTable

The multiplexed row/column address lines driven to the system

memory.

2-3

2-5

Supports 256 Mbit SDRAM.

BA[1:0]

AD26,

AD25

AJ33,

AK36

O

Bank Address Bits

These bits are used to select the component bank within the

SDRAM.

CS[3:0]#

AE23,

V25,

AD23,

V26

AK32,

Z34,

AN33,

AA35

Chip Selects

The chip selects are used to select the module bank within the

system memory. Each chip select corresponds to a specific mod-

ule bank.

If CS# is high, the bank(s) do not respond to RAS#, CAS#, WE#

until the bank is selected again.

RASA#,

RASB#

W24,

W25

AB36,

AB34

O

Row Address Strobe

RAS#, CAS#, WE# and CKE are encoded to support the differ-

ent SDRAM commands. RASA# is used with CS[1:0]#. RASB#

is used with CS[3:2]#.

CASA#,

CASB#

P25,

R26

W37,

X36

Column Address Strobe

RAS#, CAS#, WE# and CKE are encoded to support the differ-

ent SDRAM commands. CASA# is used with CS[1:0]#. CASB#

is used with CS[3:2]#.

WEA#,

WEB#

R25,

R24

W33,

W35

Write Enable

RAS#, CAS#, WE# and CKE are encoded to support the differ-

ent SDRAM commands. WEA# is used with CS[1:0]#. WEB# is

used with CS[3:2]#.

Revision 3.1

29

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Signal Definitions (Continued)

2.2.3 Memory Controller Interface Signals (Continued)

BGA

SPGA

Signal Name

Pin No. Pin No.

Type

Description

DQM[7:0]

Refer Refer

O

Data Mask Control Bits

toTable toTable

During memory read cycles, these outputs control whether the

SDRAM output buffers are driven on the MD bus or not. All DQM

signals are asserted during read cycles.

2-3

2-5

During memory write cycles, these outputs control whether or

not MD data will be written into the SDRAM.

DQM[7:0] connect directly to the DQM7-0 pins of each connec-

tor.

CKEA,

CKEB

AF24,

AD16

AL33,

AN23

O

Clock Enable

For normal operation CKE is held high. CKE goes low during

Suspend.

SDCLK[3:0]

AE4,

AF5,

AE5,

AF4

AM8,

AK10,

AL7,

SDRAM Clocks

The SDRAM samples all the control, address, and data using

these clocks.

AK8

SDCLK_IN

AE8

AK12

I

SDRAM Clock Input

The GXm processor samples the memory read data on this

clock. Works in conjunction with the SDCLK_OUT signal.

SDCLK_OUT

AF8

AL13

O

SDRAM Clock Output

This output is routed back to SDCLK_IN. The board designer

should vary the length of the board trace to control skew

between SDCLK_IN and SDCLK.

2.2.4 Video Interface Signals

BGA

SPGA

Signal Name

Pin No

Type

Description

PCLK

AC1

AJ1

O

Pixel Port Clock

Pixel Port Clock represents the pixel dotclock or a 2x multiple of

the dotclock for some 16-bit-per-pixel modes. It determines the

data transfer rate from the GXm processor to the CS5530.

VID_CLK

DCLK

P1

V4

O

I

Video Clock

Video Clock represents the video port clock to the CS5530. This

pin is only used if the Video Port is enabled.

AB1

AD4

DOT Clock

The DCLK input is driven from the CS5530 and represents the

pixel dot clock. In some cases, such as when displaying 16 BPP

data with an eight-bit-graphics pixel port, this clock will actually

be a 2x multiple of the dotclock.

CRT_HSYNC

W2

AD2

O

CRT Horizontal Sync

CRT Horizontal Sync establishes the line rate and horizontal

retrace interval for an attached CRT. The polarity is programma-

ble and depends on the display mode.

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30

Revision 3.1

Signal Definitions (Continued)

2.2.4 Video Interface Signals (Continued)

BGA

SPGA

Signal Name

Pin No

Type

Description

CRT_VSYNC

AA3

AH2

O

CRT Vertical Sync

CRT Vertical Sync establishes the screen refresh rate and verti-

cal retrace interval for an attached CRT. The polarity is program-

mable and depends on the display mode.

FP_HSYNC

L2

R4

O

Flat Panel Horizontal Sync

Flat Panel Horizontal Sync establishes the line rate and horizon-

tal retrace interval for a TFT display. Polarity is programmable

and depends on the display mode.

This signal is an input to the CS5530. The CS5530 re-drives this

signal to the flat panel.

If no flat panel is used in the system, this signal does not need to

be connected.

FP_VSYNC

J1

P2

O

Flat Panel Vertical Sync

Flat Panel Vertical Sync establishes the screen refresh rate and

vertical retrace interval for a TFT display. Polarity is programma-

ble and depends on the display mode.

This signal is an input to the CS5530. The CS5530 re-drives this

signal to the flat panel.

If no flat panel is used in the system, this signal does not need to

be connected.

ENA_DISP

VID_RDY

AD5

AM6

O

Display Enable

Display Enable indicates the active display portion of a scan line

to the CS5530.

In a CS5530-based system, this signal is required to be con-

nected even if there is no TFT panel in the system.

AD1

M2

AK2

S3

I

Video Ready

This input signal indicates that the video FIFO in the CS5530 is

ready to receive more data.

VID_VAL

O

Video Valid

VID_VAL qualifies valid video data to the CS5530.

Video Data Bus

VID_DATA[7:0]

Refer

to

Refer

toTable

2-5

When the Video Port is enabled, this bus drives Video (Y-U-V)

data synchronous to the VID_CLK output.

PIXEL[17:0]

Refer

O

Graphics Pixel Data Bus

toTable toTable

2-3 2-5

This bus drives graphics pixel data synchronous to the PCLK

output.

Revision 3.1

31

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Signal Definitions (Continued)

2.2.5 Power, Ground, and No Connect Signals

BGA

SPGA

Signal Name

Pin No. Pin No.

Type

Description

VOLDET

AC5

AM36

O

Voltage Detect

In early schematic revisions this pin was identified as VOLDET.

However, in the production version this pin is a "no connect" and

should be left disconnected.

VSS

VCC2

VCC3

NC

Refer

toTable toTable

2-3

(Total

of 71)

Refer

GND

PWR

Ground Connection

2-5

(Total

of 50)

Refer

toTable toTable

2-3

(Total

of 32)

Refer

2.9V (nominal) Core Power Connection

3.3V (nominal) I/O Power Connection

2-5

(Total

of 32)

Refer

toTable toTable

2-3

(Total

of 32)

Refer

2-5

(Total

of 18)

--

Q5, X2,

Z2

No Connection

A line designated as NC should be left disconnected.

2.2.6

Internal Test and Measurement Signals

BGA SPGA

Signal Name

Pin No. Pin No.

Type

Description

Float

FLT#

AC2

AJ3

I

Float Outputs force the GXm processor to float all outputs in the

high-impedance state and to enter a power-down state.

RW_CLK

TEST[3:0]

AE6

AL11

O

Raw Clock

This output is the GXm processor clock. This debug signal can

be used to verify clock operation.

B22,

A23,

B21,

C21

D28,

B32,

D26,

A33

SDRAM Test Outputs

These outputs are used for internal debug only.

TCLK

TDI

J2

(PU)

P4

(PU)

I

Test Clock

JTAG test clock.

This pin is internally connected to a 20-kohm pull-up resistor.

Test Data Input

D2

F4

(PU)

JTAG serial test-data input.

This pin is internally connected to a 20-kohm pull-up resistor.

Test Data Output

TDO

F1

J1

O

JTAG serial test-data output.

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32

Revision 3.1

Signal Definitions (Continued)

2.2.6

Internal Test and Measurement Signals

BGA SPGA

Signal Name

Pin No. Pin No.

Type

Description

TMS

TEST

TDP

H1

(PU)

N3

(PU)

I

Test Mode Select

JTAG test-mode select.

This pin is internally connected to a 20-kohm pull-up resistor.

F3

(PD)

J5

(PD)

I

Test

Test-mode input.

This pin is internally connected to a 20-kohm pull-down resistor.

Thermal Diode Positive

E24

D26

F36

E37

O

TDP is the positive terminal of the thermal diode on the die. The

diode is used to do thermal characterization of the device in a

system. This signal works in conjunction with TDN.

TDN

O

Thermal Diode Negative

TDN is the negative terminal of the thermal diode on the die. The

diode is used to do thermal characterization of the device in a

system. This signal works in conjunction with TDP.

Revision 3.1

33

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Signal Definitions (Continued)

2.3 SUBSYSTEM SIGNAL CONNECTIONS

As previously stated, the GXm Integrated Subsystem with

MMX support consists of two chips: the GXm Processor

and the CS5530 I/O companion. Figure 2-4 shows the

signal connections between the processor and the I/O

companion chip.

SYSCLK

SERIALP

IRQ13

GX_CLK

PSERIAL

IRQ13

SMI#

PCLK

DCLK

CRT_HSYNC

CRT_VSYNC

HSYNC

VSYNC

Exclusive

Interconnect

(Note)

PIXEL[17:0]

PIXEL[23:0]

Signals

Not needed if

CRT only (no TFT)

FP_HSYNC

FP_VSYNC

ENA_DISP

VID_VAL

FP_HSYNC

FP_VSYNC

FP_ENA_DISP

VID_VAL

(Do not connect to

any other device)

VID_CLK

VID_DATA[7:0]

VID_RDY

RESET

VID_DATA[7:0]

VID_RDY

CPU_RST

INTR

Geode™ CS5530

I/O Companion

Geode™ GXm

Processor

SUSP#

SUSPA#

AD[31:0]

C/BE[3:0]#

PAR

SUSP#

SUSPA#

AD[31:0]

C/BE[3:0]#

PAR

Nonexclusive

Interconnect

Signals

FRAME#

IRDY#

TRDY#

STOP#

LOCK#

DEVSEL#

PERR#

SERR#

REQ0#

GNT0#

FRAME#

IRDY#

TRDY#

STOP#

LOCK#

DEVSEL#

PERR#

SERR#

REQ#

(May also connect

to other circuitry)

GNT#

Note: Refer to Figure 2-5 for interconnection of these lines.

Figure 2-4. Subsystem Signal Connections

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34

Revision 3.1

Signal Definitions (Continued)

PIXEL17

PIXEL23

PIXEL22

PIXEL21

PIXEL20

PIXEL19

PIXEL18

PIXEL17

PIXEL16

PIXEL15

PIXEL14

PIXEL13

PIXEL12

PIXEL11

PIXEL10

PIXEL9

PIXEL8

PIXEL7

PIXEL6

PIXEL5

PIXEL4

PIXEL3

PIXEL2

PIXEL1

PIXEL0

Geode™ GXm

Processor

Geode™ CS5530

I/O Companion

PIXEL16

PIXEL15

PIXEL14

PIXEL13

PIXEL12

PIXEL11

PIXEL10

PIXEL9

PIXEL8

PIXEL7

PIXEL6

PIXEL5

PIXEL4

PIXEL3

PIXEL2

PIXEL1

PIXEL0

Figure 2-5. PIXEL Signal Connections

Revision 3.1

35

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Signal Definitions (Continued)

2.4 POWER PLANES

Figure 2-6 shows layout recommendations for splitting the

power plane between VCC2 (core: 2.9V) and VCC3 (I/O:

3.3V) volts in the BGA package.

Figure 2-7 shows layout recommendations for splitting the

power plane between VCC2 (core: 2.9V) and VCC3 (I/O:

3.3V) volts for the GXm in the SPGA package.

The illustration assumes there is one power plane, and no

components on the back of the board

3.3V Plane

(VCC3)

26

A

1

A

2.9V Plane

(VCC2)

3.3V Plane

(VCC3)

Geode™ GXm

Processor

352 BGA - Top View

2.9V Plane

(VCC2)

AF

1

26

Legend

3.3V Plane

(VCC3)

= High frequency capacitor

= 220µF, low ESR capacitor

= 3.3V connection

= 2.9V connection

Figure 2-6. BGA Recommended Split Power Plane and Decoupling

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36

Revision 3.1

Signal Definitions (Continued)

3.3V Plane

(VCC3)

1

37

A

2.9V Plane

(VCC2)

Geode™ GXm

Processor

3.3V Plane

(VCC3)

3.3V Plane

(VCC3)

320 SPGA - Top View

2.9V Plane

(VCC2)

AN

1

37

To 2.9V

Regulator

3.3V Plane

(VCC3)

Legend

= High frequency capacitor

= 220 µF, low ESR capacitor

= 3.3V connection

Note: Where signals cross plane splits, it is recommended to include AC

decoupling between planes with 47pF capacitors.

= 2.9V connection

Figure 2-7. SPGA Recommended Split Power Plane and Decoupling

Revision 3.1

37

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3.0 Processor Programming

This section describes the internal operations of the

Geode GXm processor from a programmer’s point of view.

It includes a description of the traditional “core” process-

ing and FPU operations. The integrated function registers

are described at the end of this chapter.

3.1 CORE PROCESSOR INITIALIZATION

The GXm processor is initialized when the RESET signal

is asserted. The processor is placed in real mode and the

registers listed in Table 3-1 are set to their initialized val-

ues. RESET invalidates and disables the CPU cache, and

turns off paging. When RESET is asserted, the CPU ter-

minates all local bus activity and all internal execution.

During the entire time that RESET is asserted, the inter-

nal pipeline is flushed and no instruction execution or bus

activity occurs.

The primary register sets within the processor core

include:

•

Application Register Set

System Register Set

Model Specific Register Set

Floating Point Unit Register Set.

Approximately 150 to 250 external clock cycles after

RESET is deasserted, the processor begins executing

instructions at the top of physical memory (address loca-

tion FFFFFFF0h). The actual time depends on the clock

scaling in use. Also, an additional 2²⁰clock cycles are

needed when self-test is requested.

The initialization of the major registers within in core are

shown in Table 3-1.

The integrated function sets are located in main memory

space and include:

Typically, an intersegment jump is placed at FFFFFFF0h.

This instruction will force the processor to begin execution

in the lowest 1 MB of address space.

•

Internal Bus Interface Unit Register Set

Graphics Pipeline Register Set

Display Controller Register Set

Memory Controller Register Set

Power Management Register Set

The following table, Table 3-1, lists the core registers and

illustrates how they are initialized.

Table 3-1. Initialized Core Register Controls

Register

Register Name

Accumulator

Initialized Contents

Comments

EAX

EBX

ECX

EDX

EBP

ESI

xxxxxxxxh

xxxx 04 [DIR0]h

xxxxxxxxh

00000002h

0000FFF0h

0000h

00000000h indicates self-test passed.

Base

Count

Data

DIR0 = Device ID

Base Pointer

Source Index

Destination Index

Stack Pointer

Extended FLAGS

Instruction Pointer

Extra Segment

Code Segment

Stack Segment

Data Segment

Extra Segment

EDI

ESP

EFLAGS

EIP

See Table 3-4 on page 43 for bit definitions.

ES

Base address set to 00000000h. Limit set to FFFFh.

Base address set to FFFF0000h. Limit set to FFFFh.

Base address set to 00000000h. Limit set to FFFFh.

CS

F000h

SS

0000h

DS

0000h

FS

0000h

GS

0000h

IDTR

GDTR

LDTR

TR

Interrupt Descriptor Table Register Base = 0, Limit = 3FFh

Global Descriptor Table Register

Local Descriptor Table Register

Task Register

xxxx xxxxh

xxxxh

CR0

CR2

CR3

CR4

CCR1

CCR2

CCR3

CCR7

SMAR0

Machine Status Word

Control Register 2

60000010h

xxxxxxxxh

00000000h

00h

See Table 3-7 on page 49 for bit definitions.

See Table 3-11 on page 49 for bit definitions.

See Table 3-11 on page 50 for bit definitions.

See Table 3-11 on page 51 for bit definitions.

Control Register 3

Control Register 4

Configuration Control 1

Configuration Control 2

Configuration Control 3

Configuration Control 7

SMM Address 0

00h

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38

Revision 3.1

Processor Programming (Continued)

Table 3-1. Initialized Core Register Controls (Continued)

Register

Register Name

SMM Address 1

Initialized Contents

00h

Comments

SMAR1

SMAR2

DIR0

See Table 3-11 on page 50 for bit definitions.

SMM Address 2 / SMAR Size

Device Identification 0

00h

4xh

Device ID and reads back initial CPU clock-speed set-

ting. See Table 3-11 on page 51 for bit definitions.

DIR1

DR7

Device Identification 1

Debug Register 7

xxh

Stepping and Revision ID (RO). See Table 3-11 on

page 51 for bit definitions.

00000400h

See Table 3-13 on page 53 for bit definitions.

Note: x = Undefined value

3.2 INSTRUCTION SET OVERVIEW

The GXm processor instruction set can be divided into

nine types of operations:

Operand lengths of 8, 16, 32 or 48 bits are supported as

well as 64 or 80 bits associated with floating-point instruc-

tions. Operand lengths of 8 or 32 bits are generally used

when executing code written for 386- or 486-class (32-bit

code) processors. Operand lengths of 8 or 16 bits are

generally used when executing existing 8086 or 80286

code (16-bit code). The default length of an operand can

be overridden by placing one or more instruction prefixes

in front of the opcode. For example, the use of prefixes

allows a 32-bit operand to be used with 16-bit code or a

16-bit operand to be used with 32-bit code.

•

Arithmetic

Bit Manipulation

Shift/Rotate

String Manipulation

Control Transfer

Data Transfer

Floating Point

High-Level Language Support

Operating System Support

Section 9.1 “General Instruction Set Format” on page 202

contains the clock count table that lists each instruction in

the CPU instruction set. Included in the table are the

associated opcodes, execution clock counts, and effects

on the EFLAGS register.

GXm processor instructions operate on as few as zero

operands and as many as three operands. An NOP

instruction (no operation) is an example of a zero-operand

instruction. Two-operand instructions allow the specifica-

tion of an explicit source and destination pair as part of

the instruction. These two-operand instructions can be

divided into ten groups according to operand types:

3.2.1 Lock Prefix

The LOCK prefix may be placed before certain instruc-

tions that read, modify, then write back to memory. The

PCI will not be granted access in the middle of locked

instructions. The LOCK prefix can be used with the follow-

ing instructions only when the result is a write operation to

memory.

•

Register to Register

Register to Memory

Memory to Register

Memory to Memory

Register to I/O

I/O to Register

Memory to I/O

I/O to Memory

Immediate Data to Register

Immediate Data to Memory

•

Bit Test Instructions (BTS, BTR, BTC)

Exchange Instructions (XADD, XCHG, CMPXCHG)

One-Operand Arithmetic and Logical Instructions

(DEC, INC, NEG, NOT)

An operand can be held in the instruction itself (as in the

case of an immediate operand), in one of the processor’s

registers or I/O ports, or in memory. An immediate oper-

and is fetched as part of the opcode for the instruction.

•

Two-Operand Arithmetic and Logical Instructions

(ADC, ADD, AND, OR, SBB, SUB, XOR).

An invalid opcode exception is generated if the LOCK pre-

fix is used with any other instruction or with one of the

instructions above when no write operation to memory

occurs (for example, when the destination is a register).

Revision 3.1

39

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Processor Programming (Continued)

3.3 REGISTER SETS

The accessible registers in the processor are grouped into

three sets:

3.3.1.1 General Purpose Registers

The General Purpose Registers are divided into four data

registers, two pointer registers, and two index registers as

shown in Table 3-2.

1) The Application Register Set contains the registers

frequently used by application programmers. Table 3-

2 shows the general purpose, segment, the instruc-

tion pointer and the EFLAGS Registers.

The Data Registers are used by the applications pro-

grammer to manipulate data structures and to hold the

results of logical and arithmetic operations. Different por-

tions of general data registers can be addressed by using

different names.

2) The System Register Set contains the registers typi-

cally reserved for operating-systems programmers:

control, system address, debug, configuration, and

test registers.

An “E” prefix identifies the complete 32-bit register. An “X”

suffix without the “E” prefix identifies the lower 16 bits of

the register.

3) The Model Specific Register (MSR) Set is used to

monitor the performance of the processor or a

specific component within the processor. The model

specific register set has one 64-bit register called the

Time Stamp Counter.

The lower two bytes of a data register are addressed with

an “H” suffix (identifies the upper byte) or an “L” suffix (iden-

tifies the lower byte). These _L and _H portions of the

data registers act as independent registers. For example,

if the AH register is written to by an instruction, the AL reg-

ister bits remain unchanged.

Each of these register sets are discussed in detail in the

subsections that follow. Additional registers to support

integrated GXm processor subsystems are described in

Section 4.1 “Integrated Functions Programming Interface”

on page 92.

The Pointer and Index Registers are listed below.

SI or ESI

Source Index

Destination Index

Stack Pointer

Base Pointer

3.3.1 Application Register Set

DI or EDI

SP or ESP

BP or EBP

The Application Register Set consists of the registers most

often used by the applications programmer. These regis-

ters are generally accessible, although some bits in the

EFLAGS register are protected.

These registers can be addressed as 16- or 32-bit registers,

with the “E” prefix indicating 32 bits. The pointer and index

registers can be used as general purpose registers; how-

ever, some instructions use a fixed assignment of these

registers. For example, repeated string operations always

use ESI as the source pointer, EDI as the destination

pointer, and ECX as a counter. The instructions that use

fixed registers include multiply and divide, I/O access,

string operations, stack operations, loop, variable shift and

rotate, and translate instructions.

The General Purpose Register contents are frequently

modified by instructions and typically contain arithmetic

and logical instruction operands.

In real mode, Segment Registers contain the base

address for each segment. In protected mode, the seg-

ment registers contain segment selectors. The segment

selectors provide indexing for tables (located in memory)

that contain the base address for each segment, as well

as other memory addressing information.

The GXm processor implements a stack using the ESP

register. This stack is accessed during the PUSH and

POP instructions, procedure calls, procedure returns,

interrupts, exceptions, and interrupt/exception returns.

The GXm processor automatically adjusts the value of the

ESP during operations that result from these instructions.

The Instruction Pointer Register points to the next

instruction that the processor will execute. This register is

automatically incremented by the processor as execution

progresses.

The EFLAGS Register contains control bits used to

reflect the status of previously executed instructions. This

register also contains control bits that affect the operation

of some instructions.

The EBP register may be used to refer to data passed on

the stack during procedure calls. Local data may also be

placed on the stack and accessed with BP. This register

provides a mechanism to access tack data in high-level

languages.

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Revision 3.1

Processor Programming (Continued)

Table 3-2. Application Register Set

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

General Purpose Registers

9

8

7

6

5

4

3

2

1

0

AX

AH

AL

BL

CL

DL

EAX (Extended A Register)

BX

CX

DX

BH

EBX (Extended B Register)

CH

ECX (Extended C Register)

DH

EDX (Extended D Register)

SI (Source Index)

ESI (Extended Source Index)

DI (Destination Index)

BP (Base Pointer)

SP (Stack Pointer)

EDI (Extended Destination Index)

EBP (Extended Base Pointer)

ESP (Extended Stack Pointer)

Segment (Selector) Registers

CS (Code Segment)

SS (Stack Segment)

DS (D Data Segment)

ES (E Data Segment)

FS (F Data Segment)

GS (G Data Segment)

Instruction Pointer and EFLAGS Registers

EIP (Extended Instruction Pointer)

ESP (Extended FLAGS Register)

Revision 3.1

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Processor Programming (Continued)

3.3.1.2 Segment Registers

The active segment register is selected according to the

rules listed in Table 3-3 and the type of instruction being

currently processed. In general, the DS register selector is

used for data references. Stack references use the SS

register, and instruction fetches use the CS register. While

some of these selections may be overridden, instruction

fetches, stack operations, and the destination write opera-

tion of string operations cannot be overridden. Special

segment-override instruction prefixes allow the use of

alternate segment registers. These segment registers

include the ES, FS, and GS registers.

The 16-bit segment registers, part of the main memory

addressing mechanism, are described in Section 3.5 “Off-

set, Segment, and Paging Mechanisms” on page 61. The

six segment registers are:

CS

DS

SS

ES

FS

GS

-

Code Segment

Data Segment

Stack Segment

Extra Segment

Additional Data Segment

3.3.1.3 Instruction Pointer Register

The segment registers are used to select segments in

main memory. A segment acts as private memory for dif-

ferent elements of a program such as code space, data

space, and stack space.

The Instruction Pointer (EIP) Register contains the off-

set into the current code segment of the next instruction to

be executed. The register is normally incremented by the

length of the current instruction with each instruction exe-

cution unless it is implicitly modified through an interrupt,

exception, or an instruction that changes the sequential

execution flow (for example JMP and CALL).

There are two segment mechanisms, one for real and vir-

tual 8086 operating modes and one for protective mode.

Initialization and transition to protective mode is described

in Section 3.13.4 “Initialization and Transition to Protected

Mode” on page 87. The segment mechanisms are

described in Section 3.7 “Descriptors and Segment Mech-

anisms” on page 62.

Table 3-3 illustrates the code segment selection rules.

Table 3-3. Segment Register Selection Rules

Implied (Default)

Segment-Override

Prefix

Type of Memory Reference

Segment

Code Fetch

CS

SS

ES

DS

None

Destination of PUSH, PUSHF, INT, CALL, PUSHA instructions

Source of POP, POPA, POPF, IRET, RET instructions

Destination of STOS, MOVS, REP STOS, REP MOVS instructions

None

Other data references with effective address using base registers of:

EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP

CS, ES, FS, GS, SS

SS

CS, DS, ES, FS, GS

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Revision 3.1

Processor Programming (Continued)

3.3.1.4 EFLAGS Register

The EFLAGS Register contains status information and

controls certain operations on the GXm processor. The

lower 16 bits of this register are referred to as the

EFLAGS register that is used when executing 8086 or

80286 code. Table 3-4 gives the bit formats for the

EFLAGS Register

Table 3-4. EFLAGS Register

Bit

Name

Flag Type

Description

Reserved: Set to 0.

31:22

21

RSVD

ID

--

System

Identification Bit: The ability to set and clear this bit indicates that the CPUID instruction is sup-

ported. The ID can be modified only if the CPUID bit in CCR4 (Index E8h[7]) is set.

20:19

18

RSVD

AC

--

Reserved: Set to 0.

System

Alignment Check Enable: In conjunction with the AM flag (bit 18) in CR0, the AC flag deter-

mines whether or not misaligned accesses to memory cause a fault. If AC is set, alignment faults

are enabled.

17

16

VM

RF

System

Debug

Virtual 8086 Mode: If set while in protected mode, the processor switches to virtual 8086 opera-

tion handling segment loads as the 8086 does, but generating exception 13 faults on privileged

opcodes. The VM bit can be set by the IRET instruction (if current privilege level

is 0) or by task switches at any privilege level.

Resume Flag: Used in conjunction with debug register breakpoints. RF is checked at instruction

boundaries before breakpoint exception processing. If set, any debug fault is ignored on the next

instruction.

15

14

RSVD

NT

--

Reserved: Set to 0.

System

Nested Task: While executing in protected mode, NT indicates that the execution of the current

task is nested within another task.

13:12

IOPL

System

Arithmetic

Control

I/O Privilege Level: While executing in protected mode, IOPL indicates the maximum current

privilege level (CPL) permitted to execute I/O instructions without generating an exception 13

fault or consulting the I/O permission bit map. IOPL also indicates the maximum CPL allowing

alteration of the IF bit when new values are popped into the EFLAGS register.

11

OF

Overflow Flag: Set if the operation resulted in a carry or borrow into the sign bit of the result but

did not result in a carry or borrow out of the high-order bit. Also set if the operation resulted in a

carry or borrow out of the high-order bit but did not result in a carry or borrow into the sign bit of

the result.

10

DF

Direction Flag: When cleared, DF causes string instructions to auto-increment (default) the

appropriate index registers (ESI and/or EDI). Setting DF causes auto-decrement of the index

registers to occur.

9

8

IF

System

Debug

Interrupt Enable Flag: When set, maskable interrupts (INTR input pin) are acknowledged and

serviced by the CPU.

TF

Trap Enable Flag: Once set, a single-step interrupt occurs after the next instruction completes

execution. TF is cleared by the single-step interrupt.

7

6

5

4

SF

ZF

Arithmetic

--

Sign Flag: Set equal to high-order bit of result (0 indicates positive, 1 indicates negative).

Zero Flag: Set if result is zero; cleared otherwise.

Reserved: Set to 0.

RSVD

AF

Arithmetic

Auxiliary Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) bit position 3

of the result occurs; cleared otherwise.

3

2

RSVD

PF

--

Reserved: Set to 0.

Arithmetic

Parity Flag: Set when the low-order 8 bits of the result contain an even number of ones; other-

wise PF is cleared.

1

0

RSVD

CF

Reserved: Set to 1.

Arithmetic

Carry Flag: Set when a carry out of (addition) or borrow into (subtraction) the most significant bit

of the result occurs; cleared otherwise.

Revision 3.1

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Processor Programming (Continued)

3.3.2 System Register Set

Table 3-5. System Register Set

The system register set, shown in Table 3-5, consists of

registers not generally used by application programmers.

These registers are typically employed by system level

programmers who generate operating systems and mem-

ory management programs. Associated with the system

register set are certain tables and segments which are

listed in Table 3-5.

Width

(Bits)

Group

Control

Name

CR0

Function

System Control

Register

32

Registers

CR2

CR3

Page Fault Linear

Address Register

Page Directory Base

Register

The Control Registers control certain aspects of the

GXm processor such as paging, coprocessor functions,

and segment protection.

CR4

GDT

IDT

Time Stamp Counter

32

Descriptor

Tables

General Descriptor Table

The Descriptor Tables hold descriptors that manage

memory segments and tables, interrupts and task switch-

ing. The tables are defined by corresponding registers.

Interrupt Descriptor

Table

LDT

Local Descriptor Table

GDT Register

16

32

16

The two Task State Segments Tables defined by TSS reg-

ister are used to save and load the computer state when

switching tasks.

Descriptor

Table

Registers

GDTR

IDTR

LDTR

TSS

IDT Register

LDT Register

The Configuration Registers are used to define the

GXm CPU setup including cache management.

Task State

Segment and

Registers

Task State Segment

Tables

TR

TSS Register Setup

16

8

The ID registers allow BIOS and other software to identify

the specific CPU and stepping. System Management

Mode (SMM) control information is stored in the SMM reg-

isters.

Configuration CCRn

Registers

Configuration Control

Registers

ID

DIRn

Device Identification

Registers

8

Registers

The Debug Registers provide debugging facilities for the

GXm processor and enable the use of data access break-

points and code execution breakpoints.

SMM

Registers

SMARn

SMHRn

SMM Address Region

Registers

SMM Header Addresses

8

The Test Registers provide a mechanism to test the con-

tents of both the on-chip 16 KB cache and the Translation

Lookaside Buffer (TLB). The TLB is used as a cache for

the tables that are used in to translate linear addresses to

physical addresses while paging is enabled.

Performance PCR0

Registers

Performance Control

Register

Debug

Registers

DR0

DR1

DR2

DR3

Linear Breakpoint

Address 0

32

Linear Breakpoint

Address 1

Table 3-5 lists the system register sets along with their

size and function.

Linear Breakpoint

Address 2

Linear Breakpoint

Address 3

DR6

DR7

TR3

TR4

TR5

TR6

TR7

Breakpoint Status

Breakpoint Control

Cache Test

32

Test

Registers

Cache Test

TLB Test Control

TLB Test Status

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Revision 3.1

Processor Programming (Continued)

3.3.2.1 Control Registers

the general state of the CPU. The lower 16 bits of CR0 are

referred to as the Machine Status Word (MSW).

A map of the Control Registers (CR0, CR2, CR3, and

CR4) is shown in Table 3-6 and the bit definitions are given

in Table 3-7. (These registers should not be confused with

the CRRn registers.) The CR0 register contains system

control bits which configure operating modes and indicate

When operating in real mode, any program can read and

write the control registers. In protected mode, however,

only privilege level 0 (most-privileged) programs can read

and write these registers.

Table 3-6. Control Registers Map

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

CR4 Register

Control Register 4 (R/W)

RSVD

T

S

C

RSVD

CR3 Register

CR2 Register

CR1 Register

CR0 Register

Control Register 3 (R/W)

PDBR (Page Directory Base Register)

RSVD

0

RSVD

Control Register 2 (R/W)

PFLA (Page Fault Linear Address)

Control Register 1 (R/W)

RSVD

Control Register 0 (R/W)

P

G

C

D

N

W

RSVD

A

M

R

S

V

D

W

P

RSVD

N

E

R

S

V

D

T

S

E

M

P

E

Machine Status Word (MSW)

Table 3-7. CR4-CR0 Bit Definitions

Bit

Name Description

CR4 Register

Control Register 4 (R/W)

31:3

2

RSVD Reserved: Set to 0 (always returns 0 when read).

TSC

Time Stamp Counter Instruction:

If = 1 RDTSC instruction enabled for CPL = 0 only; reset state.

If = 0 RDTSC instruction enabled for all CPL states.

1:0

RSVD Reserved: Set to 0 (always returns 0 when read).

Control Register 3 (R/W)

CR3 Register

31:12

11:0

PDBR Page Directory Base Register: Identifies page directory base address on a 4 KB page boundary.

RSVD Reserved: Set to 0.

CR2 Register

Control Register 2 (R/W)

31:0

PFLA

Page Fault Linear Address: With paging enabled and after a page fault, PFLA contains the linear address of the

address that caused the page fault.

CR1 Register

Control Register 1 (R/W)

31:0

RSVD Reserved

CR0 Register

Control Register 0 (R/W)

31

PG

Paging Enable Bit: If PG = 1 and protected mode is enabled (PE = 1), paging is enabled. After changing the

state of PG, software must execute an unconditional branch instruction (e.g., JMP, CALL) to have the change

take effect.

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Processor Programming (Continued)

Table 3-7. CR4-CR0 Bit Definitions (Continued)

Bit

Name Description

30

CD

Cache Disable: If CD = 1, no further cache line fills occur. However, data already present in the cache continues

to be used if the requested address hits in the cache. Writes continue to update the cache and cache invalida-

tions due to inquiry cycles occur normally. The cache must also be invalidated with a WBINVD instruction to com-

pletely disable any cache activity.

29

NW

Not Write-Through: If NW = 1, the on-chip cache operates in write-back mode. In write-back mode, writes are

issued to the external bus only for a cache miss, a line replacement of a modified line, execution of a locked

instruction, or a line eviction as the result of a flush cycle. If NW = 0, the on-chip cache operates in write-through

mode. In write-through mode, all writes (including cache hits) are issued to the external bus. This bit cannot be

changed if LOCK_NW = 1 in CCR2.

18

16

5

AM

WP

NE

Alignment Check Mask: If AM = 1, the AC bit in the EFLAGS register is unmasked and allowed to enable align-

ment check faults. Setting AM = 0 prevents AC faults from occurring.

Write Protect: Protects read-only pages from supervisor write access. WP = 0 allows a read-only page to be

written from privilege level 0-2. WP = 1 forces a fault on a write to a read-only page from any privilege level.

Numerics Exception: NE = 1 to allow FPU exceptions to be handled by interrupt 16. NE = 0 if FPU exceptions

are to be handled by external interrupts.

4

3

RSVD Reserved: Do not attempt to modify, always 1.

TS

Task Switched: Set whenever a task switch operation is performed. Execution of a floating point instruction with

TS = 1 causes a DNA fault. If MP = 1 and TS = 1, a WAIT instruction also causes a DNA fault.

2

1

EM

MP

Emulate Processor Extension: If EM = 1, all floating point instructions cause a DNA fault 7.

Monitor Processor Extension: If MP = 1 and TS = 1, a WAIT instruction causes Device Not Available (DNA)

fault 7. The TS bit is set to 1 on task switches by the CPU. Floating point instructions are not affected by the state

of the MP bit. The MP bit should be set to one during normal operations.

0

PE

Protected Mode Enable: Enables the segment based protection mechanism. If PE = 1, protected mode is

enabled. If PE = 0, the CPU operates in real mode and addresses are formed as in an 8086-style CPU. Refer to

Section 3.13 “Protection” on page 86.

Table 3-8. Effects of Various Combinations of EM, TS, and MP Bits

CR0[3:1]

EM

Instruction Type

TS

MP

WAIT

ESC

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Execute

Fault 7

Execute

Fault 7

Execute

Fault 7

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Revision 3.1

Processor Programming (Continued)

3.3.2.2 Configuration Registers

Each data transfer through I/O Port 23h must be preceded

by a register index selection through I/O Port 22h; other-

wise, subsequent I/O Port 23h operations are directed off-

chip and produce external I/O cycles.

The configuration registers listed in Table 3-9 are CPU

registers and are selected by register index numbers. The

registers are accessed through I/O memory locations 22h

and 23h. Registers are selected for access by writing an

index number to I/O Port 22h using an OUT instruction

prior to transferring data through I/O Port 23h.

If MAPEN, bit 4 of CCR3 (Index C3h[4]) = 0, external I/O

cycles occur if the register index number is outside the

range C0h-CFh, FEh, and FFh. The MAPEN bit should

remain 0 during normal operation to allow system regis-

ters located at I/O Port 22h to be accessed.

Table 3-9. Configuration Register Summary

Access Default

Reference

Index

Type

Name

Controlled By*

Value

(Bit Formats)

C1h

C2h

C3h

E8h

EBh

20h

B0h

B1h

B2h

B3h

B8h

B9h

R/W

CCR1 — Configuration Control 1

CCR2 — Configuration Control 2

CCR3 — Configuration Control 3

CCR4 — Configuration Control 4

CCR7 — Configuration Control 7

PCR — Performance Control

SMI_LOCK

--

00h

85h

00h

07h

xxh

00h

Table 3-11 on page 49

Table 3-11 on page 50

Table 4-1 on page 92

Table 5-5 on page 173

SMI_LOCK

MAPEN

--

MAPEN

--

SMHR0 — SMM Header Address 0

SMHR1 — SMM Header Address 1

SMHR2 — SMM Header Address 2

SMHR3 — SMM Header Address 3

GCR — Graphics Control Register

VGACTL — VGA Control Register

VGAM0 — VGA Mask Register

BAh-

BDh

--

CDh

CEh

CFh

FEh

FFh

R/W

RO

SMAR0 — SMM Address 0

SMAR1 — SMM Address 1

SMAR2 — SMM Address 2

DIR0 — Device ID 0

SMI_LOCK

00h

4xh

xxh

Table 3-11 on page 51

SMI_LOCK

--

RO

DIR1 — Device ID 1

Note: *MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3).

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Processor Programming (Continued)

Table 3-10. Configuration Register Map

Register

(Index)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Control Registers

CCR1 (C1h)

RSVD

SMAC

USE_SMI

RSVD

CCR2 (C2h)

CCR3 (C3h)

CCR4 (E8h)

CCR7 (EBh)

PCR (20h)

USE_SUSP

LSS_34

RSVD

WT1

SUSP_HLT

LOCK_NW

RSVD

LSS_23

LSS_12

RSVD

MAPEN

DTE_EN

RSVD

NMI_EN

IORT1

RSVD

SMI_LOCK

IORT0

CPUID

SMI_NEST

MEM_BYP

RSVD

IORT2

NMI

EMMX

LSSER

Device ID Registers

DIR0 (FEh)

DIR1 (FFh)

DID3

SID3

DID2

SID2

DID1

SID1

DID0

SID0

RSVD

RID3

CLKMODE1

RID2

RSVD

RID1

CLMODE0

RID0

SMM Base Header Address Registers

SMAR0 (CDh)

SMAR1 (CEh)

SMAR2 (CFh)

SMHR0 (B0h)

SMHR1 (B1h)

SMHR2 (B2h)

SMHR3 (B3h)

A31

A23

A15

A7

A30

A22

A14

A6

A29

A21

A13

A5

A28

A20

A12

A4

A27

A19

SIZE3

A3

A26

A18

SIZE2

A2

A25

A17

SIZE1

A1

A24

A16

SIZE0

A0

A15

A23

A31

A14

A22

A30

A13

A21

A29

A12

A20

A28

A11

A19

A27

A10

A18

A26

A9

A8

A17

A26

A16

A24

Graphics/VGA Related Registers

GCR (B8h)

RSVD

Scratchpad Size

Base Address Code

VGACTL (B9h)

RSVD

Enable SMI Enable SMI Enable SMI

for VGA

memory

B8000h to

BFFFFh

for VGA

memory

B0000h to

B7FFFh

for VGA

memory

A0000h to

AFFFFh

VGAM0 (BAh)

VGAM1 (BBh)

VGAM2 (BCh)

VGAM3 (BDh)

VGA Mask Register Bits [7:0]

VGA Mask Register Bits [15:8]

VGA Mask Register Bits [23:16]

VGA Mask Register Bits [31:24]

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Revision 3.1

Processor Programming (Continued)

Table 3-11. Configuration Registers

Bit

Name

Description

Index C1h

CCR1 — Configuration Control Register 1 (R/W)

Reserved: Set to 0.

Default Value = 00h

7:3

2:1

RSVD

SMAC

System Management Memory Access:

If = 00: SMM is disabled.

If = 01: SMI# pin is active to enter SMM. SMINT instruction is inactive.

If = 10: SMM is disabled.

If = 11: SMINT instruction is active to enter SMM. SMI# pin is inactive.

Note: SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write this bit.

Reserved: Set to 0.

0

RSVD

Note: Bits 1 and 2 are cleared to zero at reset.

Index C2h

CCR2 — Configuration Control Register 2 (R/W)

Default Value = 00h

7

USE_SUSP

Enable Suspend Pins:

If = 1: SUSP# input and SUSPA# output are enabled.

If = 0: SUSP# input is ignored.

6

5

4

RSVD

WT1

Reserved: This is a test bit that must be set to 0.

Reserved: Set to 0.

Write-Through Region 1:

If = 1: Forces all writes to the address region between 640 KB to 1 MB that hit in the on-chip cache

to be issued on the external bus.

3

2

SUSP_HLT

LOCK_NW

Suspend on HALT:

If = 1: CPU enters suspend mode following execution of a HALT instruction.

Lock NW Bit:

If = 1: Prohibits changing the state of the NW bit (CR0[29]) (refer to Table 3-7 on page 45).

Set to 1 after setting NW.

1:0

RSVD

Reserved: Set to 0.

Note: All bits are cleared to zero at reset.

Index C3h

CCR3 — Configuration Control Register 3 (R/W)

Load/Store Serialize 3 GB to 4 GB:

Default Value = 00h

7

6

5

4

LSS_34

LSS_23

LSS_12

MAPEN

If = 1: Strong R/W ordering imposed in address range C0000000h to FFFFFFFFh:

Load/Store Serialize 2 GB to 3 GB:

If = 1: Strong R/W ordering imposed in address range 80000000h to BFFFFFFFh:

Load/Store Serialize 1 GB to 2 GB:

If = 1: Strong R/W ordering imposed in address range 40000000h to 7FFFFFFFh

Map Enable:

If = 1: All configuration registers are accessible. All accesses to Port 22h are trapped.

If = 0: Only configuration registers Index C1h through CFh, FEh, FFh (CCRn, SMAR, DIRn) are

accessible. Other configuration registers (including PCR, SMHRn, GCR, VGACTL, VGAM0) are not

accessible.

3

SUSP_SMM_EN Enable Suspend in SMM Mode:

0 = SUSP# ignored in SMM mode.

1 = SUSP# recognized in SMM mode.

2

1

RSVD

Reserved: Set to 0.

NMI_EN

NMI Enable:

If = 1: NMI is enabled during SMM.

If = 0: NMI is not recognized during SMM.

Note: SMI_LOCK (CCR3[0]) must = 0 or the CPU must be in SMI mode to write to this bit.

0

SMI_LOCK

SMM Register Lock:

If = 1: SMM Address Region Register (SMAR[31:0]), SMAC (CCR1[2]), USE_SMI (CCR1[1])

cannot be modified unless in SMM routine. Once set, SMI_LOCK can only be cleared by asserting

the RESET pin.

Note: All bits are cleared to zero at reset.

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Processor Programming (Continued)

Table 3-11. Configuration Registers (Continued)

Bit

Name

Description

Index E8h

CCR4 — Configuration Control Register 4 (R/W)

Enable CPUID Instruction:

Default Value = 85h

7

CPUID

If = 1: The ID bit in the EFLAGS register to be modified and execution of the CPUID instruction

occurs as documented in Table 9-2 on page 202.

If = 0: The ID bit can not be modified and execution of the CPUID instruction causes an invalid

opcode exception.

6

5

SMI_NEST

SMI Nest:

If = 1: SMI interrupts can occur during SMM mode. SMI handlers can optionally set SMI_NEST high

to allow higher-priority SMI interrupts while handling the current event

FPU_FAST_EN

FPU Fast Mode Enable:

If = 0: Disable FPU Fast Mode

If = 1: Enable FPU Fast Mode.

4

3

DTE_EN

MEM_BYP

IORT(2:0)

Directory Table Entry Cache:

If = 1: Enables directory table entry to be cached.

Cleared to 0 at reset.

Memory Read Bypassing:

If = 1: Enables memory read bypassing.

Cleared to 0 at reset.

2:0

I/O Recovery Time: Specifies the minimum number of bus clocks between I/O accesses:

000 = No clock delay

001 = 2-clock delay

010 = 4-clock delay

011 = 8-clock delay

100 = 16-clock delay

101 = 32-clock delay (default value after reset)

110 = 64-clock delay

111 = 128-clock delay

Cleared to 0 at reset.

Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.

Index EBh

CCR7 — Configuration Control Register 7 (R/W)

Default Value = 00h

7:3

2

RSVD

NMI

Reserved: Set to 0.

Generate NMI:

0 = Do nothing

1 = Generate NMI

In order to generate multiple NMIs, this bit must be set to zero between each setting of 1.

Reserved: Set to 0.

1

0

RSVD

EMMX

Extended MMX Instructions Enable:

If = 1: extended MMX instructions are enabled

Index 20h

PCR — Performance Control Register (R/W)

Default Value = 07h

7

LSSER

Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memory-

mapped I/O devices operating outside of the address range 640K to 1M will operate correctly. For

memory accesses above 1 GB, refer to CCR3[7:5] (LSS_34, LSS_23, LSS_12.)

If = 1: All memory read and write operations will occur in execution order (load/store serializing

enabled, reordering disabled).

If = 0: Memory reads and write can be reordered for optimum performance (load/store serializing

disabled, reordering enabled).

Memory accesses in the address range 640K to 1M will always be issued in execution order.

6

5

RSVD

Reserved: Set to 0.

Reserved: This is a test bit that must be set to 0.

Reserved: Set to 0.

4:0

Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.

Index B0h, B1h, B2h, B3h

SMHR — SMI Header Address Register (R/W)

Default Value = xxh

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Table 3-11. Configuration Registers (Continued)

Bit

Name

Description

Index

SMHR Bits

SMM Header Address Bits [A31:0]: SMHR address bits [31:0] contain the physical base address

for the SMM header space. For example, bits [31:24] correspond with Index B3h

Refer to Section 3.11.4 “SMM Configuration Registers” on page 80 for more information.

B3h

B2h

B1h

B0h

A[31:24]

A[23:16]

A[15:12]

A[7:0]

Note: MAPEN (CCR3[4]) must = 1 to read or write to this register.

Index CDh, CEh, CFh SMAR — SMM Address Region/Size Register (R/W)

Default Value = 00h

Index

SMAR Bits

SMM Address Region Bits [A31:A12]: SMAR address bits [31:12] contain the base address for

the SMM region.

Bits [31:24] correspond with Index CDh

Bits [23:16] correspond with Index CEh

Bits [15:12] correspond with Index CFh[7:4]

CDh

CEh

CFh[7:4]

A[31:24]

A[23:16]

A[15:12]

Index CFh allows simultaneous access to SMAR address regions bits SMAR[15:12] and size code

bits SIZE[3:0]. During access, the upper 4-bits of Port 23h hold SMAR[15:12].

Refer to Section 3.11.4 “SMM Configuration Registers” on page 80 for more information.

CFh[3:0]

SIZE[3:0]

SMM Region Size Bits [3:0]: SIZE bits contain the size code for the SMM region. During access

the lower 4-bits of port 23 hold SIZE[3:0]. Index CFh allows simultaneous access to SMAR address

regions bits SMAR[15:12] (see above) and size code bits.

0000 = SMM Disabled

0001 = 4 KB

0010 = 8 KB

0011 = 16 KB

0001)

0100 = 32 KB

0101 = 64 KB

0110 = 128 KB

0111 = 256 KB

1000 = 512 KB

1001 = 1 MB

1010 = 2 MB

1011 = 4 MB

1100 = 8 MB

1101 = 16 MB

1110 = 32 MB

1111 = 4 KB (same as

Note: SMI_LOCK (CCR3[0]) must = 0, or the CPU must be in SMI mode, to write these registers/bits.

Index FEh

DIR0 — Device Identification Register 0 (RO)

Default Value = 4xh

7:4

3:0

DID[3:0]

Device ID (Read Only): Identifies device as GXm processor.

MULT[3:0]

Core Multiplier (Read Only) — Identifies the core multiplier set by the CLKMODE[2:0] pins (see

signal descriptions page 21)

If DIR1 (Index FFh) is 30h-4Fh then MULT[3:0]:

0000 = SYSCLK multiplied by 4 (Test mode only)

0001 = SYSCLK multiplied by 6

0010 = SYSCLK multiplied by 4 (Test mode only)

0011 = SYSCLK multiplied by 6

0100 = SYSCLK multiplied by 7

0101 = SYSCLK multiplied by 8

0110 = SYSCLK multiplied by 7

0111 = SYSCLK multiplied by 5

1xxx = Reserved

If DIR1 (Index FFh) is 50h or greater then MULT[3:0]:

0000 = SYSCLK multiplied by 4 (Test mode only)

0001 = SYSCLK multiplied by 10

0010 = SYSCLK multiplied by 4 (Test mode only)

0011 = SYSCLK multiplied by 6

0100 = SYSCLK multiplied by 9

0101 = SYSCLK multiplied by 5

0110 = SYSCLK multiplied by 7

0111 = SYSCLK multiplied by 8

1xxx = Reserved

Index FFh

DIR1 -- Device Identification Register 1 (RO)

Default Value = xxh

7:0

DIR1

Device Identification Revision (Read Only) — DIR1 indicates device revision number.

If DIR1 is 30h-33h = GXm processor revision 1.0 - 2.3

If DIR1 is 34h-4Fh = GXm processor revision 2.4 - 3.x

If DIR1 is 50h or greater = GXm processor revision 5.0 - 5.4..

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Processor Programming (Continued)

3.3.2.3 Debug Registers

The Debug Address Registers (DR0-DR3) each contain

the linear address for one of four possible breakpoints.

Each breakpoint is further specified by bits in the Debug

Control Register (DR7). For each breakpoint address in

DR0-DR3, there are corresponding fields L, R/W, and

LEN in DR7 that specify the type of memory access asso-

ciated with the breakpoint.

Six debug registers (DR0-DR3, DR6 and DR7) support

debugging on the GXm processor. Memory addresses

loaded in the debug registers, referred to as “breakpoints,”

generate a debug exception when a memory access of

the specified type occurs to the specified address. A

breakpoint can be specified for a particular kind of mem-

ory access such as a read or write operation. Code and

data breakpoints can also be set allowing debug excep-

tions to occur whenever a given data access (read or write

operation) or code access (execute) occurs. The size of

the debug target can be set to 1, 2, or 4 bytes. The debug

registers are accessed through MOV instructions that can

be executed only at privilege level 0 (real mode is always

privilege level 0).

The R/W field can be used to specify instruction execution

as well as data access breakpoints. Instruction execution

breakpoints are always taken before execution of the

instruction that matches the breakpoint. The Debug Reg-

isters are mapped in Table 3-12

Table 3-12. Debug Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DR7 Register

Debug Control Register 7 (R/W)

LEN3 R/W3 LEN2 R/W2 LEN1 R/W1 LEN0 R/W0

0

G

D

0

1

0

G

3

L

3

G

2

L

2

G

1

L

1

G

0

L0

DR6 Register

Debug Status Register 6 (RO)

0

B

T

B

S

0

1

B3 B2 B1 B0

DR3 Register‘

DR2 Register

DR1 Register

DR0 Register

Debug Address Register 3 (R/W))

Breakpoint 3 Linear Address

Debug Address Register 2 (R/W)

Breakpoint 2 Linear Address

Debug Address Register 1 (R/W)

Breakpoint 1 Linear Address

Debug Address Register 0 (R/W)

Breakpoint 0 Linear Address

Note: All bits marked as 0 or 1 are reserved and should not be modified.

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Processor Programming (Continued)

The Debug Status Register (DR6) reflects conditions that

were in effect at the time the debug exception occurred.

The contents of the DR6 register are not automatically

cleared by the processor after a debug exception occurs,

and therefore should be cleared by software at the appro-

priate time. Table 3-13 lists the field definitions for the DR6

and DR7 registers.

Code execution breakpoints may also be generated by

placing the breakpoint instruction (INT3) at the location

where control is to be regained. The single-step feature

may be enabled by setting the TF flag (bit 8) in the

EFLAGS register. This causes the processor to perform a

debug exception after the execution of every instruction.

Debug Registers 6 and 7 are shown in Table 3-13.

Table 3-13. DR7 and DR6 Bit Definitions

Number

of Bits

Field(s)

Description

DR7 Register

Debug Control Register 7 (R/W)

R/Wn

2

Applies to the DRn breakpoint address register:

00 = Break on instruction execution only

01 = Break on data write operations only

10 = Not used

11 = Break on data reads or write operations.

LENn

Applies to the DRn breakpoint address register:

00 = One-byte length

01 = Two-byte length

10 = Not used

11 = Four-byte length.

Gn

Ln

1

If = 1: breakpoint in DRn is globally enabled for all tasks and is not cleared by the processor as the

result of a task switch.

If = 1: breakpoint in DRn is locally enabled for the current task and is cleared by the processor as the

result of a task switch.

GD

Global disable of debug register access. GD bit is cleared whenever a debug exception occurs.

DR6 Register

Debug Status Register 6 (RO)

Bn

1

Bn is set by the processor if the conditions described by DRn, R/Wn, and LENn occurred when the

debug exception occurred, even if the breakpoint is not enabled via the Gn or Ln bits.

BT

BS

BT is set by the processor before entering the debug handler if a task switch has occurred to a task with

the T bit in the TSS set.

BS is set by the processor if the debug exception was triggered by the single-step execution mode (TF

flag, bit 8, in EFLAGS set).

Note: n = 0, 1, 2, and 3

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Processor Programming (Continued)

3.3.2.4 Test Registers

The TLB Test Data Register (TR7) contains the upper 20

bits of the physical address (TLB data field), three LRU

bits and a control bit. During TLB write operations, the

physical address in TR7 is written into the TLB entry

selected by the contents of TR6. During TLB lookup oper-

ations, the TLB data selected by the contents of TR6 is

loaded into TR7. Table 3-15 lists the bit definitions for TR7

and TR6.

The five test registers are used in testing the processor’s

Translation Lookaside Buffer (TLB) and on-chip cache. TR6

and TR7 are used for TLB testing, and TR3-TR5 are used

for cache testing. Table 3-14 is a register map for the Test

Registers with their bit definitions given in Tables 3-15 and

3-17.

TLB Test Registers

The TLB Test Control Register (TR6) contains a com-

mand bit, the upper 20 bits of a linear address, a valid bit

and the attribute bits used in the test operation. The con-

tents of TR6 are used to create the 24-bit TLB tag during

both write and read (TLB lookup) test operations. The

command bit defines whether the test operation is a read

or a write.

The processor’s TLB is a 32-entry, four-way set associa-

tive memory. Each TLB entry consists of a 24-bit tag and

20-bit data. The 24-bit tag represents the high-order 20

bits of the linear address, a valid bit, and three attribute

bits. The 20-bit data portion represents the upper 20 bits

of the physical address that corresponds to the linear

address.

Table 3-14. TLB Test Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

TR7 Register

TLB Test Data Register (R/W)

Physical Address

0

TLB LRU

0

PL REP

0

TR6 Register

TLB Test Control Register (R/W)

Linear Address

V

D

D#

U

U#

R

R#

0

C

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Table 3-15. TR7-TR6 Bit Definitions

Bit

Name

Description

TR7 Register

TLB Test Data Register (R/W)

31:12

Physical

Address

Physical Address:

TLB lookup: Data field from the TLB.

TLB write: Data field written into the TLB.

11:10

9:7

RSVD

Reserved: Set to 0.

TLB LRU

LRU Bits:

TLB lookup: LRU bits associated with the TLB entry before the TLB lookup.

TLB write: Ignored.

4

PL

PL Bit:

TLB lookup: If PL = 1, read hit occurred. If PL = 0, read miss occurred.

TLB write: If PL = 1, REP field is used to select the set. If PL = 0, the pseudo-LRU replacement algorithm

is used to select the set.

3:2

REP

Set Selection:

TLB lookup: If PL = 1, this field indicates the set in which the tag was found. If PL = 0, undefined data.

TLB write: If PL = 1, this field selects one of the four sets for replacement. If PL = 0, ignored.

Reserved: Set to 0.

1:0

RSVD

TR6 Register

31:12

TLB Test Control Register (R/W)

Linear Address:

Linear

Address

TLB lookup: The TLB is interrogated per this address. If one and only one match occurs in the TLB, the

rest of the fields in TR6 and TR7 are updated per the matching TLB entry.

TLB write: A TLB entry is allocated to this linear address.

Valid Bit:

11

V

TLB write: If V = 1, the TLB entry contains valid data. If V = 0, target entry is invalidated.

10:9

8:7

6:5

D, D#

U, U#

R, R#

Dirty Attribute Bit and its Complement (D, D#)

User/Supervisor Attribute Bit and its Complement (U, U#)

Read/Write Attribute Bit and its Complement (R, R#)

Effect on TLB Lookup

Effect on TLB Write

00 =

01 =

10 =

11 =

Do not match

Undefined

Clear the bit

Set the bit

Undefined

Match if D, U, or R bit is a 0

Match if D, U, or R bit is a 1

Match if D, U, or R bit is either a 1 or 0

4:1

0

RSVD

C

Reserved: Set to 0.

Command Bit:

If C = 1: TLB lookup.

If C = 0: TLB write.

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Processor Programming (Continued)

Cache Test Registers

status for one double-word (4 bytes) within the 16-byte

data field.

The processor’s 16 KB on-chip cache is a four-way set

associative memory that is configured as write-back

cache. Each cache set contains 256 entries. Each entry

consists of a 20-bit tag address, a 16-byte data field, a

valid bit, and four dirty bits.

For each line in the cache, there are three LRU bits that

indicate which of the four sets was most recently

accessed. A line is selected using bits [11:4] of the physi-

cal address. Figure 3-1 illustrates the CPU cache archi-

tecture.

The 20-bit tag represents the high-order 20 bits of the

physical address. The 16-byte data represents the 16

bytes of data currently in memory at the physical address

represented by the tag. The valid bit indicates whether the

data bytes in the cache actually contain valid data. The

four dirty bits indicate if the data bytes in the cache have

been modified internally without updating external mem-

ory (write-back configuration). Each dirty bit indicates the

The CPU contains three test registers (TR5-TR3) that

allow testing of its internal cache. Bit definitions for the

cache test registers are shown in Table 3-17. Using a 16-

byte cache fill buffer and a 16-byte cache flush buffer,

cache reads and writes may be performed.

.

Line

Address

Set 0

Set 1

Set 2

Set 3

LRU

255

D

E

C

O

D

E

254

A11-A4

.

0

.

152 --- 0

2 --- 0

= Cache Entry (153 bits)

Tag Address (20 bits)

Data (128 bits)

Valid Status (1 bit)

Dirty Status (4 bits)

Figure 3-1. CPU Cache Architecture

Table 3-16. Cache Test Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

TR5 Register (R/W)

RSVD

Line Selection

LRU Bits

Set/

DWORD

Control

Bits

TR4 Register (R/W)

Cache Tag Address

0

Dirty Bits

0

TR3 Register (R/W)

Cache Data

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Table 3-17. TR5-TR3 Bit Definitions

Bit

Name

Description

TR5 Register (R/W)

11:4

3:2

Line Selection Line Selection:

Physical address bits 11-4 used to select one of 256 lines.

Set/DWORD Set/DWord Selection:

Cache read: Selects which of the four sets in the cache is used as the source for data

transferred to the cache flush buffer.

Cache write: Selects which of the four sets in the cache is used as the destination for data transferred

from the cache fill buffer.

Flush buffer read: Selects which of the four Dword in the flush buffer is

used during a TR3 read.

Fill buffer write: Selects which of the four Dword in the fill buffer is written during a TR3 write.

Control Bits:

1:0

Control Bits

If = 00: flush read or fill buffer write.

If = 01: cache write.

If = 10: cache read.

If = 11: cache flush.

TR4 Register (R/W)

31:12

Upper Tag

Upper Tag Address:

Address

Cache read: Upper 20 bits of tag address of the selected entry.

Cache write: Data written into the upper 20 bits of the tag address of the selected entry.

Valid Bit:

10

Valid Bit

Cache read: Valid bit for the selected entry.

Cache write: Data written into the valid bit for the selected entry.

LRU Bits:

9:7

LRU Bits

Cache read: The LRU bits for the selected line.

xx1 = Set 0 or Set 1 most recently accessed.

xx0 = Set 2 or Set 3 most recently accessed.

x1x = Most recent access to Set 0 or Set 1 was to Set 0.

x0x = Most recent access to Set 0 or Set 1 was to Set 1.

1xx = Most recent access to Set 2 or Set 3 was to Set 2.

0xx = Most recent access to Set 2 or Set 3 was to Set 3.

Cache write: Ignored.

6:3

2:0

Dirty Bits

RSVD

Dirty Bits:

Cache read: The dirty bits for the selected entry (one bit per DWord).

Cache write: Data written into the dirty bits for the selected entry.

Reserved: Set to 0.

TR3 Register (R/W)

31:0

Cache Data

Cache Data:

Flush buffer read: Data accessed from the cache flush buffer.

Fill buffer write: Data to be written into the cache fill buffer.

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Processor Programming (Continued)

There are five types of test operations that can be exe-

cuted:

times. Once the fill buffer holds a complete cache line of

data (16 bytes), a cache write operation transfers the data

from the fill buffer to the cache.

•

Flush buffer read

Fill buffer write

Cache write

Cache read

Cache flush

To read the contents of a cache line, a cache read opera-

tion transfers the data in the selected cache line to the

flush buffer. Once the flush buffer is loaded, the program-

mer accesses the contents of the flush buffer by executing

four flush buffer read operations.

These operations are described in detail in Table 3-18. To

fill a cache line with data, the fill buffer must be written four

Table 3-18. Cache Test Operations

Test Operation

Code Sequence

MOV TR5, 0h

Action Taken

Flush Buffer Read

Set DWORD = 0, control = 00 = flush buffer read.

Flush buffer (31:0) --> dest.

MOV dest,TR3

MOV TR5, 4h

Set DWORD = 1, control = 00 = flush buffer read.

Flush buffer (63:32) --> dest.

MOV dest,TR3

MOV TR5, 8h

Set DWORD = 2, control = 00 = flush buffer read.

Flush buffer (95:64) --> dest.

MOV dest,TR3

MOV TR5, Ch

Set DWORD = 3, control = 00 = flush buffer read.

Flush buffer (127:96) --> dest.

MOV dest,TR3

Fill Buffer Write

MOV TR5, 0h

Set DWORD = 0, control = 00 = fill buffer write.

Cache_data --> fill buffer (31:0).

MOV TR3, cache_data

MOV TR5, 4h

Set DWORD = 1, control = 00 = fill buffer write.

Cache_data --> fill buffer (63:32).

MOV TR3, cache_data

MOV TR5, 8h

Set DWORD = 2, control = 00 = fill buffer write.

Cache_data --> fill buffer (95:64).

MOV TR3, cache_data

MOV TR5, Ch

Set DWORD = 3, control = 00 = fill buffer write.

Cache_data --> fill buffer (127:96).

MOV TR3, cache_data

MOV TR4, cache_tag

MOV TR5, line+set+control=01

MOV TR5, line+set+control=10

MOV dest, TR4

Cache Write

Cache Read

Cache Flush

Cache_tag --> tag address, valid and dirty bits.

Fill buffer (127:0) --> cache line (127:0).

Cache line (127:0) --> flush buffer (127:0).

Cache line tag address, valid/LRU/dirty bits --> dest.

Control = 11 = cache flush, all cache valid bits = 0.

MOV TR5, 3h

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Processor Programming (Continued)

3.3.3 Model Specific Register Set

3.3.4 Time Stamp Counter

The Model Specific Register (MSR) Set is used to monitor

the performance of the processor or a specific component

within the processor.

The processor contains a model specific register (MSR)

called the Time Stamp Counter (TSC). The TSC,

(MSR[10]), is a 64-bit counter that counts the internal

CPU clock cycles since the last reset. The TSC uses a

continuous CPU core clock and will continue to count

clock cycles even when the processor is in suspend or

shutdown mode.

A MSR can be read using the RDMSR instruction, opcode

0F32h. During a MSR read, the contents of the particular

MSR, specified by the ECX Register, is loaded into the

EDX:EAX Registers.

The TSC is read using a RDMSR instruction, opcode 0F

32h, with the ECX register set to 10h. During a TSC read,

the contents of the TSC is loaded into the EDX:EAX regis-

ters.

A MSR can be written using the WRMSR instruction,

opcode 0F30h. During a MSR write, the contents of

EX:EAX are loaded into the MSR specified in the ECX

Register.

The TSC is written to using a WRMSR instruction, opcode

0F 30h with the ECX register set to 10h. During a TSC

write, the contents of EX:EAX are loaded into the TSC.

The RDMSR and WRMSR instructions are privileged

instructions.

The GXm processor contains one 64-bit Model Specific

Register (MSR10) the Time Stamp Counter (TSC).

The RDMSR and WRMSR instructions are privileged

instructions.

In addition, the TSC can be read using the RDTSC

instruction, opcode 0F 31h. The RDTSC instruction loads

the contents of the TSC into EDX:EAX. The use of the

RDTSC instruction is restricted by the TSC flag (bit 2) in

the CR4 register (refer to Tables 3-6 and 3-7 on pages 45

and 45 for CR4 register information). When the TSC bit =

0, the RDTSC instruction can be executed at any privilege

level. When the TSC bit = 1, the RDTSC instruction can

only be executed at privilege level 0.

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Processor Programming (Continued)

3.4 ADDRESS SPACES

The GXm processor can directly address either memory

or I/O space. Figure 3-2 illustrates the range of addresses

available for memory address space and I/O address

space. For the CPU, the addresses for physical memory

range between 00000000h and FFFFFFFFh (4 GBytes).

The accessible I/O addresses space ranges between

00000000h and 0000FFFFh (64 KB). The CPU does not

use coprocessor communication space in upper I/O space

between 800000F8h and 800000FFh as do the 386-style

CPUs. The I/O locations 22h and 23h are used for GXm

processor configuration register access.

I/O accesses to port address range 3B0h through 3DFh

can be trapped to SMI by the CPU if this option is enabled

in the BC_XMAP_1 register (see SMIB, SMIC, and SMID

bits in Table 4-10 on page 101). Figure 3-2 illustrates the

I/O address space.

3.4.2 Memory Address Space

The processor directly addresses up to 4 GB of physical

memory even though the memory controller addresses

only 1 GB of DRAM. Memory address space is accessed

as bytes, words (16 bits) or DWORDs (32 bits). Words

and DWORDs are stored in consecutive memory bytes

with the low-order byte located in the lowest address. The

physical address of a word or DWORD is the byte address

of the low-order byte.

3.4.1 I/O Address Space

The CPU I/O address space is accessed using IN and

OUT instructions to addresses referred to as “ports.” The

accessible I/O address space is 64 KB and can be

accessed as 8-bit, 16-bit or 32-bit ports.

The processor allows memory to be addressed using nine

different addressing modes. These addressing modes are

used to calculate an offset address, often referred to as an

effective address. Depending on the operating mode of

the CPU, the offset is then combined, using memory man-

agement mechanisms, into a physical address that is

applied to the physical memory devices.

The GXm processor configuration registers reside within

the I/O address space at port addresses 22h and 23h and

are accessed using the standard IN and OUT instructions.

The configuration registers are modified by writing the

index of the configuration register to port 22h, and then

transferring the data through port 23h. Accesses to the

on-chip configuration registers do not generate external

I/O cycles. However, each operation on port 23h must be

preceded by a write to port 22h with a valid index value.

Otherwise, subsequent port 23h operations will communi-

cate through the I/O port to produce external I/O cycles with-

out modifying the on-chip configuration registers. Write

operations to port 22h outside of the CPU index range

(C0h-CFh and FEh-FFh) result in external I/O cycles and

do not affect the on-chip configuration registers. Reading

port 22h generates external I/O cycles.

Memory management mechanisms consist of segmenta-

tion and paging. Segmentation allows each program to

use several independent, protected address spaces. Pag-

ing translates a logical address into a physical address

using translation lookup tables. Virtual memory is often

implemented using paging. Either or both of these mecha-

nisms can be used for management of the GXm proces-

sor memory address space.

Accessible

Programmed

I/O Space

Physical

Memory Space

FFFFFFFFh

Not

Accessible

Physical Memory

4 GB

CPU General

Configuration

Register I/O

0000FFFFh

Space

64 KB

00000023h

00000022h

00000000h

Figure 3-2. Memory and I/O Address Spaces

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Processor Programming (Continued)

3.5 OFFSET, SEGMENT, AND PAGING MECHANISMS

The mapping of address space into a sequence of mem-

ory locations (often cached) is performed by the offset,

segment and paging mechanisms.

Nine valid combinations of the base, index, scale factor

and displacement can be used with the CPU instruction

set. These combinations are listed in Table 3-19 on page

61. The base and index both refer to contents of a register

as indicated by [Base] and [Index].

In general, the offset, segment and paging mechanisms

work in tandem as shown below:

In real mode operation, the CPU only addresses the low-

est 1 MB of memory and the offset contains 16-bits. In

protective mode the offset contains 32 bits. Initialization

and transition to protective mode is described in Section

3.13.4 “Initialization and Transition to Protected Mode” on

page 87.

instruction offset offset mechanism offset address

offset address

segment mechanism linear address

linear address paging mechanism physical page.

As will be explained, the actual operations depend on sev-

eral factors such as the current operating mode and if

paging is enabled. Note: the paging mechanism uses part

of the linear address as an offset on the physical page.

Index

3.6 OFFSET MECHANISM

In all operating modes, the offset mechanism computes

an offset (effective) address by adding together up to

three values: a base, an index and a displacement. The

base, if present, is the value in one of eight general regis-

ters at the time of the execution of the instruction. The

index, like the base, is a value that is contained in one of

the general registers (except the ESP register) when the

instruction is executed. The index differs from the base in

that the index is first multiplied by a scale factor of 1, 2, 4

or 8 before the summation is made. The third component

added to the memory address calculation is the displace-

ment that is a value supplied as part of the instruction.

Figure 3-3 illustrates the calculation of the offset address.

Base

Displacement

Scaling

x1, x2, x4, x8

+

Offset Address

(Effective Address)

Figure 3-3. Offset Address Calculation

Table 3-19. Memory Addressing Modes

Scale

Factor

(SF)

Displacement

Offset Address (OA)

Calculation

Addressing Mode

Direct

Base

Index

(DP)

x

OA = DP

Register Indirect

Based

x

OA = [BASE]

x

OA = [BASE] + DP

Index

x

OA = [INDEX] + DP

Scaled Index

Based Index

Based Scaled Index

x

OA = ([INDEX] * SF) + DP

OA = [BASE] + [INDEX]

OA = [BASE] + ([INDEX] * SF)

OA = [BASE] + [INDEX] + DP

x

Based Index with

Displacement

x

Based Scaled Index with

Displacement

x

OA = [BASE] + ([INDEX] * SF) + DP

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Processor Programming (Continued)

3.7 DESCRIPTORS AND SEGMENT MECHANISMS

Memory is divided into contiguous regions called “seg-

ments.” The segments allow the partitioning of individual

elements of a program. Each segment provides a zero

address-based private memory for such elements as

code, data and stack space.

To calculate a physical memory address, the 16-bit seg-

ment base address located in the selected segment regis-

ter is multiplied by 16 and then a 16-bit offset address is

added. The resulting 20-bit address is then extended with

twelve zeros in the upper address bits to crate 32-bit phys-

ical address.

The segment mechanisms select a segment in memory.

Memory is divided into an arbitrary number of segments,

each containing usually much less than the 2³²byte (4

GByte) maximum.

The value of the selector (the INDEX field) is multiplied by

16 to produce a base address (Figure 3-4.) The base

address is summed with the instruction offset value to pro-

duce a physical address.

There are two segment mechanisms, one for Real and

Virtual 8086 Operating Modes, and one for Protective

Mode.

Virtual 8086 Mode Segment Mechanism

In Virtual 8086 mode the operation is performed as in real

mode except that a paging mechanism is added. When

paging is enabled, the paging mechanism translates the

linear address into a physical address using cached look-

up tables (refer to Section 3.9 “Paging Mechanism” on

page 72).

3.7.1 Real and Virtual 8086 Mode Segment

Mechanisms

Real Mode Segment Mechanism

In real mode operation, the CPU addresses only the low-

est 1 MB of memory. In this mode a selector located in

one of the segment registers is used to locate a segment.

12 High Order Address Bits

000h

16

Offset Address

Offset Mechanism

12

20

32

Linear Address

(Physical Address)

16

20

Base Address

Selected Segment

Register

X 16

Figure 3-4. Real Mode Address Calculation

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Processor Programming (Continued)

3.7.2 Segment Mechanism in Protective Mode

The segment mechanism in protective mode is more com-

plex. Basically as in Real and Virtual 8086 modes the off-

set address is added to the segment base address to

produce a linear address (Figure 3-5). However, the cal-

culation of the segment base address is based on the

contents of descriptor tables.

divided in to three fields: the RPL, TI and INDEX fields as

shown in Figure 3-6.

The segments are assigned permission levels to prevent

application program errors from disrupting operating pro-

grams. The Requested Privilege Level (RPL) determines

the Effective Privilege Level of an instruction. RPL = 0 indi-

cates the most privileged level, and RPL = 3 indicates the

least privileged level. Refer to Section 3.13 “Protection” on

page 86.

Again, if paging is enabled the linear address is further

processed by the paging mechanism.

Descriptor tables hold descriptors that allow management

of segments and tables in address space while in protec-

tive mode. The Table Indicator Bit (TI) in the selector

selects either the General Descriptor Table (GDT) or one

Local Descriptor Tables (LDT) tables. If TI = 0, GDT is

selected; if TI =1, LDT is selected. The 13-bit INDEX field

in the segment selector is used to index a GDT or LDT

table.

A more detailed look at the segment mechanisms for real,

virtual 8086 and protective modes is illustrated in Figure

3-6. In protective mode, the segment selector is cached.

This is illustrated in Figure 3-7 on page 65.

3.7.2.1 Segment Selectors

The segment registers are used to store segment selec-

tors. In protective mode, the segment selectors are

32

Offset Address

Offset Mechanism

Linear

Address

Physical

Memory

Address

32

Optional

Paging Mechanism

32

Segment Base

Address

32

Selector Mechanism

Figure 3-5. Protected Mode Address Calculation

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Processor Programming (Continued)

Logical Address

Segment Selector

INDEX

15

0

INSTRUCTION OFFSET

Logical

Address

x 16

+

p

Segment

Base

Address

Linear

Address

Physical

Address

p= Paging Mechanism for Virtual 8086 Mode only

Main Memory

Real and Virtual 8086 Modes

Logical Address

Segment Selector

15

3

2

1

0

INSTRUCTION OFFSET

INDEX

TI RPL

Segment Descriptor

p

x 8

+

Segment

Base

Address

Linear

Address

Physical

Address

p = Paging Mechanism

GDT or LDT Descriptor Table

Main Memory

Protective Mode

Figure 3-6. Selector Mechanisms

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Processor Programming (Continued)

Selector Load Instruction

Segment Register

Selected By Decoded

Instruction

15

0

Selector

In Segment

Register

INDEX

TI RPL

Segment

Caching

Cached Segment

and Descriptor

Segment

Descriptor

TI = 0

TI = 1

Cached

Selector

Used If

Segment

Base

Address

Global Descriptor

Table

Available

Segment

Descriptor

Local Descriptor

Table

Figure 3-7. Selector Mechanism Caching

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Processor Programming (Continued)

3.7.3 GDTR and LDTR Registers

3.7.3.1 Segment Descriptors

The GDT, and LDT descriptor tables are defined by the

Global Descriptor Table Register (GDTR) and the Local

Descriptor Table Register (LDTR) respectively. Some texts

refer to these registers as GDT, and LDT descriptors.

There are several types of descriptors. A segment

descriptor defines the base address, limit and attributes of

a memory segment.

The GDT or LDT can hold several types of descriptors. In

particular, the segment descriptors are stored in either of

two registers, the GDT, or the LDT as shown in Table 3-

20). Either of these tables can store as many as 8,192

(2¹³) eight-byte selectors taking as much as 64 KB of

memory.

The following instructions are used in conjunction with the

GDT and LDT registers:

•

LGDT - Load memory to GDTR

LLDT - Load memory to LDTR

SGDT - Store GDTR to memory

SLDT - Store LDTR to memory

The first descriptor in the GDT (location 0) is not used by

the CPU and is referred to as the “null descriptor.”

The GDTR is set up in REAL mode using the LGDT

instruction. This is possible as the LGDT instruction is one

of two instructions that directly load a linear address

(instead of a segment relative address) in protective

mode. (The other instruction is the Load Interrupt Descrip-

tor Table [LIDT]).

Types of Segment Descriptors

The type of memory segments are defined by correspond-

ing types of segment descriptors:

•

Code Segment Descriptors

Data Segment Descriptors

Stack Segment Descriptors

LDT Segment Descriptors

As shown in Table 3-20, the GDT registers contain a

BASE ADDRESS field and a LIMIT field that define the

GDT tables. (The IDTR is described in Section 3.7.3.2

“Task, Gate and Interrupt Descriptors” on page 67.)

Also shown in Table 3-20, the LDTR is only two bytes wide

as it contains only a SELECTOR field. The contents of the

SELECTOR field point to a descriptor in the GDT.

Table 3-20. GDTR, LDTR and IDTR Registers

47

16 15 14 13 12 11 10

Global Descriptor Table Register

9

8

7

6

5

4

3

2

1

0

GDT Register

BASE

LIMIT

IDT Register

LDT Register

Interrupt Descriptor Table Register

Local Descriptor Table Register

SELECTOR

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Processor Programming (Continued)

3.7.3.2 Task, Gate and Interrupt Descriptors

The IDT descriptor table is defined by the Interrupt

Descriptor Table Register (IDTR). Some texts refer to this

register as an IDT descriptor.

Besides segment descriptors there are descriptors used

in task switching, switching between tasks with different

priority and those used to control interrupt functions:

The following instructions are used in conjunction with the

IDTR registers:

•

Task State Segment Table Descriptors

Gate Table Descriptors

Interrupt Descriptors.

•

LIDT - Load memory to IDTR

SIDT - Store IDTR to memory

All descriptors have some things in common. They are all

eight bytes in length and have three fields (BASE, LIMIT

and TYPE). The BASE field defines the starting location

for the table or segment. The LIMIT field defines the size

and the TYPE field depends on the type of descriptor.

One of the main functions of the TYPE field is to define

the access rights to the associated segment or table.

The IDTR is set up in REAL mode using the LIDT instruc-

tion. This is possible as the LIDT instructions is only one

of two instructions that directly load a linear address

(instead of a segment relative address) in protective

mode.

As previously shown in Table 3-20, the IDTR contains a

BASE ADDRESS field and a LIMIT field that define the

IDT tables.

Interrupt Descriptor Table

The Interrupt Descriptor Table is an array of 256 8-byte (4-

byte for real mode) interrupt descriptors, each of which is

used to point to an interrupt service routine. Every inter-

rupt that may occur in the system must have an associ-

ated entry in the IDT. The contents of the IDTR are

completely visible to the programmer through the use of

the SIDT instruction.

3.7.4 Descriptor Bit Structure

The bit structure for application and system descriptors is

shown in Table 3-21. The explanation of the TYPE field is

shown in Table 3-23 on page 68.

Table 3-21. Application and System Segment Descriptors

31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Memory Offset +4

9

8

7

6

5

4

3

2

1

0

BASE[31:24]

G

D

0

A

V

L

LIMIT[19:16]

P

DPL

S

TYPE

BASE[23:16]

Memory Offset +0

BASE[15:0]

LIMIT[15:0]

Table 3-22. Application and System Segment Descriptors Bit Definitions

Memory

Bit

Offset

Name

Description

31:24

7:0

+4

+0

+4

+0

BASE

Segment Base Address: Three fields which collectively define the base location for the segment in

4 GB physical address space.

31:16

19:16

15:0

LIMIT

Segment Limit: Two fields that define the size of the segment based on the Segment Limit

Granularity Bit.

If G = 1: Limit value interpreted in units of 4 KB.

If G = 0: Limit value is interpreted in bytes.

23

22

+4

G

D

Segment Limit Granularity Bit: Defines LIMIT multiplier.

If G = 1: Limit value interpreted in units of 4 KB. Segment size ranges from 1 byte to 1 MB.

If G = 0: Limit value is interpreted in bytes. Segment size ranges from 4 KB to 4 GB.

Default Length for Operands and Effective Addresses:

If D = 1: Code segment = 32-bit length for operands and effective addresses

If D = 0: Code segment = 16-bit length for operands and effective addresses

If D = 1: Data segment = Pushes, calls and pop instructions use 32-bit ESP register

If D = 0: Data segment = Stack operations use 16-bit SP register

20

+4

AVL

Segment Available: This field is available for use by system software.

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Processor Programming (Continued)

Table 3-22. Application and System Segment Descriptors Bit Definitions (Continued)

Memory

Bit

Offset

Name

Description

15

+4

P

Segment Present:

If = 1: Segment is memory segment allocated.

If = 0: The BASE and LIMIT fields become available for use by the system. Also, If = 0, a segment-

not-present exception generated when selector for the descriptor is loaded into a segment register

allowing virtual memory management.

14:13

12

+4

DPL

S

Descriptor Privilege Level:

If = 00: Highest privilege level

If = 11: Low privilege level

Descriptor Type:

If = 1: Code or data segment

If = 0: System segment

11:8

TYPE

Segment Type: Refer to Table 3-23 on page 68 for TYPE bit definitions.

Bit 11 = Executable

Bit 10 = Conforming if bit 12 = 1

Bit 10 = Expand Down if bit 12 = 0

Bit 9 = Readable, if Bit 12 = 1

Bit 9 = Writable, if Bit 12 = 0

Bit 8 = Accessed

Table 3-23. Application and System Segment Descriptors TYPE Bit Definitions

TYPE

Bits [11:8]

System Segment and Gate Types

Bit 12 = 0

Application Segment Types

Bit 12 = 1

Num

SEWA

0000

0001

0010

0011

0100

0101

0110

0111

SCRA

1000

1001

1010

1011

1100

1101

1110

1111

TYPE (Data Segments)

0

1

Reserved

Available 16-Bit TSS

LDT

Data

Read-Only

Read-Only, accessed

2

Read/Write

3

Busy 16-Bit TSS

16-Bit Call Gate

Task Gate

Read/Write accessed

Read-Only, expand down

Read-Only, expand down, accessed

Read/Write, expand down

Read/Write, expand down, accessed

4

5

6

16-Bit Interrupt Gate

16-Bit Trap Gate

7

Num

8

TYPE (Code Segments)

Reserved

Available 32-Bit TSS

Reserved

Code

Execute-Only

9

Execute-Only, accessed

A

Execute/Read

B

Busy 32-Bit TSS

32-Bit Call Gate

Reserved

Execute/Read, accessed

C

D

E

Execute/Read, conforming

Execute/Read, conforming, accessed

Execute/Read-Only, conforming

Execute/Read-Only, conforming accessed

32-Bit Interrupt Gate

32-Bit Trap Gate

F

S = Code Segment (not Data Segment)

A = Accessed

E = Expand Down

W = Write Enable

C = Conforming Code Segment

R = Read Enable

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Processor Programming (Continued)

3.7.5 Gate Descriptors

The following privilege levels are tested during the transfer

through the call gate:

Four kinds of gate descriptors are used to provide protec-

tion during control transfers: call gates, trap gates, inter-

rupt gates and task gates. (For more information on

protection refer to Section 3.13 “Protection” on page 86.)

•

CPL = Current Privilege Level

RPL = Segment Selector Field

DPL = Descriptor Privilege Level in the call gate

descriptor.

Call Gate Descriptor (CGD). Call gates are used to

define legal entry points to a procedure with a higher priv-

ilege level. The call gates are used by CALL and JUMP

instructions in much the same manner as code segment

descriptors. When the CPU decodes an instruction and

sees it refers to a call gate descriptor in the GDT table or a

LDT table, the call gate is used to point to another

descriptor in the table that defines the destination code

segment.

•

DPL = Descriptor Privilege Level in the destination

code segment.

The maximum value of the CPL and RPL must be equal

or less than the gate DPL. For a JMP instruction the desti-

nation DPL equals the CPL. For a CALL instruction the

destination DPL is less or equals the CPL.

Conforming Code Segments. Transfer to a procedure

with a higher privilege level can also be accomplished by

bypassing the use of call gates, if the requested proce-

dure is to be executed in a conforming code segment.

Conforming code segments have the C bit set in the

TYPE field in their descriptor.

The bit structure and definitions for gate descriptors are

shown in Tables 3-24 and Table 3-25 on page 69.

Table 3-24. Gate Descriptors

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Memory Offset +4

9

8

7

6

5

4

3

2

1

0

OFFSET[31:16]

P

DPL

0

TYPE

0

PARAMETERS

Memory Offset +0

SELECTOR[15:0]

OFFSET[15:0]

Table 3-25. Gate Descriptors Bit Definitions

Memory

Bit

Offset

Name

Description

31:16

15:0

31:16

15

+4

+0

+4

OFFSET

Offset: Offset used during a call gate to calculate the branch target.

SELECTOR

P

Segment Selector

Segment Present

14:13

11:8

DPL

Descriptor Privilege Level

Segment Type:

TYPE

0100 = 16-bit call gate

0101 = Task gate

0110 = 16-bit interrupt gate

0111 = 16-bit trap gate

1100 = 32-bit call gate

1110 = 32-bit interrupt gate

1111 = 32-bit trap gate

4:0

+4

PARAMETERS Parameters: Number of parameters to copy from the caller’s stack to the called proce-

dure’s stack.

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Processor Programming (Continued)

3.8 MULTITASKING AND TASK STATE SEGMENTS

The CPU enables rapid task switching using JMP and

CALL instructions that refer to Task State Segments

(TSS). During a switch, the complete task state of the cur-

rent task is stored in its TSS, and the task state of the

requested task is loaded from its TSS. The TSSs are

defined through special segment descriptors and gates.

During task switching, the processor saves the current

CPU state in the TSS before starting a new task. The TSS

can be either a 386/486-type 32-bit TSS (see Table 3-26) or a

286-type 16-bit TSS (see Table 3-27 on page 71).

Task Gate Descriptors. A task gate descriptor provides

controlled access to the descriptor for a task switch. The

DPL of the task gate is used to control access. The selec-

tor’s RPL and the CPL of the procedure must be a higher

level (numerically less) than the DPL of the descriptor.

The RPL in the task gate is not used.

The Task Register (TR) holds 16-bit descriptors that con-

tain the base address and segment limit for each task

state segment. The TR is loaded and stored via the LTR

and STR instructions, respectively. The TR can only be

accessed only during protected mode and can be loaded

when the privilege level is 0 (most privileged). When the

TR is loaded, the TR selector field indexes a TSS descrip-

tor that must reside in the Global Descriptor Table (GDT).

The I/O Map Base Address field in the 32-bit TSS points

to an I/O permission bit map that often follows the TSS at

location +68h.

Only the 16-bit selector of a TSS descriptor in the TR is

accessible. The BASE, TSS LIMT and ACCESS RIGHT

fields are program invisible.

Table 3-26. 32-Bit Task State Segment (TSS) Table

31

16 15

0

I/O Map Base Address

0

T

+64h

+60h

+5Ch

+58h

+54h

+50h

+4Ch

+48h

+44h

+40h

+3Ch

+38h

+34h

+30h

+2Ch

+28h

+24h

+20h

+1Ch

+18h

+14h

+10h

+Ch

0

Selector for Task’s LDT

0

GS

FS

DS

SS

CS

ES

0

EDI

ESI

EBP

ESP

EBX

EDX

ECX

EAX

EFLAGS

EIP

CR3

0

SS for CPL = 2

SS for CPL = 1

SS for CPL = 0

ESP for CPL = 2

0

ESP for CPL = 1

0

+8h

ESP for CPL = 0

+4h

0

Back Link (Old TSS Selector)

+0h

Note: 0 = Reserved

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Table 3-27. 16-Bit Task State Segment (TSS) Table

15

0

Selector for Task’s LDT

+2Ah

+28h

+26h

+24h

+22h

+20h

+1Eh

+1Ch

+1Ah

+18h

+16h

+14h

+12h

+10h

+Eh

DS

SS

CS

ES

DI

SI

BP

SP

BX

DX

CX

AX

EFLAGS

IP

SS for Privilege Level 0

SP for Privilege Level 1

SS for Privilege Level 1

SP for Privilege Level 1

SS for Privilege Level 0

SP for Privilege Level 0

Back Link (Old TSS Selector)

+Ch

+Ah

+8h

+6h

+4h

+2h

+0h

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Processor Programming (Continued)

3.9 PAGING MECHANISM

The paging mechanism translates a linear address to its

corresponding physical address. If the required page is

not currently present in RAM, an exception is generated.

When the operating system services the exception, the

required page can be loaded into memory and the instruc-

tion restarted. Pages are either 4 KB or 1 MB in size. The

CPU defaults to 4 KB pages that are aligned to 4 KB

boundaries.

locate an entry in the page directory table. The page

directory table acts as a 32-bit master index to up to 1 K

individual second-level page tables. The selected entry in

the page directory table, referred to as the directory table

entry (DTE), identifies the starting address of the second-

level page table. The page directory table itself is a page

and is, therefore, aligned to a 4 KB boundary. The physi-

cal address of the current page directory table is stored in

the CR3 control register, also referred to as the Page

Directory Base Register (PDBR).

A page is addressed by using two levels of tables as illus-

trated in Figure 3-8. Bits[31:22] of the 32-bit linear

address, the Directory Table Index (DTI) are used to

Linear

Address

31

22 21

12 11

0

Directory Table Index

(DTI)

Page Table Index

(PTI)

Page Frame Offset

(PFO)

4 GB

31

0

1

0

Main TLB

32-Entry

4-Way Set

Associative

DTE Cache

2-Entry

Fully Associative

-4 KB

4 KB

Physical Page

Memory

DTE

PTE

-0

0

CR3

0

Control

Register

Directory Table

Page Table

External Memory

Figure 3-8. Paging Mechanism

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Processor Programming (Continued)

Bits [21:12] of the 32-bit linear address, referred to as the

Page Table Index (PTI), locate a 32-bit entry in the sec-

ond-level page table. This Page Table Entry (PTE) con-

tains the base address of the desired page frame. The

second-level page table addresses up to 1K individual

page frames. A second-level page table is 4 KB in size

and is itself a page. Bits [11:0] of the 32-bit linear address,

the Page Frame Offset (PFO), locate the desired physical

data within the page frame.

The present bits must be set to validate the remaining bits

in the DTE and PTE. If either of the present bits are not

set, a page fault is generated when the DTE or PTE is

accessed. If P = 0, the remaining DTE/PTE bits are avail-

able for use by the operating system. For example, the

operating system can use these bits to record where on

the hard disk the pages are located. A page fault is also

generated if the memory reference violates the page pro-

tection attributes.

Since the page directory table can point to 1 K page

tables, and each page table can point to 1 K page frames,

a total of 1 M page frames can be implemented. Since

each page frame contains 4 KB, up to 4 GB of virtual

memory can be addressed by the CPU with a single page

directory table.

Translation Look-Aside Buffer

The translation look-aside buffer (TLB) is a cache for the

paging mechanism and replaces the two-level page table

lookup procedure for TLB hits. The TLB is a four-way set

associative 32-entry page table cache that automatically

keeps the most commonly used page table entries in the

processor. The 32-entry TLB, coupled with a 4 K page

size, results in coverage of 128 KB of memory addresses.

Along with the base address of the page table or the page

frame, each directory table entry or page table entry con-

tains attribute bits and a present bit as illustrated in Table

3-28.

The TLB must be flushed when entries in the page tables

are changed. The TLB is flushed whenever the CR3 regis-

ter is loaded. An individual entry in the TLB can be flushed

using the INVLPG instruction.

If the present bit (P) is set in the DTE, the page table is

present and the appropriate page table entry is read. If P

= 1 in the corresponding PTE (indicating that the page is

in memory), the accessed and dirty bits are updated, if

necessary, and the operand is fetched. Both accessed

bits are set (DTE and PTE), if necessary, to indicate that

the table and the page have been used to translate a linear

address. The dirty bit (D) is set before the first write is made

to a page.

DTE Cache

The DTE cache caches the two most recent DTEs so that

future TLB misses only require a single page table read to

calculate the physical address. The DTE cache is dis-

abled following reset and can be enabled by setting the

DTE_EN bit in CCR4[4] (Index E8h).

Table 3-28. Directory Table Entry (DTE) and Page Table Entry (PTE)

Bit

Name

Description

31:12

BASE

Base Address: Specifies the base address of the page or page table.

ADDRESS

11:9

8:7

6

AVAILABLE

RSVD

D

Available: Undefined and Available to the Programmer

Reserved: Unavailable to programmer

Dirty Bit:

PTE format — If = 1: Indicates that a write access has occurred to the page.

DTE format — Reserved.

5

4:3

2

A

Accessed Flag: If set, indicates that a read access or write access has occurred to the page.

RSVD

U/S

Reserved: Set to 0.

User/Supervisor Attribute:

If = 1: Page is accessible by User at privilege level 3.

If = 0: Page is accessible by Supervisor only when CPL ≤ 2.

1

0

W/R

P

Write/Read Attribute:

If = 1: Page is writable.

If = 0: Page is read only.

Present Flag:

If = 1: The page is present in RAM and the remaining DTE/PTE bits are validated

If = 0: The page is not present in RAM and the remaining DTE/PTE bits are available for use by the pro-

grammer.

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Processor Programming (Continued)

3.10 INTERRUPTS AND EXCEPTIONS

The processing of either an interrupt or an exception

changes the normal sequential flow of a program by trans-

ferring program control to a selected service routine.

Except for SMM interrupts, the location of the selected

service routine is determined by one of the interrupt vec-

tors stored in the interrupt descriptor table.

The INTR interrupt is unmasked when the Interrupt

Enable Flag (IF, bit 9) in the EFLAGS register is set to 1.

Except for string operations, INTR interrupts are acknowl-

edged between instructions. Long string operations have

interrupt windows between memory moves that allow

INTR interrupts to be acknowledged.

True interrupts are hardware interrupts and are generated

by signal sources external to the processor. All exceptions

(including so-called software interrupts) are produced inter-

nally by the processor.

When an INTR interrupt occurs, the processor performs

an interrupt-acknowledge bus cycle. During this cycle, the

CPU reads an 8-bit vector that is supplied by an external

interrupt controller. This vector selects which of the 256

possible interrupt handlers will be executed in response to

the interrupt.

3.10.1 Interrupts

External events can interrupt normal program execution

by using one of the three interrupt pins on the GXm pro-

cessor:

The SMM interrupt has higher priority than either INTR or

NMI. After SMI# is asserted, program execution is passed

to an SMI service routine that runs in SMM address space

reserved for this purpose. The remainder of this section

does not apply to the SMM interrupts. SMM interrupts are

described in greater detail later in this section.

•

Non-maskable Interrupt (NMI pin)

Maskable Interrupt (INTR pin)

SMM Interrupt (SMI# pin)

For most interrupts, program transfer to the interrupt rou-

tine occurs after the current instruction has been com-

pleted. When the execution returns to the original

program, it begins immediately following the interrupted

instruction.

3.10.2 Exceptions

Exceptions are generated by an interrupt instruction or a

program error. Exceptions are classified as traps, faults or

aborts depending on the mechanism used to report them

and the restartability of the instruction which first caused

the exception.

The NMI interrupt cannot be masked by software and

always uses interrupt vector 2 to locate its service routine.

Since the interrupt vector is fixed and is supplied inter-

nally, no interrupt acknowledge bus cycles are performed.

This interrupt is normally reserved for unusual situations

such as parity errors and has priority over INTR interrupts.

A Trap exception is reported immediately following the

instruction that generated the trap exception. Trap excep-

tions are generated by execution of a software interrupt

instruction (INTO, INT3, INTn, BOUND), by a single-step

operation or by a data breakpoint.

Once NMI processing has started, no additional NMIs are

processed until an IRET instruction is executed, typically

at the end of the NMI service routine. If NMI is re-asserted

before execution of the IRET instruction, one and only one

NMI rising edge is stored and then processed after execu-

tion of the next IRET.

Software interrupts can be used to simulate hardware

interrupts. For example, an INTn instruction causes the

processor to execute the interrupt service routine pointed

to by the nth vector in the interrupt table. Execution of the

interrupt service routine occurs regardless of the state of

the IF flag (bit 9) in the EFLAGS register.

During the NMI service routine, maskable interrupts may

be enabled. If an unmasked INTR occurs during the NMI

service routine, the INTR is serviced and execution

returns to the NMI service routine following the next IRET.

If a HALT instruction is executed within the NMI service

routine, the CPU restarts execution only in response to

RESET, an unmasked INTR or a System Management

Mode (SMM) interrupt. NMI does not restart CPU execu-

tion under this condition.

The one byte INT3, or breakpoint interrupt (vector 3), is a

particular case of the INTn instruction. By inserting this

one byte instruction in a program, the user can set break-

points in the code that can be used during debug.

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Processor Programming (Continued)

Single-step operation is enabled by setting the TF bit (bit

8) in the EFLAGS register. When TF is set, the CPU gen-

erates a debug exception (vector 1) after the execution of

every instruction. Data breakpoints also generate a debug

exception and are specified by loading the debug regis-

ters (DR0-DR7) with the appropriate values.

3.10.3.2 Interrupt Descriptor Table

The interrupt vector number is used by the processor to

locate an entry in the interrupt descriptor table (IDT). In

real mode, each IDT entry consists of a four-byte far

pointer to the beginning of the corresponding interrupt

service routine. In protected mode, each IDT entry is an

8-byte descriptor. The Interrupt Descriptor Table Register

(IDTR) specifies the beginning address and limit of the

IDT. Following reset, the IDTR contains a base address of

0h with a limit of 3FFh.

A Fault exception is reported before completion of the

instruction that generated the exception. By reporting the

fault before instruction completion, the processor is left in

a state that allows the instruction to be restarted and the

effects of the faulting instruction to be nullified. Fault

exceptions include divide-by-zero errors, invalid opcodes,

page faults and coprocessor errors. Debug exceptions

(vector 1) are also handled as faults (except for data

breakpoints and single-step operations). After execution

of the fault service routine, the instruction pointer points to

the instruction that caused the fault.

The IDT can be located anywhere in physical memory as

determined by the IDTR. The IDT may contain different

types of descriptors: interrupt gates, trap gates and task

gates. Interrupt gates are used primarily to enter a hard-

ware interrupt handler. Trap gates are generally used to

enter an exception handler or software interrupt handler. If

an interrupt gate is used, the Interrupt Enable Flag (IF) in

the EFLAGS register is cleared before the interrupt han-

dler is entered. Task gates are used to make the transition

to a new task.

An Abort exception is a type of fault exception that is

severe enough that the CPU cannot restart the program at

the faulting instruction. The double fault (vector 8) is the

only abort exception that occurs on the processor.

3.10.3 Interrupt Vectors

Table 3-29. Interrupt Vector Assignments

When the processor services an interrupt or exception,

the current program’s instruction pointer and flags are

pushed onto the stack to allow resumption of execution of

the interrupted program. In protected mode, the processor

also saves an error code for some exceptions. Program

control is then transferred to the interrupt handler (also

called the interrupt service routine). Upon execution of an

IRET at the end of the service routine, program execution

resumes at the instruction pointer address saved on the

stack when the interrupt was serviced.

Interrupt

Vector

Exception

Type

Function

Divide error

0

Fault

1

Debug exception

NMI interrupt

Trap/Fault*

2

3

Breakpoint

Trap

4

Interrupt on overflow

BOUND range exceeded

Invalid opcode

Trap

5

Fault

Abort

6

3.10.3.1 Interrupt Vector Assignments

7

Device not available

Double fault

Each interrupt (except SMI#) and exception is assigned

one of 256 interrupt vector numbers as shown in Table 3-

29. The first 32 interrupt vector assignments are defined

or reserved. INT instructions acting as software interrupts

may use any of interrupt vectors, 0 through 255.

8

9

Reserved

10

11

12

13

14

15

16

17

18:31

32:55

0:255

Invalid TSS

Fault

Segment not present

Stack fault

Fault

The non-maskable hardware interrupt (NMI) is assigned

vector 2. Illegal opcodes including faulty FPU instructions

will cause an illegal opcode exception, interrupt vector 6.

NMI interrupts are enabled by setting bit 2 of the CCR7

register (Index EBh[2] = 1, see Table 3-11 on page 49 for

register format).

Fault

General protection fault

Page fault

Trap/Fault

Fault

Reserved

FPU error

Fault

Alignment check exception

Reserved

In response to a maskable hardware interrupt (INTR), the

processor issues interrupt acknowledge bus cycles used to

read the vector number from external hardware. These vec-

tors should be in the range 32 to 255 as vectors 0 to 31 are

predefined. In PCs, vectors 8 through 15 are used.

Maskable hardware interrupts

Programmed interrupt

Trap

Note: *Data breakpoints and single steps are traps. All other

debug exceptions are faults.

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Processor Programming (Continued)

3.10.4 Interrupt and Exception Priorities

generated upon each attempt to execute the instruction.

Each exception service routine should make the appropri-

ate corrections to the instruction and then restart the

instruction. In this way, exceptions can be serviced until

the instruction executes properly.

As the CPU executes instructions, it follows a consistent

policy for prioritizing exceptions and hardware interrupts.

The priorities for competing interrupts and exceptions are

listed in Table 3-30. SMM interrupts always take prece-

dence. Debug traps for the previous instruction and next

instructions are handled as the next priority. When NMI

and maskable INTR interrupts are both detected at the

same instruction boundary, the GXm processor services

the NMI interrupt first.

The CPU supports instruction restart after all faults,

except when an instruction causes a task switch to a task

whose task state segment (TSS) is partially not present. A

TSS can be partially not present if the TSS is not page

aligned and one of the pages where the TSS resides is

not currently in memory.

The CPU checks for exceptions in parallel with instruction

decoding and execution. Several exceptions can result

from a single instruction. However, only one exception is

Table 3-30. Interrupt and Exception Priorities

Priority

Description

Notes

0

1

Warm Reset.

Caused by the assertion of WM_RST.

SMM hardware interrupt.

SMM interrupts are caused by SMI# asserted and always have

highest priority.

2

3

Debug traps and faults from previous instruction.

Debug traps for next instruction.

Includes single-step trap and data breakpoints specified in the

debug registers.

Includes instruction execution breakpoints specified in the debug

registers.

4

5

6

Non-maskable hardware interrupt.

Maskable hardware interrupt.

Caused by NMI asserted.

Caused by INTR asserted and IF = 1.

Faults resulting from fetching the next instruction.

Includes segment not present, general protection fault and page

fault.

7

8

Faults resulting from instruction decoding.

WAIT instruction and TS = 1 and MP = 1.

ESC instruction and EM = 1 or TS = 1.

Floating point error exception.

Includes illegal opcode, instruction too long, or privilege violation.

Device not available exception generated.

9

Device not available exception generated.

10

11

Caused by unmasked floating point exception with NE = 1.

Includes segment not present, stack fault, and general protection

Segmentation faults (for each memory reference

required by the instruction) that prevent transferring fault.

the entire memory operand.

12

13

Page Faults that prevent transferring the entire

memory operand.

Alignment check fault.

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3.10.5 Exceptions in Real Mode

3.10.6 Error Codes

Many of the exceptions described in Table 3-29 on page

75 are not applicable in real mode. Exceptions 10, 11, and

14 do not occur in real mode. Other exceptions have

slightly different meanings in real mode as listed in Table

3-31.

When operating in protected mode, the following exceptions

generate a 16-bit error code:

•

Double Fault

Alignment Check

Invalid TSS

Segment Not Present

Stack Fault

General Protection Fault

Page Fault

Table 3-31. Exception Changes in Real Mode

Vector

Number

Protected Mode

Function

Real Mode

Function

The error code format and bit definitions are shown in

Table 3-32. Bits [15:3] (selector index) are not meaningful

if the error code was generated as the result of a page

fault. The error code is always zero for double faults and

alignment check exceptions.

8

Double fault.

Invalid TSS.

Interrupt table limit overrun.

Does not occur.

10

11

Segment not

present.

Does not occur.

12

13

Stack fault.

SS segment limit overrun.

General protection CS, DS, ES, FS, GS seg-

fault.

ment limit overrun. In pro-

tected mode, an error is

pushed. In real mode, no

error is pushed.

14

Page fault.

Does not occur.

Table 3-32. Error Codes

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Selector Index

S2

S1

S0

Table 3-33. Error Code Bit Definitions

Fault

Type

Selector Index

(Bits 15:3)

S2 (Bit 2)

S1 (Bit 1)

S0 (Bit 0)

Page

Fault

Reserved.

Fault caused by:

Fault occurred during:

Fault occurred during

0 = Not present page

1 = Page-level protection

violation

0 = Read access

1 = Write access

0 = Supervisor access

1 = User access.

IDT Fault Index of faulty IDT Reserved

selector.

1

0

If = 1, exception occurred while

trying to invoke exception or

hardware interrupt handler.

Segment Index of faulty

TI bit of faulty selector

If =1, exception occurred while

trying to invoke exception or

hardware interrupt handler.

Fault

selector.

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Processor Programming (Continued)

3.11 SYSTEM MANAGEMENT MODE

System Management Mode (SMM) is usually employed

for system power management or software-transparent

emulation of I/O peripherals. SMM mode is entered

through a hardware signal “System Management Inter-

rupt” (SMI# pin) that has a higher priority than any other

interrupt, including NMI. An SMM interrupt can also be

triggered from software using an SMINT instruction. Fol-

lowing an SMM interrupt, portions of the CPU state are

automatically saved, SMM mode is entered, and program

execution begins at the base of SMM address space (Fig-

ure 3-9).

The GXm processor extends System Management Mode

(SMM) to support the virtualization of many devices,

including VGA video. The SMM mechanism can be trig-

gered not only by I/O activity, but by access to selected

memory regions. For example, SMM interrupts are gener-

ated when VGA addresses are accessed. As will be

described, other SMM enhancements have reduced SMM

overhead and improved virtualization-software perfor-

mance

Potential

Physical

Memory Space

SMM Address

Space

FFFFFFFFh

Defined

SMM

Address

Space

Physical Memory

4 GB

4 KB to 32 MB

00000000h

Non-SMM

00000000h

SMM

Figure 3-9. System Management Memory Address Space

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Processor Programming (Continued)

3.11.1 SMM Enhancements

Table 3-34. SMI# and SMINT Recognition

Requirements

Eight SMM instructions have been added to the x86

instruction set that permit initiating SMM through software

and saving and restoring the total CPU state when in

SMM.

Register Bits

SMI#

SMINT

USE_SMI, CCR1[1] (Index C1h)

SMAC, CCR1[2] (Index C1h)

1

0

1

The SMM header now:

•

Stores 32-bits memory addresses.

Stores 32-bit memory data.

SIZE[3:0], SMAR3[3:0] (Index CFh)

>0

Differentiates memory and I/O accesses.

Indicates if an SMM interrupt was generated by access

to a VGA region.

SMI# Sampled Active or

SMINT Instruction Executed

The SMM service code is now cacheable. An SMAR reg-

ister specifies the SMM region code base and limit. An

SMHR register specifies the physical address for the

SMM header. The SMI_NEST bit enables the nesting of

SMM interrupts.

CPU State Stored in SMM

Address Space Header

3.11.2 SMM Operation

SMM execution flow is summarized in Figure 3-10. Enter-

ing SMM requires the assertion of the SMI# pin for at least

two SYSCLK periods or execution of the SMINT instruction.

For the SMI# signal or SMINT instruction to be recog-

nized, configuration register bits must be set as shown in

Table 3-34. (The configuration registers are discussed in

detail in Section 3.3.2.2 “Configuration Registers” on page

47.)

Program Flow Transfers

to SMM Address Space

CPU Enters Real Mode

After triggering an SMM through the SMI# pin or a SMINT

instruction, selected CPU state information is automati-

cally saved in the SMM memory space header located at

the top of SMM memory space. After saving the header,

the CPU enters real mode and begins executing the SMM

service routine starting at the SMM memory region base

address.

Execution Begins at SMM

Address Space Base Address

The SMM service routine is user definable and may con-

tain system or power management software. If the power

management software forces the CPU to power down or if

the SMM service routine modifies more registers than are

automatically saved, the complete CPU state information

should be saved.

RSM Instruction Restores CPU

State Using Header Information

Normal Execution Resumes

Figure 3-10. SMM Execution Flow

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Processor Programming (Continued)

3.11.3 The SMI# Pin

3.11.5 SMM Memory Space Header

External chipsets can generate an SMI based on numer-

ous asynchronous events, including power management

timers, I/O address trapping, external devices, audio FIFO

events, and others. Since SMI# is edge sensitive, the

chipset must generate an edge for each of the events

above, requiring arbitration and storage of multiple SMM

events. These functions are provided by the CS5530 I/O

companion device. The processor generates an SMI

when the external pin changes from high-to-low or when

an RSM occurs if SMI# has not remained low since the

initiation of the previous SMI.

Tables 3-35 and show the SMM header. A memory

address field has been added to the end (offset –40h) of

the header for the GXm processor. Memory data will be

stored overlapping the I/O data, since these events can-

not occur simultaneously. The I/O address is valid for both

IN and OUT instructions, and I/O data is valid only for

OUT. The memory address is valid for read and write

operations, and memory data is valid only for write opera-

tions.

With every SMI interrupt or SMINT instruction, selected

CPU state information is automatically saved in the SMM

memory space header located at the top of SMM address

space. The header contains CPU state information that is

modified when servicing an SMM interrupt. Included in

this information are two pointers. The current IP points to

the instruction executing when the SMI was detected, but

it is valid only for an internal I/O SMI.

3.11.4 SMM Configuration Registers

The SMAR register specifies the base location of SMM

code region and its size limit. This SMAR register is identi-

cal to many of the National Semconductor processors.

A new configuration control register called SMHR has

been added to specify the 32-bit physical address of the

SMM header. The SMHR address must be 32-bit aligned

as the bottom two bits are ignored by the microcode.

Hardware will detect write operations to SMHR, and sig-

nal the microcode to recompute the header address.

Access to these registers is enabled by MAPEN (Index

C3h[4]).

The Next IP points to the instruction that will be executed

after exiting SMM. The contents of Debug Register 7

(DR7), the Extended FLAGS Register (EFLAGS), and

Control Register 0 (CR0) are also saved. If SMM has

been entered due to an I/O trap for a REP INSx or REP

OUTSx instruction, the Current IP and Next IP fields con-

tain the same addresses. In addition, the I and P fields con-

tain valid information.

The SMAR register writes to the SMM header when the

SMAR register is changed. For this reason, changes to

the SMAR register should be completed prior to setting up

the SMM header. The configuration registers bit formats

are detailed in Table 3-11 on page 49.

If entry into SMM is the result of an I/O trap, it is useful for

the programmer to know the port address, data size and

data value associated with that I/O operation. This informa-

tion is also saved in the header and is valid only if SMI# is

asserted during an I/O bus cycle. The I/O trap information is

not restored within the CPU when executing a RSM instruction.

Table 3-35. SMM Memory Space Header

Mem.

Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

-4h

DR7

EFLAGS

CR0

–8h

–Ch

–10h

–14h

–18h

–1Ch

–20h

–24h

–28h

–2Ch

–30h

–32h

Current IP

Next IP

RSVD

CS Selector

CS Descriptor [63:32]

CS Descriptor [31:0]

RSVD

N

V

X

M

H

S

P

I

C

I/O Data Size

I/O Address [15:0]

I/O or Memory Data [31:0] (Note)

Restored ESI or EDI

Memory Address [31:0]

Note: Check the M bit at offset 24h to determine if the data is memory or I/O.

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Processor Programming (Continued)

Table 3-36. SMM Memory Space Header Description

Name

Description

Size

DR7

Debug Register 7: The contents of Debug Register 7.

4 Bytes

EFLAGS

CR0

Extended FLAGS Register: The contents of Extended FLAGS Register.

Control Register 0: The contents of Control Register 0.

Current IP

Current Instruction Pointer: The address of the instruction executed prior to servicing SMM

interrupt.

Next IP

Next Instruction Pointer: The address of the next instruction that will be executed after exiting

4 Bytes

SMM.

CS Selector

Code Segment Selector: Code segment register selector for the current code segment.

Code Segment Descriptor: Encoded descriptor bits for the current code segment.

Nested SMI Status: Flag that determines whether an SMI occurred during SMM (i.e., nested)

SoftVGA SMI Status: SMI was generated by an access to VGA region.

External SMI Status:

2 Bytes

8 Bytes

1 Bit

CS Descriptor

N

V

X

1 Bit

If = 1: SMI generated by external SMI# pin

If = 0: SMI internally generated by Internal Bus Interface Unit.

M

H

Memory or I/O Access: 0 = I/O access; 1 = Memory access.

1 Bit

Halt Status: Indicates that the processor was in a halt or shutdown prior to servicing the SMM

interrupt.

S

Software SMM Entry Indicator:

1 Bit

If = 1: Current SMM is the result of an SMINT instruction.

If = 0: Current SMM is not the result of an SMINT instruction.

P

REP INSx/OUTSx Indicator:

If = 1: Current instruction has a REP prefix.

If = 0: Current instruction does not have a REP prefix.

I

IN, INSx, OUT, or OUTSx Indicator:

1 Bit

If = 1: Current instruction performed is an I/O WRITE.

If = 0: Current instruction performed is an I/O READ.

C

CS Writable: Code Segment Writable

1 Bit

If = 1: CS is writable

If = 0: CS is not writable

I/O Data Size

Indicates size of data for the trapped I/O cycle:

2 Bytes

01h = byte

03h = word

0Fh = DWORD

I/O Address

Processor port used for the trapped I/O cycle.

2 Bytes

4 Bytes

I/O or Memory Data

Restored ESI or EDI

Data associated with the trapped I/O or memory cycleS.

Restored ESI or EDI Value: Used when it is necessary to repeat a REP OUTSx or REP INSx

instruction when one of the I/O cycles caused an SMI# trap.

Memory Address

Physical address of the operation that caused the SMI.

4 Bytes

Note: INSx = INS, INSB, INSW or INSD instruction.

OUTSx = OUTS, OUTSB, OUTSW and OUTSD instruction.

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Processor Programming (Continued)

3.11.6 SMM Instructions

If any one of the conditions above is not met and an

attempt is made to execute an SVDC, RSDC, SVLDT,

RSLDT, SVTS, RSTS, or RSM instruction, an invalid

opcode exception is generated. The SMM instructions can

be executed outside of defined SMM space provided the

conditions above are met.

The GXm processor core automatically saves the minimal

amount of CPU state information when entering an SMM

cycle that allows fast SMM service-routine entry and exit.

After entering the SMM service routine, the MOV, SVDC,

SVLDT and SVTS instructions can be used to save the

complete CPU state information. If the SMM service rou-

tine modifies more state information than is automatically

saved or if it forces the CPU to power down, the complete

CPU state information must be saved. Since the CPU is a

static device, its internal state is retained when the input

clock is stopped. Therefore, an entire CPU-state save is

not necessary before stopping the input clock.

The SMINT instruction can be used by software to enter

SMM. The SMINT instruction can only be used outside an

SMM routine if all the conditions listed below are true.

1) USE_SMI = 1

2) SMAR size > 0

3) Current Privilege Level = 0

4) SMAC = 1

The SMM instructions, listed in Table 3-37, can be exe-

cuted only if all the conditions listed below are met.

1) USE_SMI = 1.

If SMI# is asserted to the CPU during a software SMI, the

hardware SMI# is serviced after the software SMI has

been exited by execution of the RSM instruction.

2) SMAR SIZE > 0.

3) Current Privilege level = 0.

All the SMM instructions (except RSM and SMINT) save

or restore 80 bits of data, allowing the saved values to

include the hidden portion of the register contents.

4) SMAC bit is high or the CPU is in an SMI service

routine.

Table 3-37. SMM Instruction Set

Instruction

Opcode

Format

Description

SVDC

0F 78h [mod sreg3 r/m]

SVDC mem80, sreg3

Save Segment Register and Descriptor

Saves reg (DS, ES, FS, GS, or SS) to mem80.

Restore Segment Register and Descriptor

RSDC

0F 79h [mod sreg3 r/m]

RSDC sreg3, mem80

Restores reg (DS, ES, FS, GS, or SS) from mem80. Use RSM

to restore CS.

Note: Processing “RSDC CS, Mem80” will produce an excep-

tion.

SVLDT

RSLDT

SVTS

0F 7Ah [mod 000 r/m]

0F 7Bh [mod 000 r/m]

0F 7Ch [mod 000 r/m]

0F 7Dh [mod 000 r/m]

0F 38h

SVLDT mem80

RSLDT mem80

SVTS mem80

RSTS mem80

SMINT

Save LDTR and Descriptor

Saves Local Descriptor Table (LDTR) to mem80.

Restore LDTR and Descriptor

Restores Local Descriptor Table (LDTR) from mem80.

Save TSR and Descriptor

Saves Task State Register (TSR) to mem80.

Restore TSR and Descriptor

RSTS

Restores Task State Register (TSR) from mem80.

Software SMM Entry

SMINT

CPU enters SMM. CPU state information is saved in SMM

memory space header and execution begins at SMM base

address.

RSM

0F AAh

RSM

Resume Normal Mode

Exits SMM. The CPU state is restored using the SMM memory

space header and execution resumes at interrupted point.

Note: smem80 = 80-bit memory location.

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3.11.7 SMM Memory Space

Hardware interrupts, INTRs and NMIs, may be serviced

during an SMI service routine. If interrupts are to be ser-

viced while executing in the SMM memory space, the

SMM memory space must be within the address range of

0 to 1 MB to guarantee proper return to the SMI service

routine after handling the interrupt.

SMM memory space is defined by specifying the base

address and size of the SMM memory space in the SMAR

register. The base address must be a multiple of the SMM

memory space size. For example, a 32 KB SMM memory

space must be located at a 32 KB address boundary. The

memory space size can range from 4 KB to 32 MB. Execu-

tion of the interrupt begins at the base of the SMM memory

space.

INTRs are automatically disabled when entering SMM

since the IF flag (EFLAGS register, bit 9) is set to its reset

value. Once in SMM, the INTR can be enabled by setting

the IF flag. An NMI event in SMM can be enabled by set-

ting NMI_EN high in the CCR3 register (Index C3h[1]). If

NMI is not enabled while in SMM, the CPU latches one

NMI event and services the interrupt after NMI has been

enabled or after exiting SMM through the RSM instruction.

The processor is always in real mode in SMM, but it may

exit to either real or protected mode depending on its

state when SMM was initiated. The IDT (Interrupt Descrip-

tor Table) indicates which state it will exit to.

SMM memory space accesses are always cacheable,

which allows SMM routines to run faster.

3.11.8 SMI Generation

Virtualization software depends on processor-specific

hardware to generate SMI interrupts for each memory or

I/O access to the device being implemented. The GXm

processor implements SMI generation for VGA accesses.

Memory write operations in regions A0000h to AFFFFh,

B0000h to B7FFFh, and B8000h to BFFFFh generate an

SMI.

Within the SMI service routine, protected mode may be

entered and exited as required, and real or protected

mode device drivers may be called.

Memory reads are not trapped by the GXm processor.

The GXm processor traps I/O addresses for VGA in the

following regions: 3B0h to 3BFh, 3C0h to 3CFh, and 3D0h

to 3DFh. Memory-write trapping is performed during

instruction decode in the processor core. I/O read and

write trapping is implemented in the Internal Bus Interface

Unit of the GXm processor.

To exit the SMI service routine, a Resume (RSM) instruc-

tion, rather than an IRET, is executed. The RSM instruc-

tion causes the GXm processor core to restore the CPU

state using the SMM header information and resume exe-

cution at the interrupted point. If the full CPU state was

saved by the programmer, the stored values should be

reloaded before executing the RSM instruction using the

MOV, RSDC, RSLDT and RSTS instructions.

The SMI-generation hardware requires two additional

configuration registers to control and mask SMI interrupts

in the VGA memory space: VGACTL and VGAM. The

VGACTL register has a control bit for each address range

shown above. The VGAM register has 32 bits that can

selectively disable 2 KB regions within the VGA memory.

The VGAM applies only to the A0000h-to-AFFFFh region.

If this region is not enabled in VGA_CTL, then the con-

tents of VGAM is ignored. The purpose of VGAM is to pre-

vent SMI from occurring when non-displayed VGA

memory is accessed. This is an enhancement which

improves performance for double-buffered applications.

The format of each register is shown in Chapter 4 of this

document.

3.11.9.1 SMI Nesting

The SMI mechanism supports nesting of SMI interrupts

through the SMI handler, the SMI_NEST bit in CCR4[6]

(Index E8h), and the Nested SMI Status bit (bit N in the

SMM header, see Table on page 80). Nesting is an impor-

tant capability in allowing high-priority events, such as

audio virtualization, to interrupt lower-priority SMI code for

VGA virtualization or power management. SMI_NEST

controls whether SMI interrupts can occur during SMM.

SMI handlers can optionally set SMI_NEST high to allow

higher-priority SMI interrupts while handling the current

event.

3.11.9 SMI Service Routine Execution

The SMI handler is responsible for managing the SMI

header data for nested SMI interrupts. The SMI header

must be saved before SMI_NEST is set high, and

SMI_NEST must be cleared and its header information

restored before an RSM instruction is executed.

Upon entry into SMM, after the SMM header has been

saved, the CR0, EFLAGS, and DR7 registers are set to

their reset values. The Code Segment (CS) register is

loaded with the base, as defined by the SMAR register,

and a limit of 4 GBytes. The SMI service routine then

begins execution at the SMM base address in real mode.

The Nested SMI Status bit has been added to the SMM

header to show whether the current SMI is nested. The

processor sets Nested SMI Status high if the processor

was in SMM when the SMI was taken. The processor

uses Nested SMI Status on exit to determine whether the

processor should stay in SMM.

The programmer must save the value of any registers that

may be changed by the SMI service routine. For data

accesses immediately after entering the SMI service rou-

tine, the programmer must use CS as a segment override.

I/O port access is possible during the routine but care

must be taken to save registers modified by the I/O

instructions. Before using a segment register, the register

and the register’s descriptor cache contents should be saved

using the SVDC instruction.

When SMI nesting is disabled, the processor holds off

external SMI interrupts until the currently executing SMM

code exits. When SMI nesting is enabled, the processor

can proceed with the SMI. The SMI handler will guarantee

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Processor Programming (Continued)

that no internal SMIs are generated in SMM, so the pro-

cessor ignores such events. If the internal and external

SMI signals are received simultaneously, then the internal

SMI is given priority to avoid losing the event.

set high. The microcode clears SMI_NEST, sets

Nested SMI Status high and saves the previous

value of Nested SMI Status (1) in the SMI header.

E. The second-level SMI handler saves the header and

sets SMI_NEST to re-enable SMI interrupts within

SMM. Another level of nesting could occur during

this period.

The state diagram of the SMI_NEST and Nested SMI Sta-

tus bits are shown in Figure 3-11 with each state

explained next.

A. When the processor is outside of SMM, Nested SMI

Status is always clear and SMI_NEST is set high.

F. The second-level SMI handler clears SMI_NEST to

disable SMI interrupts, then restores its SMI header.

B. The first-level SMI interrupt is received by the

processor. The microcode clears SMI_NEST, sets

Nested SMI Status high and saves the previous

value of Nested SMI Status (0) in the SMI header.

G. The second-level SMI handler executes an RSM.

The microcode sets SMI_NEST, and restores the

Nested SMI Status (1) based on the SMI header.

H. The first-level SMI handler clears SMI_NEST to

disable SMI interrupts, then restores its SMI header.

C. The first-level SMI handler saves the header and

sets SMI_NEST high to re-enable SMI interrupts

from SMM.

I. The first-level SMI handler executes an RSM. The

microcode sets SMI_NEST high and restores the

Nested SMI Status (0) based on the SMI header.

D. A second-level (nested) SMI interrupt is received by

the processor. This SMI is taken even though the

processor is in SMM because the SMI_NEST bit is

When the processor is outside of SMM, Nested SMI Sta-

tus is always clear and SMI_NEST is set high.

SMI_NEST

Nested SMI Status

A

B

C

D

E

F

G

H

I

Figure 3-11. SMI Nesting State Machine

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3.11.9.2 CPU States Related to SMM and Suspend

Mode

latched. (In order for INTR to be latched, the IF flag,

EFLAGS register bit 9, must be set.) The INTR or NMI is

serviced after exiting Suspend mode.

The state diagram shown in Figure 3-12 illustrates the var-

ious CPU states associated with SMM and Suspend

mode. While in the SMI service routine, the GXm proces-

sor core can enter Suspend mode either by (1) executing

a halt (HLT) instruction or (2) by asserting the SUSP#

input.

If Suspend mode is entered through a HLT instruction

from the operating system or application software, the

reception of an SMI# interrupt causes the CPU to exit

Suspend mode and enter SMM. If Suspend mode is

entered through the hardware (SUSP# = 0) while the

operating system or application software is active, the

CPU latches one occurrence of INTR, NMI, and SMI#.

During SMM operations and while in SUSP#-initiated

Suspend mode, an occurrence of either NMI or INTR is

Suspend Mode

(SUSPA# = 0)

NMI or INTR

Interrupt Service

Routine

IRET*

HLT*

NMI or INTR

SUSP# = 0

Suspend Mode

(SUSPA# = 0)

OS/Application

Software

RESET

SUSP# = 1

(INTR, NMI and SMI# latched)

SMI# = 0

SMINT*

SMI# = 0

RSM*

Non-SMM Operations

SMM Operations

SMI Service Routine

(SMI# = 0)

HLT*

Suspend Mode

(SUSPA# = 0)

IRET*

NMI or INTR

IRET*

SUSP# = 1

SUSP# = 0

NMI or INTR

Interrupt Service

Routine

Suspend Mode

(SUSPA# = 0)

Interrupt Service

Routine

*Instructions

(INTR and NMI latched)

Figure 3-12. SMM and Suspend Mode State Diagram

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3.12 SHUTDOWN AND HALT

The Halt Instruction (HLT) stops program execution and

generates a special Halt bus cycle. The GXm processor

core then drives out a special Stop Grant bus cycle and

enters a low-power Suspend mode if the SUSP_HLT bit in

CCR2 (Index C2h[3]) is set. SMI#, NMI, INTR with inter-

rupts enabled (IF bit in EFLAGS = 1), or RESET forces

the CPU out of the halt state. If the halt state is inter-

rupted, the saved code segment and instruction pointer

specify the instruction following the HLT.

The Descriptor Privilege Level (DPL) is the privilege

level defined for a segment in the segment descriptor. The

DPL field specifies the minimum privilege level needed to

access the memory segment pointed to by the descriptor.

The Current Privilege Level (CPL) is defined as the cur-

rent task’s privilege level. The CPL of an executing task is

stored in the hidden portion of the code segment register

and essentially is the DPL for the current code segment.

The Requested Privilege Level (RPL) specifies a selec-

tor’s privilege level. RPL is used to distinguish between

the privilege level of a routine actually accessing memory

(the CPL), and the privilege level of the original requester

(the RPL) of the memory access. If the level requested by

RPL is less than the CPL, the RPL level is accepted and

the Effective Privilege Level (EPL) is changed to the RPL

value. If the level requested by RPL is greater than CPL,

the CPL overrides the requested RPL and EPL becomes

the CPL value.

Shutdown occurs when a severe error is detected that

prevents further processing. The most common severe

error is the triple fault, a fault event while handling a dou-

ble fault. Setting the IDT or the GDT limit to zero will

cause a triple fault.

An NMI input or a reset can bring the processor out of

shutdown. An NMI will work if the IDT limit is large

enough, at least 000Fh, to contain the NMI interrupt vec-

tor and if the stack has enough room. The stack must be

large enough to contain the vector and flag information

(the stack pointer must be greater than 0005h).

The lesser of the RPL and CPL is called the Effective Privi-

lege Level (EPL). Therefore, if RPL = 0 in a segment selec-

tor, the EPL is always determined by the CPL. If RPL = 3,

the EPL is always 3 regardless of the CPL.

3.13 PROTECTION

Segment protection and page protection are safeguards

built into the GXm processor’s protected-mode architec-

ture that deny unauthorized or incorrect access to

selected memory addresses. These safeguards allow

multitasking programs to be isolated from each other and

from the operating system. This section concentrates on

segment protection.

For a memory access to succeed, the EPL must be at

least as privileged as the Descriptor Privilege Level (EPL

≤ DPL). If the EPL is less privileged than the DPL (EPL >

DPL), a general protection fault is generated. For exam-

ple, if a segment has a DPL = 2, an instruction accessing

the segment only succeeds if executed with an EPL ≤ 2.

3.13.2 I/O Privilege Levels

Selectors and descriptors are the key elements in the seg-

ment protection mechanism. The segment base address,

size, and privilege level are established by a segment

descriptor. Privilege levels control the use of privileged

instructions, I/O instructions and access to segments and

segment descriptors. Selectors are used to locate seg-

ment descriptors.

The I/O Privilege Level (IOPL) allows the operating sys-

tem executing at CPL = 0 to define the least privileged

level at which IOPL-sensitive instructions can uncondition-

ally be used. The IOPL-sensitive instructions include CLI,

IN, OUT, INS, OUTS, REP INS, REP OUTS, and STI.

Modification of the IF bit in the EFLAGS register is also

sensitive to the I/O privilege level.

Segment accesses are divided into two basic types, those

involving code segments (e.g., control transfers) and

those involving data accesses. The ability of a task to

access a segment depends on the:

The IOPL is stored in the EFLAGS register (bits [31:12]).

An I/O permission bit map is available as defined by the

32-bit Task State Segment (TSS). Since each task can

have its TSS, access to individual I/O ports can be

granted through separate I/O permission bit maps.

•

segment type

instruction requesting access

type of descriptor used to define the segment

associated privilege levels (described next)

If CPL ≤ IOPL, IOPL-sensitive operations can be per-

formed. If CPL > IOPL, a general protection fault is gener-

ated if the current task is associated with a 16-bit TSS. If

the current task is associated with a 32-bit TSS and CPL

> IOPL, the CPU consults the I/O permission bitmap in the

TSS to determine on a port-by-port basis whether or not I/O

instructions (IN, OUT, INS, OUTS, REP INS, REP OUTS)

are permitted. The remaining IOPL-sensitive operations

generate a general protection fault.

Data stored in a segment can be accessed only by code

executing at the same or a more privileged level. A code

segment or procedure can only be called by a task exe-

cuting at the same or a less privileged level.

3.13.1 Privilege Levels

The values for privilege levels range between 0 and 3.

Level 0 is the highest privilege level (most privileged), and

level 3 is the lowest privilege level (least privileged). The

privilege level in real mode is zero.

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3.13.3 Privilege Level Transfers

3.13.3.1 Gates

A task’s CPL can be changed only through intersegment

control transfers using gates or task switches to a code

segment with a different privilege level. Control transfers

result from exception and interrupt servicing and from

execution of the CALL, JMP, INT, IRET and RET instruc-

tions.

Gate descriptors described in Section 3.7.5 “Gate

Descriptors” on page 69, provide protection for privilege

transfers among executable segments. Gates are used to

transition to routines of the same or a more privileged

level. Call gates, interrupt gates and trap gates are used for

privilege transfers within a task. Task gates are used to

transfer between tasks.

There are five types of control transfers that are summa-

rized in Table 3-38. Control transfers can be made only

when the operation causing the control transfer references

the correct descriptor type. Any violation of these descriptor

usage rules causes a general protection fault.

Gates conform to the standard rules of privilege. In other

words, gates can be accessed by a task if the effective

privilege level (EPL) is the same or more privileged than

the gate descriptor’s privilege level (DPL).

Any control transfer that changes the CPL within a task

results in a change of stack. The initial values for the stack

segment (SS) and stack pointer (ESP) for privilege levels

0, 1, and 2 are stored in the TSS. During a JMP or CALL

control transfer, the SS and ESP are loaded with the new

stack pointer and the previous stack pointer is saved on

the new stack. When returning to the original privilege

level, the RET or IRET instruction restores the SS and

ESP of the less-privileged stack.

3.13.4 Initialization and Transition to Protected Mode

The GXm processor core switches to real mode immedi-

ately after RESET. While operating in real mode, the sys-

tem tables and registers should be initialized. The GDTR

and IDTR must point to a valid GDT and IDT, respectively. The

size of the IDT should be at least 256 bytes, and the GDT

must contain descriptors that describe the initial code and

data segments.

The processor can be placed in protected mode by setting

the PE bit (CR0 register bit 0). After enabling protected

mode, the CS register should be loaded and the instruc-

tion decode queue should be flushed by executing an

intersegment JMP. Finally, all data segment registers

should be initialized with appropriate selector values.

Table 3-38. Descriptor Types Used for Control Transfer

Descriptor

Referenced

Descriptor

Table

Type of Control Transfer

Operation Types

Intersegment within the same privilege

level.

JMP, CALL, RET, IRET*

Code Segment

GDT or LDT

Intersegment to the same or a more

privileged level. Interrupt within task

(could change CPL level).

CALL

Gate Call

GDT or LDT

Interrupt Instruction, Exception,

External Interrupt

Trap or Interrupt Gate IDT

Intersegment to a less privileged level

(changes task CPL).

RET, IRET*

Code Segment

GDT or LDT

Task Switch via TSS

CALL, JMP

Task State Segment

Task Gate

GDT

Task Switch via Task Gate

GDT or LDT

IDT

IRET**, Interrupt Instruction,

Exception, External Interrupt

Task Gate

Note: *NT = 0 (Nested Task bit in EFLAGS, bit 14)

**NT =1 (Nested Task bit in EFLAGS, bit 14)

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Processor Programming (Continued)

3.14 VIRTUAL 8086 MODE

Both real mode and virtual 8086 (V86) modes are sup-

ported by the GXm processor, allowing execution of 8086

application programs and 8086 operating systems. V86

mode allows the execution of 8086-type applications, yet

still permits use of the paging and protection mechanisms.

V86 tasks run at privilege level 3. Before entry, all seg-

ment limits must be set to FFFFh (64K) as in real mode.

3.14.3 Interrupt Handling

To fully support the emulation of an 8086-type machine,

interrupts in V86 mode are handled as follows. When an

interrupt or exception is serviced in V86 mode, program

execution transfers to the interrupt service routine at privi-

lege level 0 (i.e., transition from V86 to protected mode

occurs). The VM bit in the EFLAGS register (bit 17) is

cleared. The protected mode interrupt service routine

then determines if the interrupt came from a protected

mode or V86 application by examining the VM bit in the

EFLAGS image stored on the stack. The interrupt service

routine may then choose to allow the 8086 operating sys-

tem to handle the interrupt or may emulate the function of

the interrupt handler. Following completion of the interrupt

service routine, an IRET instruction restores the EFLAGS

register (restores VM = 1) and segment selectors and

control returns to the interrupted V86 task.

3.14.1 Memory Addressing

While in V86 mode, segment registers are used in an

identical fashion to real mode. The contents of the Seg-

ment register are multiplied by 16 and added to the offset

to form the Segment Base Linear Address. The GXm pro-

cessor permits the operating system to select which pro-

grams use the V86 address mechanism and which

programs use protected mode addressing for each task.

The GXm processor also permits the use of paging when

operating in V86 mode. Using paging, the 1 MB address

space of the V86 task can be mapped to any region in the

4 GB linear address space.

3.14.4 Entering and Leaving Virtual 8086 Mode

V86 mode is entered from protected mode by either exe-

cuting an IRET instruction at CPL = 0 or by task switching.

If an IRET is used, the stack must contain an EFLAGS

image with VM = 1. If a task switch is used, the TSS must

contain an EFLAGS image containing a 1 in the VM bit

position. The POPF instruction cannot be used to enter

V86 mode since the state of the VM bit is not affected.

V86 mode can only be exited as the result of an interrupt

or exception. The transition out must use a 32-bit trap or

interrupt gate that must point to a non-conforming privi-

lege level 0 segment (DPL = 0), or a 32-bit TSS. These

restrictions are required to permit the trap handler to IRET

back to the V86 program.

The paging hardware allows multiple V86 tasks to run

concurrently, and provides protection and operating sys-

tem isolation. The paging hardware must be enabled to

run multiple V86 tasks or to relocate the address space of

a V86 task to physical address space other than 0.

3.14.2 Protection

All V86 tasks operate with the least amount of privilege

(level 3) and are subject to all CPU protected mode protec-

tion checks. As a result, any attempt to execute a privi-

leged instruction within a V86 task results in a general

protection fault.

In V86 mode, a slightly different set of instructions are

sensitive to the I/O privilege level (IOPL) than in protected

mode. These instructions are: CLI, INT n, IRET, POPF,

PUSHF, and STI. The INT3, INTO and BOUND variations

of the INT instruction are not IOPL sensitive.

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3.15 FLOATING POINT UNIT OPERATIONS

The FPU is x87-instruction-set compatible and adheres to

the IEEE-754 standard. Because most applications that

contain FPU instructions intermix with integer instructions,

the GXm processor’s FPU achieves high performance by

completing integer and FPU operations in parallel.

3.15.3 FPU Status Register

The FPU communicates status information and operation

results to the CPU through the status register. The fields

in the FPU status register are detailed in Table 3-39 on

page 90. These fields include information related to

exception status, operation execution status, register sta-

tus, operand class, and comparison results. This register

is continuously accessible to the CPU regardless of the

state of the Control or Execution Units.

3.15.1 FPU (Floating Point Unit) Register Set

In addition to the registers described to this point, the FPU

within the CPU provides the user eight data registers

accessed in a stack-like manner, a control register, and a

status register. The CPU also provides a data register tag

word that improves context switching and stack perfor-

mance by maintaining empty/non-empty status for each of

the eight data registers. In addition, registers contain

pointers to (a) the memory location containing the current

instruction word and (b) the memory location containing

the operand associated with the current instruction word

(if any).

3.15.4 FPU Mode Control Register

The FPU Mode Control Register (MCR) shown in Table 3-

39 on page 90 is used by the GXm processor to specify

the operating mode of the FPU. The MCR register fields

include information related to the rounding mode selected,

the amount of precision to be used in the calculations, and

the exception conditions which should be reported to the

GXm processor using traps. The user controls precision,

rounding, and exception reporting by setting or clearing

appropriate bits in the MCR.

3.15.2 FPU Tag Word Register

The CPU maintains a tag word register that is divided into

eight tag word fields. These fields assume one of four val-

ues depending on the contents of their associated data

registers: Valid (00), Zero (01), Special (10), and Empty

(11). Note: Denormal, Infinity, QNaN, SNaN and unsup-

ported formats are tagged as “Special”. Tag values are

maintained transparently by the CPU and are only avail-

able to the programmer indirectly through the FSTENV and

FSAVE instructions. The tag word with tag fields for each

associated physical register, tag(n), is shown in Table 3-39

on page 90.

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Processor Programming (Continued)

Table 3-39. FPU Registers

Bit

Name

Description

FPU Tag Word Register (R/W) (Note)

15:14

13:12

11:10

9:8

TAG7

TAG6

TAG5

TAG4

TAG3

TAG2

TAG1

TAG0

TAG7: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

TAG6: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

TAG5: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

TAG4: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

TAG3: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

TAG2: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

TAG1: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

TAG0: 00 = Valid; 01 = Zero; 10 = Special; 11 = Empty.

7:6

5:4

3:2

1:0

FPU Status Register (R/W) (Note)

15

B

C3

S

Copy of ES bit (bit 7 this register)

14

Condition code bit 3

13:11

Top-of-Stack: Register number that points to the current TOS.

Condition code bits [2:0]

10:8

7

C[2:0]

ES

SF

P

Error indicator: Set to 1 if unmasked exception detected.

Stack Full: FPU Status Register: or invalid register operation bit.

Precision error exception bit

6

5

4

U

Underflow error exception bit

3

O

Overflow error exception bit

2

Z

Divide-by-zero exception bit

1

D

Denormalized-operand error exception bit

Invalid operation exception bit

0

I

FPU Mode Control Register (R/W) (Note)

15:12

11:10

RSVD

RC

Reserved: Set to 0.

Rounding Control Bits:

00 = Round to nearest or even

01 = Round towards minus infinity

10 = Round towards plus infinity

11 = Truncate

9:8

PC

Precision Control Bits:

00 = 24-bit mantissa

01 = Reserved

10 = 53-bit mantissa

11 = 64-bit mantissa

7:6

5

RSVD

Reserved: Set to 0.

P

U

O

Z

D

I

Precision error exception bit

FPU Mode Control Register

Overflow error exception bit

Divide-by-zero exception bit

Denormalized-operand error exception bit

Invalid-operation exception bit

4

3

2

1

0

Note: R/W only through the environment at store and restore commands.

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4.0 Integrated Functions

The Geode GXm processor integrates a memory control-

ler, graphics pipeline and display controller in a Unified

Memory Architecture (UMA). UMA simplifies system

designs and significantly reduces overall system costs

associated with high chip count, small footprint notebook

designs. Performance degradation in traditional UMA sys-

tems is reduced through the use of National Semiconduc-

tor’s Display Compression Technology (DCT).

Figure 4-1 shows the major functional blocks of the GXm

processor and how the internal bus interface unit operates

as the interface between the processor’s core units and

the integrated functions.

This section details how the integrated functions and inter-

nal bus interface unit operate and their respective regis-

ters.

Write-Back

Cache Unit

Integer

FPU

MMU

Unit

C-Bus

Internal Bus Interface Unit

X-Bus

Graphics

Pipeline

Memory

Controller

Display

Controller

PCI

Controller

Integrated

Functions

PCI Bus

SDRAM Port

CS5530

(CRT/LCD TFT)

Figure 4-1. Internal Block Diagram

Revision 3.1

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Integrated Functions (Continued)

4.1 INTEGRATED FUNCTIONS PROGRAMMING INTERFACE

The GXm processor performs mapping for the dedicated

cache, graphics pipeline, display controller, memory con-

troller, and graphics memory, including the frame buffer. It

maps these to high memory addresses or GXm processor

memory space. The base address for these is controlled

by the Graphics Configuration Register (GCR, Index B8h),

which specifies address bits [31:30] in physical memory.

cation of selectors that point to the GXm processor. The

processor may be accessed in protected mode by creat-

ing a selector with the physical address shown in Table 4-

1, and a limit of 16 MB. A selector with a 64 KB limit is

large enough to access all of the GXm processor’s regis-

ters and scratchpad RAM.

4.1.1 Graphics Control Register

Figure 4-2 on page 93 shows the address map for the

GXm processor. When accessing the GXm processor

memory space, address bits [29:24] must be zero. This

allows the GXm processor a linear address space with a

total of 16 MB. Address bit 23 divides this space into 8 MB

for control (bit 23 = 0) and 8 MB for graphics memory (bit

23 = 1). In control space, bits [22:16] are not decoded, so

the programmer should set them to zero. Address bit 15

divides the remaining 64 KB address space into scratch-

pad RAM and PCI access (bit 15 = 0) and control regis-

ters (bit 15 = 1).

The GXm processor incorporates graphics functions that

require registers to implement and control them. Most of

these registers are memory mapped and physically

located in the logical units they control. The mapping of

these units is controlled by this configuration register. The

Graphics Control Register (GCR, Index B8h) is I/O-

mapped because it must be accessed before memory

mapping can be enabled. Refer to Section 3.3.2.2 “Con-

figuration Registers” on page 47 for information on how to

access this register.

Device drivers must be responsible for performing physi-

cal-to-virtual memory-address translation, including allo-

Table 4-1. GCR Register

Bit

Name

Description

Index B8h

GCR Register (R/W)

Default Value = 00h

7:4

3:2

RSVD

SP

Reserved: Set to 0.

Scratchpad Size: Specifies the size of the scratchpad cache.

00 = 0 KB

01 = 2 KB

10 = 3 KB

11 = 4 KB

1:0

GX

GXm Base Address: Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, the

graphics memory (frame buffer, compression buffer, etc.) and the other memory mapped registers.

00 = Scratchpad RAM, Graphics Subsystem, and memory-mapped configuration registers are disabled.

01 = Scratchpad RAM and control registers start at GX_BASE = 40000000h.

10 = Scratchpad RAM and control registers start at GX_BASE = 80000000h.

11 = Scratchpad RAM and control registers start at GX_BASE = C0000000h.

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Integrated Functions (Continued)

Physical Address Map

FFFFFFFFh (4 GB)

MAX

ROM Access

(256 KB)

FFFC0000h

PCI Access

GX_BASE+1000000h

Graphics Memory

(Frame Buffer, etc.)

GX_BASE+800000h

SMM System Code

GX_BASE+400000h

GX_BASE+9000h

Power Management Registers

(See Table 6-1 on page 179)

GX_BASE+8500h

GX_BASE+8400h

GX_BASE+8300h

GX_BASE+8100h

Memory Controller Registers

(See Table 4-15 on page 108)

DRAM Map

FFFF FFFFh

MAX

Display Controller Registers

(See Table 4-29 on page 136)

Graphics Memory

(Frame Buffer, etc.)

Graphics Pipeline Registers

(See Table 4-24 on page 124)

Internal Bus IF Unit Registers

(See Table 4-9 on page 101)

GX_BASE+8000h

GX_BASE+1000h

PCI Access

Scratchpad

(See Table 4-5 on page 97)

PCI Access

GX_BASE (See Table

4-1 on page 92)

*GBADD or Top of DRAM

Extended Memory

100000h (1 MB)

*Top of DRAM

100000h (1 MB)

E8000h

Extended Memory

System BIOS

Video BIOS

Shadowed System BIOS

E8000h

Shadowed Video BIOS

E0000h

UMBs and

Expansion ROMs

UMBs and Expansion ROMs

C0000h

VGA/MDA

Frame Buffers

(Soft VGA and/or PCA/ISA)

SMM System Code

A0000h (640 KB)

Conventional Memory

0h

A0000h (640 KB)

0h

Conventional Memory

* See BC_DRAM_TOP Table 4-10 on page 101 or MC_GBASE_ADD on page 111.

Figure 4-2. Geode™ GXm Processor Memory Space

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Integrated Functions (Continued)

4.1.2 Control Registers

Graphics memory is allocated from system DRAM by the

system BIOS. The graphics memory size is programmed

by setting the graphics memory base address in the mem-

ory controller. Display drivers communicate with system

BIOS about resolution changes, to ensure that the correct

amount of graphics memory is allocated. When a graphics

resolution change requires an increased amount of graph-

ics memory, the system must be rebooted! The reason for

this restriction is that no mechanism exists to recover sys-

tem DRAM from the operating system without rebooting.

The control registers for the GXm processor use 32 KB of

the memory map, starting at GX_BASE+8000h (see Fig-

ure 4-2 on page 93). This area is divided into internal bus

interface unit, graphics pipeline, display controller, mem-

ory controller, and power management sections:

•

The internal bus interface unit maps 100h locations

starting at GX_BASE+8000h.

The graphics pipeline maps 200h locations starting at

GX_BASE+8100h.

Table 4-2. Display Resolution Skip Counts

The display controller maps 100h locations starting at

GX_BASE+8300h.

Screen

Pixel

Skip

The memory controller maps 100h locations starting at

GX_BASE+8400h

Resolution

Depth

Count

640x480

800x600

1024x768

8 bits

16 bits

8 bits

1024

2048

1024

2048

1024

2048

GX_BASE+8500h-8FFFh is dedicated to power

management registers for the serial packet transmis-

sion control, the user-defined power management

address space, Suspend Refresh, and SMI status for

Suspend/Resume.

16 bits

8 bits

The register descriptions are contained in the individual

subsections of this chapter. Accesses to undefined regis-

ters in the GXm processor control register space will not

cause a hardware error.

16 bits

4.1.3 Graphics Memory

The GXm processor’s graphics memory is mapped into 8

MB starting at GX_BASE+800000h. This area includes

the frame buffer memory and storage for internal display

controller state. The frame buffer is a linear map whose

size depends on the current resolution setup in the mem-

ory controller. Frame buffer scan lines are not contiguous

in many resolutions, so software that renders to the frame

buffer must use a skip count to advance between scan

lines. The display controller uses the graphics memory

that lies between scan lines for internal state. For this rea-

son, accessing graphics memory between the end of a

scan line and the start of another can cause display prob-

lems. The skip count for all supported resolutions is

shown in Table 4-2.

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Integrated Functions (Continued)

4.1.4 L1 Cache Controller

operations needed during a replacement or flush opera-

tion.

The GXm processor contains an on-board 16 KB unified

data/instruction L1 cache. It operates in write-back mode.

Since the memory controller is also on-board, the L1

cache requires no external logic to maintain coherency. All

DMA cycles automatically snoop the L1 cache. For

improved graphics performance, part of the L1 cache

operates as a scratchpad RAM to be used by the graphics

pipeline as a BLT Buffer.

The GXm processor will cache SMM regions. This speeds

up system management overhead to allow for hardware

emulation such as VGA.

The cache of the GXm processor provides the ability to

redefine 2 KB, 3 KB, or 4 KB of the L1 cache to be

scratchpad memory. The scratchpad area is memory

mapped to the upper memory region defined by the GCR

register (Index B8h). The valid bits for the scratchpad

RAM will always be true and the scratchpad RAM loca-

tions will never be flushed to memory. The scratchpad

RAM serves as a general purpose high speed RAM and

as a BLT buffer for the graphics pipeline. Incrementing

BLT buffer address registers have been added to enable

the graphics pipeline to access this memory as a BLT

buffer. A 16-byte line buffer dedicated to the graphics

pipeline accesses has been added to minimize graphics

interference with normal CPU operation.

The CD bit (Cache Disable, bit 30) in CR0 globally con-

trols the operating mode of the L1 cache. LCD and LWT,

Local Cache Disable and Local Write-through bits in the

Translation Lookaside Buffer, control the mode on a page-

by-page basis. Additionally, memory configuration control

can specify certain memory regions as non-cacheable.

If the cache is disabled, no further cache line fills occur.

However, data already present in the cache continues to

be used. For the cache to be completely disabled, the

cache must be invalidated with a WBINVD instruction

after the cache has been disabled.

Table 4-3 summarizes the registers contained in the L1

cache. These registers do not have default values and

must be initialized before use. Table 4-4 on page 96 gives

the register/bit formats.

Write-back caching improves performance by relieving

congestion on slower external buses. With four dirty bits,

the cache marks dirty locations on a double-word basis.

This further reduces the number of double-word bus write

Table 4-3. L1 Cache BitBLT Register Summary

Function

Mnemonic Name

L1_BB0_BASE

L1 Cache BitBLT 0 Base Address

Contains the address offset to the first byte of BLT Buffer 0 in the scratch-

pad memory.

L1_BB0_POINTER

L1 Cache BitBLT 0 Pointer

Contains the address offset to the current line of BLT Buffer 0 in the

scratchpad memory.

L1_BB1_BASE

L1 Cache BitBLT 1 Base Address

Contains the offset to the first byte of BLT Buffer 1 in the scratchpad mem-

ory.

L1_BB1_POINTER

L1 Cache BitBLT 1 Pointer

Contains the address offset to the current line of BLT Buffer 1 in the

scratchpad memory.

Note: For information on accessing these registers, refer to Section 4.1.6 “CPU_READ/CPU_WRITE Instructions”

on page 99.

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Integrated Functions (Continued)

Table 4-4. L1 Cache BitBLT Registers

Bit

Name

Description

L1_BB0_BASE Register (R/W)

Default Value = None

15:12

11:4

3:0

RSVD

INDEX

BYTE

Reserved: Set to 0.

BitBLT 0 Base Index: The index to the starting line of BLT Buffer 0.

BitBLT 0 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 0.

L1_BB0_POINTER Register (R/W)

Reserved: Set to 0.

Default Value = None

15:12

11:4

3:0

RSVD

INDEX

RSVD

BitBLT 0 Pointer Index: The index to the current line of BLT Buffer 0.

Reserved: Set to 0.

L1_BB1_Base Register (R/W)

15:12

11:4

3:0

RSVD

INDEX

BYTE

Reserved: Set to 0.

BitBLT 1 Base Index: The index to the starting line of BLT Buffer 1.

BitBLT 1 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 1.

L1_BB1_POINTER Register (R/W) Default Value = None

Reserved: Set to 0.

15:12

11:4

3:0

RSVD

INDEX

RSVD

BitBLT 1 Pointer Index: The index to the current line of BLT Buffer 1.

Reserved: Set to 0.

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Integrated Functions (Continued)

4.1.4.1 Scratchpad Memory

or the frame buffer. The graphics pipeline accesses the

BLT buffers for many common operations, including Bit-

BLT transfers, output primitives, and raster text. Display

drivers also use a small portion of the scratchpad as an

extended register file, since scratchpad read and write

accesses are very fast compared to normal memory oper-

ations.

The scratchpad RAM is a dedicated high-speed memory

cache that contains BLT buffers, SMM header, and a

scratchpad area for display drivers. It provides both L1

cache performance and a dedicated resource that cannot

be thrown out by other system activity. The configuration

of the scratchpad is based on graphics resolution and is

described in Table 4-5.

The virtualization software uses the scratchpad area to

store critical SMM information, including the SMI header

and SMM system state. No SMM code currently resides in

the scratchpad area, although this is an option for future

products.

The scratchpad memory is part of the on-chip L1 cache

memory. The memory size is controlled by bits in the GCR

register (Index B8h). The scratchpad memory can be dis-

abled, or sized to 2 KB, 3 KB, or 4 KB. The remaining L1

cache size is 16 KB minus the scratchpad size, and all of

the scratchpad area is subtracted from a single way.

When the BLT buffer pointer is used (refer to Table 4-8 on

page 99) addresses outside the scratchpad range will

wrap around back into the scratchpad RAM. Table 4-5

shows the allocation of scratchpad memory for the 2 KB

and 3 KB configurations of the scratchpad. The 2 KB con-

figuration uses GX_BASE+0800h to GX_BASE+1000h.

The scratchpad memory is used by display drivers and

virtualization software. Because this resource must be

tightly controlled to avoid conflicts, application software

and third-party drivers should avoid accesses to the

scratchpad area.

The

3 KB configuration uses GX_BASE+0400h to

GX_BASE+1000h. These configurations are fixed by the

system BIOS during boot and cannot be changed without

rebooting the system.

The display driver creates and manages two BLT buffers

from within the scratchpad area. These BLT buffers are

used to transfer source data from system memory into the

frame buffer, or for destination data from system memory

Table 4-5. Scratchpad Organization

2 KB Configuration

Offset

3 KB Configuration

Size

Offset

Size

Description

GX_BASE + 0EE0h

288 bytes

128 bytes

816 bytes

GX_BASE + 0EE0h

GX_BASE + 0E60h

GX_BASE + 0930h

GX_BASE + 0400h

288 bytes

128 bytes

1328 bytes

SMM scratchpad

Driver scratchpad

BLT Buffer 0

GX_BASE + 0E60h

GX_BASE + 0B30h

GX_BASE + 0800h

BLT Buffer 1

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Integrated Functions (Continued)

4.1.5 Display Driver Instructions

The GXm processor has four instructions to access pro-

cessor core registers. Table 4-6 shows these instructions.

enable or disable all of the graphics instructions. If the

scratchpad size bits are zero, meaning that none of the

cache is defined as scratchpad, then hardware will

assume that the graphics controller is not being used and

the graphics instructions will be disabled. Any other

scratchpad size will enable all of the new instructions.

Note that the base address of the memory map in the

GCR register can still be set up to allow access to the

memory controller registers.

Adding CPU instructions does not create a compatibility

problem for applications that may depend on receiving

illegal opcode traps. The solution is to make these instruc-

tions generate an illegal opcode trap unless a compatibil-

ity bit is explicitly set. The GXm processor uses the

scratchpad size field (bits [3:2] in GCR, Index B8h) to

Table 4-6. Display Driver Instructions

Syntax

Opcode

Description

BB0_RESET

BB1_RESET

CPU_WRITE

CPU_READ

0F3A

0F3B

0F3C

0F3D

Reset the BLT Buffer 0 pointer to the base.

Reset the BLT Buffer 1 pointer to the base.

Write data to CPU internal register.

Read data from CPU internal register.

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Integrated Functions (Continued)

4.1.6 CPU_READ/CPU_WRITE Instructions

destination. Both instructions always transfer 32 bits of

data.

The GXm processor has several internal registers that

control the BLT buffer and power management circuitry in

the dedicated cache subsystem. To avoid adding addi-

tional instructions to read and write these registers, the

GXm processor has a general mechanism to access inter-

nal CPU registers with reasonable performance. The

GXm processor has two special instructions to read and

write CPU registers: CPU_READ and CPU_WRITE. Both

instructions fetch a 32-bit register address from EBX as

shown in Table 4-7 and Table 4-8. CPU_WRITE uses EAX

for the source data, and CPU_READ uses EAX as the

These instructions work by initiating a special I/O transac-

tion where the high address bit is set. This provides a very

large address space for internal CPU registers.

The BLT buffer base registers define the starting physical

addresses of the BLT buffers located within the dedicated

L1 cache. The dedicated cache can be configured for up

to 4 KB, so 12 address bits are required for each base

address.

Table 4-7. CPU-Access Instructions

Syntax

Opcode

Registers

Length

CPU_WRITE

CPU_READ

0F3Ch

0F3Dh

EBX = 32-bit address, EAX = Source

2 bytes

EBX = 32-bit address, EAX = Destination

Table 4-8. Address Map for CPU-Access Registers

Register

EBX Address

Description

L1_BB0_BASE

L1_BB1_BASE

L1_BB0_POINTER

L1_BB1_POINTER

PM_BASE

FFFFFF0Ch

FFFFFF1Ch

FFFFFF2Ch

FFFFFF3Ch

FFFFFF6Ch

FFFFFF7Ch

BLT Buffer 0 base address (see Table 4-4 on page 96).

BLT Buffer 1 base address (see Table 4-4 on page 96).

BLT Buffer 0 pointer address (see Table 4-4 on page 96).

BLT Buffer 1 pointer address (see Table 4-4 on page 96).

Power management base address (see Table 6-3 on page 181).

Power management address mask (see Table 6-3 on page 181).

PM_MASK

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Integrated Functions (Continued)

4.2 INTERNAL BUS INTERFACE UNIT

The Geode GXm processor’s internal bus interface unit

provides control and interface functions to the internal C-

Bus (processor core, FPU, graphics pipeline, and L1

cache) and X-Bus (PCI controller, display controller, mem-

ory controller, and graphics accelerator) paths, provides

control for several sections of memory, and plays an

important part in the virtual VGA function.

4.2.2 A20M Support

The GXm processor provides an A20M bit in the

BC_XMAP_1 Register (GX_BASE+ 8004h[21]) to replace

the A20M# pin on the 486 microprocessor. When the

A20M bit is set high, all non-SMI accesses will have

address bit 20 forced to zero. External hardware must do

an SMI trap on I/O locations that toggle the A20M# pin.

The SMI software can then change the A20M bit as

desired.

The internal bus interface unit performs, without loss of

compatibility, the functions that previously required the

external pins IGNNE# and A20M#.

This maintains compatibility with software that depends

on wrapping the address at bit 20.

The internal bus interface unit provides configuration con-

trol for up to 20 different regions within system memory. It

provides 19 configurable memory regions in the address

space between 640 KB and 1 MB, with separate control

for read access, write access, cacheability, and PCI

access.

4.2.3 SMI Generation

The internal bus interface unit can generate SMI inter-

rupts whenever an I/O cycle in the VGA address range is

3B0h-3BFh and 3C0h-3CFh. An I/O cycle to 3D0h-3DFh

can be trapped. In case an external VGA card is present,

the Internal Bus Interface Unit default values will not gen-

erate an interrupt on VGA accesses. (Refer to Section

5.2.3.1 “SMI Generation” on page 168 for instructions on

how to configure the registers to generate the SMI inter-

rupt.)

The memory configuration control includes a top-of-mem-

ory register and hardware support for VGA emulation

plus, the capability to program 20 regions of the memory

map for different ROM configurations, and to locate mem-

ory-mapped I/O.

4.2.1 FPU Error Support

4.2.4 640 KB to 1 MB Region

The FERR# (floating point error) and IGNNE# (ignore

numeric error) pins of the 486 microprocessor have been

replaced with an IRQ13 (interrupt request 13) pin. In DOS

systems, FPU errors are reported by the external vector

13. This mode of operation is specified by clearing the NE

bit (bit 5) in the CR0 register. If the NE bit is active, the

IRQ13 output of the GXm processor is always driven inac-

tive. If the NE bit is cleared, the GXm processor drives

IRQ13 active when the ES bit (bit 7) in the FPU Status

Register is set high. Software must respond to this inter-

rupt with an OUT instruction of an 8-bit operand to F0h or

F1h. When the OUT cycle occurs, the IRQ13 pin is driven

inactive and the FPU starts ignoring numeric errors. When

the ES bit is cleared, the FPU resumes monitoring

numeric errors.

There are 19 configurable memory regions located

between 640 KB and 1 MB. Three of the regions are

A0000h-AFFFFh,

B0000h-B7FFFh,

and

B8000h-

BFFFFh. The area between C0000h and FFFFFh is

divided into 16 KB segments to form the remaining 16

regions. Each of these regions has four control bits to

allow any combination of read-access, write-access,

cache, and PCI-access capabilities (Table 4-11 on page

102).

In addition, each of the three regions defined in the

A0000h-BFFFh area of memory has a VGA control bit that

can cause the graphics pipeline to handle accesses to

that section of memory (see Table 5-3 on page 170).

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Integrated Functions (Continued)

4.2.5 Internal Bus Interface Unit Registers

The Internal Bus Interface Unit maps 100h locations start-

ing at GX_BASE+8000h. Refer to Section 4.1.2 “Control

Registers” on page 94 for instructions on accessing these

registers.

Table 4-9 summarizes the four 32-bit registers contained

in the Internal Bus Interface Unit and Table 4-10 gives the

register/bit formats.

Table 4-9. Internal Bus Interface Unit Register Summary

GX_BASE+

Memory Offset

Default

Value

Type

Name/Function

BC_DRAM_TOP

8000h-8003h

R/W

3FFFFFFFh

Top of DRAM: Contains the highest available address of system memory not

including the memory that is set aside for graphics memory, which corresponds to

1 GByte of memory. The largest possible value for the register is 3FFFFFFFh.

8004h-8007h

R/W

BC_XMAP_1

00000000h

Memory X-Bus Map Register 1 (A and B Region Control: Contains the region

control of the A and B regions and the SMI controls required for VGA emulation.

PCI access to internal registers and the A20M function are also controlled by this

register.

8008h-800Bh

800Ch-800Fh

R/W

BC_XMAP_2

00000000h

Memory X-Bus Map Register 2 (C and D Region Control): Contains region con-

trol fields for eight regions in the address range C0h through DCh.

BC_XMAP_3

Memory X-Bus Map Register 3 (E and F Region Control): Contains the region

control fields for memory regions in the address range E0h through FCh.

Table 4-10. Internal Bus Interface Unit Registers

Bit

Name

Description

GX_BASE+8000h-8003h

BC_DRAM_TOP Register (R/W)

Default Value = 3FFFFFFFh

Default Value = 00000000h

31:30

29:17

RSVD

Reserved: Set to 0.

TOP OF

DRAM

Top of DRAM: Maximum value is FFFh.

16:0

1FFFF

Granularity: Must be set to 1FFFFh (128 KB).

BC_XMAP_1 Register (R/W)

Reserved: Set to 0.

GX_BASE+8004h-8007h

31:29

28

RSVD

GEB8

Graphics Enable for B8 Region: Allow memory R/W operations for address range B8000h-BFFFFh be

directed to the graphics pipeline: 0 = Disable; 1 = Enable.

(Used for VGA emulation.)

27:24

B8

B8 Region: Region control field for address range B8000h-BFFFFh.

Note: Refer to Table 4-11 for decode.

Reserved: Set to 0.

23

22

RSVD

PRAE

PCI Register Access Enable: Allow PCI Slave to access internal registers on the X-Bus:

0 = Disable; 1 = Enable.

21

20

A20M

GEB0

Address Bit 20 Mask: Address bit 20 is always forced to a zero except for SMI accesses:

0 = Disable; 1 = Enable.

Graphics Enable for B0 Region: Allow memory R/W operations for address range B0000h-B7FFFh be

directed to the graphics pipeline: 0 = Disable; 1 = Enable.

(Used for VGA emulation.)

19:16

15

B0

B0 Region: Region control field for address range B0000h-B7FFFh.

Note: Refer to Table 4-11 for decode.

SMID

SMIC

SMIB

SMID: All I/O accesses for address range 3D0h-3DFh generate an SMI: 0 = Disable; 1 = Enable.

(Used for VGA virtualization.)

14

SMIC: All I/O accesses for address range 3C0h-3CFh generate an SMI: 0 = Disable; 1 = Enable.

(Used for VGA virtualization.)

13

SMIB: All I/O accesses for address range 3B0h-3BFh generate an SMI: 0 = Disable; 1 = Enable

(Used for VGA virtualization.)

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Integrated Functions (Continued)

Table 4-10. Internal Bus Interface Unit Registers (Continued)

Bit

Name

Description

12:8

7

RSVD

XPD

Reserved: Set to 0.

X-Bus Pipeline Disable: When cleared, the address for the next cycle can be driven on the internal X-

Bus before the completion of the data phase of the current cycle.

6

5

4

GNWS

XNWS

GEA

X-Bus Graphics Pipe No Wait State: Data driven on X-Bus from graphics pipeline:

0 = 1 full clock before X_DSX is asserted

1 = On the same clock in which X_RDY is asserted

X-Bus No Wait State: Data driven on X-Bus from Internal Bus Interface Unit:

0 = 1 full clock before X_DSX is asserted

1 = On the same clock in which X_RDY is asserted

Graphics Enable for A Region: Memory R/W operations for address range A0000h-AFFFFh are

directed to the graphics pipeline: 0 = Disable; 1 = Enable.

(Used for VGA emulation.)

3:0

A0

A0 Region: Region control field for address range A0000h-AFFFFh.

Note: Refer to Table 4-11 for decode.

GX_BASE+8008h-800Bh

BC_XMAP_2 Register (R/W)

Default Value = 00000000h

31:28

27:24

23:20

19:16

15:12

11:8

DC

D8

D4

D0

CC

C8

C4

C0

DC Region: Region control field for address range DC000h to DFFFFh.

D8 Region: Region control field for address range D8000h to DBFFFh.

D4 Region: Region control field for address range D4000h to D7FFFh.

D0 Region: Region control field for address range D0000h to D3FFFh.

CC Region: Region control field for address range CC000h to CFFFFh.

C8 Region: Region control field for address range C8000h to CBFFF.

C4 Region: Region control field for address range C4000h to C7FFFh.

C0 Region: Region control field for address range C0000h to C3FFFh.

7:4

3:0

Note: Refer to Table 4-11 for decode.

GX_BASE+800Ch-800Fh

BC_XMAP_3 Register (R/W)

Default Value = 00000000h

31:28

27:24

23:20

19:16

15:12

11:8

FC

F8

F4

F0

EC

E8

E4

E0

FC Region: Region control field for address range FC000h to FFFFFh.

F8 Region: Region control field for address range F8000h to FBFFFh.

F4 Region: Region control field for address range F4000h to F7FFFh.

F0 Region: Region control field for address range F0000h to F3FFFh.

EC Region: Region control field for address range EC000h to EFFFFh.

E8 Region: Region control field for address range E8000h to EBFFFh.

E4 Region: Region control field for address range E4000h to E7FFFh.

E0 Region: Region control field for address range E0000h to E3FFFh.

7:4

3:0

Note: Refer to Table 4-11 for decode.

Table 4-11. Region-Control-Field Bit Definitions

Bit

Position Function

3

PCI Accessible: The PCI slave can access this memory if this bit is set high and if the appropriate Read or Write Enable

bit is also set high.

2

1

Cache Enable: Caching this region of memory is inhibited if this bit is cleared.

Write Enable: Write operations to this region of memory are allowed if this bit is set high. If this bit is cleared, then write

operations in this region are directed to the PCI master.

0

Read Enable: Read operations to this region of memory are allowed if this bit is set high. If this bit is cleared then read

operations in this region are directed to the PCI master.

Note: If Cache Enable = 1 and Write Enable = 1, the Write Enable determination occurs after the data has passed the cache. Since

the cache does write update, write data will change the cache if the address is cached. If a read then occurs to that address.

the data will come from the written data that is in the cache even though the address is not writable. If this must be avoided

then do not make the region cacheable.

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Integrated Functions (Continued)

4.3 MEMORY CONTROLLER

The memory controller operates with the Processor Inter-

face (X-Bus), Display Controller Interface, Graphics Pipe-

line Interface, and the SDRAM Interface.

MHz and 100 MHz. The core clock can be divided down

from two to five in half clock increments to generate the

SDRAM clock. SDRAM frequencies between 79 MHz and

100 MHz are only supported for certain types of closed

systems and strict design rules must be adhered to. For

further details, please contact your local National Semi-

conductor technical support representative.

The GXm processor supports LVTTL (low voltage TTL)

technology. LVTTL technology allows the SDRAM inter-

face of the memory controller to run at frequencies up to

100 MHz.

A basic block diagram of the memory controller is shown

in Figure 4-3.

The SDRAM clock is a function of the core clock. The

SDRAM bus can be run at speeds that range between 66

REF

Processor/PCI

Processor I/F

Control

DQM[7:0]

RASA#,RASB#

SDRAM

Sequence

Controller

CASA#,CASB#

CS[3:0]#

Display Controller

Timing

Controller

Display Controller I/F

Graphics Pipeline I/F

Arbiter

Control

WEA#/WEB#

CKEA#, CKEB#

Graphics Pipeline

Control

Configuration

Registers

Processor/PCI Address

MA[12:0]

BA[1:0]

Address

Control/MUX

Display Controller Address

Graphics Pipeline Address

Processor/PCI

Write Buffer (16 Bytes)

Processor/PCI Data

Display Controller Data

Graphics Pipeline Data

Display Controller

Write Buffer (16 Bytes)

MD[63:0]

Graphics Controller

Write Buffer (16 Bytes)

Read Buffer

(16 Bytes)

Clock Divider

2, 2.5, 3, 3.5, 4

Core Clock (ph2)

SDCLK[3:0]

Figure 4-3. Memory Controller Block Diagram

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103

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Integrated Functions (Continued)

4.3.1 Memory Array Configuration

component banks. Component bank selection is done

through the bank address (BA) lines.

The memory controller supports up to two 64-bit, 168-pin

unbuffered SDRAM modules (DIMM). Each DIMM

receives a unique set of RAS, CAS, WE, and CKE lines.

Each DIMM can have one or two 64-bit DIMM banks.

Each DIMM bank is selected by a unique chip select (CS).

There are four chip select signals to choose between a

total of four DIMM banks. Each DIMM bank also receives

a unique SDCLK. Each DIMM bank can have two or four

For example, 16 Mb SDRAMS have two component

banks and 64 Mb SDRAMs have two or four component

banks. For single DIMM bank modules, the memory con-

troller can support two DIMMS with a maximum of eight

component banks. For dual DIMM bank modules, the

memory controller can support two DIMMs with a maxi-

mum of 16 component banks. Up to 16 banks can be

open at the same time.

DIMM 0

Bank 0

Bank 1

MA[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RASA#

CASA#

WEA#

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

CAS#

WE#

CAS#

WE#

CS0#

S0#, S2#

CS1#

CKEA

S1#, S3#

CKE1

CKE0

SDCLK0

SDCLK1

CK0, CK2

CK1, CK3

Geode™ GXm

Processor

DIMM 1

Bank 0

Bank 1

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

A[12:0]

BA[1:0]

MD[63:0]

DQM[7:0]

RAS#

RASB#

CASB#

WEB#

CAS#

WE#

CAS#

WE#

CS2#

S0#, S2#

CS3#

CKEB

S1#, S3#

CKE1

CKE0

SDCLK2

SDCLK3

CK0, CK2

CK1, CK3

Figure 4-4. Memory Array Configuration

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Integrated Functions (Continued)

4.3.2 Memory Organizations

The memory controller supports JEDEC standard synchronous DRAMs in 16 Mb and 64 Mb configurations. Supported

configurations are shown in Table 4-12.

Table 4-12. Synchronous DRAM Configurations

Row

Bank

Total # of

Depth

Organization

Address

Column Address

Address

Address bits

1

2

1 Mx16

2 Mx8

A10-A0

A11-A0

A12-A0

A10-A0

A11-A0

A12-A0

A10-A0

A11-A0

A12-A0

A11-A0

A12-A0

A11-A0

A12-A0

A11-A0

A12-A0

A7-A0

A8-A0

A7-A0

A8-A0

A6-A0

A9-A0

A7-A0

A9-A0

A8-A0

A7-A0

A9-A0

A8-A0

A9-A0

A9-A0,A11

BA0

20

21

22

23

24

25

26

2 Mx32

4 Mx4

BA1-BA0

BA0

BA1-BA0

BA0

4

8

BA0

4 Mx16

8 Mx8

BA1-BA0

BA0

BA1-BA0

BA0

8 Mx8

8 Mx32

16 Mx4

16 Mx16

32 Mx8

64 Mx4

BA1-BA0

BA0

16

BA1-BA0

32

64

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Integrated Functions (Continued)

4.3.3 SDRAM Commands

MRS — The Mode Register command defines the specific

mode of operation of the SDRAM. This definition includes

the selection of burst length, burst type, and CAS latency.

CAS latency is the delay, in clock cycles, between the reg-

istration of a read command and the availability of the first

piece of output data.

This subsection discusses the SDRAM commands sup-

ported by the memory controller. Table 4-13 summarizes

these commands followed by detailed operational infor-

mation regarding each command.

The burst length is programmed by address bits MA[2:0],

the burst type by address bit MA3 and the CAS latency by

address bits MA[6:4].

Table 4-13. Basic Command Truth Table

Name

Command

CS RAS CAS WE

MRS

PRE

ACT

Mode Register Set

Bank Precharge

L

H

L

The memory controller only supports a burst length of two

and burst type of interleave.

Bank activate/row-

address entry

H

The field value on MA[12:0] and BA[1:0] during the MRS

cycle are as shown in Table 4-14.

WRT

Column address

entry/Write operation

L

H

X

L

X

L

H

X

H

PRE — The precharge command is used to deactivate

the open row in a particular bank or the open row in both

component banks. Address pin MA10 determines whether

one or both banks are to be precharged. In the case

where only one component bank is to be precharged,

BA[1:0] selects which bank. Once a bank has been pre-

charged, it is in the Idle state and must be activated prior

to any read or write commands.

READ

DESL

Column address

entry/Read operation

Control input inhibit/

No operation

H

L

REFR* CBR Refresh or Auto

Refresh

Note: *This command is CBR (CAS-before-RAS) refresh

when CKE is high and self refresh when CKE is low.

Table 4-14. Address Line Programming during MRS Cycles

BA[1:0]

MA[12:7]

MA[6:4]

MA3

MA2

MA1

MA0

00

000000

CAS Latency:

1

0

1

000 = Reserved

010 = 2 CLK

100 = 4 CLK

110 = 6 CLK

001 = 1 CLK

011 = 3 CLK

101 = 5 CLK

111 = 7 CLK

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Integrated Functions (Continued)

ACT — The activate command is used to open a row in a

particular bank for a subsequent access. The value on the

BA lines selects the bank, and the address on the MA

lines selects the row. This row remains open for accesses

until a precharge command is issued to that bank. A pre-

charge command must be issued before opening a differ-

ent row in the same bank.

REF — Auto refresh is used during normal operation and

is analogous to the CAS-before-RAS (CBR) refresh in

conventional DRAMs.During auto refresh the address bits

are "don’t care". The memory controller precharges all

banks prior to an auto refresh cycle. Auto refresh cycles

are issued approximately 15 µs apart.

The self refresh command is used to retain data in the

SDRAMs even when the rest of the system is powered

down. The self refresh command is similar to an auto

refresh command except CKE is disabled (low). The

memory controller issues a self refresh command during

3V Suspend mode when all the internal clocks are

stopped.

READ — The read command is used to initiate a burst

read access to an active row. The value on the BA lines

select the component bank, and the address provided by

the MA lines select the starting column location. The

memory controller does not perform auto precharge dur-

ing read operations. Valid data-out from the starting col-

umn address is available following the CAS latency after

the read command. The DQM signals are asserted low

during read operations.

4.3.3.1 SDRAM Initialization Sequence

After the clocks have started and stabilized, the memory

controller SDRAM initialization sequence begins:

WRT — The write command is used to initiate a burst

write access to an active row. The value on the BA liens

select the component bank, and the address provided by

the MA lines select the starting column location. The

memory controller does not perform auto precharge dur-

ing write operations. This leaves the page open for subse-

quent accesses. Data appearing on the MD lines is

written to the DQM logic level appearing coincident with

the data. If the DQM signal is registered low, the corre-

sponding data will be written to memory. If the DQM is

driven high, the corresponding data will be ignored, and a

write will not be executed to that location.

1) Precharge all component banks

2) Perform eight refresh cycles

3) Perform an MRS cycle

4) Perform eight refresh cycles

This sequence is compatible with the majority of SDRAMs

available from the various vendors.

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Integrated Functions (Continued)

4.3.4 Memory Controller Register Description

The Memory Controller maps 100h locations starting at

GX_BASE+8400h. Refer to Section 4.1.2 “Control Regis-

ters” on page 94 for instructions on accessing these regis-

ters.

Table 4-15 summarizes the 32-bit registers contained in

the memory controller. Table 4-16 gives detailed regis-

ter/bit formats.

Table 4-15. Memory Controller Register Summary

GX_BASE+

Memory Offset

Type

Name/Function

Default Value

8400h-8403h

8404h-8407h

8408h-840Bh

R/W

MC_MEM_CNTRL1

248C0040h

Memory Controller Control Register 1: Memory controller configuration informa-

tion e.g., refresh interval, SDCLK ratio, etc.

R/W

MC_MEM_CNTRL2

00000801h

41104110h

Memory Controller Control Register 2: Memory controller configuration informa-

tion to control SDCLK.

MC_BANK_CFG

Memory Controller Bank Configuration: Contains the configuration information for

the each of the two DIMMs in the memory array. BIOS programs this register dur-

ing boot by running an autosizing routine on the memory.

840Ch-840Fh

8414h-8417h

R/W

MC_SYNC_TIM1

2A733225h

00000000h

Memory Controller Synchronous Timing Register 1: SDRAM memory timing

information - This register controls the memory timing of all four banks of DRAM.

BIOS programs this register based on the processor frequency and the SDCLK

divide ratio.

MC_GBASE_ADD

Memory Controller Graphics Base Address Register: This register sets the

graphics memory base address, which is programmable on 512 KB boundaries.

The display controller and the graphics pipeline generate a 20-bit DWORD offset

that is added to the graphics memory base address to form the physical memory

address. Typically, the graphics memory region is located at the top of physical

memory.

8418h-841Bh

841Ch-841Fh

R/W

MC_DR_ADD

00000000h

0000000xh

Memory Controller Dirty RAM Address Register: This register is used to set the

Dirty RAM address index for processor diagnostic access. This register should be

initialized before accessing the MC_DR_ACC register

MC_DR_ACC

Memory Controller Dirty RAM Access Register: This register is used to access

the Dirty RAM. A read/write to this register will access the Dirty RAM at the

address specified in the MC_DR_ADD register.

Table 4-16. Memory Controller Registers

Bit

Name

Description

GX_BASE+ 8400h-8403h

MC_MEM_CNTRL1 (R/W)

Default Value = 248C0040h

31:29

MDHDCTL

MD High Drive Control: Controls the high drive and slew rate of the memory data bus (MD[63:0]):

000 = Tristate

001 = Smallest drive strength

010 -110 = Represents gradual drive strength increase

111 = Highest drive strength

28:26

MABAHDCTL

MA/BA High Drive Control: Controls the high drive and slew rate of the memory address bus includ-

ing the memory bank address bus (MA[12:0] and BA[1:0]):

000 = Tristate

001 = Smallest drive strength

010 -110 = Represents gradual drive strength increase

111 = Highest drive strength

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Integrated Functions (Continued)

Table 4-16. Memory Controller Registers (Continued)

Bit

Name

Description

25:23

MEMHDCTL

Control High Drive/Slew Control: Controls the high drive and slew rate of the memory control sig-

nals (CASA#, CASB#, RASA#, RASB#, CKEA, CKEB, WEA#, WEA#, DQM[7:0], and CS[3:0]#):

000 = Tristate

001 = Smallest drive strength

010 -110 = Represents gradual drive strength increase

111 = Highest drive strength

22

21

RSVD

Reserved: Set to 0.

Reserved: Must be set to 0. Wait state on the X-Bus x_data during read cycles - for debug only.

SDRAM Clock Ratio: Selects SDRAM clock ratio:

20:18

SDCLKRATE

000 = Reserved

001 = ÷ 2

010 = ÷ 2.5

100 = ÷ 3.5

101 = ÷ 4

110 = ÷ 4.5

111 = ÷ 5

011 = ÷ 3 (Default)

Ratio does not take effect until the SDCLKSTRT bit (bit 17 of this register) transitions from 0 to 1.

17

SDCLKSTRT

Start SDCLK: Start operating SDCLK using the new ratio and shift value (selected in bits [20:18] of

this register): 0 = Clear; 1 = Enable.

This bit should be cleared every time before a one is written to it in order to start SDCLK or to change

the shift value.

16:8

7:6

RFSHRATE

RFSHSTAG

Refresh Interval: This field determines the number of processor core clocks multiplied by 64 between

refresh cycles to the DRAM. By default, the refresh interval is 00h. This implies that refresh is turned

off by default.

Refresh Staggering: This field determines number of clocks between REF commands to different

banks during refresh cycles:

00 = 0 SDRAM clocks

01 = 1 SDRAM clocks (Default)

10 = 2 SDRAM clocks

11 = 4 SDRAM clocks

Staggering is used to help reduce power spikes during refresh. When only DIMM0 is installed and it

has only one DIMM bank, then this field must be set to 00.

5

2CLKADDR

Two Clock Address Setup: Assert memory address for one extra clock before CS# is asserted:

0 = Disable; 1 = Enable.

This can be used to compensate for address setup at high frequencies.

4

3

RFSHTST

XBUSARB

Test Refresh: This bit, when set high, generates a refresh request. This bit is only used for testing

purposes.

X-Bus Round Robin: When enabled, processor requests are arbitrated at the same priority level than

graphics pipeline requests and non-critical display controller requests. When disabled, processor

requests are arbitrated at a higher priority level. High priority display controller requests always have

the highest arbitration priority: 0 = Enable; 1 = Disable.

2

VGAWRP

VGA Wrap Enable: Allow memory wrapping into the VGA memory address space from A0000h to

BFFFFh: 0 = Disable; 1 = Enable.

1

0

RSVD

Reserved: Set to 0.

SDRAMPRG

Program SDRAM: When this bit is set the memory controller will program the SDRAM MRS register

using LTMODE in MC_SYNC_TIM1.

This bit should be cleared every time before a one is written to it in order to program the SDRAM.

GX_BASE+8404h-8407h

MC_MEM_CNTRL2 (R/W)

Default Value = 00000801h

31:18

17:16

RSVD

Reserved: Set to 0.

SDCLKRISE

SDCLK Rising Delay: Controls the delay between the core clock and the rising edge of SDCLK dur-

ing all modes. (Set by BIOS.)

15:14

13:11

SDCLKFALL

SDCLK Falling Delay: Controls the delay between the core clock and the falling edge of SDCLK dur-

ing 2.5 and 3.5 clock modes. (Set by BIOS.)

SDCLKHDCTL SDCLK High Drive/Slew Control: Controls the high drive and slew rate of SDCLK[3:0] and

SDCLK_OUT.

000 = Highest drive strength. (No braking applied in the pads)

001 = Smallest drive strength

010 -110 = Represent gradual drive strength increase

111 = Highest drive strength

10

SDCLKOMSK

Mask SDCLK_OUT: 0 = Not masked; 1 = Mask.

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Integrated Functions (Continued)

Table 4-16. Memory Controller Registers (Continued)

Bit

Name

Description

9

8

SDCLK3MSK

SDCLK2MSK

SDCLK1MSK

SDCLK0MSK

SHFTSDCLK

Mask SDCLK3: 0 = Not masked; 1 = Mask.

Mask SDCLK2: 0 = Not masked; 1 = Mask

Mask SDCLK1: 0 = Not masked; 1 = Mask.

Mask SDCLK0: 0 = Not masked; 1 = Mask

7

6

5:3

Shift SDCLK: This function allows shifting SDCLK to meet SDRAM setup and hold time requirements.

The shift function will not take effect until the SDCLKSTRT bit (bit 17 of MC_MEM_CNTRL1) transi-

tions from 0 to 1:

000 = No shift

100 = Shift 2 core clocks

101 = Shift 2.5 core clocks

110 = Shift 3 core clocks

111 = Reserved

001 = Shift 0.5 core clock

010 = Shift 1 core clock

011 = Shift 1.5 core clock

Note: Refer to Figure 4-10 for an example of SDCLK shifting.

Reserved: Set to 0.

2

1

RSVD

RD

Read Data Phase: Selects if read data is latched one or two core clock after the rising edge of

SDCLK: 0 = 1 core clock; 1 = 2 core clocks.

0

FSTRDMSK

Fast Read Mask: Do not allow core reads to bypass the request FIFO: 0 = Disable; 1 = Enable.

GX_BASE+8408h-840Bh

MC_BANK_CFG (R/W)

Default Value = 41104110h

31

30

RSVD

Reserved: Set to 0.

DIMM1_

DIMM1 Module Banks: Selects the number of module banks per DIMM for DIMM1:

MOD_BNK

0 = 1 Module bank

1 = 2 Module banks

29

28

RSVD

Reserved: Set to 0.

DIMM1_

DIMM1 Component Banks: Selects the number of component banks per module bank for DIMM1:

COMP_BNK

0 = 2 Component banks

1 = 4 Component banks

27

RSVD

Reserved: Set to 0.

26:24

DIMM1_SZ

DIMM1 Size: Selects the size of DIMM1:

000 = 4 MB

001 = 8 MB

010 = 16 MB

011 = 32 MB

100 = 64 MB

101 = 128 MB

110 = 256 MB

111 = 512 MB

23

RSVD

Reserved: Set to 0.

22:20

DIMM1_PG_SZ DIMM1 Page Size: Selects the page size of DIMM1:

000 = 1 KB

001 = 2 KB

010 = 4 KB

011 = 8 KB

1xx = 16 KB

111 = DIMM1 not installed

When DIMM1 is not installed, program all other DIMM1 fields to 0.

Reserved: Set to 0.

19:15

14

RSVD

DIMM0_

DIMM0 Module Banks: Selects number of module banks per DIMM for DIMM0:

MOD_BNK

0 = 1 Module bank

1 = 2 Module banks

13

12

RSVD

Reserved: Set to 0.

DIMM0_

DIMM0 Component Banks: Selects the number of component banks per module bank for DIMM0:

COMP_BNK

0 = 2 Component banks

1 = 4 Component banks

11

RSVD

Reserved: Set to 0.

10:8

DIMM0_SZ

DIMM0 Size: Selects the size of DIMM1:

000 = 4 MB

001 = 8 MB

010 = 16 MB

011 = 32 MB

100 = 64 MB

101 = 128 MB

110 = 256 MB

111 = 512 MB

7

RSVD

Reserved: Set to 0.

6:4

DIMM0_PG_SZ DIMM0 Page Size: Selects the page size of DIMM0:

000 = 1 KB

001 = 2 KB

010 = 4 KB

011 = 8 KB

1xx = 16 KB

111 = DIMM0 not installed

When DIMM0 is not installed, program all other DIMM0 fields to 0.

3:0

RSVD

Reserved: Set to 0.

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Integrated Functions (Continued)

Table 4-16. Memory Controller Registers (Continued)

Bit

Name

Description

GX_BASE+840Ch-840Fh

MC_SYNC_TIM1 (R/W)

Default Value = 2A733225h

31

RSVD

Reserved: Set to 0.

30:28

LTMODE

CAS Latency (LTMODE): CAS latency is the delay, in clock cycles, between the registration of a read

command and the availability of the first piece of output data (BIOS interrogates EEPROM across the

2

I C interface to determine this value):

000 = Reserved

001 = 1 CLK

010 = 2 CLK

011 = 3 CLK

100 = 4 CLK

101 = 5 CLK

110 = 6 CLK

111 = 7 CLK

This field will not take effect until SDRAMPRG (bit 0 of MC_MEM_CNTRL1) transitions from 0 to 1.

ERRATA: CAS Latency of 1 CLK is not currently supported.

27:24

23:20

RC

REF to REF/ACT Command Period (tRC): Minimum number of SDRAM clock between REF and

REF/ACT commands:

0000 = Reserved 0100 = 5 CLK

1000 = 9 CLK

1001 = 10 CLK

1010 = 11 CLK

1011 = 12 CLK

1100 = 13 CLK

1101 = 14 CLK

1110 = 15 CLK

1111 = 16 CLK

0001 = 2 CLK

0010 = 3 CLK

0011 = 4 CLK

0101 = 6 CLK

0110 = 7 CLK

0111 = 8 CLK

RAS

ACT to PRE Command Period (tRAS): Minimum number of SDRAM clocks between ACT and PRE

commands:

0000 = Reserved 0100 = 5 CLK

1000 = 9 CLK

1001 = 10 CLK

1010 = 11 CLK

1011 = 12 CLK

1100 = 13 CLK

1101 = 14 CLK

1110 = 15 CLK

1111 = 16 CLK

0001 = 2 CLK

0010 = 3 CLK

0011 = 4 CLK

0101 = 6 CLK

0110 = 7 CLK

0111 = 8 CLK

19

RSVD

RP

Reserved: Set to 0.

18:16

PRE to ACT Command Period (tRP): Minimum number of SDRAM clocks between PRE and ACT

commands:

000 = Reserved

001 = 1 CLK

010 = 2 CLK

011 = 3 CLK

100 = 4 CLK

101 = 5 CLK

110 = 6 CLK

111 = 7 CLK

15

RSVD

RCD

Reserved: Set to 0.

14:12

Delay Time ACT to READ/WRT Command (tRCD): Minimum number of SDRAM clock between ACT

and READ/WRT commands:

000 = Reserved

001 = 1 CLK

010 = 2 CLK

011 = 3 CLK

100 = 4 CLK

101 = 5 CLK

110 = 6 CLK

111 = 7 CLK

11

RSVD

RRD

Reserved: Set to 0.

10:8

ACT(0) to ACT(1) Command Period (tRRD): Minimum number of SDRAM clocks between ACT and

ACT command to two different component banks within the same module bank. The memory control-

ler does not perform back-to-back Activate commands to two different component banks without a

READ or WIRTE command between them. Hence, this field should be set to 001.

7

RSVD

DPL

Reserved: Set to 0.

6:4

Data-in to PRE command period (tDPL): Minimum number of SDRAM clocks from the time the last

write datum is sampled till the bank is precharged:

000 = Reserved

001 = 1 CLK

010 = 2 CLK

011 = 3 CLK

100 = 4 CLK

101 = 5 CLK

110 = 6 CLK

111 = 7 CLK

3:0

RSVD

Reserved: Set to 0 or leave unchanged.

MC_GBASE_ADD (R/W)

GX_BASE+8414h-8417h

Default Value = 00000000h

31:18

17

RSVD

TE

Reserved: Set to 0.

Test Enable TEST[3:0]:

0 = TEST[3:0] are driven low

1 = TEST[3:0] pins are used to output test information

16

TECTL

Test Enable Shared Control Pins:

0 = RASB#, CASB#, CKEB, WEB# are driven low

1 = RASB#, CASB#, CKEB, WEB# are used to output test information

Select: This field is used for debug purposes only.

Reserved: Set to 0.

15:12

11

SEL

RSVD

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Integrated Functions (Continued)

Table 4-16. Memory Controller Registers (Continued)

Bit

Name

Description

10:0

GBADD

Graphics Base Address: This field indicates the graphics memory base address, which is program-

mable on 512 KB boundaries. This field corresponds to address bits [29:19].

Note that BC_DRAM_TOP must be set to a value lower than the Graphics Base Address.

GX_BASE+8418h-841Bh

MC_DR_ADD (R/W)

Default Value = 00000000h

31:10

9:0

RSVD

Reserved: Set to 0.

DRADD

Dirty RAM Address: This field is the address index that is used to access the Dirty RAM with the

MC_DR_ACC register. This field does not auto increment.

GX_BASE+841Ch-841Fh

MC_DR_ACC (R/W)

Default Value = 0000000xh

31:2

1

RSVD

Reserved: Set to 0.

D

V

Dirty Bit: This bit is read/write accessible.

Valid Bit: This bit is read/write accessible.

0

4.3.5 Address Translation

4.3.5.3 Physical Address to DRAM Address

Conversion

The memory controller supports two address translations

depending on the method used to interleave pages.

Auto LOI is in effect whenever the two DIMMs have the

same number of DIMM banks, component banks, module

sizes and page sizes.

4.3.5.1 High Order Interleaving

High Order Interleaving (HOI) uses the most significant

address bits to select which bank the page is located in.

This has the effect of allowing any mixture of DIMM types.

However, it spreads the pages over wide address ranges.

For example, two 8 MB DIMMs contain a total of four com-

ponent pages. Two pages are together in one DIMM sepa-

rated from the other two pages by 8 MB.

Tables 4-17 and Table 4-18 on page 113 give Auto LOI

address conversion examples when two DIMMs of the

same size are used in a system. Table 4-17 shows a one

DIMM bank conversion example, while Table 4-18 shows

a two DIMM bank example.

Table 4-19 and Table 4-20 on page 114 give Non-Auto LOI

address conversion examples when either one or two

DIMMs of different sizes are used in a system. Table 4-19

shows a one DIMM bank address conversion example,

while Table 4-20 shows a two DIMM bank example. The

addresses are computed on a per DIMM basis.

4.3.5.2 Low Order Interleaving

Low Order Interleaving (LOI) uses the least significant bits

after the page bits to select which bank the page is

located in. This requires that memory is a power of 2, that

the number of banks is a power of 2, and that the page

sizes are the same. In other words, the DIMMs have to be

of the same type. However, LOI does give a good benefit

by providing a moving page throughout memory. Using

the same example as above, two banks would be on one

DIMM and the next two banks would be on the second

DIMM, but they would be linear in address space. For an

eight bank system that has 1 KB address (8 KB data)

pages, there would be an effective moving page of 64 KB

of data.

Since the DRAM interface is 64 bits wide, the lower three

bits of the physical address get mapped onto the

DQM[7:0] lines. Thus, the address conversion tables

(Tables 4-17 through 4-20) show the physical address

starting from A3.

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Integrated Functions (Continued)

Table 4-17. Auto LOI -- 2 DIMMs, Same Size, 1 DIMM Bank

1 K Page Size

2 K Page Size

Row Col

2 Component Banks

4 K Page Size

1 K Page Size

2 K Page Size

Row Col

4 Component Banks

4 Page Size

Row

Col

Row

Col

Row

Col

Row

Col

Address

MA12

MA11

MA10

MA9

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

--

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

--

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

--

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

--

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

--

A9

A8

A7

A6

A5

A4

A3

A8

A7

A6

--

MA8

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

MA7

--

A10

A9

A8

A7

A6

A5

A4

A3

A10

A9

A8

A7

A6

A5

A4

A3

MA6

A9

A8

A7

A6

A5

A4

A3

MA5

MA4

MA3

MA2

MA1

MA0

CS0#/CS1#

CS2#/CS#3

BA0/BA1

A11

--

A12

--

A13

--

A12

--

A13

--

A14

--

A10

A11

A12

A11/A10

A12/A11

A13/A12

Table 4-18. Auto LOI -- 2 DIMMs, Same Size, 2 DIMM Banks

1 K Page Size

2 K Page Size

Row Col

2 Component Banks

4 K Page Size

1 K Page Size

2 Page Size

Row Col

4 Component Banks

4 K Page Size

Row

Col

Row

Col

Row

Col

Row

Col

Address

MA12

MA11

MA10

MA9

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

--

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

--

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

--

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

--

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

--

MA8

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

MA7

--

A10

A9

A8

A7

A6

A5

A4

A3

--

A10

A9

A8

A7

A6

A5

A4

A3

MA6

A9

A8

A7

A6

A5

A4

A3

A9

A8

A7

A6

A5

A4

A3

MA5

MA4

MA3

MA2

MA1

MA0

CS0#/CS1#

CS2#/CS3#

BA0/BA1

A12

A11

A10

A13

A12

A11

A14

A13

A12

A13

A12

A14

A13

A15

A14

A11/A10

A12/A11

A13/A12

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Integrated Functions (Continued)

Table 4-19. Non-Auto LOI -- 1 or 2 DIMMs, Different Sizes, 1 DIMM Bank

1 K Page Size

2 K Page Size

Row Col

2 Component Banks

4 K Page Size

1 K Page Size

2 K Page Size

Row Col

4 Component Banks

4 K Page Size

Row

Col

Row

Col

Row

Col

Row

Col

Address

MA12

MA11

MA10

MA9

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

--

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

--

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

--

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

--

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

--

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

--

MA8

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

MA7

--

A10

A9

A8

A7

A6

A5

A4

A3

--

A10

A9

A8

A7

A6

A5

A4

A3

MA6

A9

A8

A7

A6

A5

A4

A3

A9

A8

A7

A6

A5

A4

A3

MA5

MA4

MA3

MA2

MA1

MA0

CS0#/CS1#

CS2#/CS3#

BA0/BA1

--

A10

A11

A12

A11/A10

A12/A11

A13/A12

Table 4-20. Non-Auto LOI -- 1 or 2 DIMMs, Different Sizes, 2 DIMM Banks

1 K Page Size

2 K Page Size

Row Col

2 Component Banks

4 K Page Size

1 K Page Size

2 K Page Size

Row Col

4 Component Banks

4 K Page Size

Row

Col

Row

Col

Row

Col

Row

Col

Address

MA12

MA11

MA10

MA9

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

--

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

--

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

--

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

--

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

--

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

--

MA8

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

--

A11

A10

A9

A8

A7

A6

A5

A4

A3

MA7

--

A10

A9

A8

A7

A6

A5

A4

A3

--

A10

A9

A8

A7

A6

A5

A4

A3

MA6

A9

A8

A7

A6

A5

A4

A3

A9

A8

A7

A6

A5

A4

A3

MA5

MA4

MA3

MA2

MA1

MA0

CS0#/CS1#

CS2#/CS3#

BA0/BA1

A11

--

A12

--

A13

A12

A13

A14

A10

A11

A11/A10

A12/A11

A13/A12

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Integrated Functions (Continued)

4.3.6 Memory Cycles

SDRAM Read Cycle

Figures 4-5 through Figure 4-8 on page 117 illustrate vari-

ous memory cycles that the memory controller supports.

The following subsections describe some of the sup-

ported cycles.

Figure 4-5 shows a SDRAM read cycle. The figure

assumes that a previous ACT command has presented

the row address for the read operation. Note that the burst

length for the READ command is always two.

SDCLK

CS#

RAS#

CAS#

WE#

MA

DQM

MD

COL n

n

n+1

Figure 4-5. Basic Read Cycle with a CAS Latency of Two

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Integrated Functions (Continued)

SDRAM Write Cycle

Figure 4-6 shows a SDRAM write cycle. The burst length for the WRT command is 2.

SDCLK

CS#

RAS#

CAS#

WE#

MA

MD

COL n

n

n+1

DQM

Figure 4-6. Basic Write Cycle

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Integrated Functions (Continued)

SDRAM Refresh Cycle

Page Miss

Figure 4-7 shows a SDRAM auto refresh cycle. The mem-

ory controller always precedes the refresh cycle with a

PRE command to all banks.

Figure 4-8 shows a Read/WRT command after a page

miss cycle. In order to program the new row address, a

PRE command must be issued followed by an ACT com-

mand.

SDCLK

CS#

RAS#

CAS#

WE#

MA[10]

Figure 4-7. Auto Refresh Cycle

SDCLK

COMMAND

PRE

BA

NOP

ACT

NOP

R/W

COL

NOP

tRCD

tRP

ADDRESS

ROW

Figure 4-8. Read/WRT Command to a New Row Address

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117

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Integrated Functions (Continued)

4.3.7 SDRAM Interface Clocking

The delay for SDCLKIN must be designed so that it lags

the SDCLKs at the DRAM by approximately 2ns. The

delay should also include the SDCLK transmission line

delay. The SDCLK traces on the board need to be laid out

so there is no skew between each of the four sinks. These

guidelines allow the memory interface to be closer to the

DRAM specifications. They improve performance by run-

ning the SDCLK up to frequencies of 100 MHz and a CAS

latency of two.

The GXm processor drives the SDCLK to the SDRAMs;

one for each DIMM bank. All the control, data, and

address signals driven by the memory controller are sam-

pled by the SDRAM at the rising edge of SDCLK. SDCLK-

OUT is a reference signal used to generate SDCLKIN.

Read data is sampled by the memory controller at the ris-

ing edge of SDCLKIN.

SDCLK0

DIMM

SDCLK[3:0]

0

SDCLK1

SDCLKOUT

SDCLK2

DIMM

Geode™ GXm

1

SDCLK3

Delay

Processor

SDCLKIN

Figure 4-9. SDCLKIN Clocking

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The SDRAM interface timings are programmable. The

SHFTSDCLK bits in the MC_MEM_CNTRL2 register can

be used to change the relationship between SDCLK and

the control/address/data signals. To meet setup and hold

time requirements for SDRAM across different board lay-

outs, the SHFTSDCLK bits are used. SHFTSDCLK bit val-

ues are selected based upon the SDRAM signals loads

and the core frequency (refer to Table 7-10 on page 190 ).

ler runs off this processor clock. The memory clock is gen-

erated by dividing down the processor clock. SDCLK is

generated from the memory clock. In the example dia-

gram, the processor clock is running 6X times the PCI

clock and the memory clock is running in divide by 3

mode.

The SDRAM control, address, and data signals are driven

off edge "x" of the memory clock to be setup before edge

"y". With no shift applied, the control signals could end up

being latched on edge "x". A shift value of two or three

could be used so that SDCLK at the SDRAM is centered

around when the control signals change.

Figure 4-10 shows an example of how the SHFTSDCLK

bits setting affects SDCLK. The PCI clock is the input

clock to the GXm processor. The core clock is the internal

processor clock that is multiplied up. The memory control-

PCI Clock

Core Clock

(Internal)

0

1

2

x

3

4

5

y

6

Memory

Clock

(Internal)

CNTRL

Valid

SDCLK

(Note)

x

y

SDCLK

(Note)

4

3

2

1

0

Shift =

Note: The first SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 000, no shift.

The second SDCLK shows how SDCLK operates with the SHFTSDCLK bits = 001, shift 0.5 core clock.

(See MC_MEMCNTRL2 bits [5:3], Table 4-16 on page 108 , for remaining decode values.)

Figure 4-10. Effects of SHFTSDCLK Programming Bits Example

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Integrated Functions (Continued)

4.4 GRAPHICS PIPELINE

The graphics pipeline of the GXm processor includes a

BitBLT/vector engine which has been optimized for

Microsoft Windows. The hardware supports pattern gen-

eration, source expansion, pattern/source transparency,

and 256 ternary raster operations. The block diagram of

the graphics pipeline is shown in Figure 4-11.

4.4.1 BitBLT/Vector Engine

BLTs are initiated by writing to the GP_BLT_MODE regis-

ter, which specifies the type of source data (none, frame

buffer, or BLT buffer), the type of the destination data

(none, frame buffer, or BLT buffer), and a source expan-

sion flag.

Scratchpad RAM

and

BitBLT Buffers

C-Bus

Graphics

Pipeline

Output Aligner

Pattern

Source

Hardware

Expansion

Internal Bus

Control Logic

Interface Unit

BE

PAT

BE

SRC

DST

Raster Operation

Register Access

DRAM Interface

X-Bus

Key:

BE = Byte Enable

PAT = Pattern Data

SRC = Source Data

DST = Destination Data

Memory

Controller

Figure 4-11. Graphics Pipeline Block Diagram

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Integrated Functions (Continued)

The BLT buffers in the dedicated cache temporarily store

source and destination data, typically on a scan line basis.

The hardware automatically loads frame-buffer data

(source or destination) into the BLT buffers for each scan

line. The software is responsible for making sure that this

does not overflow the memory allocated for the BLT buff-

ers. When the source data is a bitmap, the data is loaded

directly into the BLT buffer before starting the BLT.

pipeline registers will corrupt the values of the pending

BLT. Software must prevent this from happening by check-

ing the “BLT Pending” bit in the GP_BLT_STATUS register

(GX_BASE+820Ch[2].

Most of the graphics pipeline registers are latched directly

from the master registers to the slave registers when

starting a new BitBLT or vector operation. Some registers,

however, use the updated slave values if the master regis-

ters have not been written, which allows software to ren-

der successive primitives without loading some of the

registers as outlined in Table 4-21.

Vectors

are

initiated

by

writing

to

the

GP_VECTOR_MODE register (GX_BASE+8204h), which

specifies the direction of the vector and a “read destina-

tion data” flag. If the flag is set, the hardware will read

destination data along the vector and store it temporarily

in BLT Buffer 0.

4.4.3 Pattern Generation

The graphics pipeline contains hardware support for 8x8

monochrome patterns (expanded to two colors), 8x8

dither patterns (expanded to four colors), and 8x1 color

patterns. The pattern hardware, however, does not main-

tain a pattern origin, so the pattern data must be justified

before it is loaded into the GXm processor’s registers. For

solid primitives, the pattern hardware is disabled and the

4.4.2 Master/Slave Registers

When starting a BitBLT or vector operation, the graphics

pipeline registers are latched from the master registers to

the slave registers. A second BitBLT or vector operation

can then be loaded into the master registers while the first

operation is rendered. If a second BLT is pending in the

master registers, any write operations to the graphics

pattern

color

is

always

sourced

from

the

GP_PAT_COLOR_0 register (GX_BASE+8110h).

Table 4-21. Graphics Pipeline Registers

Function

Master

GP_DST_XCOOR

Next X position along vector.

Master register if written, otherwise:

Unchanged slave if BLT, source mode = bitmap.

Slave + width if BLT, source mode = text glyph

GP_DST_YCOOR

Next Y position along vector.

Master register if written, otherwise:

Slave +/- height if BLT, source mode = bitmap.

Unchanged slave if BLT, source mode = text glyph.

GP_INIT_ERROR

GP_SRC_YCOOR

Master register if written, otherwise:

Initial error for the next pixel along the vector.

Master register if written, otherwise:

Slave +/- height if BLT, source mode = bitmap.

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Integrated Functions (Continued)

4.4.3.1 Monochrome Patterns

4.4.3.2 Dither Patterns

Monochrome patterns are selected by setting the pattern

mode to 01b in the GP_RASTER_MODE register

(GX_BASE+ 8200h). Those pixels corresponding to a

clear bit (0) in the pattern are rendered using the color

specified in the GP_PAT_COLOR_0 register, and those

pixels corresponding to a set bit (1) in the pattern are ren-

dered using the color specified in the GP_PAT_COLOR_1

register (GX_BASE+8112h).

Dither patterns are selected by setting the pattern mode

to 10 b in the GP_RASTER_MODE register (Table 4-25

on page 125). Two bits of pattern data are used for each

pixel, allowing color expansion to four colors. The colors

are specified in the GP_PAT_COLOR_0 through

GP_PAT_COLOR_3 registers (Table 4-25 on page 125).

Dither patterns use all 128 bits of pattern data. Bits [15:0]

correspond to the first row of the pattern (the lower byte

contains the LSB of the pattern color and the upper byte

contains the MSB of the pattern color). This is illustrated

in Figure 4-13.

If the pattern transparency bit is set high in the

GP_RASTER_MODE register, those pixels corresponding

to a clear bit in the pattern data are not drawn.

Monochrome patterns use bits [63:0] of the pattern data.

Bits [7:0] correspond to the first row of the pattern, and bit

7 corresponds to the leftmost pixel on the screen. This is

illustrated in Figure 4-12.

GP_PAT_DATA_0 = 0x441100AA

GP_PAT_DATA_1 = 0x115500AA

GP_PAT_DATA_2 = 0x441100AA

GP_PAT_DATA_3 = 0x115500AA

GP_PAT_DATA_0 = 0x80412214

GP_PAT_DATA_1 = 0x08142241

00AA

4411

00AA

1155

00AA

4411

00AA

1155

14

22

41

80

41

22

14

08

Figure 4-13. Example of Dither Patterns

Figure 4-12. Example of Monochrome Patterns

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Integrated Functions (Continued)

4.4.3.3 Color Patterns

Table 4-22. GP_RASTER_MODE Bit Patterns

Color patterns are selected by setting the pattern mode to

11 b in the GP_RASTER_MODE register. Bits [63:0] are

used to hold a row of pattern data for an 8-BPP pattern,

with bits [7:0] corresponding to the leftmost pixel of the

row. Likewise, bits [127:0] are used for a 16-BPP color

pattern, with bits [15:0] corresponding to the leftmost pixel

of the row.

Pattern

(bit)

Source

(bit)

Destination

(bit)

Output

(bit)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ROP[0]

ROP[1]

ROP[2]

ROP[3]

ROP[4]

ROP[5]

ROP[6]

ROP[7]

To support an 8x8 color pattern, software must load the

pattern data for each row.

4.4.4 Source Expansion

The graphics pipeline contains hardware support for color

expansion of source data (primarily used for text). Those

pixels corresponding to a clear bit (0) in the source data

are rendered using the color specified in the

GP_SRC_COLOR_0 register (GX_BASE+810Ch), and

those pixels corresponding to a set bit (1) in the source

data are rendered using the color specified in the

GP_SRC_COLOR_1 register (GX_BASE+810Eh).

Table 4-23. Common Raster Operations

ROP

Description

If the source transparency bit is set in the

GP_RASTER_MODE register, those pixels corresponding

to a clear bit (0) in the source data are not drawn.

F0h

CCh

5Ah

66h

55h

Output = Pattern

Output = source

Output = Pattern XOR destination

Output = Source XOR destination

Output = ~Destination

4.4.5 Raster Operations

The GP_RASTER_MODE register specifies how the pat-

tern data, source data (color-expanded if necessary), and

destination data are combined to produce the output from

the graphics pipeline. The definition of the ROP valu

matches that of the Microsoft API. This allows Windows

display drivers to load the raster operation directly into

hardware. Table 4-22 illustrates this definition. Some com-

mon raster operations are described in Table 4-23.

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Integrated Functions (Continued)

4.4.6 Graphics Pipeline Register Descriptions

The graphics pipeline maps 200h locations starting at

GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-

ters” on page 94 for instructions on accessing these regis-

ters.

Table 4-24 summarizes the graphics pipeline registers

and Table 4-25 on page 125 gives detailed register/bit for-

mats.

Table 4-24. Graphics Pipeline Configuration Register Summary

GX_BASE+

Memory Offset

Type

Name / Function

Default Value

8100h-8103h

8104-8107h

8108h-810Bh

R/W

GP_DST/START_Y/XCOOR

00000000h

Destination/Starting Y and X Coordinates Register — In BLT mode this register

specifies the destination Y and X positions for a BLT operation. In Vector mode it

specifies the starting Y and X positions in a vector.

R/W

GP_WIDTH/HEIGHT and GP_VECTOR_LENGTH/INIT_ERROR

00000000h

Width/Height or Vector Length/Initial Error Register — In BLT mode this register

specifies the BLT width and height in pixels. In Vector mode it specifies the vector

initial error and pixel length.

GP_SRC_X/YCOOR and GP_AXIAL/DIAG_ERROR

Source X/Y Coordinate Axial/Diagonal Error Register — In BLT mode this register

specifies the BLT X and Y source. In Vector mode it specifies the axial and diago-

nal error for rendering a vector.

810Ch-810Fh

8110h-8113h

8114h-8117h

R/W

GP_SRC_COLOR_0 and GP_SCR_COLOR_1

00000000h

Source Color Register — Determines the colors used when expanding mono-

chrome source data in either the 8-BPP mode or the 16-BPP mode.

GP_PAT_COLOR_0 and GP_PAT_COLOR_1

Graphics Pipeline Pattern Color 0 and 1 Registers — These two registers deter-

mine the colors used when expanding pattern data.

GP_PAT_COLOR_2 and GP_PAT_COLOR_3

Graphics Pipeline Pattern Color 2 and 3 Registers — These two registers deter-

mine the colors used when expanding pattern data.

8120h-8123h

8124h-8127h

8128h-812Bh

812Ch-812Fh

R/W

GP_PAT_DATA 0 through 3

00000000h

Graphics Pipeline Pattern Data Registers 0 through 3 — Together these registers

contain 128 bits of pattern data.

GP_PAT_DATA_0 corresponds to bits [31:0] of the pattern data.

GP_PAT_DATA_1 corresponds to bits [63:32] of the pattern data.

GP_PAT_DATA_2 corresponds to bits [95:64] of the pattern data.

GP_PAT_DATA_3 corresponds to bits [127:96] of the pattern data.

GP_VGA_WRITE

8140h-8143h

(Note)

R/W

xxxxxxxxh

00000000h

Graphics Pipeline VGA Write Patch Control Register — Controls the VGA mem-

ory write path in the graphics pipeline.

8144h-8147h

(Note)

GP_VGA_READ

Graphics Pipeline VGA Read Patch Control Register — Controls the VGA mem-

ory read path in the graphics pipeline.

8200h-8203h

GP_RASTER_MODE

Graphics Pipeline Raster Mode Register — This register controls the manipula-

tion of the pixel data through the graphics pipeline. Refer to Section 4.4.5 “Raster

Operations” on page 123.

8204h-8207h

8208h-820Bh

R/W

GP_VECTOR_MODE

00000000h

Graphics Pipeline Vector Mode Register — Writing to this register initiates the

rendering of a vector.

GP_BLT_MODE

Graphics Pipeline BLT Mode Register — Writing to this initiates a BLT operation.

Note: The registers at GX_BASE+8140, 8144h, 8210h, and 8217h are located in the area designated for the graphics pipeline but

are used for VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

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Table 4-24. Graphics Pipeline Configuration Register Summary (Continued)

GX_BASE+

Memory Offset

Type

Name / Function

GP_BLT_STATUS

Default Value

820Ch-820Fh

R/W

00000000h

Graphics Pipeline BLT Status Register — Contains configuration and status infor-

mation for the BLT engine. The status bits are contained in the lower byte of the

register.

8210h-8213h

(Note)

R/W

GP_VGA_BASE

xxxxxxxxh

Graphics Pipeline VGA Memory Base Address Register — Specifies the offset of

the VGA memory, starting from the base of graphics memory.

8214h-8217h

(Note)

GP_VGA_LATCH

Graphics Pipeline VGA Display Latch Register — Provides a memory mapped

way to read or write the VGA display latch.

Note: The registers at GX_BASE+8140, 8144h, 8210h, and 8217h are located in the area designated for the graphics pipeline but

are used for VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

Table 4-25. Graphics Pipeline Configuration Registers

Bit

Name

Description

GX_BASE+8100h-8103h

GP_DST/START_X/YCOOR Register (R/W)

Default Value = 00000000h

31:16

15:0

DESTINATION/STARTING Y POSITION (SIGNED):

BLT Mode — Specifies the destination Y position for a BLT operation.

Vector Mode — Specifies the starting Y position in a vector.

DESTINATION/STARTING X POSITION (SIGNED):

BLT Mode — Specifies the destination X position for a BLT operation.

Vector Mode — Specifies the starting X position in a vector.

GX_BASE+8104h-8107h

GP_WIDTH/HEIGHTand

Default Value = 00000000h

GP_VECTOR_LENGTH/INIT_ERROR Register (R/W)

31:16

PIXEL_WIDTH or VECTOR_LENGTH (UNSIGNED):

BLT Mode — Specifies the width, in pixels, of a BLT operation. No pixels are rendered for a width of zero.

Vector Mode — Bits [31:30] are reserved in this mode allowing this 14-bit field to specify the length, in pixels, of a vector. No

pixels are rendered for a length of zero. This field is limited to 14 bits due to a lack of precision in the registers used to hold

the error terms.

15:0

PIXEL_HEIGHT or VECTOR_INITIAL_ERROR (UNSIGNED):

BLT Mode — Specifies the height, in pixels, of a BLT operation. No pixels are rendered for a height of zero.

Vector Mode — Specifies the initial error for renderng a vector.

GX_BASE+8108h-810Bh

GP_SCR_X/YCOOR and GP_AXIAL/DIAG_ERROR Register (R/W) Default Value = 00000000h

SRC_X_POS or VECTOR_AXIAL_ERROR (SIGNED):

BLT Mode — Specifies the source X position for a BLT operation.

31:16

Vector Mode — Specifies the axial error for rendering a vector.

SRC_Y_POS or VECTOR_DIAG_ERROR (SIGNED):

15:0

Source Y Position (Signed) — Specifies the source Y position for a BLT operation.

Vector Mode — Specifies the diagonal error for rendering a vector.

GX_BASE+810Ch-810Fh

8-BPP Mode

GP_SRC_COLOR Register (R/W)

Default Value = 00000000h

31:24

23:16

GP_SRC_COLOR_0:

8-BPP Color Index — The color index must be duplicated in the upper byte of GP_SRC_COLOR_0 when rendering 8-BPP

data.

15:8

7:0

GP_SRC_COLOR_1:

8-BPP Color Index — The color index must be duplicated in the upper byte of GP_SRC_COLOR_1 when rendering 8-BPP

data.

16-BPP Mode

31:16

15:0

GP_SRC_COLOR_0: 16-BPP Color (RGB)

GP_SRC_COLOR_1: 16-BPP Color (RGB)

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Table 4-25. Graphics Pipeline Configuration Registers (Continued)

Bit

Name

Description

Note: The Graphics Pipeline Source Color Register specifies the colors used when expanding monochrome source data in either the

8-BPP mode or the 16-BPP mode. Those pixels corresponding to clear bits (0) in the source data are rendered using

GP_SRC_COLOR_0 and those pixels corresponding to set bits (1) in the source data are rendered using

GP_SRC_COLOR_1.

GX_BASE+8110h-8113h

8-BPP Mode

GP_PAT_COLOR_A Register (R/W)

Default Value = 00000000h

31:24

23:16

GP_PAT_COLOR_0:

8-BPP Color Index — The color index must be duplicated in the upper byte of GP_PAT_COLOR_0 when rendering 8-BPP

data.

15:8

7:0

GP_PAT_COLOR_1:

8-BPP Color Index — The color index must be duplicated in the upper byte of GP_PAT_COLOR_1 when rendering 8-BPP

data.

16-BPP Mode

31:16

15:0

GP_PAT_COLOR_0: 16-BPP Color (RGB)

GP_PAT_COLOR_1: 16-BPP Color (RGB)

Note: The Graphics Pipeline Pattern Color A and B Registers specify the colors used when expanding pattern data.

GX_BASE+8114h-8117h

8-BPP Mode

GP_PAT_COLOR_B Register (R/W)

Default Value = 00000000h

31:24

23:16

GP_PAT_COLOR_2:

8-BPP Color Index — The color index must be duplicated in the upper byte of GP_PAT_COLOR_2 when rendering 8-BPP

data.

15:8

7:0

GP_PAT_COLOR_3:

8-BPP Color Index — The color index must be duplicated in the upper byte of GP_PAT_COLOR_3 when rendering 8-BPP

data.

16-BPP Mode

31:16

15:0

GP_PAT_COLOR_2: 16-BPP Color (RGB)

GP_PAT_COLOR_3: 16-BPP Color (RGB)

Note: The Graphics Pipeline Pattern Color A and B Registers specify the colors used when expanding pattern data.

GX_BASE+8120h-8123h GP_PAT_DATA_0 Register (R/W) Default Value = 00000000h

31:0

GP Pattern Data Register 0: The Graphics Pipeline Pattern Data Registers 0 through 3 together contain 128 bits of pat-

tern data. The GP_PAT_DATA_0 register corresponds to bits [31:0] of the pattern data.

GX_BASE+8124h-8127h

GP_PAT_DATA_1 Register (R/W)

Default Value = 00000000h

31:0

GP Pattern Data Register 1: The Graphics Pipeline Pattern Data Registers 0 through 3 together contain 128 bits of pat-

tern data. The GP_PAT_DATA_1 register corresponds to bits [63:32] of the pattern data.

GX_BASE+8128h-812Bh

GP_PAT_DATA_2 Register (R/W)

Default Value = 00000000h

31:0

GP Pattern Data Register 2: The Graphics Pipeline Pattern Data Registers 0 through 3 together contain 128 bits of pat-

tern data. The GP_PAT_DATA_2 register corresponds to bits [95:64] of the pattern data.

GX_BASE+812Ch-812Fh

GP_PAT_DATA_3 Register (R/W)

Default Value = 00000000h

31:0

GP Pattern Data Register 3: The Graphics Pipeline Pattern Data Registers 0 through 3 together contain 128 bits of pat-

tern data. The GP_PAT_DATA_3 register corresponds to bits [127:96] of the pattern data.

GX_BASE+8140h-8143h

GP_VGA_WRITE Register (R/W)

Default Value = xxxxxxxxh

Note that the registers at GX_BASE+82140h and 8144h are located in the area designated for the graphics pipeline but are used for

VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

GX_BASE+8144h-8147h

GP_VGA_READ Register (R/W)

Default Value = 00000000h

Note that the registers at GX_BASE+82140h and 8144h are located in the area designated for the graphics pipeline but are used for

VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

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Integrated Functions (Continued)

Table 4-25. Graphics Pipeline Configuration Registers (Continued)

Bit

Name

Description

GX_BASE+8200h-8203h

GP_RASTER_MODE Register (R/W)

Default Value = 00000000h

31:13

12

RSVD

TB

Reserved: Set to 0.

Transparent BLIT: When set, this bit enables transparent BLIT. The source color data will be compared to a

color key and if it matches, that pixel will not be drawn. The color key value is stored in the BLIT buffer as

destination data. The raster operation must be set to C6h, and the pattern registers must be all F’s for this

mode to work properly.

11

10

ST

PT

PM

Source Transparency: Enables transparency for monochrome source data. Those pixels corresponding to

clear bits in the source data are not drawn.

Pattern Transparency: Enables transparency for monochrome pattern data. Those pixels corresponding to

clear bits in the pattern data are not drawn.

9:8

Pattern Mode: Specifies the format of the pattern data.

00 = Indicates a solid pattern. The pattern data is always sourced from the GP_PAT_COLOR_0 register.

01 = Indicates a monochrome pattern. The pattern data is sourced from the GP_PAT_COLOR_0 and

GP_PAT_COLOR_1 registers.

10 = Indicates a dither pattern. All four pattern color registers are used.

11 =Indicates a color pattern. The pattern data is sourced directly from the pattern data registers.

Raster Operation: Specifies the raster operation for pattern, source, and destination data.

7:0

ROP

GX_BASE+8204h-8207h

GP_VECTOR_MODE Register (R/W)

Default Value = 00000000h

31:4

RSVD

DEST

DMIN

DMAJ

YMAJ

Reserved: Set to 0.

3

2

1

0

Read Destination Data: Indicates that frame-buffer destination data is required.

Minor Direction: Indicates a positive minor axis step.

Major Direction: Indicates a positive major axis step.

Major Direction: Indicates a Y Major vector.

GX_BASE+8208h-820Bh

GP_BLT_MODE Register (R/W)

Default Value = 00000000h

31:9

8

RSVD

Y

Reserved: Set to 0.

Reverse Y Direction: Indicates a negative increment for the Y position. This bit is used to control the direc-

tion of screen to screen BLTs to prevent data corruption in overlapping windows.

7:6

SM

Source Mode: Specifies the format of the source data.

00 = Source is a color bitmap.

01 = Source is a monochrome bitmap (use source color expansion).

10 = Unused.

11 = Source is a text glyph (use source color expansion). This differs from a monochrome bitmap in that the

X position is adjusted by the width of the BLT and the Y position remains the same.

5

RSVD

RD

Reserved: Set to 0.

4:2

Destination Data: Specifies the destination data location.

000 = No destination data is required. The destination data into the raster operation unit is all ones.

010 = Read destination data from BLT Buffer 0.

011 = Read destination data from BLT Buffer 1.

100 = Read destination data from the frame buffer (store temporarily in BLT Buffer 0).

101 = Read destination data from the frame buffer (store temporarily in BLT Buffer 1).

Source Data: Specifies the source data location.

1:0

RS

00 = No source data is required. The source data into the raster operation unit is all ones.

01 = Read source data from the frame buffer (temporarily stored in BLT Buffer 0).

10 = Read source data from BLT Buffer 0.

11 = Read source data from BLT Buffer 1.

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Table 4-25. Graphics Pipeline Configuration Registers (Continued)

Bit

Name

Description

GX_BASE+820Ch-820Fh

GP_BLT_STATUS Register (R/W)

Default Value = 00000000h

31:10

RSVD

W

Reserved: Set to 0.

9

8

Screen Width: Selects a frame-buffer width of 2048 bytes (default is 1024 bytes).

16-BPP Mode: Selects a pixel data format of 16 BPP (default is 8 BPP).

Reserved: Set to 0.

M

7:3

2

RSVD

BP (RO)

BLT Pending (Read Only): Indicates that a BLT operation is pending in the master registers.

The “BLT Pending” bit must be clear before loading any of the graphics pipeline registers. Loading registers

when this bit is set high will destroy the values for the pending BLT.

1

PB (RO)

Pipeline Busy (Read Only): Indicates that the graphics pipeline is processing data.

The “Pipeline Busy” bit differs from the “BLT Busy” bit in that the former only indicates that the graphics pipe-

line is processing data. The “BLT Busy” bit also indicates that the memory controller has not yet processed

all of the requests for the current operation.

The “Pipeline Busy” bit must be clear before loading a BLT buffer if the previous BLT operation used the

same BLT buffer.

0

BB (RO)

BLT Busy (Read Only): Indicates that a BLT / vector operation is in progress.

The “BLT Busy” bit must be clear before accessing the frame buffer directly.

GX_BASE+8210h-8213h

GP_VGA_BASE (R/W)

Default Value = xxxxxxxxh

Note that the registers at GX_BASE+8210h and 8214h are located in the area designated for the graphics pipeline but are used for

VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

GX_BASE+8214h-8217h

GP_VGA_LATCH Register (R/W)

Default Value = xxxxxxxxh

Note that the registers at GX_BASE+8210h and 8214h are located in the area designated for the graphics pipeline but are used for

VGA emulation purposes. Refer to Table 5-5 on page 173 for these register’s bit formats.

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4.5 DISPLAY CONTROLLER

The GXm processor incorporates a display controller that

retrieves display data from the memory controller and for-

mats it for output on a variety of display devices. The GXm

processor can directly connect to an active matrix TFT

LCD flat panel or to an external RAMDAC for CRT display

or both. The display controller includes a display FIFO,

compression/decompression (CODEC) hardware, hard-

ware cursor, a 256-entry-by-18-bit palette RAM (plus

three extension colors), display timing generator, dither

and frame-rate-modulation circuitry for TFT panels, and

flexible output formatting logic. A diagram of the display

controller subsystem is shown in Figure 4-14.

32

Compressed

Line Buffer

(64x32 bit)

18

8

32

Memory

RAMDAC

16

Data

Output

Format

18

Dither

and

FRM

Display

FIFO

(64x64 bit)

64

8

Panel

Extensions

Codec

9

18

Palette

Addr.

Logic

Palette

RAM

(264x18

2

Cursor

Latch

Pseudo/True

Color Mux

bit)

Palette Data

9

18

20

Memory

Address

Generator

Control Registers

and

Control Logic

Output

Control

Memory

Address

Timing

Generator

Figure 4-14. Display Controller Block Diagram

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Integrated Functions (Continued)

4.5.1 Display FIFO

The compression logic has the ability to insert a program-

mable number of "static" frames, during which time dirty

bits are ignored and the valid bits are read to determine

whether a line should be retrieved from the frame buffer or

compressed display buffer. The less frequently the dirty

bits are sampled, the more frequently lines will be

retrieved from the compressed display buffer. This allows

a programmable screen image update rate (as opposed to

refresh rate). Generally, an update rate of 30 frames per

second is adequate for displaying most types of data,

including real- time video. However, if a flat panel display

is used that has a slow response time, such as 100 ms,

the image need not be updated faster than ten frames per

second, since the panel could not display changes

beyond that rate.

The display controller contains a large (64x64 bit) FIFO for

queuing up display data from the memory controller as it

is required for output to the screen. The memory control-

ler must arbitrate between the display controller requests

and other requests for memory access from the micropro-

cessor core, L1 cache controller, and the graphics pipe-

line.

Since display data is required in real time, this data is the

highest priority in the system. Without efficient memory

management, system performance would suffer dramati-

cally due to the constant display-refresh requests from the

display controller. The large size of the display FIFO is

desirable so that the FIFO may primarily be loaded during

times when there is no other request pending to the

DRAM controller and so that the memory controller can

stay in page mode for a long period of time when servicing

the display FIFO. When a priority request from the cache

or graphics pipeline occurs, if the display FIFO has

enough data queued up, the DRAM controller can imme-

diately service the request without concern that the dis-

play FIFO will underflow. If the display FIFO is below a

programmable threshold, a high-priority request will be

sent to the DRAM controller, which will take precedence

over any other requests that are pending.

The compression algorithm used in the GXm processor

commonly achieves compression ratios between 10:1 and

20:1, depending on the nature of the display data. This

high level of compression provides higher system perfor-

mance by reducing typical latency for normal system

memory access, higher graphics performance by increas-

ing available drawing bandwidth to the DRAM array, and

much lower power consumption by significantly reducing

the number of off-chip DRAM accesses required for

refreshing the display. These advantages become even

more pronounced as display resolution, color depth, and

refresh rate are increased and as the size of the installed

DRAM increases.

The display FIFO is 64 bits wide to accommodate high-

speed burst read operations from the DRAM controller at

maximum memory bandwidth. In addition to the normal

pixel data stream, the display FIFO also queues up cursor

patterns.

As uncompressed lines are fed to the display, they will be

compressed and stored in an on-chip compressed line

buffer (64x32 bits). Lines will not be written back to the

compressed display buffer in the DRAM unless a valid

compression has resulted, so there is no penalty for

pathological frame buffer images where the compression

algorithm breaks down.

4.5.2 Compression Technology

To reduce the system memory contention caused by the

display refresh, the display controller contains compres-

sion and decompression logic for compressing the frame

buffer image in real time as it is sent to the display. It com-

bines this compressed display buffer into the extra off-

screen memory within the graphics memory aperture.

Coherency of the compressed display buffer is maintained

by use of dirty and valid bits for each line. The dirty and

valid RAM is contained on-chip for maximum efficiency.

Whenever a line has been validly compressed, it will be

retrieved from the compressed display buffer for all future

accesses until the line becomes dirty again. Dirty lines will

be retrieved from the normal uncompressed frame buffer.

4.5.3 Motion Video Acceleration Support

The display controller of the GXm processor supports the

CS5530 and future I/O companion chips’ hardware motion

video acceleration by reading the off-screen video buffer

and serializing the video data onto the RAMDAC port. The

display controller supplies video data to the I/O compan-

ion chips in either interleaved YUV4:2:2 format or

RGB5:6:5 format. The I/O companion chips can then

scale and filter the data, apply color space conversion to

YUV data, and mix the video data with graphics data also

supplied by the display controller.

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Integrated Functions (Continued)

4.5.4 Hardware Cursor

The timing generator supports overscan to maintain full

backward compatibility with the VGA. This feature is sup-

ported primarily for CRT display devices since flat panel

displays have fixed resolutions and do not provide for

overscan. However, the GXm processor supports a mech-

anism to center the display when a display mode is

selected having a lower resolution than the panel resolu-

tion. The border region is effectively stretched to fill the

remainder of the screen. The border color is at palette

extension 104h. For 8 BPP operation with an external

The display controller contains hardware cursor logic to

allow overlay of the cursor image onto the pixel data

stream. Overhead for updating this image on the screen is

kept to a minimum by requiring that only the X and Y posi-

tion be changed. This eliminates "submarining" effects

commonly associated with software cursors. The cursor,

32x32 pixels with two bits per pixel, is loaded into off-

screen memory within the graphics memory aperture. The

two-bit code selects color 0, color 1, transparent, or back-

ground-color inversion for each pixel in the cursor (see

Table 4-31 on page 144. The two cursor colors will be

stored as extensions to the normal 256-entry palette at

locations 100h and 101h. These palette extensions will be

used when driving a flat panel or a RAMDAC operating in

16 BPP (bits per pixel) mode. For 8 BPP operation using

an external RAMDAC, the DC_CURSOR_COLOR regis-

ter (GX_BASE+8360h) should be programmed to set the

indices for the cursor colors. To avoid corruption of the

cursor colors by an application program that modifies the

external palette, care should be taken to program the cur-

sor color indices to one of the static color indices. Since

Microsoft Windows typically uses only black and white

cursor colors and these are static colors, this kind of prob-

lem should rarely occur.

RAMDAC,

the

DC_BORDER_COLOR

register

(GX_BASE+8368h) should also be programmed.

4.5.6 Dither and Frame-Rate Modulation

The display controller supports 2x2 dither and two-level

frame-rate modulation (FRM) to increase the apparent

number of colors displayed on 9-bit or 12-bit TFT panels.

Dither and FRM are individually programmable. With dith-

ering and FRM enabled, 185,193 colors are possible on a

9-bit TFT panel, and 226,981 colors are possible on a 12-

bit TFT panel.

4.5.7 Display Modes

The GXm processor supports 640x480, 800x600, and

1024x768 display resolutions at both 8 and 16 bits per

pixel. In addition, 1280x1024 resolution is supported at 8

bits per pixel only. Two 16-bit display formats are sup-

ported: RGB 5-6-5 and RGB 5-5-5. All CRT modes use

VESA-compatible timing. Table 4-26 on page 132 gives

the supported CRT display modes.

4.5.5 Display Timing Generator

The display controller features a fully programmable tim-

ing generator for generating all timing control signals for

the display. The timing control signals include horizontal

and vertical sync and blank signals in addition to timing for

active and overscan regions of the display. The timing

generator is similar in function to the CRTC of the original

VGA, although programming is more straightforward. Pro-

gramming of the timing registers will generally happen via

a BIOS INT10 call during a mode set. When programming

the timing registers directly, extreme care should be taken

to ensure that all timing is compatible with the display

device.

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Integrated Functions (Continued)

Table 4-26. TFT Panel Display Modes

Refresh

Rate

(Hz)

DOTCLK

Rate

(MHz)

Simultaneous

Colors

PCLK

(MHz)

Panel

Type

Maximum Displayed

Colors (Note 1)

Resolution

640x480

(Note 2)

8 BPP

256 colors out of a

palette of 256

60

25.175

40.0

25.175

40.0

9-bit

57³= 185,193

12-bit

18-bit

9-bit

61³= 226,981

4³= 262,144

16 BPP

64 K colors

5-6-5

29x57x29 = 47,937

31x61x31 = 58,621

32x64x32 = 65,535

57³= 185,193

12-bit

18-bit

9-bit

800x600

(Note 2)

8 BPP

256 colors out of a

palette of 256

12-bit

18-bit

9-bit

61³= 226,981

64³= 262,144

16 BPP

64 K Colors

5-6-5

40.0

29x57x29 = 47,937

31x61x31 = 58,621

32x64x32 = 65,535

57³= 185,193

12-bit

18-bit

9-bit/18-I/F

1024x768

8 BPP

256 colors out of a

palette of 256

60

65

32.5

16 BPP

64 K colors

5-6-5

9-bit/18-I/F

29x57x29 = 47,937

Notes: 1) 9-bit and 12-bit panels use FRM and dither to increase displayed colors. (See Section 4.5.6 “Dither and

Frame-Rate Modulation” on page 131.)

2) All 640x480 and 800x600 modes can be run in simultaneous display with CRT.

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Integrated Functions (Continued)

Table 4-27. TFT Panel Data Bus Formats

9-Bit TFT

Panel Data

Bus Bit

18-Bit

TFT

12-Bit

TFT

640x480

1024x768

R5 Even

17

16

15

14

13

12

11

10

9

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

R5

R4

R3

R2

R5

R4

R3

R4

R3

R5

R4

R3

G5

G4

G3

G5

G4

G3

B5

B4

B3

B5

B4

B3

Odd

Even

Odd

Even

Odd

G5

G4

G3

G2

G5

G4

G3

8

7

6

5

B5

B4

B3

B2

B5

B4

B3

4

3

2

1

0

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Integrated Functions (Continued)

Table 4-28. CRT Display Modes

Simultaneous

Refresh Rate

(Hz)

DOTCLK Rate

(MHz)

PCLK

(MHz)

Graphics Port

Width (Bits)

Resolution

640x480

Colors

8 BPP

256 colors out of a

palette of 256

60

72

75

60

25.175

31.5

25.175

31.5

50.35

25.175

63.0

31.5

63.0

31.5

40.0

50.0

49.5

80.0

40.0

100

8

31.5

8

16 BPP

64 K colors

RGB 5-6-5

25.175

8

16

8

72

75

31.5

16

8

16

8

800x600

8 BPP

256 colors out of a

palette of 256

60

72

75

60

40.0

50.0

49.5

40.0

8

16 BPP

64 K colors

RGB 5-6-5

8

16

8

72

75

50.0

49.5

50.0

99

16

8

49.5

65.0

75.0

78.5

65.0

75.0

78.5

108.0

54.0

67.5

16

8

1024x768

8 BPP

256 colors out of a

palette of 256

60

70

75

60

70

75

60

65.0

75.0

78.5

65.0

75.0

78.5

108.0

8

16 BPP

64 K colors

RGB 5-6-5

16

8

1280x1024

8 BPP

256 colors out of a

palette of 256

16

75

135.0

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Integrated Functions (Continued)

4.5.8 Graphics Memory Map

for the various buffers are programmable for a high

degree of flexibility in memory organization.

The GXm processor supports a maximum of 4 MB of

graphics memory and will map it to an address space (see

Figure 4-2 on page 93) higher than the maximum amount

of installed RAM. The graphics memory aperture physi-

cally resides at the top of the installed system RAM. The

start address and size of the graphics memory aperture

are programmable on 128 KB boundaries. Typically, the

system BIOS sets the size and start address of the graph-

ics memory aperture during the boot process based on

the amount of installed RAM, user defined CMOS set-

tings, and display resolution. The graphics pipeline and

display controller address the graphics memory with a 20-

bit offset (address bits [21:2]) and four byte enables into

the graphics memory aperture. The graphics memory

stores several buffers that are used to generate the dis-

play: the frame buffer, compressed display buffer, VGA

memory, and cursor pattern(s). Any remaining off-screen

memory within the graphics aperture may be used by the

display driver as desired or not at all.

4.5.8.2 Frame Buffer and Compression Buffer

Organization

The GXm processor supports primary display modes

640x480, 800x600, and 1024x768 at both 8 BPP and 16

BPP, and 1280x1024 at 8 BPP. Pixels will be packed into

DWORDs as shown in Figure 4-15.

In order to simplify address calculations by the rendering

hardware, the frame buffer is organized in an XY fashion

where the offset is simply a concatenation of the X and Y

pixel addresses. All 8 BPP display modes with the excep-

tion of 1280x1024 resolution will use a 1024-byte line

delta between the starting offsets of adjacent lines. All 16

BPP display modes and 1280x1024x8 BPP display

modes will use a 2048-byte line delta between the starting

offsets of adjacent lines. If there is room, the space

between the end of a line and the start of the next line will

be filled with the compressed display data for that line,

thus allowing efficient memory utilization. For 1024x768

display modes, the frame-buffer line size is the same as

the line delta, so no room is left for the compressed dis-

play data between lines. In this case, the compressed dis-

play buffer begins at the end of the frame buffer region

and is linearly mapped.

4.5.8.1 DC Memory Organization Registers

The display controller contains a number of registers that

allow full programmability of the graphics memory organi-

zation. This includes starting offsets for each of the buffer

regions described above, line delta parameters for the

frame buffer and compression buffer, as well as com-

pressed line-buffer size information. The starting offsets

(0, 0)

(1023,0)

DWORD 0

(0, 1023)

(1023, 1023)

Bit Position

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address

3h

2h

1h

0h

(0,0)

Pixel Org - 8 BPP

Pixel Org - 16 BPP

(3,0)

(2,0)

(1,0)

(0,0)

Figure 4-15. Pixel Arrangement Within a DWORD

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Integrated Functions (Continued)

4.5.8.3 VGA Display Support

Each pattern is a 32x32-pixel array of 2-bit codes. The

codes are a combination of AND mask and XOR mask for

a particular pixel. Each line of an overlay pattern is stored

as two DWORDs, with each DWORD containing the AND

masks for 16 pixels in the upper word and the XOR masks

for 16 pixels in the lower word. DWORDs are arranged

with the leftmost pixel block being least significant and the

rightmost pixel block being most significant. Pixels within

words are arranged with the leftmost pixels being most

significant and the rightmost pixels being least significant.

The graphics pipeline contains full hardware support for

the VGA front end. The VGA data is stored in a 256 KB

buffer located in graphics memory. The main task for Soft-

VGA is converting the data in the VGA buffer to an 8 BPP

frame buffer that can be displayed by the GXm proces-

sor’s hardware.

For some modes, the display controller can display the

VGA data directly and the data conversion is not neces-

sary. This includes standard VGA mode 13h and the vari-

ations of that mode used in several games; the display

controller can also directly display VGA planar graphics

modes D, E, F, 10, 11, and 12. Likewise, the hardware can

directly display all of the higher-resolution VESA modes.

Since the frame buffer data is written directly to memory

instead of travelling across an external bus, the GXm pro-

cessor outperforms typical VGA cards for these modes.

Multiple cursor patterns may be loaded into the off-screen

memory. An application may simply change the cursor

start offset to select a new cursor pattern. The new cursor

pattern will be used at the start of the next frame scan.

4.5.9 Display Controller Registers

The Display Controller maps 100h locations starting at

GX_BASE+8300h. Refer to Section 4.1.2 “Control Regis-

ters” on page 94 for instructions on accessing these regis-

ters.

The display controller, however, does not directly support

text modes. SoftVGA must then convert the characters

and attributes in the VGA buffer to an 8 BPP frame buffer

the hardware uses for display refresh. See Section 4 “Vir-

tual Subsystem Architecture” for SoftVGA details.

The Display Controller Registers are divided into six cate-

gories:

•

Configuration and Status Registers

Memory Organization Registers

Timing Registers

Cursor and Line Compare Registers

Color Registers

4.5.8.4 Cursor Pattern Memory Organization

The cursor overlay patterns are loaded to independent

memory locations, usually mapped above the frame buffer

and compressed display buffer (off-screen). The cursor

buffer must start on a 16-byte aligned boundary. It is lin-

early mapped, and is always 256 bytes in size. If there is

enough room (256 bytes) after the compression-buffer line

but before the next frame-buffer line starts, the cursor pat-

tern may be loaded into this area to make efficient use of

the graphics memory.

Palette and RAM Diagnostic Registers

Table 4-29 summarizes these registers and locations and

the following subsections give detailed register/bit for-

mats.

Table 4-29. Display Controller Register Summary

GX_BASE+

Memory Offset

Default

Value

Type

Name/Function

Configuration and Status Registers

8300h-8303h

R/W

DC_UNLOCK

00000000h

Display Controller Unlock — This register is provided to lock the most critical memory-

mapped display controller registers to prevent unwanted modification (write operations).

Read operations are always allowed.

8304h-8307h

8308h-830Bh

R/W

DC_GENERAL_CFG

00000000h

xx000000h

Display Controller General Configuration — General control bits for the display controller.

DC_TIMING_CFG

Display Controller Timing Configuration — Status and control bits for various display

timing functions.

830Ch-830Fh

R/W

DC_OUTPUT_CFG

xx000000h

xxxxxxxxh

Display Controller Output Configuration — Status and control bits for pixel output

formatting functions.

Memory Organization Registers

8310h-8313h

R/W

DC_FB_ST_OFFSET

Display Controller Frame Buffer Start Address — Specifies offset at which the frame buffer

starts.

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Integrated Functions (Continued)

Table 4-29. Display Controller Register Summary (Continued)

GX_BASE+

Memory Offset

Default

Value

Type

Name/Function

8314h-8317h

R/W

DC_CB_ST_OFFSET

xxxxxxxxh

Display Controller Compression Buffer Start Address — Specifies offset at which the com-

pressed display buffer starts.

8318h-831Bh

R/W

DC_CURS_ST_OFFSET

xxxxxxxxh

Display Controller Cursor Buffer Start Address — Specifies offset at which the cursor mem-

ory buffer starts.

831Ch-831Fh

8320h-8323h

--

Reserved

00000000h

xxxxxxxxh

R/W

DC_VID_ST_OFFSET

Display Controller Video Start Address — Specifies offset at which the video buffer starts.

8324h-8327h

8328h-832Bh

R/W

DC_LINE_DELTA

xxxxxxxxh

Display Controller Line Delta — Stores line delta for the graphics display buffers.

DC_BUF_SIZE

Display Controller Buffer Size — Specifies the number of bytes to transfer for a line of

frame buffer data and the size of the compressed line buffer.

832Ch-832Fh

Timing Registers

8330h-8333h

--

Reserved

00000000h

xxxxxxxxh

R/W

DC_H_TIMING_1

Display Controller Horizontal and Total Timing — Horizontal active and total timing

information.

8334h-8337h

R/W

DC_H_TIMING_2

xxxxxxxxh

Display Controller CRT Horizontal Blanking Timing — CRT horizontal blank timing

information.

8338h-833Bh

833Ch-833Fh

R/W

DC_H_TIMING_3

xxxxxxxxh

Display Controller CRT Sync Timing — CRT horizontal sync timing information.

DC_FP_H_TIMING

Display Controller Flat Panel Horizontal Sync Timing: Horizontal sync timing information for

an attached flat panel display.

8340h-8343h

R/W

DC_V_TIMING_1

xxxxxxxxh

Display Controller Vertical and Total Timing — Vertical active and total timing information.

The parameters pertain to both CRT and flat panel display.

8344h-8247h

8348h-834Bh

834Ch-834Fh

R/W

DC_V_TIMING_2

xxxxxxxxh

Display Controller CRT Vertical Blank Timing — Vertical blank timing information.

DC_V_TIMING_3

Display Controller CRT Vertical Sync Timing — CRT vertical sync timing information.

DC_FP_V_TIMING

Display Controller Flat Panel Vertical Sync Timing — Flat panel vertical sync timing

information.

Cursor and Line Compare Registers

8350h-8353h

R/W

DC_CURSOR_X

xxxxxxxxh

Display Controller Cursor X Position — X position information of the hardware cursor.

8354h-8357h

RO

DC_V_LINE_CNT

Display Controller Vertical Line Count — This read only register provides the current scan-

line for the display. It is used by software to time update of the frame buffer to avoid tearing

artifacts.

8358h-835Bh

835Ch-835Fh

R/W

DC_CURSOR_Y

xxxxxxxxh

Display Controller Cursor Y Position — Y position information of the hardware cursor.

DC_SS_LINE_CMP

Display Controller Split-Screen Line Compare — Contains the line count at which the lower

screen begins in a VGA split-screen mode.

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Integrated Functions (Continued)

Table 4-29. Display Controller Register Summary (Continued)

GX_BASE+

Memory Offset

Default

Value

Type

Name/Function

Color Registers

8360h-8363h

R/W

DC_CURSOR_COLOR

xxxxxxxxh

Display Controller Cursor Color — Contains the 8-bit indices for the cursor colors.

8364h-8367h

8368h-836Bh

--

Reserved

00000000h

xxxxxxxxh

R/W

DC_BORDER_COLOR

Display Controller Border Color — Contains the 8-bit index for the border or overscan color.

836Ch-836Fh

--

Reserved

00000000h

xxxxxxxxh

Palette and RAM Diagnostic Registers

8370h-8373h

R/W

DC_PAL_ADDRESS

Display Controller Palette Address — This register should be written with the address

(index) location to be used for the next access to the DC_PAL_DATA register.

8374h-8377h

8378h-837Bh

R/W

DC_PAL_DATA

xxxxxxxxh

Display Controller Palette Data — Contains the data for a palette access cycle.

DC_DFIFO_DIAG

Display Controller Display FIFO Diagnostic — This register is provided to enable testability

of the Display FIFO RAM.

837Ch-837Fh

R/W

DC_CFIFO_DIAG

xxxxxxxxh

Display Controller Compression FIFO Diagnostic — This register is provided to enable test-

ability of the Compressed Line Buffer (FIFO) RAM.

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Integrated Functions (Continued)

4.5.9.1 Configuration and Status Registers

The Configuration and Status Registers group consists of

four 32-bit registers located at GX_BASE+8300h-830Ch.

These registers are described below and Table 4-30 gives

their bit formats.

•

Display Controller General Configuration

(DC_GENERAL_CFG)

-

General control bits for the display controller.

Display Controller Timing Configuration

(DC_TIMING_CFG)

-

Status and control bits for various display timing

functions.

•

Display Controller Unlock (DC_UNLOCK)

-

This register is provided to lock the most critical

memory-mapped display controller registers to

prevent unwanted modification (write operations).

Read operations are always allowed.

•

Display Controller Output Configuration

(DC_OUTPUT_CFG)

-

Status and control bits for pixel output formatting

functions.

Table 4-30. Display Controller Configuration and Status Registers

Bit

Name

Description

GX_BASE+8300h-8303h

DC_UNLOCK Register (R/W)

Default Value = 00000000h

31:16

15:0

RSVD

Reserved: Set to 0.

UNLOCK_

CODE

Unlock Code: This register must be written with the value 4758h in order to write to the protected regis-

ters. The following registers are protected by the locking mechanism.

DC_GENERAL_CFG

DC_BUF_SIZE,

DC_CB_ST_OFFSET,

DC_V_TIMING_2

DC_TIMING_CFG,

DC_H_TIMING_1,

DC_OUTPUT_CFG,

DC_FP_H_TIMING

DC_LINE_DELTA,

DC_CURS_ST_OFFSET,

DC_V_TIMING_3

DC_H_TIMNG_2,

DC_FB_ST_OFFSET,

DC_FP_V_TIMING

GX_BASE+8304h-8307h

DC_GENERAL_CFG (R/W)

Default Value = 00000000h

31

30

29

DDCK

DPCK

VRDY

Divide Dot Clock: Divide internal DOTCLK by two relative to PCLK (pertains only to 16 BPP display

modes utilizing an eight-bit RAMDAC): 0 = Disable; 1 = Enable.

Divide Pixel Clock: Divide PCLK by two relative to internal DOTCLK (pertains only to display modes that

pack two pixels together such as 1280x1024 on an external CRT only): 0 = Disable; 1 = Enable.

Video Ready Protocol: 0 = Low speed video port, use with V2.3 and older.

1 = High speed video port, use with V2.4 and newer.

28

27

VIDE

Video Enable: Motion video port: 0 = Disable; 1 = Enable.

SSLC

Split-screen Line Compare: VGA line compare function: 0 = Disable; 1 = Enable.

When enabled, the internal line counter will be compared to the value programmed in the DC_SS

_LINE_CMP register. If it matches, the frame buffer address will be reset to zero. This enables a split

screen function.

26

25

CH4S

DIAG

Chain 4 Skip: Allow display controller to read every 4th DWORD from the frame buffer for compatibility

with the VGA: 0 = Disable; 1 = Enable.

FIFO Diagnostic Mode: This bit allows testability of the on-chip Display FIFO and Compressed Line

Buffer via the diagnostic access registers. A low-to-high transition will reset the Display FIFO’s R/W point-

ers and the Compressed Line Buffer’s read pointer. 0 = Normal operation; 1 = Enable.

24

LDBL

Line Double: Allow line doubling for emulated VGA modes: 0 = Disable; 1 = Enable.

If enabled, this will cause each odd line to be replicated from the previous line as the data is sent to the dis-

play. Timing parameters should be programmed as if no pixel doubling is used, however, the frame buffer

should be loaded with half the normal number of lines.

23

CKWR

Clock Write: This bit will be output directly to an external clock chip or SYNDAC. The bit should be pulsed

high and low by the software to strobe data into the chip.

Note that this bit can be used in conjunction with the DACRS[2:0] pins.

22:20

DAC_RS[2:0] RAMDAC Register Selects: This 3-bit field sets the register select inputs to the external RAMDAC for the

next cycle. It is used to allow access to the extended register set of the RAMDAC. Alternatively, these bits

may be used in selecting the frequency for an external clock chip or SYNDAC. If more than eight frequency

selections are required, the RAMDAC extended register programming sequence must be used or the addi-

tional select bit must be provided by some other means.

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Integrated Functions (Continued)

Table 4-30. Display Controller Configuration and Status Registers (Continued)

Bit

Name

RTPM

Description

19

Real-Time Performance Monitoring: Allows real-time monitoring of a variety of internal GXm

processor signals by multiplexing the signals onto the CLKWR and DACRS[2:0] pins:

0 = Disable (Normal operation); 1 = Enable.

The CLKWR pin should not be fed to a clock chip or SYNDAC when this mode of operation is used, a dif-

ferent programming scheme should be used for the clock chip using the DACRS[2:0] signals and RAM-

DACRD# and RAMDACWR# signals. The selection of output signals is made using bits [27:16] of the

DC_BUF_SIZE register. The lower 12 bits of this field will select one of eight outputs for each pin.

18

FDTY

Frame Dirty Mode: Allow entire frame to be flagged as dirty whenever a pixel write occurs to the frame

buffer (this is provided for modes that use a linearly mapped frame buffer for which the line delta is not

equal to 1024 or 2048 bytes): 0 = Disable; 1 = Enable.

When disabled, dirty bits are set according to the Y address of the pixel write.

Reserved: Set to 0.

17

16

RSVD

CMPI

Compressor Insert Mode: Insert one static frame between update frames: 0 = Disable; 1 = Enable.

An update frame is referred to as a frame in which dirty lines will be allowed to be updated. Conversely, a

static frame is referred to as a frame in which dirty lines will not be updated (although the image may not

be static, since lines that are not compressed successfully must be retrieved from the uncompressed

frame buffer).

15:12

11:8

7:6

DFIFO

Display FIFO High Priority End Level: This field specifies the depth of the display FIFO (in 64-bit entries

HI-PRI END x 4) at which a high-priority request previously issued to the memory controller will end. The value is

LVL

dependent upon display mode.

This register should always be non-zero and should be larger than the start level.

DFIFO

HI-PRI

START LVL

Display FIFO High Priority Start Level: This field specifies the depth of the display FIFO (in 64-bit entries

x 4) at which a high-priority request will be sent to the memory controller to fill up the FIFO. The value is

dependent upon display mode.

This register should always be nonzero and should be less than the high-priority end level.

DCLK_

MUL

DCLK Multiplier: This 2-bit field specifies the clock multiplier for the input DCLK pin. After the input clock

is optionally multiplied, the internal DOTCLK, PCLK, and FPCLK may be divided as necessary.

00 = Forced Low

01 = 1 x DCLK

10 = 2 x DCLK

11 = 4 x DCLK

5

DECE

Decompression Enable: Allow operation of internal decompression hardware:

0 = Disable; 1 = Enable.

4

3

CMPE

PPC

Compression Enable: Allow operation of internal compression hardware: 0 = Disable; 1 = Enable

Pixel Panning Compatibility: This bit has the same function as that found in the VGA.

Allow pixel alignment to change when crossing a split-screen boundary - it will force the pixel alignment to

be 16-byte aligned: 0 = Disable; 1 = Enable.

If disabled, the previous alignment will be preserved when crossing a split-screen boundary.

2

DVCK

Divide Video Clock: Selects frequency of VID_CLK pin:

0 = VID_CLK pin frequency is equal to one-half (½) the frequency of the core clock.

1 = VID_CLK pin frequency is equal to one-fourth (¼) the frequency of the core clock.

Note: Bit 28 (VIDE) must be set to 1 for this bit to be valid.

1

0

CURE

DFLE

Cursor Enable: Allow operation of internal hardware cursor: 0 = Disable; 1 = Enable.

Display FIFO Load Enable: Allow the display FIFO to be loaded from memory:

0 = Disable; 1 = Enable.

If disabled, no write or read operations will occur to the display FIFO.

If enabled, a flat panel should be powered down prior to setting this bit low. Similarly, if active, a CRT

should be blanked prior to setting this bit low.

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Table 4-30. Display Controller Configuration and Status Registers (Continued)

Bit

Name

Description

GX_BASE+8308h-830Bh

DC_TIMING_CFG Register (R/W)

Default Value = xxx00000h

31

30

VINT

(RO)

Vertical Interrupt (Read Only): Is a vertical interrupt pending? 0 = No; 1 = Yes.

This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3C2h bit

7.

VNA

(RO)

Vertical Not Active (Read Only): Is the active part of a vertical scan is in progress (i.e. retrace, blanking,

or border)? 0 = Yes; 1 = No.

This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DA

bit 3.

29

28

DNA

(RO)

Display Not Active (Read Only): Is the active part of a line is being displayed (i.e. retrace, blanking, or

border)? 0 = Yes; 1 = No.

This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DA

bit 0.

SENS

(RO)

Monitor Sense (Read Only): This bit returns the result of the voltage comparator test of the RGB lines

from the external RAMDAC. The value will be a low level if one or more of the comparators exceed the 340

mV level indicating an unloaded line.

This bit can be tested repeatedly to determine the loading on the red, green, and blue lines by loading the

palette with various values. The BIOS can then determine whether a color, monochrome, or no monitor is

attached. If no RAMDAC is attached, the BIOS should assume that a color panel is attached and operate

in color mode. For VGA emulation, read operations to port 3C2 bit 4 are redirected here.

27

DDCI

(RO)

DDC Input (Read Only): This bit returns the value from the DDCIN pin that should reflect the value from

pin 12 of the VGA connector. It is used to provide support for the VESA Display Data Channel standard

level DDC1.

26:20

19:17

RSVD

Reserved: Set to 0.

PWR_SEQ

DELAY

Power Sequence Delay: This 3-bit field sets the delay between edges for the power sequencing control

logic. The actual delay is this value multiplied by one frame period (typically 16ms).

Note that a value of zero will result in a delay of only one DOTCLK period.

16

BKRT

Blink Rate:

0 = Cursor blinks on every 16 frames for a duration of 8 frames (approximately 4 times per second) and

VGA text characters will blink on every 32 frames for a duration of 16 frames (approximately 2 times per

second).

1 = Cursor blinks on every 32 frames for a duration of 16 frames (approximately 2 times per second) and

VGA text characters blink on every 64 frames for a duration of 32 frames (approximately 1 time per sec-

ond).

15

14

PXDB

INTL

Pixel Double: Allow pixel doubling to stretch the displayed image in the horizontal dimension:

0 = Disable; 1 = Enable.

If bit 15 is enabled, timing parameters should be programmed as if no pixel doubling is used, however, the

frame buffer should be loaded with half the normal pixels per line. Also, the FB_LINE_SIZE parameter in

DC_BUF_SIZE should be set for the number of bytes to be transferred for the line rather than the number

displayed.

Interlace Scan: Allow interlaced scan mode:

0 = Disable (non-interlaced scanning is supported)

1 = Enable (If a flat panel is attached, it should be powered down before setting this bit.)

VGA Planar Mode: This bit must be set high for all VGA planar display modes.

13

12

PLNR

FCEN

Flat Panel Center: Allows the border and active portions of a scan line to be qualified as “active” to a flat

panel display via the ENADISP signal. This allows the use of a large border region for centering the flat

panel display. 0 = Disable; 1 = Enable.

When disabled, only the normal active portion of the scan line will be qualified as active.

Flat Panel Vertical Sync Polarity:

11

10

FVSP

FHSP

0 = Causes TFT vertical sync signal to be normally low, generating a high pulse during sync interval.

1 = Causes TFT vertical sync signal to be normally high, generating a low pulse during sync interval.

Flat Panel Horizontal Sync Polarity:

0 = Causes TFT horizontal sync signal to be normally low, generating a high pulse during sync interval.

1 = Causes TFT horizontal sync signal to be normally high, generating a low pulse during sync interval.

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Integrated Functions (Continued)

Table 4-30. Display Controller Configuration and Status Registers (Continued)

Bit

Name

CVSP

Description

CRT Vertical Sync Polarity:

9

0 = Causes CRT VSYNC signal to be normally low, generating a high pulse during the retrace interval.

1 = Cause CRT VSYNC signal to be normally high, generating a low pulse during the retrace interval.

CRT Horizontal Sync Polarity:

8

CHSP

0 = Causes CRT HSYNC signal to be normally low, generating a high pulse during the retrace interval.

1 = Causes CRT HSYNC signal to be normally high, generating a low pulse during the retrace interval.

Blink Enable: Blink circuitry: 0 = Disable; 1 = Enable.

7

6

BLNK

VIEN

If enabled, the hardware cursor will blink as well as any pixels. This is provided to maintain compatibility

with VGA text modes. The blink rate is determined by the bit 16 (BKRT).

Vertical Interrupt Enable: Generate a vertical interrupt on the occurrence of the next vertical sync pulse:

0 = Disable, vertical interrupt is cleared;

1 = Enable.

This bit is provided to maintain backward compatibility with the VGA.

5

4

TGEN

DDCK

Timing Generator Enable: Allow timing generator to generate the timing control signals for the display.

0 = Disable, the Timing Registers may be reprogrammed, and all circuitry operating on the DOTCLK will be

reset.

1 = Enable, no write operations are permitted to the Timing Registers.

DDC Clock: This bit is used to provide the serial clock for reading the DDC data pin. This bit is multiplexed

onto the CRTVSYNC pin, but in order for it to have an effect, the VSYE bit must be set low to disable the

normal vertical sync. Software should then pulse this bit high and low to clock data into the GXm proces-

sor.

This feature is provided to allow support for the VESA Display Data Channel standard level DDC1.

3

2

BLKE

VSYE

Blank Enable: Allow generation of the composite blank signal to the display device:

0 = Disable; 1 = Enable.

When disabled, the BLANK# output will be a static low level. This allows VESA DPMS compliance.

Horizontal Sync Enable: Allow generation of the horizontal sync signal to a CRT display device:

0 = Disable; 1 = Enable.

When disabled, the HSYNC output will be a static low level. This allows VESA DPMS compliance.

Note that this bit only applies to the CRT; the flat panel HSYNC is controlled by the automatic power

sequencing logic.

1

0

HSYE

FPPE

Vertical Sync Enable: Allow generation of the vertical sync signal to a CRT display device:

0 = Disable; 1 = Enable.

When disabled, the VSYNC output will be a static low level. This allows VESA DPMS compliance.

Note that this bit only applies to the CRT; the flat panel VSYNC is controlled by the automatic power

sequencing logic.

Flat Panel Power Enable: On a low-to-high transition this bit will enable the flat panel power-up sequence

to begin. This will first turn on VDD to the panel, then start the clocks, syncs, and pixel bus, then turn on

the LCD bias voltage, and finally the backlight.

On a high-to-low transition, this bit will disable the outputs in the reverse order.

GX_BASE+830Ch-830Fh

DC_OUTPUT_CFG Register (R/W)

Default Value = xxx00000h

31:16

15

RSVD

DIAG

Reserved: Set to 0.

Compressed Line Buffer Diagnostic Mode: This bit will allow testability of the Compressed Line Buffer

via the diagnostic access registers. A low-to-high transition will reset the Compressed Line Buffer write

pointer. 0 = Disable (Normal operation); 1 = Enable.

14

13

CFRW

PDEH

Compressed Line Buffer Read/Write Select: Enables the read/write address to the Compressed Line

Buffer for use in diagnostic testing of the RAM.

0 = Write address enabled

1 = Read address enabled

Panel Data Enable High:

0 = The PANEL[17:9] data bus to be driven to a logic low level to effectively blank an attached flat panel

display or disable the upper pixel data bus for 16-bit pixel port RAMDACs.

1 = If no flat panel is attached, the PANEL[17:9] data bus will be driven with active pixel data. If a flat panel

is attached, setting this bit high will have no effect − the upper panel bus will be driven based upon the

power sequencing logic.

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Integrated Functions (Continued)

Table 4-30. Display Controller Configuration and Status Registers (Continued)

Bit

Name

PDEL

Description

Panel Data Enable Low:

12

0 = This bit will cause the PANEL[8:0] data bus to be driven to a logic low level to effectively blank an

attached flat panel display or disable the lower panel data bus if it is not required.

1= If no flat panel is attached, the PANEL[8:0] data bus will be driven with active pixel data. If a flat panel is

attached, setting this bit high will have no effect − the lower panel bus will be driven based upon the power

sequencing logic.

11

PRMP

Palette Re-map:

0 = The modified codes are sent to the RAMDAC and the external palette should uses the modified map-

ping.

1 = Bits [8:1] of the palette output register are routed to the RAMDAC data bus. The GXm processor inter-

nal palette RAM may be loaded with 8-bit VGA indices to translate the modified codes stored in display

memory so that the RAMDAC data bus will contain the expected indices. The modified codes are used to

achieve character blinking in VGA text modes. This mode should be set high set high only for desktop sys-

tems with no flat panel attached. It should only be necessary when 8514/A or VESA standard feature con-

nector support is required.

10

CKSL

Clock Select: Selects output used to clock PANEL[17:0], FPHSYNC, FPVSYNC, and ENADISP output

pins.

1 = PCLK

0 = FPCLK (based upon the power sequencing logic)

This bit should be high when using a 16-bit RAMDAC.

Frame Rate Modulation Select:

9

8

FRMS

0 = Enables FRM circuitry to change the pattern displayed every frame.

1 = Enables FRM circuitry to change the pattern displayed every two frames (to allow for slower response

time liquid crystal materials).

3/4ADD

3- or 4-bit Add:

0 = Enables dither and FRM circuitry to operate on the 3 most significant bits of each color component for

9-bit TFT panels.

1 = Enables the dither and FRM circuitry to operate on the 4 most significant bits of each color component

for 12-bit TFT panels.

7

6

5

4

RSVD

DITE

Reserved: Must be set to 0.

Dither Enable: Allow a 2x2 spatial dither on the 3-bit or 4-bit color value. Note that dither will not be sup-

ported for 12-bit TFT panels when FRM is enabled. 0 = Disable; 1 = Enable.

3

FRME

Frame-Rate Modulation Enable: Allow FRM to be performed on the 3-bit or 4-bit color value using the

next most significant bit after the least significant bit sent to the panel.

0 = Disable (no FRM performed);

1 = Enable.

2

PCKE

PCLK Enable:

0 = PCLK is disabled and a low logic level is driven off-chip. Also, the RAMDAC data bus is driven low.

1 = Enable PCLK to be driven off-chip.

This clock operates the RAMDAC interface.

1

0

16FMT

8BPP

16 BPP Format: Selects RGB display mode:

0 = RGB 5-6-5 mode

1 = RGB 5-5-5 display mode

This bit is only significant if 8 BPP is low, indicating 16 BPP mode.

8 BPP / 16 BPP Select:

0 = 16-bit per pixel display mode is selected. (Bit 1 of OUTPUT_CONFIG will indicate the format of the 16

bit data.)

1 = 8-bit-per-pixel display mode is selected. This is the also the mode used in VGA emulation.

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Integrated Functions (Continued)

4.5.10 Memory Organization Registers

•

Display Controller Frame Buffer Start Address

(DC_FB_ST_OFFSET)

The GXm processor utilizes a graphics memory aperture

that is up to 4 MB in size. The base address of the graph-

ics memory aperture is stored in the DRAM controller.

The graphics memory is made up of the normal uncom-

pressed frame buffer, compressed display buffer, and cur-

sor buffer. Each buffer begins at a programmable offset

within the graphics memory aperture.

-

Specifies the offset at which the frame buffer starts.

Display Controller Compression Buffer Start Address

(DC_CB_ST_OFFSET)

-

Specifies the offset at which the compressed display

buffer starts.

•

Display Controller Cursor Buffer Start Address

(DC_CURS_ST_OFFSET)

The various memory buffers are arranged so as to effi-

ciently pack the data within the graphics memory aper-

ture. This requires flexibility in the way that the buffers are

arranged when different display modes are in use. The

cursor buffer is a linear block so addressing is straightfor-

ward. The frame buffer and compressed display buffer are

arranged based upon scan lines. Each scan line has a

maximum number of valid or active DWORDs and a delta,

that when added to the previous line offset, points to the

next line. In this way, the buffers may be stored as linear

blocks or as logical blocks as may be desired.

-

Specifies the offset at which the cursor memory

buffer starts.

Display Controller Video Start Address

(DC_VID_ST_OFFSET)

-

Specifies the offset at which the video buffer starts.

•

Display Controller Line Delta (DC_LINE_DELTA)

-

Stores the line delta for the graphics display buffers.

Display Controller Buffer Size (DC_BUF_SIZE)

-

Specifies the number of bytes to transfer for a line of

frame buffer data and the size of the compressed

line buffer. (The compressed line buffer will be invali-

dated if it exceeds the CB_LINE_SIZE, bits [15:9].)

The Memory Organization Registers group consists of six

32-bit registers located at GX_BASE+8310h-8328h.

These registers are described below and Table 4-31 gives

their bit formats.

Table 4-31. Display Controller Memory Organization Registers

Bit

Name

Description

GX_BASE+8310h-8313h

DC_FB_ST_OFFSET Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:22

21:0

RSVD

FB_START

_OFFSET

Frame Buffer Start Offset: This value represents the byte offset of the starting location of the displayed

frame buffer. This value may be changed to achieve panning across a virtual desktop or to allow multiple

buffering.

When this register is programmed to a nonzero value, the compression logic should be disabled. The

memory address defined by bits [21:4] will take effect at the start of the next frame scan. The pixel offset

defined by bits [3:0] will take effect immediately (in general, it should only change during vertical blank-

ing).

GX_BASE+8314h-8317h

DC_CB_ST_OFFSET Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:22

21:0

RSVD

CB_START

_OFFSET

Compressed Display Buffer Start Offset: This value represents the byte offset of the starting location

of the compressed display buffer. Bits [3:0] should always be programmed to zero so that the start offset

is aligned to a 16-byte boundary. This value should change only when a new display mode is set due to

a change in size of the frame buffer.

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Integrated Functions (Continued)

Table 4-31. Display Controller Memory Organization Registers (Continued)

Bit

Name

Description

GX_BASE+8318h-831Bh

DC_CUR_ST_OFFSET Register (R/W)

Reserved: Set to 0.

CUR_START Cursor Start Offset: This value represents the byte offset of the starting location of the cursor display

Default Value = xxxxxxxxh

31:22

21:0

RSVD

_OFFSET

pattern. Bits [1:0] should always be programmed to zero so that the start offset is DWORD aligned. The

cursor data will be stored as a linear block of data. The active cursor will always be 32x32x2 bits in size.

Multiple cursor patterns may be loaded into off-screen memory. The start offset is loaded at the start of a

frame. Each cursor pattern will be exactly 256 bytes in size. Note that if there is a Y offset for the cursor

pattern, the cursor start offset should be set to point to the first displayed line of the cursor pattern. The

cursor code for a given pixel is determined by an AND mask and an XOR mask. Each line of a cursor will

be stored as two DWORDs, with each DWORD containing the AND masks for 16 pixels in the upper

word and the XOR masks for 16 pixels in the lower word. DWORDs will be arranged with the leftmost

block of 16 pixels being least significant and the rightmost block being most significant. Pixels within

words will be arranged with the leftmost pixels being most significant and the rightmost pixels being least

significant. The 2-bit cursor codes are as follows.

AND

XOR

Displayed

0

1

0

1

0

1

Cursor Color 0

Cursor Color 1

Transparent − Background Pixel

Inverted − Bit-wise Inversion of Background Pixel

GX_BASE+831Ch-831Fh

GX_BASE+8320h-8323h

Reserved

Default Value = 00000000h

Default Value = xxxxxxxxh

DC_VID_ST_OFFSET Register (R/W)

Reserved: Set to 0.

31:21

20:0

RSVD

VID_START

_OFFSET

Video Buffer Start Offset Value: This is the value for the Video Buffer Start Offset. It represents the

starting location for Video Buffer. Bits [3:0] should always be programmed as zero so that the start offset

is aligned to a 16 byte boundary.

GX_BASE+8324h-8327h

DC_LINE_DELTA Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:22

21:12

RSVD

CB_LINE_

DELTA

Compressed Display Buffer Line Delta: This value represents number of DWORDs that, when added

to the starting offset of the previous line, will point to the start of the next compressed line in memory. It

is used to always maintain a pointer to the starting offset for the compressed display buffer line being

loaded into the display FIFO.

11:10

9:0

RSVD

Reserved: Set to 0.

FB_LINE_

DELTA

Frame Buffer Line Delta: This value represents number of DWORDs that, when added to the starting

offset of the previous line, will point to the start of the next frame buffer line in memory. It is used to

always maintain a pointer to the starting offset for the frame buffer line being loaded into the display

FIFO.

GX_BASE+8328h-832Bh

DC_BUF_SIZE Register (R/W)

Default Value = xxxxxxxxh

31:30

29:16

RSVD

Reserved: Set to 0.

VID_BUF_

SIZE

Video Buffer Size: These bits set the video buffer size, in 64-byte segments. The maximum size is 1

MB.

15:9

8:0

CB_LINE_

SIZE

Compressed Display Buffer Line Size: This value represents the number of DWORDs for a valid com-

pressed line plus 1. It is used to detect an overflow of the compressed data FIFO. It should never be

larger than 41h or 65Dh since the maximum size of the compressed data FIFO is 64 DWORDs.

FB_LINE_

SIZE

Frame Buffer Line Size: This value specifies the number of QWORDS (8-byte segments) to transfer for

each display line from the frame buffer.

If panning is enabled, this value can generally be programmed to the displayed number of QWORDS + 2

so that enough data is transferred to handle any possible alignment. Extra pixel data in the FIFO at the

end of a line will automatically be discarded.

GX_BASE+832Ch-832Fh

Reserved

Default Value = 00000000h

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Integrated Functions (Continued)

4.5.11 Timing Registers

-

Contains CRT horizontal sync timing information.

Note, however, that this register should also be

programmed appropriately for flat panel only display

since the horizontal sync transition determines when

to advance the vertical counter.

The GXm processor timing registers control the genera-

tion of sync, blanking, and active display regions. They

provide complete flexibility in interfacing to both CRT and

flat panel displays. These registers will generally be pro-

grammed by the BIOS from an INT 10h call or by the

extended mode driver from a display timing file. Note that

the horizontal timing parameters are specified in character

clocks, which actually means pixels divided by 8, since all

characters are bit mapped. For interlaced display the ver-

tical counter will be incremented twice during each display

line, so vertical timing parameters should be programmed

with reference to the total frame rather than a single field.

•

Display Controller Flat Panel Horizontal Sync Timing

(DC_FP_H_TIMING)

-

Contains horizontal sync timing information for an

attached flat panel display.

Display Controller Vertical and Total Timing

(DC_V_TIMING_1)

-

Contains vertical active and total timing information.

The parameters pertain to both CRT and flat panel

display.

The Timing Registers group consists of six 32-bit registers

located at GX_BASE+8330h-834Ch. These registers are

described below and Table 4-32 gives their bit formats.

•

Display Controller CRT Vertical Blank Timing

(DC_V_TIMING_2)

-

•

Display Controller Horizontal and Total Timing

(DC_H_TIMING_1)

Contains vertical blank timing information.

-

Contains horizontal active and total timing informa-

tion.

Display Controller CRT Vertical Sync Timing

(DC_V_TIMING_3)

-

Contains CRT vertical sync timing information.

•

Display Controller CRT Horizontal Blanking Timing

(DC_H_TIMING_2 Register)

Display Controller Flat Panel Vertical Sync Timing

(DC_FP_V_TIMING)

-

Contains CRT horizontal blank timing information.

Contains flat panel vertical sync timing information.

Display Controller CRT Sync Timing

(DC_H_TIMING_3)

Table 4-32. Display Controller Timing Registers

Bit

Name

Description

GX_BASE+8330h-8333h

DC_H_TIMING_1 Register (R/W)

Default Value = xxxxxxxxh

31:27

26:19

RSVD

Reserved: Set to 0.

H_TOTAL

Horizontal Total: This field represents the total number of character clocks for a given scan line

minus 1. Note that the value is necessarily greater than the H_ACTIVE field because it includes bor-

der pixels and blanked pixels. For flat panels, this value will never change. The field [26:16] may be

programmed with the pixel count minus 1, although bits [18:16] are ignored. The horizontal total is

programmable on 8-pixel boundaries only.

18:16

15:11

10:3

RSVD

Reserved: These bits are readable and writable but have no effect.

Reserved: Set to 0.

H_ACTIVE

Horizontal Active: This field represents the total number of character clocks for the displayed por-

tion of a scan line minus 1. The field [10:0] may be programmed with the pixel count minus 1,

although bits [2:0] are ignored. The active count is programmable on 8-pixel boundaries only. Note

that for flat panels, if this value is less than the panel active horizontal resolution (H_PANEL), the

parameters H_BLANK_START, H_BLANK_END, H_SYNC_START, and H_SYNC_END should be

reduced by the value of H_ADJUST (or the value of H_PANEL - H_ACTIVE / 2)to achieve horizontal

centering.

2:0

RSVD

Reserved: These bits are readable and writable but have no effect.

Note: Note also that for simultaneous CRT and flat panel display the H_ACTIVE and H_TOTAL parameters pertain to both.

GX_BASE+8334h-8337h DC_H_TIMING_2 Register (R/W) Default Value = xxxxxxxxh

Reserved: Set to 0.

31:27

26:19

RSVD

H_BLK_END

Horizontal Blank End: This field represents the character clock count at which the horizontal blank-

ing signal becomes inactive minus 1. The field [26:16] may be programmed with the pixel count

minus 1, although bits [18:16] are ignored. The blank end position is programmable on 8-pixel

boundaries only.

18:16

15:11

RSVD

Reserved: These bits are readable and writable but have no effect.

Reserved: Set to 0.

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Integrated Functions (Continued)

Table 4-32. Display Controller Timing Registers (Continued)

Bit

Name

Description

10:3

H_BLK_START

Horizontal Blank Start: This field represents the character clock count at which the horizontal

blanking signal becomes active minus 1. The field [10:0] may be programmed with the pixel count

minus 1, although bits [2:0] are ignored. The blank start position is programmable on 8-pixel bound-

aries only.

2:0

RSVD

Reserved: These bits are readable and writable but have no effect.

Note: A minimum of four character clocks is required for the horizontal blanking portion of a line in order for the timing generator to

function correctly.

GX_BASE+8338h-833Bh

DC_H_TIMING_3 Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:27

26:19

RSVD

H_SYNC_END

Horizontal Sync End: This field represents the character clock count at which the CRT horizontal

sync signal becomes inactive minus 1. The field [26:16] may be programmed with the pixel count

minus 1, although bits [18:16] are ignored. The sync end position is programmable on 8-pixel bound-

aries only.

18:16

15:11

10:3

RSVD

Reserved: These bits are readable and writable but have no effect.

Reserved: Set to 0.

H_SYNC_START Horizontal Sync Start: This field represents the character clock count at which the CRT horizontal

sync signal becomes active minus 1. The field [10:0] may be programmed with the pixel count minus

1, although bits [2:0] are ignored. The sync start position is programmable on 8-pixel boundaries

only.

2:0

RSVD

Reserved: These bits are readable and writable but have no effect.

Note: This register should also be programmed appropriately for flat panel only display since the horizontal sync transition deter-

mines when to advance the vertical counter.

GX_BASE+833Ch-833Fh

C_FP_H_TIMING Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:27

26:16

RSVD

FP_H_SYNC

_END

Flat Panel Horizontal Sync End: This field represents the pixel count at which the flat panel hori-

zontal sync signal becomes inactive minus 1.

15:11

10:0

RSVD

Reserved: Set to 0.

FP_H_SYNC

_START

Flat Panel Horizontal Sync Start: This field represents the pixel count at which the flat panel hori-

zontal sync signal becomes active minus 1.

Note: All values are specified in pixels rather than character clocks to allow precise control over sync position. Note, however, that for

flat panels which combine two pixels per panel clock, these values should be odd numbers (even pixel boundary) to guarantee

that the sync signal will meet proper setup and hold times.

GX_BASE+8340h-8343h

DC_V_TIMING_1 Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:27

26:16

RSVD

V_TOTAL

Vertical Total: This field represents the total number of lines for a given frame scan minus 1. Note

that the value is necessarily greater than the V_ACTIVE field because it includes border lines and

blanked lines. If the display is interlaced, the total number of lines must be odd, so this value should

be an even number.

15:11

10:0

RSVD

Reserved: Set to 0.

V_ACTIVE

Vertical Active: This field represents the total number of lines for the displayed portion of a frame

scan minus 1. Note that for flat panels, if this value is less than the panel active vertical resolution

(V_PANEL), the parameters V_BLANK_START, V_BLANK_END, V_SYNC_START, and

V_SYNC_END should be reduced by the following value (V_ADJUST) to achieve vertical centering:

V_ADJUST = (V_PANEL - V_ACTIVE) / 2

If the display is interlaced, the number of active lines should be even, so this value should be an odd

number.

Note: All values are specified in lines.

GX_BASE+8344h-8347h

DC_V_TIMING_2 Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:27

26:16

RSVD

V_BLANK_END

Vertical Blank End: This field represents the line at which the vertical blanking signal becomes

inactive minus 1. If the display is interlaced, no border is supported, so this value should be identical

to V_TOTAL.

15:11

RSVD

Reserved: Set to 0.

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Integrated Functions (Continued)

Table 4-32. Display Controller Timing Registers (Continued)

Bit

Name

Description

10:0

V_BLANK_

START

Vertical Blank Start: This field represents the line at which the vertical blanking signal becomes

active minus 1. If the display is interlaced, this value should be programmed to V_ACTIVE plus 1.

Note: All values are specified in lines. For interlaced display, no border is supported, so blank timing is implied by the total/active tim-

ing.

GX_BASE+8348h-834Bh

DC_V_TIMING_3 Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:27

26:16

RSVD

V_SYNC_END

Vertical Sync End: This field represents the line at which the CRT vertical sync signal becomes

inactive minus 1.

15:11

10:0

RSVD

Reserved: Set to 0.

V_SYNC_START Vertical Sync Start: This field represents the line at which the CRT vertical sync signal becomes

active minus 1. For interlaced display, note that the vertical counter is incremented twice during each

line and since there are an odd number of lines, the vertical sync pulse will trigger in the middle of a

line for one field and at the end of a line for the subsequent field.

Note: All values are specified in lines.

GX_BASE+834Ch-834Fh

DC_FP_V_TIMING Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:27

26:16

RSVD

FP_V_SYNC

_END

Flat Panel Vertical Sync End: This field represents the line at which the flat panel vertical sync sig-

nal becomes inactive minus 2. Note that the internal flat panel vertical sync is latched by the flat

panel horizontal sync prior to being output to the panel.

15:11

10:0

RSVD

Reserved: Set to 0.

FP_VSYNC

_START

Flat Panel Vertical Sync Start: This field represents the line at which the internal flat panel vertical

sync signal becomes active minus 2. Note that the internal flat panel vertical sync is latched by the

flat panel horizontal sync prior to being output to the panel.

Note: All values are specified in lines.

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Integrated Functions (Continued)

4.5.12 Cursor Position Registers

•

Display Controller Vertical Line Count

(DC_V_LINE_CNT)

The Cursor Position Registers contain pixel coordinate

information for the cursor. These values are not latched by

the timing generator until the start of the frame to avoid

tearing artifacts when moving the cursor.

-

This register is read only. It provides the current

scanline for the display. It is used by software to time

update of the frame buffer to avoid tearing artifacts.

•

Display Controller Cursor Y Position (DC_CURSOR_Y)

The Cursor Position group consists of four 32-bit registers

located at GX_BASE+8350h-835Ch. These registers are

described below and Table 4-33 gives their bit formats.

-

Contains the Y position information of the hardware

cursor.

Display Controller Split-Screen Line Compare

(DC_SS_LINE_CMP)

•

Display Controller Cursor X Position (DC_CURSOR_X)

-

Contains the X position information of the hardware

cursor.

-

Contains the line count at which the lower screen

begins in a VGA split-screen mode.

Table 4-33. Display Controller Cursor Position Registers

Bit

Name

Description

GX_BASE+8350h-8353h

DC_CURSOR_X Register (R/W)

Default Value = xxxxxxxxh

31:16

15:11

RSVD

Reserved: Set to 0.

X_OFFSET

X Offset: This field represents the X pixel offset within the 32x32 cursor pattern at which the displayed

portion of the cursor is to begin. Normally, this value is set to zero to display the entire cursor pattern, but

for cursors for which the "hot spot" is not at the left edge of the pattern, it may be necessary to display

the rightmost pixels of the cursor only as the cursor moves close to the left edge of the display.

10:0

CURSOR_X Cursor X: This field represents the X coordinate of the pixel at which the upper left corner of the cursor

is to be displayed. This value is referenced to the screen origin (0,0) which is the pixel in the upper left

corner of the screen.

GX_BASE+8354h-8357h

DC_V_LINE_CNT Register (RO)

Reserved (Read Only)

Default Value = xxxxxxxxh

31:11

10:0

RSVD

V_LINE_CNT Vertical Line Count (Read Only): This value is the current scanline of the display.

(RO)

Note: The value in this register is driven directly off of the DOTCLK, and consequently it is not synchronized with the CPU clock. Soft-

ware should read this register twice and compare the result to ensure that the value is not transitioning.

GX_BASE+8358h-835Bh

DC_CURSOR_Y Register (R/W)

Default Value = xxxxxxxxh

31:16

15:11

RSVD

Reserved: Set to 0.

Y_OFFSET

Y Offset: This field represents the Y line offset within the 32x32 cursor pattern at which the displayed

portion of the cursor is to begin. Normally, this value is set to zero to display the entire cursor pattern, but

for cursors for which the "hot spot" is not at the top edge of the pattern, it may be necessary to display

the bottommost lines of the cursor only as the cursor moves close to the top edge of the display. Note

that if this value is nonzero, the CUR_START_OFFSET must be set to point to the first cursor line to be

displayed.

10

RSVD

Reserved: Set to 0.

9:0

CURSOR_Y Cursor Y: This field represents the Y coordinate of the line at which the upper left corner of the cursor is

to be displayed. This value is referenced to the screen origin (0,0) which is the pixel in the upper left cor-

ner of the screen.

This field is alternately used as the line-compare value for a newly-programmed frame buffer start offset.

This is necessary for VGA programs that change the start offset in the middle of a frame. In order to use

this function, the hardware cursor function should be disabled.

GX_BASE+835Ch-835Fh

DC_SS_LINE_CMP Register (R/W)

Reserved: Set to 0.

SS_LINE_CM Split-Screen Line Compare: This is the line count at which the lower screen begins in a VGA split-

screen mode.

Default Value = xxxxxxxxh

31:11

10:0

RSVD

P

Note: When the internal line counter hits this value, the frame buffer address is reset to 0. This function is enabled with the SSLC bit

in the DC_GENERAL_CFG register.

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4.5.13 Color Registers

The Color Registers group consists of two 32-bit registers

located at GX_BASE+8360h-8368h. These registers are

described below and Table 4-34 gives their bit formats.

These registers are used in 8 BPP display mode with an

external RAMDAC for passing cursor and border color

indices to the palette in the RAMDAC. For the flat panel

color translation, the cursor and border color data is

loaded into palette extensions as described in the Palette

Access Registers section.

•

Display Controller Cursor Color

(DC_CURSOR_COLOR)

-

Contains the 8-bit indices for the cursor colors.

•

Display Controller Border Color

(DC_BORDER_COLOR)

Contains the 8-bit index for the border or overscan color.

Table 4-34. Display Controller Color Registers

Bit

Name

Description

GX_BASE+8360h-8363h

DC_CURSOR_COLOR Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:16

15:8

RSVD

CURS_CLR_1

Cursor Color 1: This is the 8-bit index to the external palette for the cursor color 1. It should point to

a reserved or static color.

7:0

CURS_CLR_0

Cursor Color 0: This is the 8-bit index to the external palette for the cursor color 0. It should point to

a reserved or static color.

GX_BASE+8364h-8367h

GX_BASE+8368h-836Bh

Reserved

Default Value = 00000000h

Default Value = xxxxxxxxh

DC_BORDER_COLOR Register (RO)

31:8

7:0

RSVD

Reserved: Set to 0.

BORDER_CLR

Border Color: This is the 8-bit index to the external palette for the border color. It should point to a

reserved or static color.

GX_BASE+836Ch-836Fh

Reserved

Default Value = 00000000h

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4.5.14 Palette Access Registers

•

Display Controller Palette Data (DC_PAL_DATA)

Contains the data for a palette access cycle.

-

These registers are used for accessing the internal palette

RAM and extensions. In addition to the standard 256

entries for 8 BPP color translation, the GXm processor

palette has extensions for cursor colors and overscan

(border) color.

Display Controller Display FIFO Diagnostic

(DC_DFIFO_DIAG)

-

This register is provided to enable testability of the

Display FIFO RAM.

The Palette Access Register group consists of four 32-bit

registers located at GX_BASE+8370h-837Ch. These reg-

isters are described below and Table 4-35 gives their bit

formats.

•

Display Controller Compression FIFO Diagnostic

(DC_CFIFO_DIAG)

-

This register is provided to enable testability of the

Compressed Line Buffer (FIFO) RAM.

•

Display Controller Palette Address

(DC_PAL_ADDRESS)

-

This register should be written with the address

(index) location to be used for the next access to the

DC_PAL_DATA register.

Table 4-35. Display Controller Palette and RAM Diagnostic Registers

Bit

Name

Description

GX_BASE+8370h-8373h

DC_PAL_ADDRESS Register (R/W)

Reserved: Set to 0.

Default Value = xxxxxxxxh

31:9

8:0

RSVD

PALETTE_ADDR Palette Address: This 9-bit field specifies the address to be used for the next access to the

DC_PAL_DATA register. Each access to the data register will automatically increment the palette

address register. If non-sequential access is made to the palette, the address register must be

loaded between each non-sequential data block. The address ranges are as follows.

Address

0h - FFh

100h

101h

102h

Color

Standard Palette Colors

Cursor Color 0

Cursor Color 1

Reserved

103h

Reserved

104h

105h - 1FFh

Overscan Color

Not Valid

Note that in general, 18-bit values will be loaded for all color extensions. However, if a 16 BPP mode

is active, only the appropriate most significant bits will be used (5-5-5 or 5-6-5). If an 8 BPP display

mode is active and an external RAMDAC is used, the cursor index will be obtained from the

DC_CURSOR_COLOR register. The border index will be obtained from the DC_BORDER_COLOR

register.

GX_BASE+8374h-8377h

DC_PAL_DATA Register (R/W)

Reserved: Set to 0.

PALETTE_DATA Palette Data: This 18-bit field contains the read or write data for a palette access.

Default Value = xxxxxxxxh

31:18

17:0

RSVD

Note: When a read or write to the palette RAM occurs, the previous output value will be held for one additional DOTCLK period. This

effect should go unnoticed and will provide for sparkle-free update. Prior to a read or write to this register, the

DC_PAL_ADDRESS register should be loaded with the appropriate address. The address automatically increments after each

access to this register, so for sequential access, the address register need only be loaded once

GX_BASE+8378h-837Bh

DC_DFIFO_DIAG Register (R/W)

Default Value = xxxxxxxxh

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Integrated Functions (Continued)

Table 4-35. Display Controller Palette and RAM Diagnostic Registers (Continued)

Bit

Name

Description

31:0

DISPLAY FIFO

Display FIFO Diagnostic Read or Write Data: Before this register is accessed, the DIAG bit in

DIAGNOSTIC

DATA

DC_GENERAL_CFG register should be set high and the DFLE bit should be set low. Since, each

FIFO entry is 64 bits, an even number of write operations should be performed. Each pair of write

operations will cause the FIFO write pointer to increment automatically. After all write operations

have been performed, a single read of don't care data should be performed to load data into the out-

put latch. Each subsequent read will contain the appropriate data which was previously written.

Each pair of read operations will cause the FIFO read pointer to increment automatically. A pause of

at least four core clocks should be allowed between subsequent read operations to allow adequate

time for the shift to take place.

GX_BASE+837Ch-837Fh

DC_CFIFO_DIAG Register (R/W)

Compressed Data FIFO Diagnostic Read or Write Data: Before this register is accessed, the

FIFO DIAGNOS- DIAG bit in DC_GENERAL_CFG register should be set high and the DFLE bit should be set low.

Default Value = xxxxxxxxh

31:0

COMPRESSED

TIC DATA

Also, the DIAG bit in DC_OUTPUT_CFG should be set high and the CFRW bit in

DC_OUTPUT_CFG should be set low. After each write, the FIFO write pointer will automatically

increment. After all write operations have been performed, the CFRW bit of DC_OUTPUT_CFG

should be set high to enable read addresses to the FIFO and a single read of don't care data should

be performed to load data into the output latch. Each subsequent read will contain the appropriate

data which was previously written. After each read, the FIFO read pointer will automatically incre-

ment.

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Integrated Functions (Continued)

4.5.15 CS5530 Display Controller Interface

As previously stated in Section 1.6 “Geode GXM/CS5530

System Designs” on page 11, the GXm processor inter-

faces with either the CS5530 I/O companion chip. This

section will discuss the specifics on signal connections

between the two devices with regards to the display con-

troller.

When the GXm processor is used in a system with the

CS5530 I/O companion chip, the need for an external

RAMDAC is eliminated. The CS5530 contains the DACs,

a video accelerator engine, and the TFT interface.

A GXm processor and CS5530-based system supports

both portable and desktop configurations. Figure 4-16

shows the signal connections for both types of systems.

Portable

Configuration

Power

Control

Logic

FP_ENA_VDD

FP_ENA_BKL

FP_DISP_ENA_OUT

VDD

12VBKL

ENAB

Geode™ GXm

Processor

FP_HSYNC

FP_VSYNC

FP_CLK

HSYNC

VSYNC

CLK

PCLK

VID_CLK

PCLK

VID_CLK

DCLK

TFT

Flat

DCLK

Panel

FP_HSYNC

FP_VSYNC

ENA_DISP

VID_RDY

FP_HSYNC

FP_VSYNC

FP_DISP_ENA

VID_RDY

VID_DATA[7:0]

PIXEL[23:18]*

PIXEL[15:10]*

PIXEL[7:2]*

VID_VAL

FP_DATA[17:12]

FP_DATA[11:16]

FP_DATA[5:0]

R[5:0]

G[5:0]

B[5:0]

VID_DATA[7:0]

PIXEL[17:12]

PIXEL[11:6]

PIXEL[5:0]

VID_VAL

HSYNC_OUT

VSYNC_OUT

Pin 13 Pin 3

Pin 14 Pin 2

Pin 1

CRT_HSYNC

CRT_VSYNC

HSYNC

VSYNC

VGA

Port

DDC_SCL

DDC_SDA

Pin 15

Pin 12

Geode™ CS5530

I/O Companion

IOUTR

IOUTG

IOUTB

Figure 4-16. Display Controller Signal Connections

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Integrated Functions (Continued)

4.5.15.1 CS5530 Video Port Data Transfer

VID_DATA[7:0] is advanced when both VID_VAL and

VID_RDY are asserted. VID_RDY is driven one clock

early to the GXm processor while VID_VAL is driven coin-

cident with VID_DATA[7:0]. A sample interface functional

timing diagram is shown in Figure 4-17.

VID_VAL indicates that the GXm processor has placed

valid data on VID_DATA[7:0]. VID_RDY indicates that the

CS5530 is ready to accept the next byte of video data.

VID_CLK

8 + 3 CLKs

VID_VAL

VID_RDY

8 CLKs

3 CLKs

VID_DATA

[7:0]

4 CLKs

8 CLKs

1

2

1

2

4 CLKs

CLK CLKs CLK CLKs

CLKs

Note: VID_CLK = CORE_CLK/2

Figure 4-17. Video Port Data Transfer (CS5530)

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Integrated Functions (Continued)

4.6 PCI CONTROLLER

The GXm processor includes an integrated PCI controller

with the following features.

4.6.4 Generating Configuration Cycles

Configuration space is a physical address space unique to

PCI. Configuration Mechanism #1 must be used by soft-

ware to generate configuration cycles. Two DWORD I/O

locations are used in this mechanism. The first DWORD

location (CF8h) references a read/write register that is

named CONFIG_ADDRESS. The second DWORD

4.6.1 X-Bus PCI Slave

•

16-byte PCI write buffer

16-byte PCI read buffer from X-bus

Supports cache line bursting

Write/Inv line support

Pacing of data for read or write operations with X-bus

No active byte enable transfers supported

address (CFCh) references

CONFIG_DATA. The general method for accessing con-

figuration space is to write value into

a

register named

a

CONFIG_ADDRESS that specifies the PCI bus, device on

that bus, and configuration register in that device being

accessed. A read or write to CONFIG_DATA will then

cause the bridge to translate that CONFIG_ADDRESS

value to the requested configuration cycle on the PCI bus.

4.6.2 X-Bus PCI Master

•

16 byte X-bus to PCI write buffer

Configuration read/write Support

Int Acknowledge support

Lock conversion

Support fast back-to-back cycles as slave

4.6.5 Generating Special Cycles

A special cycle is a broadcast message to the PCI bus.

Two hardcoded special cycle messages are defined in the

command encode: HALT and SHUTDOWN. Software can

also generate special cycles by using special cycle gener-

ation for configuration mechanism #1 as described in the

PCI Specification 3.6.4.1.2 and briefly described here. To

initiate a special cycle from software, the host must write a

value to CONFIG_ADDRESS encoded as shown in Table

4-36.

4.6.3 PCI Arbiter

•

Fixed, rotating, hybrid, or ping-pong arbitration

(programmable)

•

Support four masters, three on PCI

Internal REQ for CPU

Master retry mask counter

Master dead timer

Resource or total system lock support

The next value written to CONFIG_DATA is the encoded

special cycle. Type 0 or Type 1 conversion will be based

on the Bus Bridge number matching the GXm processor’s

bus number of 00h.

Table 4-36. Special-Cycle Code to CONFIG_ADDRESS

31

30

24

23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

1

0 0 0 0 0 0 0

RSVD

Bus No. = Bridge

BUS NUMBER

1

0

T

CONFIG

ENABLE

DEVICE NUMBER FUNCTION REGISTER NUMBER TRANS

NUMBER

LATION

TYPE

Note: See Table 4-37 on page 156, bits [1:0] for translation type.

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Integrated Functions (Continued)

4.6.6 PCI Configuration Space Control Registers

this register all others will be forwarded as normal I/O

cycles to the PCI bus.

There

are

two

registers

in

this

category:

CONFIG_ADDRESS and CONFIG_DATA.

The CONFIG_DATA register contains the data that is sent

or received during a PCI configuration space access.

The CONFIG_ADDRESS register contains the address

information for the next configuration space access to

CONFIG_DATA. Only DWORD accesses are permitted to

Table 4-37 gives the bit formats for these two registers.

Table 4-37. PCI Configuration Registers

Bit

Name

Description

I/O Offset 0CF8h-0CFBh

CONFIG_ADDRESS Register (R/W)

Default Value = 00000000h

31

CFG_EN

Config Enable: Determines when accesses should be translated to configuration cycles on the PCI

bus, or treated as a normal I/O operation. This register will be updated only on full DWORD I/O oper-

ations to the CONFIG_ADDRESS. Any other accesses are treated as normal I/O cycles in order to

allow I/O devices to use BYTE or WORD registers at the same address an remain unaffected. Once

bit 31 is set high, subsequent accesses to CONFIG_DATA are then translated to configuration

cycles.

1 = Generate configuration cycles

0 = Normal I/O cycles

30:24

23:16

15:11

RSVD

BUS

Reserved: Set to 0.

Bus: Specifies a PCI bus number in the hierarchy of 1 to 256 buses.

DEVICE

Device: Selects a device on a specified bus. A device value of 00h will select the GXm processor if

the bus number is also 00h. DEVICE values of 01h to 15h will be mapped to AD[31:11], so only 21 of

the 32 possible devices are supported. A DEVICE value of 00001b will map to AD[11] while a device

of 10101b will map to AD[31].

10:8

7:2

FUNCTION

REGISTER

TT

Function: Selects a function in a multi-function device.

Register: Chooses a configuration DWORD space register in the selected device.

1:0

Translation Type Bits: These bits indicate if the configuration access is local or one that requires

translation through other bridges to another PCI bus. When an access occurs to the CONFIG_DATA

address and the specified bus number matches the GXm processor’s bus number (00h), then a

Type 0 translation takes place.

For a Type 0 translation, the CONFIG_ADDRESS register values are translated to AD lines on the

PCI bus. Note that bits 10:2 are passed unchanged. The DEVICE value is mapped to one of 21 AD

lines. The translation type bits are set to 00 to indicate a transaction on the local PCI bus.

When an access occurs to the CONFIG_DATA address and the specified bus number is not 00h

(Type 1), the GXm processor passes this cycle to the PCI bus by copying the contents of the

CONFIG_ADDRESS register onto the AD lines during the address phase of the cycle while driving

the translation type bits AD[1:0] to 01.

I/O Offset 0CFCh-0CFFh

CONFIG_DATA (R/W)

Default Value = 00000000h

31:0

CONFIG_DATA

Configuration Data Register: Contains the data that is sent or received during a PCI configuration

space access. The register accessed is determined by the value in the CONFIG_ADDRESS regis-

ter. The CONFIG_DATA register supports BYTE, WORD, or DWORD accesses. To access this reg-

ister, bit 31 of the CONFIG_ADDRESS register must be set to 0 and a full DWORD I/O access must

be done. Configuration cycles are performed when bit 31 of the CONFIG_ADDRESS register is set

to 1

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Integrated Functions (Continued)

4.6.7 PCI Configuration Space Registers

cant bits of the offset are used, and the two least signifi-

cant bits must be 00b.

To access the internal PCI configuration registers of the

GXm processor, the Configuration Address Register

(CONFIG_ADDRESS) must be written as a DWORD

using the format shown in Table 4-38. Any other size will

be interpreted as an I/O write to Port 0CF8h. Also, when

entering the Configuration Index, only the six most signifi-

Table 4-39 summarizes the registers located within the

Configuration Space. The tables that follow, give detailed

register/bit formats.

Table 4-38. Format for Accessing the Internal PCI Configuration Registers

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

RESERVED

9

8

7

6

5

4

3

2

1

0

1

0

Configuration Index

0

Table 4-39. PCI Configuration Space Register Summary

Index

Type

Name

Default Value

00h-01h

02h-03h

04h-05h

06h-07h

08h

RO

R/W

RO

R/W

--

Vendor Identification

Device Identification

PCI Command

1078h

0001h

0007h

0280h

00h

Device Status

Revision Identification

Class Code

09h-0Bh

0Ch

060000h

00h

Cache Line Size

Latency Timer

0Dh

0Eh-3Fh

40h

Reserved

00h

R/W

--

PCI Control Function 1

PCI Control Function 2

Reserved

00h

41h

96h

42h

00h

43h

R/W

--

PCI Arbitration Control 1

PCI Arbitration Control 2

Reserved

80h

44h

00h

45h-FFh

00h

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Integrated Functions (Continued)

Table 4-40. PCI Configuration Registers

Bit

Name

Description

Index 00h-01h

Vendor Identification Register (RO)

Default Value = 1078h

31:0

VID (RO)

Vendor Identification Register (Read Only): The combination of this value and the device ID uniquely

identifies any PCI device. The Vendor ID is the ID given to national Semiconductor Corporation by the

PCI SIG.

Index 02h-03h

Device Identification Register (RO)

Default Value = 0001h

31:0

DIR (RO)

Device Identification Register (Read Only): This value along with the vendor ID uniquely identifies any

PCI device.

Index 04h-05h

PCI Command Register (R/W)

Default Value = 0007h

15:10

9

RSVD

FBE

Reserved: Set to 0.

Fast Back-to-Back Enable: As a master, the GXm processor does not support this function.

This bit returns 0.

8

7

SERR

WAT

SERR# Enable: This is used as an output enable gate for the SERR# driver.

Wait Cycle Control: GXm processor does not do address/ data stepping.

This bit is always set to 0.

6

PE

Parity Error Response:

0 = GXm processor ignores parity errors on the PCI bus.

1 = GXm processor checks for parity errors.

5

4

3

2

VPS

MS

VGA Palette Snoop: GXm processor does not support this function.

This bit is always set to 0.

Memory Write and Invalidate Enable: As a master, the GXm processor does not support this function.

This bit is always set to 0.

SPC

BM

Special Cycles: GXm processor does not respond to special cycles on the PCI bus.

This bit is always set to 0.

Bus Master:

0 = GXm processor does not perform master cycles on the PCI.

1 = GXm processor can act as a bus master on the PCI.

1

0

MS

Memory Space: GXm processor will always respond to memory cycles on the PCI.

This bit is always set to 1.

IOS

I/O Space: GXm processor will not respond to I/O accesses from the PCI.

This bit is always set to 1.

Index 06h-07h

PCI Device Status Register (RO, R/W Clear)

Default Value = 0280h

15

DPE

Detected Parity Error: When a parity error is detected, this bit is set to 1.

This bit can be cleared to 0 by writing a 1 to it.

14

13

SSE

Signaled System Error: This bit is set whenever SERR# is driven active.

RMA

Received Master Abort: This bit is set whenever a master abort cycle occurs. A master abort will occur

whenever a PCI cycle is not claimed except for special cycles.

This bit can be cleared to 0 by writing a 1 to it.

12

11

RTA

STA

Received Target Abort: This bit is set whenever a target abort is received while the GXm processor is

master of the cycle.

This bit can be cleared to 0 by writing a 1 to it.

Signaled Target Abort: This bit is set whenever the GXm processor signals a target abort. A target

abort is signaled when an address parity occurs for an address that hits in the GXm processor’s address

space.

This bit can be cleared to 0 by writing a 1 to it.

10:9

DT

Devise Timing:

00 = Fast

01 = Medium

10 = Slow

11 = Reserved

The GXm processor performs medium DEVSEL# active for addresses that hit into the GXm processor

address space. These two bits are always set to 01.

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Table 4-40. PCI Configuration Registers (Continued)

Bit

Name

Description

8

DPD

Data Parity Detected: This bit is set when three conditions are met.

1) GXm processor asserted PERR# or observed PERR# asserted;

2) GXm processor is the master for the cycle in which the PERR# occurred; and

3) PE (bit 6 of Command Register) is enabled.

This bit can be cleared to 0 by writing a 1 to it.

7

FBS

Fast Back-to-Back Capable: As a target, the processor is capable of accepting Fast Back-to-Back

transactions.

This bit is always set to 1.

6:0

Index 08h

7:0

RSVD

Reserved: Set to 0.

Revision Identification Register (RO)

Default Value = 00h

RID (RO)

Revision ID (Read Only): This register contains the revision number of the GXm design.

Index 09h-0Bh

Class Code Register (RO)

Default Value = 060000h

23:16

CLASS

Class Code: The class code register is used to identify the generic function of the device. The

GXm processor is classified as a host bridge device (06).

15:0

Index 0Ch

7:0

RSVD (RO)

Reserved (Read Only)

Cache Line Size Register (RO)

Default Value = 00h

CACHELINE Cache Line Size (Read Only): The cache line size register specifies the system cacheline size in units

of 32-bit words. This function is not supported in the GXm processor.

Index 0Dh

Latency Timer Register (R/W)

Default Value = 00h

7:5

4:0

RSVD

Reserved: Set to 0.

LAT_TIMER Latency Timer: The latency timer as used in this implementation will prevent a system lockup resulting

from a slave the does not responded to the master. If the register value is set to 00h, the timer is dis-

abled. Otherwise, Timer represents the 5 MSBs of an 8-bit counter. The counter will reset on each valid

data transfer. If the counter expires before the next TRDY# is received active, then the slave is consid-

ered to be incapable of responding, and the master will stop the transaction with a master abort and flag

an SERR# active. This would also keep the master from being retried forever by a slave device that con-

tinues to issue retries. In these cases, the master will also stop the cycle with a master abort.

Index 0Eh-3Fh

Index 40h

Reserved

Default Value = 00h

PCI Control Function 1 Register (R/W)

7

6

RSVD

SW

Reserved: Set to 0.

Single Write Mode: PCI slave supports:

0 = Multiple PCI write cycles

1 = Single cycle write transfers on the PCI bus. The slave will perform a target disconnect with the first

data transferred.

5

4

SR

Single Read Mode: PCI slave supports:

0 = Multiple PCI read cycles.

1 = Single cycle read transfers on the PCI bus. The slave will perform a target disconnect with the first

data transferred.

RXBNE

Force Retry when X-Bus Buffers are Not Empty:

0 = PCI slave accepts the PCI cycle with data in the PCI master write buffers. The data in the PCI master

write buffers will not be affected or corrupted. The PCI master holds request active indicating the need to

access the PCI bus.

1 = PCI slave retries cycles if the PCI master X-bus write buffers contain buffered data.

PCI Slave Write Buffer Enable: PCI slave write buffers: 0 = Disable; 1 = Enable.

PCI Cache Line Read Enable: Read operations from the PCI into the GXm processor:

3

2

SWBE

CLRE

0 = Single cycle unless a read multiple or memory read line command is used.

1 = Cause a cache line read to occur.

1

0

XBE

X-Bus Burst Enable: PCI slave acting as a master performs burst cycles on the X-bus on write-back

invalidate cycles from the PCI. 0 = Disable; 1 = Enable.

(This bit does not control read bursting; bit 2 does.)

RSVD

Reserved: Should return a value of 0.

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Table 4-40. PCI Configuration Registers (Continued)

Bit

Name

Description

Index 41h

PCI Control Function 2 Register (R/W)

Reserved: Set to 0.

Default Value = 96h

7

6

5

RSVD

RW_CLK

PFS

RAW Clock: A debug signal used to view internal clock operation. 0 = Disable; 1 = Enable.

PERR# forces SERR#: PCI master drives an active SERR# anytime it also drives or receives an active

PERR#: 0 = Disable; 1 = Enable.

4

XWB

SDB

X-Bus to PCI Write Buffer: Enable GXm processor PCI master’s X-Bus write buffers (non-locked mem-

ory cycles are buffered, I/O cycles and lock cycles are not buffered): 0 = Disable; 1 = Enable.

3:2

Slave Disconnect Boundary: PCI slave issues a disconnect with data when it crosses line boundary:

00 = 128 bytes

01 = 256 bytes

10 = 512 bytes

11 = 1024 bytes

Works in conjunction with bit 1.

1

0

SDBE

XWS

Slave Disconnect Boundary Enable:

0 = PCI slave disconnects on boundaries set by bits [3:2].

1 = PCI disconnects on cache line boundary which is 16 bytes.

X-Bus Wait State Enable: The PCI slave acting as a master on the X-bus will insert wait states on write

cycles for data setup time. 0 = Disable; 1 = Enable.

Index 43h

PCI Arbitration Control 1 Register (R/W)

Default Value = 80h

7

BG

Bus Grant:

0 = Grants bus regardless of X-bus buffers.

1 = Grants bus only if X-bus buffers are empty.

6

5

RSVD

RME2

Reserved: Set to 1.

REQ2# Retry Mask Enable: Arbiter allows the REQ2# to be masked based on the master retry mask in

bits [2:1]: 0 = Disable; 1 = Enable.

4

3

RME1

RME0

MRM

REQ1# Retry Mask Enable: Arbiter allows the REQ1# to be masked based on the master retry mask in

bits [2:1]: 0 = Disable; 1 = Enable.

REQ0# Retry Mask Enable: Arbiter allows the REQ0# to be masked based on the master retry mask in

bits [2:1]: 0 = Disable; 1 = Enable.

2:1

Master Retry Mask: When a target issues a retry to a master, the arbiter can mask the request from the

retried master in order to allow other lower order masters to gain access to the PCI bus:

00 = No retry mask

01 = Mask for 16 PCI clocks

10 = Mask for 32 PCI clocks

11 = Mask for 64 PCI clocks

0

HXR

Hold X-bus on Retries: Arbiter holds the X-Bus X_HOLD for two additional clocks to see if the retried

master will request the bus again: 0 = Disable; 1 = Enable

(This may prevent retry thrashing in some cases.)

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Integrated Functions (Continued)

Table 4-40. PCI Configuration Registers (Continued)

Bit

Name

Description

Index 44h

PCI Arbitration Control 2 Register (R/W)

Default Value = 00h

7

PP

Ping-Pong:

0 = Arbiter grants the processor bus per the setting of bits [2:0].

1 = Arbiter grants the processor bus ownership of the PCI bus every other arbitration cycle.

6:4

FAC

Fixed Arbitration Controls: These bits control the priority under fixed arbitration. The priority table is as

follows (priority listed highest to lowest):

000 = REQ0#, REQ1#, REQ2#

001 = REQ1#, REQ0#, REQ2#

010 = REQ0#, REQ2#,REQ1#

011 = Reserved

100 = REQ1#, REQ2#, REQ0#

101 = Reserved

110 = REQ2#, REQ1#, REQ0#

111 = REQ2#, REQ0#, REQ1#

Note: The rotation arbitration bits [2:0] must be set to 000 for full fixed arbitration. If rotation bits are not

set to 000, then hybrid arbitration will occur. If Ping-Pong is enabled (bit 7 = 1), the processor will

have priority every other arbitration. In this mode, the arbiter grants the PCI bus to a master and

ignores all other requests. When the master finishes, the processor will be guaranteed access. At

this point PCI requests will again be recognized. This will switch arbitration from CPU-to-PCI to

CPU-to-PCI, etc.

3

RSVD

--

Reserved: Set to 0.

45h-FFh

Reserved

Revision 3.1

161

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Integrated Functions (Continued)

4.6.8 PCI Cycles

The following sections and diagrams provide the func-

tional relationships for PCI cycles.

valid address and C/BE[3:0]# contains a valid bus com-

mand. The first data phase begins on clock 3. During the

data phase, AD[31:0] contains data and C/BE[3:0]# indi-

cate which byte lanes of AD[31:0] carry valid data. The

first data phase completes with zero delay cycles. How-

ever, the second phase is delayed one cycle because the

target was not ready so it deasserted TRDY# on clock 5.

The last data phase is delayed one cycle because the

master deasserted IRDY# on clock 7.

4.6.8.1 PCI Read Transaction

A PCI read transaction consists of an address phase and

one or more data phases. Data phases may consist of

wait cycles and a data transfer. Figure 4-18 illustrates a

PCI read transaction. In this example, there are three data

phases.

For additional information refer to Chapter 3.3.1, Read

Transaction, of the PCI Local Bus Specification, Revision

2.1.

The address phase begins on clock 2 when FRAME# is

asserted. During the address phase, AD[31:0] contains a

CLK

FRAME#

DATA-3

ADDR

DATA-2

DATA-1

AD

C/BE#

BUS CMD

BE#s

IRDY#

TRDY#

DEVSEL#

DATA

PHASE

ADDR

PHASE

DATA

PHASE

DATA

PHASE

BUS TRANSACTION

Figure 4-18. Basic Read Operation

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Integrated Functions (Continued)

4.6.8.2 PCI Write Transaction

The address phase begins on clock 2 when FRAME# is

asserted. The first and second data phases complete

without delays. During data phase 3, the target inserts

three wait cycles by deasserting TRDY#.

A PCI write transaction is similar to a PCI read transac-

tion, consisting of an address phase and one or more data

phases. Since the master provides both address and

data, no turnaround cycle is required following the

address phase. The data phases work the same for both

read and write transactions. Figure 4-19 illustrates a write

transaction.

For additional information refer to Chapter 3.3.2, Write

Transaction, of the PCI Local Bus Specification, Revision

2.1.

CLK

FRAME#

DATA-3

BE#’s-3

DATA-2

DATA-1

ADDR

AD

BE#’s-2

BUS CMD BE#’s-1

C/BE#

IRDY#

TRDY#

DEVSEL#

DATA

PHASE

DATA

PHASE

DATA

PHASE

ADDR

PHASE

BUS TRANSACTION

Figure 4-19. Basic Write Operation

Revision 3.1

163

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Integrated Functions (Continued)

4.6.8.3

PCI Arbitration

The GXm processor’s PCI arbiter can then grant access

to agent A, and does so on clock 7. Note that all buffers

must flush before a grant is given to a new agent.

An agent requests the bus by asserting its REQ#. Based

on the arbitration scheme set in the PCI Arbitration Con-

trol 2 Register (Index 44h), the GX PCI arbiter will grant

the request by asserting GNT#. Figure 4-20 illustrates

basic arbitration.

For additional information refer to Chapter 3.4.1, Arbitra-

tion Signaling Protocol, of the PCI Local Bus Specifica-

tion, Revision 2.1.

REQ#-a is asserted at clock 1. The PCI GXm processor

arbiter grants access to Agent A by asserting GNT#-a on

clock 2. Agent A must begin a transaction by asserting

FRAME# within 16 clocks, or the GX PCI arbiter will

remove GNT#. Also, it is possible for Agent A to lose bus

ownership sooner if another agent with higher priority

requests the bus. However, in this example, Agent A

starts the transaction on clock 3 by asserting FRAME#

and completes its transaction. Since Agent A requests

another transaction, REQ#-a remains asserted. When

FRAME# is asserted on clock 3, the GXm processor’s PCI

arbiter determines Agent B should go next, asserts

GNT#-b and deasserts GNT#-a on clock 4. Agent B

requires only a single transaction. It completes the trans-

action, then deasserts FRAME# and REQ#-b on clock 6.

4.6.8.4

PCI Halt Command

Halt is a broadcast message from the processor indicating

it has executed a halt instruction. The PCI Special Cycle

command is used to broadcast the message to all agents

on the bus segment. During the address phase of the Halt

Special cycle, C/BE[3:0]# = 0001 and AD[31:0] are driven

to random values. During the data phase, C/BE[3:0]# =

1100 indicating bytes 1 and 0 are valid and AD[15:0] =

0001h.

For additional information, refer to Chapter 3.7.2, Special

Cycle, and Appendix A, Special Cycle Messages, of the

PCI Local Bus Specification, Revision 2.1.

CLK

REQ#-a

REQ#-b

GNT#-a

GNT#-b

FRAME#

ADDR

DATA

AD

access-a

access-b

Figure 4-20. Basic Arbitration

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5.0 Virtual Subsystem Architecture

This section describes the Virtual Subsystem Architec-

ture^®(VSA™) as implemented with the Geode GXm pro-

cessor(s) and VSA enhanced I/O companion device(s).

VSA provides a framework to enable software implemen-

tation of traditionally hardware-only components. VSA

software executes in System Management Mode (SMM),

enabling it to execute transparently to the operating sys-

tem, drivers and applications.

5.1 VIRTUAL VGA

The GXm processor reduces the burden of PC-legacy

hardware by using a balanced mix of hardware and soft-

ware to provide the same functionality. The graphics pipe-

line contains full hardware support for the VGA “front-

end”, the logic that controls read and write operations to

the VGA frame buffer (located in graphics memory). For

some modes, the hardware can also provide direct display

of the data in the VGA buffer. Virtual VGA traps frame

buffer accesses only when necessary, but it must trap all

VGA I/O accesses to maintain the VGA state and properly

program the graphics pipeline and display controller.

The VSA design is based upon a simple model for replac-

ing hardware components with software. Hardware to be

virtualized is merely replaced with simple access detec-

tion circuitry which asserts the processor’s SMI# (System

Management Interrupt) pin when hardware accesses are

detected. The current execution stream is immediately

preempted, and the processor enters SMM. The SMM

system software then saves the processor state, initializes

the VSA execution environment, decodes the SMI source

and dispatches handler routines which have registered

requests to service the decoded SMI source. Once all

handler routines have completed, the processor state is

restored and normal execution resumes. In this manner,

hardware accesses are transparently replaced with the

execution of SMM handler software.

VGA functionality with the GXm processor includes the

standard VGA modes (VGA, EGA, CGA, and MDA) as

well as the higher-resolution VESA modes. The CGA and

MDA modes (modes 0 through 7) require that Virtual VGA

convert the data in the VGA buffer to a separate 8-BPP

frame buffer that the hardware can use for display refresh.

The remaining modes, VGA, EGA, and VESA, can be dis-

played directly by the hardware, with no data conversion

required. For these modes, Virtual VGA outperforms typi-

cal VGA cards because the frame buffer data does not

travel across an external bus.

Historically, SMM software was used primarily for the sin-

gle purpose of facilitating active power management for

notebook designs. That software’s only function was to

manage the power up and down of devices to save power.

With high performance processors now available, it is fea-

sible to implement, primarily in SMM software, PC capa-

bilities traditionally provided by hardware. In contrast to

power management code, this virtualization software gen-

erally has strict performance requirements to prevent

application performance from being significantly

impacted.

Display drivers for popular GUI (graphical user interface)

based operating systems are provided by National Semi-

conductor which enable a full featured 2D hardware accel-

erator to be used instead of the emulated VGA core.

5.1.1 Traditional VGA Hardware

A VGA card consists of display memory and control regis-

ters. The VGA display memory shows up in system mem-

ory between addresses A0000h and BFFFFh. It is

possible to map this memory to three different ranges

within this 128 KB block.

Several functions can be virtualized in a GXm processor

based design using the VSA environment. The VSA

enhanced chipsets provide programmable resources to

trap both memory and I/O accesses. However, specific

hardware is included to support the virtualization of VGA

core compatibility and audio functionality in the system.

The first range is

-

A0000h to B0000h for EGA and VGA modes,

the second range is

-

B0000h to B7FFFh for MDA modes,

and the third range is

-

B8000h to BFFFFh for CGA modes.

The hardware support for VGA emulation resides com-

pletely inside the GXm processor. Legacy VGA accesses

do not generate off-chip bus cycles. However, the VSA

support hardware for

XpressAUDIO resides in the CS5530 I/O companion

device and is described in the CS5530 specification.

The VGA control registers are mapped to the I/O address

range from 3B0h to 3DFh. The VGA registers are

accessed with an indexing scheme that provides more

registers than would normally fit into this range. Some

registers are mapped at two locations, one for mono-

chrome, and another for color.

The VGA hardware can be accessed by calling BIOS rou-

tines or by directly writing to VGA memory and control

registers. DOS always calls BIOS to set up the display

mode and render characters. Many other applications

access the VGA memory and control registers directly.

The VGA card can be set up to a virtually unlimited num-

ber of modes. However, many applications use one of the

predefined modes specified by the BIOS routine which

sets up the display mode. The predefined modes are

translated into specific VGA control register setups by the

BIOS. The standard modes supported by VGA cards are

shown in Table 5-1.

Revision 3.1

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Virtual Subsystem Architecture (Continued)

Table 5-1. Standard VGA Modes

Text or


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