DP7419 [NIDEC]
Dual Digital Potentiometers;
| 型号： | DP7419 |
| 厂家： | 
NIDEC COMPONENTS |
| 描述： | Dual Digital Potentiometers |
| 文件： | 总16页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DP7419
Dual Digital Potentiometers (DP)
with 64 Taps and 2-wire Interface
FEATURES
DESCRIPTION
The DP7419 is two Digital Potentiometers (DPs)
integrated with control logic and 16 bytes of
NVRAM memory.
Two linear-taper digital potentiometers
64 resistor taps per potentiometer
End to end resistance 2.5k, 10k, 50k or
100k
A separate 6-bit control register (WCR) independently
controls the wiper tap position for each DP.
Associated with each wiper control register are four 6-
bit non-volatile memory data registers (DR) used for
storing up to four wiper settings. Writing to the wiper
control register or any of the non-volatile data regis-
ters is via a 2-wire serial bus (I2C-like). On power-up,
the contents of the first data register (DR0) for each of
the two potentiometers is automatically loaded into its
respective wiper control registers (WCR).
Potentiometer control and memory access via
2-wire Interface (I2C like)
Low wiper resistance, typically 80
Four non-volatile wiper settings for each
potentiometer
Recall of wiper settings at power up
2.5 to 6.0 volt operation
Standby current less than 1µA
¯¯¯
The Write Protection (WP) pin protects against
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and 24-lead TSSOP
Write protection for data register
inadvertent programming of the data register.
The DP7419 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications.
PIN CONFIGURATION
For Ordering Information details, see page 15.
SOIC (W)
(top view)
TSSOP (Y)
(top view)
FUNCTIONAL DIAGRAM
VCC
RL0
RH0
RW0
A2
1
2
3
4
5
6
7
8
9
24 NC
¯¯¯
WP
SDA
A1
1
2
3
4
5
6
7
8
9
24
R
R
H1
H0
23 NC
22 NC
21 NC
20 A0
23 A2
RL1
22 RW0
21 RH0
20 RL0
19 VCC
WIPER
CONTROL
REGISTERS
RH1
RW1
GND
NC
2-WIRE BUS
INTERFACE
SCL
SDA
R
R
W0
¯¯¯
WP
19 NC
CAT
CAT
5419 18
5419 18
SDA
A1
A3
NC
W1
WP
17 SCL
16 NC
15 NC
14 NC
13 NC
NC
17 NC
16 NC
15 NC
14 A0
A0
A1
A2
A3
NONVOLATILE
DATA
REGISTERS
RL1
NC
CONTROL
LOGIC
RH1 10
RW1 11
NC 10
SCL 11
A3 12
R
R
L1
GND 12
13 NC
L0
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
1
Doc. No. MD-2115 Rev. H
DP7419
PIN DESCRIPTIONS
SCL: Serial Clock
The DP7419 serial clock input pin is used to
clock all data transfers into or out of the device.
Pin
Pin
Name
Function
SOIC TSSOP
1
2
19
20
VCC
RL0
Supply Voltage
SDA: Serial Data
Low Reference Terminal for
Potentiometer 0
The DP7419 bidirectional serial data pin is used
to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-
OR'd with the other open drain or open collector
outputs.
High Reference Terminal for
Potentiometer 0
3
4
21
22
RH0
Wiper Terminal for
Potentiometer 0
RW0
A2
A0, A1, A2, A3: Device Address Inputs
5
6
7
8
23
24
1
Device Address
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with the
address input in order to initiate communication
with the DP7419.
¯¯¯
WP
Write Protection
SDA
A1
Serial Data Input/Output
Device Address
2
Low Reference Terminal for
Potentiometer 1
9
3
4
5
RL1
RH1
RW1
High Reference Terminal for
Potentiometer 1
RH, RL: Resistor End Points
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
10
11
Wiper Terminal for
Potentiometer 1
RW: Wiper
12
13
14
15
16
17
18
19
20
21
22
23
24
6
GND
NC
NC
NC
NC
SCL
A3
Ground
The RW pins are equivalent to the wiper terminal of
a mechanical potentiometer.
7
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
No Connect
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
8
¯¯¯
WP: Write Protect Input
9
¯¯¯
The WP pin when tied low prevents non-volatile
10
11
12
13
14
15
16
17
18
writes to the data registers (change of wiper
control register is allowed) and when tied high or
left floating normal read/write operations are
allowed. See page 7, Write Protection for more
details.
NC
A0
NC
NC
NC
NC
DEVICE OPERATION
The DP7419 is two resistor arrays integrated with 2wire serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers. Each resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL). RH and RL are symmetrical and may be interchanged. The tap positions between and
at the ends of the series resistors are connected to the output wiper terminals (RW) by a CMOS transistor switch.
Only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the
value of the wiper control register. Data can be read or written to the wiper control registers or the non-volatile
memory data registers via the 2-wire bus. Additional instructions allow data to be transferred between the wiper
control registers and each respective potentiometer's non-volatile data registers. Also, the device can be
instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2115 Rev. H
2
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7419
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
-55 to +125
-65 to +150
-2.0 to VCC +2.0
-2.0 to +7.0
1.0
Units
ºC
ºC
V
Temperature Under Bias
Storage Temperature Range
Voltage to any Pins with Respect to VSS
VCC with Respect to GND
(2) (3)
V
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Wiper Current
W
300
ºC
mA
12
RECOMMENDED OPERATING CONDITIONS
Parameters
VCC
Ratings
+2.5 to 6.0
-40 to +85
Units
V
Industrial Temperature
ºC
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Test Conditions
Min
Typ
100
50
Max
Units
k
RPOT
RPOT
RPOT
RPOT
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
Potentiometer Resistance (-10)
Potentiometer Resistance (-2.5)
Potentiometer Resistance Tolerance
RPOT Matching
k
10
k
2.5
k
20
1
%
%
Power Rating
25°C, each pot
50
mW
mA
IW
RW
Wiper Current
6
Wiper Resistance
IW = 3mA @ VCC = 3V
IW = 3mA @ VCC = 5V
300
150
VCC
RW
Wiper Resistance
80
VTERM
VN
Voltage on any RH or RL Pin
Noise
VSS = 0V
(4)
GND
V
TBD
1.6
nV/¥Hz
Resolution
%
(8)
Absolute Linearity (5)
Relative Linearity (6)
RW(n)(actual)-R(n)(expected)
1
LSB (7)
LSB (7)
ppm/°C
ppm/°C
pF
(8)
RW(n+1)-[RW(n)+LSB
]
0.2
(4)
TCRPOT
TCRATIO
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
300
(4)
(4)
20
CH/CL/CW Potentiometer Capacitances
fc Frequency Response
10/10/25
0.4
(4)
RPOT = 50k
MHz
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(7) LSB = RTOT / 63 or (RH - RL) / 63, single pot
(8) n = 0, 1, 2, ..., 63
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
3
Doc. No. MD-2115 Rev. H
DP7419
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
ICC Power Supply Current
ISB
Test Conditions
Min
Max
Units
mA
µA
µA
µA
V
fSCL = 400kHz
1
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC; SDA Open
VIN = GND to VCC
1
10
ILI
ILO
VOUT = GND to VCC
10
VIL
VIH
VOL1
-1
VCC x 0.3
Input High Voltage
VCC x 0.7 VCC + 1.0
0.4
V
Output Low Voltage (VCC = 3.0V) IOL = 3 mA
V
PIN CAPACITANCE (1)
Applicable over recommended operating range from TA = 25?C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol Test Conditions
Min
Typ
Max
8
Units Conditions
CI/O
CIN
Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, WP)
pF
pF
VI/O = 0V
VIN = 0V
¯¯¯
6
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
Typ
Max
400
50
Units
kHz
ns
fSCL
TI(1)
tAA
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
0.9
µs
(1)
tBUF
Time the bus must be free before a new transmission can start
Start Condition Hold Time
1.2
0.6
1.2
0.6
0.6
0
µs
tHD:STA
tLOW
µs
Clock Low Period
µs
tHIGH
Clock High Period
µs
tSU:STA
tHD:DAT
tSU:DAT
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
µs
ns
Data in Setup Time
100
ns
(1)
tR
(1)
SDA and SCL Rise Time
0.3
µs
tF
SDA and SCL Fall Time
300
ns
tSU:STO
tDH
Stop Condition Setup Time
Data Out Hold Time
0.6
50
µs
ns
POWER UP TIMING (1)
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Min
Typ
Max
1
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2115 Rev. H
4
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7419
WRITE CYCLES LIMITS
Symbol Parameter
Max Units
tWR
Write Cycle Time
5
ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol Parameter
Reference Test Method
Min
1,000,000
100
Typ
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
Volts
(1)(2)
ILTH
100
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Figure 1. Bus Timing
t
t
t
R
F
HIGH
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
5
Doc. No. MD-2115 Rev. H
DP7419
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
fixed as 0101 for the DP7419 (see Figure 5). The
next four significant bits (A3, A2, A1, A0) are the
device address bits and define which device the
Master is accessing. Up to sixteen devices may be
individually addressed by the system. Typically, +5V
and ground are hard-wired to these pins to establish
the device's address.
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus
protocol:
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock is high will
be interpreted as a START or STOP condition.
After the Master sends a START condition and the
slave address byte, the DP7419 monitors the bus
and responds with an acknowledge (on the SDA line)
when its address matches the transmitted slave
address.
The device controlling the transfer is a master,
typically a processor or controller, and the device
being controlled is the slave. The master will always
initiate data transfers and provide the clock for both
transmit and receive operations. Therefore, the
DP7419 will be considered a slave device in all
applications.
Acknowledge
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8
bits of data.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The DP7419 monitors the
SDA and SCL lines and will not respond until this
condition is met.
The DP7419 responds with an acknowledge after
receiving a START condition and its slave address. If
the device has been selected along with a write
operation, it responds with an acknowledge after
receiving each 8-bit byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
When the DP7419 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the DP7419 will continue to transmit
data. If no acknowledge is sent by the Master, the
device terminates data transmission and waits for a
STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Doc. No. MD-2115 Rev. H
6
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7419
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address. If the DP7419 is still
busy with the write operation, no ACK will be returned.
If the DP7419 has completed the write operation, an
ACK will be returned and the host can then proceed
with the next instruction operation.
WRITE OPERATIONS
In the Write mode, the Master device sends the
START condition and the slave address information to
the Slave device. After the Slave generates an
acknowledge, the Master sends the instruction byte
that defines the requested operation of DP7419. The
instruction byte consist of a four-bit opcode followed
by two register selection bits and two pot selection
bits. After receiving another acknowledge from the
Slave, the Master device transmits the data to be
written into the selected register. The DP7419
acknowledges once more and the Master generates
the STOP condition, at which time if a nonvolatile data
register is being selected, the device begins an
internal programming cycle to non-volatile memory.
While this internal cycle is in progress, the device will
not respond to any request from the Master device.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the non-volatile
¯¯¯
data registers. If the WP pin is tied to LOW, the data
registers are protected and become read only.
¯¯¯
Similarly, WP pin going LOW after Start will interrupt
¯¯¯
non-volatile write to data registers, while WP pin going
LOW after internal write cycle has started will have no
effect on any write operation. The DP7419 will
accept both slave addresses and instructions, but the
data registers are protected from programming by the
device’s failure to send an acknowledge after data is
received.
Acknowledge Polling
The disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host's write operation, the DP7419 initiates the
Figure 5. Slave Address Bits
DP7419
0
1
0
1
A3 A2 A1 A0
* A0, A1, A2 and A3 correspond to pin A0, A1, A2 and A3 of the device.
** A0, A1, A2 and A3 must compare to its corresponding hard wired input pins.
Figure 6. Write Timing
S
SLAVE/DP
ADDRESS
INSTRUCTION
BYTE
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
Data Register Pot/WCR
DR1 WCR DATA
Fixed
Variable
op code
Address
Address
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
7
Doc. No. MD-2115 Rev. H
DP7419
Instruction Byte
INSTRUCTIONS AND REGISTER
DESCRIPTION
The next byte sent to the DP7419 contains the
instruction and register pointer information. The four
most significant bits used provide the instruction
opcode I [3:0]. The R1 and R0 bits point to one of the
four data registers of each associated potentiometer.
The least two significant bits point to one of two Wiper
Control Registers. The format is shown in Table 2.
INSTRUCTIONS
Slave Address Byte
The first byte sent to the DP7419 from the master/
processor is called the Slave/DP Address Byte. The
most significant four bits of the slave address are a
device type identifier. These bits for the DP7419 are
fixed at 0101[B] (refer to Table 1).
Data Register Selection
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
The next four bits, A3 - A0, are the internal slave
address and must match the physical device address
which is defined by the state of the A3 - A0 input pins
for the DP7419 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent by
the master executes the instruction. The A3 - A0
inputs can be actively driven by CMOS input signals
or tied to VCC or VSS.
0
1
1
0
1
1
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
A3
A2
A1
A0
1
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
(MSB)
I2
I1
I0
R1
R0
0
P0
(LSB)
Doc. No. MD-2115 Rev. H
8
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7419
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data
Registers is a non-volatile operation and will take a
maximum of 5ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The DP7419 contains two 6-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of 64
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written by
the host via Write Wiper Control Register instruction; it
may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction, it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as standard memory locations for system
parameters or user preference data.
INSTRUCTIONS
Four of the nine instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register – read the current
wiper position of the selected potentiometer in
the WCR
The Wiper Control Register is a volatile register that
loses its contents when the DP7419 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
— Write Wiper Control Register – change current
wiper position in the WCR of the selected
potentiometer
— Read Data Register – read the contents of the
Data Registers (DR)
selected Data Register
Each potentiometer has four 6-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
— Write Data Register – write a new value to the
selected Data Register.
Table 3. Instruction Set
Instruction Set
Note: 1/0 = data is one or zero
Instruction
Operation
I3 I2 I1 I0 R1 R0
0
WCR0/ P0
Read the contents of the Wiper Control
Register pointed to by P0
Read Wiper Control
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
1/0
Write new value to the Wiper Control
Register pointed to by P0
Write Wiper Control
Register
0
0
0
0
1/0
1/0
1/0
1/0
Read the contents of the Data Register
pointed to by P0 and R1-R0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
Write new value to the Data Register
pointed to by P0 and R1-R0
Write Data Register
Transfer the contents of the Data
Register pointed to by P0 and R1-R0 to
its associated Wiper Control Register
XFR Data Register to
Wiper Control Register
Transfer the contents of the Wiper
Control Register pointed to by P0 to the
Data Register pointed to by R1-R0
XFR Wiper Control
Register to Data
Register
1
0
1
0
1
0
0
1
1/0 1/0
1/0 1/0
0
0
1/0
0
Transfer the contents of the Data
Registers pointed to by R1-R0 of both
pots to their respective Wiper Control
Registers
Gang XFR Data
Registers to Wiper
Control Registers
Transfer the contents of both Wiper
Control Registers to their respective data
Registers pointed to by R1-R0 of both
four pots
Gang XFR Wiper
Control Registers to
Data Register
1
0
0
0
0
1
0
0
1/0 1/0
0
0
0
Enable Increment/decrement of the
Control Latch pointed to by P0
Increment/Decrement
Wiper Control Register
0
0
1/0
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
9
Doc. No. MD-2115 Rev. H
DP7419
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be
delayed by tWRL. A transfer from the WCR (current
wiper position), to a Data Register is a write to non-
volatile memory and takes a maximum of tWR to
complete. The transfer can occur between one of the
potentiometers and one of its associated registers; or
the transfer can occur between all potentiometers and
one associated register.
— Global XFR Data Register to Wiper Control
Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control Registers.
— Global XFR Wiper Counter Register to Data
Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 5
and 9). The Increment/Decrement command is
different from the other commands. Once the
command is issued and the DP7419 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby providing a fine tuning capability to the host.
For each SCL clock pulse (tHIGH) while SDA is HIGH,
the selected wiper will move one resistor segment
towards the RH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the RL terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
DP7419; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Control Register to the specified associated Data
Register.
See Instructions format for more detail.
Figure 7. Two-Byte Instruction Sequence
SDA
0
1
0
1
ID3 ID2 ID1 ID0
S
A2 A1 A0
S
T
A
R
T
A3
A I3 I2 I1
I0
R1 R0
0
P0
A
C
K
C
K
T
O
P
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 8. Three-Byte Instruction Sequence
SDA
0
1
0
1
S
T
A
R
T
I3
ID3 ID2
ID0
A
C
K
I2
I1
I0 R1 R0
0
P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
ID1
A3 A2 A1 A0
Internal
Address
Device ID
WCR[7:0]
or
Data Register D[7:0]
Instruction
Opcode
Data
Pot/WCR
Register Address
Address
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
SDA
ID3 ID2 ID1 ID0
Device ID
A3
A2 A1 A0
I3
I2
I1
I0
R1 R0
0
P0
S
T
A
R
T
A
C
K
A
C
K
I
I
D
E
C
1
S
I
D
E
C
n
N
C
1
N
C
2
T
O
P
N
C
n
Internal
Address
Instruction
Opcode
Pot/WCR
Address
Data
Register
Address
Doc. No. MD-2115 Rev. H
10
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7419
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRID
SCL
SDA
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
DATA
T
O
P
0
1
0
1
1
1
1
1
0
0
0
1
0
1
1
0
1
0
0
0
P0
P0
P0
P0
7
0
6
0
5
4
3
2
1
0
Write Wiper Control Register (WCR)
S
T
A
R
T
A
C
K
A
C
K
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
DATA
0
1
0
1
0
0
0
0
7
0
6
0
5
4
3
2
1
0
O
P
Read Data Register (DR)
S
T
A
C
K
A
C
K
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
R1 R0
DATA
0
1
0
1
1
0
7
6
5
4
3
2
1
0
A
R
T
O
P
0
0
Write Data Register (DR)
S
T
A
C
K
A
C
K
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
R1 R0
DATA
0
1
0
1
0
0
7
0
6
0
5
4
3
2
1
0
A
R
T
O
P
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
11
Doc. No. MD-2115 Rev. H
DP7419
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
A
C
K
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
R1 R0
0
1
0
1
0
0
0
1
0
0
A
R
T
O
P
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
A
C
K
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
R1 R0
0
1
0
1
1
0
0
0
0
0
0
0
A
R
T
O
P
Transfer Wiper Control Register (WCR) to Data Register (DR)
S
T
A
C
K
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
R1 R0
0
1
0
1
1
1
1
0
P0
P0
P0
A
R
T
O
P
Transfer Data Register (DR) to Wiper Control Register (WCR)
S
T
A
C
K
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
R1 R0
0
1
0
1
1
1
0
1
A
R
T
O
P
Increment (I)/Decrement (D) Wiper Control Register (WCR)
S
T
A
C
K
A
A
C
K
S
T
DEVICE ADDRESSES
A3 A2 A1 A0
INSTRUCTION
DATA
. . .
C
K
0
1
0
1
0
0
1
0
0
0
0
I/D I/D
I/D I/D
A
R
T
O
P
Note:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Doc. No. MD-2115 Rev. H
12
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7419
PACKAGE OUTLINES
SOIC 24-Lead 300mils (W)
SYMBOL
MIN
2.35
0.10
2.05
0.31
0.20
15.20
10.11
7.34
NOM
MAX
A
A1
A2
b
2.65
0.30
2.55
0.51
0.33
15.40
10.51
7.60
E1
E
c
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.75
1.27
8°
b
e
L
e
PIN#1 IDENTIFICATION
e1
5°
15°
TOP VIEW
h
D
h
e1
A2
A
e
e1
L
c
A1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
13
Doc. No. MD-2115 Rev. H
DP7419
TSSOP 24-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
7.90
6.55
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
7.70
6.25
4.30
c
E1
E
D
7.80
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
e1
0.50
0°
0.70
8°
e
TOP VIEW
D
c
A2
A1
A
e1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
Doc. No. MD-2115 Rev. H
14
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
DP7419
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
DP
7419
W
I
-00
- T1
Package
W: SOIC
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to 85ºC)
Resistance
25: 2.5k
10: 10k
Tape & Reel
T: Tape & Reel
1: 1000/Reel - SOIC
2: 2000/Reel - TSSOP
Company ID
50: 50k
00: 100k
Product Number
7419
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The device used in the above example is a DP7419WI-00-T1 (SOIC, Industrial Temperature, 100k, Tape & Reel).
Ordering Part Number
DP7419WI-25
DP7419WI-10
DP7419WI-50
DP7419WI-00
DP7419YI-25
DP7419YI-10
DP7419YI-50
DP7419YI-00
© NIDEC COPAL ELECTRONICS CORP.
Characteristics subject to change without notice
15
Doc. No. MD-2115 Rev. H
REVISION HISTORY
Date
Rev. Reason
10/08/2003
E
Update Features
Update Description
04/01/2004
F
Eliminate data sheet designation
Update Features
Update Description
Update Pin Description
Update Absolute Maximum Ratings
Update Recommended Operating Conditions
Update Potentiometer Characteristics
Update Write Protection
Update Instructions
Update Ordering Information
Updated Example of Ordering Information
04/29/2007
10/10/2007
G
H
Updated Package Outline
Updated Example of Ordering Information
Added MD- to document number
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OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
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sit uat ion where personal injury or deat h may occur.
NIDEC COPAL ELECTRONICS CORP. re se rve s t he right t o make change s t o or discont inue any product or se rvice de scribe d he re in wit hout not ice . Product s wit h dat a she e t s
labeled "Advance Informat ion" or "Preliminary" and ot her product s described herein may not be in product ion or offered for sale.
NIDEC COPAL ELECTRONICS CORP. advise s cust ome rs t o obt ain t he curre nt ve rsion of t he re le vant product informat ion be fore placing orde rs. Circuit diagrams illust rat e
t ypical semiconduct or applicat ions and may not be complet e.
NIDEC COPAL ELECTRONICS CORP.
Japan Head Office
Nishi-Shinjuku, Kimuraya Bldg.,
7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023
Phone: +81-3-3364-7055
Fax: +81-3-3364-7098
Document No: MD-2115
Revision:
H
www.nidec-copal-electronics.com
Issue date:
10/10/07
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