DP7132_技术文档

DP7132

16 Volt Digital Potentiometer (DP)

with 128 Taps and 2-wire Interface

FEATURES

DESCRIPTION

■ Single linear DP with 128 taps

The DP7132 is a high voltage Digital Potentiometer

(DP) with non-volatile wiper setting memory,

■ End-to-end resistance of 10k , 50k or 100k

7

operating

like

a

mechanical

potentiometer.

2

■

2-wire (I C-like) interface

Thetappointsbetweenthe127equalresistiveelements

are connected to the wiper output via CMOS switches.

The switches are controlled by a 7-bit Wiper Control

Register (WCR). The wiper setting can be stored in a

7-bit non-volatile Data Register (DR). The WCR is

accessed via the 2-wire serial bus.

■ Fast Up/Down wiper control mode

■ Non-volatile wiper setting storage

■ Automatic wiper setting recall at power-up

■ Digital Supply range (V ): 2.7V to 5.5V

CC

■ Analog Supply range (V+): +8V to +16V

■ Low Standby Current: 15µA

■ 100 Year wiper setting memory

■ Industrial Temperature range: -40^oC to +85^oC

■ RoHS-compliant 10-pin MSOP package

Upon power-up, the WCR is set to mid-scale (1000000).

After the power supply is stable, the contents of the DR

are transferred to the WCR and the wiper is returned to

the memorized setting.

The DP7132 has two voltage supplies: V , the digital

CC

supply and V+, the analog supply. V+ can be much

higher than V , allowing for 16V analog operations.

CC

The DP7132 can be used as a potentiometer or as a

two-terminal variable resistor.

APPLICATIONS

■ LCD screen adjustment

■ Volume control

■ Mechanical potentiometer replacement

■ Gain adjustment

■ Line impedance matching

■ VCOM setting adjustments

For Ordering Information details, see page 13.

BLOCK DIAGRAM

V

V+

CC

SDA

SCL

A0

127

R

H

CONTROL LOGIC AND

ADDRESS DECODE

A1

128 TAP POSITION

DECODE CONTROL

7-BIT

7-BIT WIPER

NONVOLATILE

MEMORY

REGISTER

(DR)

CONTROL

REGISTER

(WCR)

0

R

L

W

Doc. No. MD-2124, Rev. E

1

Characteristics subject to change without notice

DP7132

PIN CONFIGURATION

PIN DESCRIPTION

Name

Description

Number

SDA

GND

1

2

3

4

5

10

9

8

7

6

SCL

V+

1

SDA

Serial Data Input/Output - Bidirectional Serial Data pin

used to transfer data into and out of the DP7132. This

is an Open-Drain I/O and can be wire OR'd with other

Open-Drain (or Open Collector) I/Os.

V

R

CC

L

W

H

A1

A0

2

3

4

GND

V_CC

A1

Ground

Digital Supply Voltage (2.7V to 5.5V)

Address Select Input to select slave address for

2-wire bus.

MSOP 10-Pin Package

5

A0

Address Select Input to select slave address for

2-wire bus.

6

7

8

9

R_H

R_W

R_L

High Reference Terminal for the potentiometer

Wiper Terminal for the potentiometer

Low Reference Terminal for the potentiometer

Analog Supply Voltage for the potentiometer (+8.0V to

16.0V)

V+

10

SCL

Serial Bus Clock input for the 2-wire Serial Bus. This

clock is used to clock all data transfers into and out of

the DP7132

Doc. No. MD-2124, Rev. E

2

Characteristics subject to change without notice

DP7132

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Temperature Under Bias....................ꢁꢅꢅÝ& to +ꢆꢇꢅÝC

Storage Temperature........................ ꢁꢈꢅÝ& to ꢉꢆꢅꢃÝC

V_CC= +2.7V to +5.5V

V+ = +8.0V to +16V

Operating Temperature Range:ꢀꢁꢂꢃÝ&ꢀto +ꢄꢅÝC

Voltage on any SDA, SCL, A0 & A1 pins with respect

to Ground ⁽¹⁾................................. -0.3V to V_CC+ 0.3V

COMMENT

Voltage on R_H, R_L& R_Wpins with respect

Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions

outsideofthoselistedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to any absolute maximum rating for extended periods

may affect device performance and reliability.

to Ground ................................................................ V+

V_CCwith respect to Ground .................... -0.3V to +6V

V+ with respect to Ground ................. -0.3V to +16.5V

Wiper Current (10 sec) ...................................... +6mA

Lead Soldering temperature (10 sec) ..............ꢉꢊꢃꢃÝC

Notes:

1. Latch-up protection is provided for stresses up to 100mA on

address and data pins from -0.3V to V +0.3V.

CC

POTENTIOMETER CHARACTERISTICS

(Over recommended operating conditions unless otherwise stated.)

Limits

Typ

100

50

Symbol

Parameter

Test Conditions

Units

Min

Max

R_POT

R_TOL

Potentiometer Resistance (100k1)

Potentiometer Resistance (50k1)

Potentiometer Resistance (10k1)

Potentiometer Resistance Tolerance

Power Rating

k1

%

mW

mA

10

+20

50

+3

25° C

I_W

Wiper Current

1

I_W= +1mA @ V+ = 12V

I_W= +1mA @ V+ = 8V

GND = 0V; V+ = 8V to 16V

70

110

150

200

V+

R_W

Wiper Resistance

1

V_TERM

RES

A_LIN

R_LIN

TC_RPOT

TC_Ratio

Voltage on R_W, R_Hor R_L

Resolution

GND

V

%

0.78

(5), (6)

Absolute Linearity ⁽²⁾

V_W(n)(actual)- V_{W(n)(expected)}

+1

+0.5

LSB ⁽⁴⁾

ppm/° C

pF

Relative Linearity ⁽³⁾

V_W(n+1)- [V_W(n)+LSB]^{(5), (6)}

(1)

Temperature Coefficient of R_POT

Ratiometric Temperature Coefficient

+300

(1)

30

C_H/C_L/C_WPotentiometer Capacitances

fc Frequency Response

10/10/25

0.4

R_POT= 50k1

MHz

Notes:

1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

3. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer.

4. LSB = (R

R

)/127; where R

and R are the highest and lowest measured values on the wiper terminal.

HM LM

HM - LM

5. n = 1, 2, ..., 127

+

6. V @ R ; 0V @ R ; V measured @ R with no load.

H

L

W

Doc No. MD-2124, Rev. E

3

Characteristics subject to change without notice

DP7132

D.C. ELECTRICAL CHARACTERISTICS

(Over recommended operating conditions unless otherwise stated.)

Symbol

Parameter

Test Conditions

Min

Max

Units

F_SCL= 400k+], SDA Open,

Power Supply Current

(Volatile Write/Read)

I_CC1

1

mA

V_CC= 5.5V, Input = GND

F_SCL= 400k+], SDA Open,

Power Supply Current

(Nonvolatile WRITE)

I_CC2

3.0

mA

V_CC= 5.5V, Input = GND

I_SB(VCC)Standby Current (V_CC= 5V)

V_IN= GND or V_CC, SDA = V_CC

V_CC= 5V, V+ = 16V

V_IN= GND to V_CC

5

10

µA

V

I_SB(V+)

I_LI

V+ Standby Current

Input Leakage Current

Output Leakage Current

Input Low Voltage

10

I_LO

V_OUT= GND to V_CC

10

V_IL

-1

V_CCx 0.3

V_CC+ 1.0

0.4

V_I+

V_OL1

Input +igh Voltage

V_CCx 0.7

V

Output Low Voltage (V_CC= 3.0) I_OL= 3mA

V

CAPACITANCE

T_Aꢀ ꢀꢇꢅÝ&ꢋꢀIꢀ ꢀꢆꢌꢃ0+]ꢋꢀ9_CC= 5.0V

Symbol

C_I/O

Parameter

Test Conditions

V_I/O= 0V ⁽¹⁾

Min

Max

8

Units

pF

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, SCL)

C_IN

V_IN= 0V ⁽¹⁾

6

pF

A.C. CHARACTERISTICS

V_CC= 2.7 - 5.5V

Symbol

Parameter (see Fig. 1)

Min

Max

400

50

Units

k+]

ns

F_SCL

Clock Frequency

(1)

T_I

Noise Suppression Time Constant at SCL & SDA Inputs

SLC Low to SDA Data Out and ACK Out

t_AA

1

µs

(1)

t_BUF

Time the bus must be Iree beIore a new transmission can start

1.2

0.6

1.2

0.6

0

µs

t_+D:STAStart Condition +old Time

µs

t_LOW

t_+IG+

Clock Low Period

µs

Clock +igh Period

µs

t_SU:STA

Start Condition Setup Time (Ior a Repeated Start Condition)

µs

t_+D:DATData in +old Time

ns

(1)

t_R

t_F

SDA and SCL Rise Time

SDA and SCL Fall Time

0.3

µs

(1)

300

ns

t_SU:STOStop Conditions Setup Time

t_D+Data Out +old Time

0.6

µs

100

ns

Notes:

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Doc. No. MD-2124, Rev. E

4

Characteristics subject to change without notice

DP7132

POWER UP TIMING⁽¹⁾⁽²⁾

Symbol

t_PUR

Parameter

Min

Max

1

Units

ms

Power-up to Read Operation

Power-up to Write Operation

t_PUW

1

ms

DP TIMING

Symbol

Parameter

Min

Max

Units

µs

t_WRPO

t_WRL

Wiper Response Time After Power Supply Stable

Wiper Response Time After Instruction Issued

5

10

µs

WRITE CYCLE LIMITS

Symbol

Parameter

Write Cycle Time (see Fig. 2)

Min

Max

Units

t_WR

5

ms

Thewritecycleisthetimefromavalidstopconditionofawritesequencetotheendoftheinternalprogram/erasecycle.

During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not

respond to its slave address.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Endurance

Data Retention

Reference Test Method

Min

Max

Units

(1)

N_END

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

100,000

100

Cycles

Years

(1)

T_DR

Notes:

1. This parameter is tested initially and after a design or process change that affects the parameter.

2. and t are the delays required from the time VCC is stable until the specified operation can be initiated.

t

PUR

PUW

TYPICAL PERFORMANCE CHARACTERISTICS

Resistance between R_Wand R_L

Icc2 (NV write) vs Temperature

12.000

400

350

300

250

200

150

100

50

Vcc=2.7V; V+=8v

Vcc=5.5V; V+=16V

10.000

8.000

6.000

4.000

2.000

0.000

Vcc = 2.7V

Vcc = 5.5V

0

-50 -30 -10 10 30 50 70 90 110 130

Temperature ( C)

0

16

32

48

64

80

96

112

128

°

Tap position

Characteristics subject to change without notice

Doc No. MD-2124, Rev. E

5

DP7132

TYPICAL PERFORMANCE CHARACTERISTICS (CONT)

Absolute Linearity Error per Tap Position

Relative Linearity Error

1.000

0.500

Tamb = 25 C

Vcc=2.7V; V+=8v

0.800

Vcc=2.7V; V+=8V

Vcc=5.5V; V+=16V

Rtotal = 10K

Tamb = 25 C

Rtotal = 10K

0.400

0.300

0.200

0.100

0.000

-0.100

-0.200

-0.300

-0.400

-0.500

Vcc=5.5V; V+=16V

0.600

0.400

0.200

0.000

-0.200

-0.400

-0.600

-0.800

-1.000

0

16

32

48

64

80

96

112

128

0

16

32

48

64

80

96

112

128

Tap position

t

R

F

HIGH

t

LOW

SCL

t

HD:DAT

SU:STA

t

HD:STA

SU:DAT

SU:STO

BUF

SDA IN

t

DH

AA

SDA OUT

Figure 1. Bus Timing

SCL

SDA

8TH BIT

BYTE n

ACK

t

WR

STOP

START

ADDRESS

CONDITION

Figure 2. Write Cycle Timing

Characteristics subject to change without notice

Doc. No. MD-2124, Rev. E

6

DP7132

Acknowledge

SERIAL BUS PROTOCOL

After a successful data transfer, each receiving device

is required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data (see Fig. 4).

The following defines the features of the 2-wire bus

protocol:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes

in the data line while the clock is high will be

interpreted as a START or STOP condition.

The DP7132 responds with an acknowledge after

receiving a START condition and its slave address. If

thedevicehasbeenselectedalongwithawriteoperation,

it responds with an acknowledge after receiving each

8-bit byte.

The device controlling the transfer is a master, typically

aprocessororcontroller,andthedevicebeingcontrolled

istheslave.Themasterwillalwaysinitiatedatatransfers

and provide the clock for both transmit and receive

operations. Therefore, the DP7132 will be considered

a slave device in all applications.

When the DP7132 is in a READ mode it transmits 8 bits

of data, releases the SDA line, and monitors the line for

an acknowledge. Once it receives this acknowledge,

the DP7132 will continue to transmit data. If no

acknowledgeissentbytheMaster,thedeviceterminates

data transmission and waits for a STOP condition.

START Condition

Acknowledge Polling

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The DP7132 monitors the

SDA and SCL lines and will not respond until this

condition is met (see Fig. 3).

Thedisablingoftheinputscanbeusedtotakeadvantage

of the typical write cycle time. Once the STOP condition

is issued to indicate the end of the write operation, the

DP7132 initiates the internal write cycle. ACK polling

can be initiated immediately. This involves issuing the

START condition followed by the slave address. If the

DP7132 is still busy with the write operation, no ACK

will be returned. If the DP7132 has completed the write

operation,anACKwillbereturnedandthehostcanthen

proceed with the next instruction operation.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition (see Fig. 3).

SCL

SDA

START

STOP

CONDITION

Figure 3. Start/Stop Condition

BUS RELEASE DELAY (TRANSMITTER)

BUS RELEASE DELAY (RECEIVER)

SCL FROM

MASTER

1

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

ACK SETUP (r t

SU:DAT

)

START

ACK DELAY (b t

)

AA

Figure 4. Acknowledge Condition

Doc No. MD-2124, Rev. E

7

Characteristics subject to change without notice

DP7132

The next two bits, A1 and A0, are the internal slave

address and must match the physical device address

which is defined by the state of the A1 and A0 input pins.

Only the device with slave address matching the input

byte will be accessed by the master. This allows up to 4

devicestoresideonthesamebus.TheA1andA0inputs

can be actively driven by CMOS input signals or tied to

V_CCor Ground.

DEVICE DESCRIPTION

Access Control Register

The volatile register WCR and the non-volatile register

DR areaccessedonlybyaddressingthevolatileAccess

RegisterARfirst, usingthe3byteI²Cprotocolforallread

and write operations (see Table 1). The first byte is the

slave address/instruction byte (see details below). The

second byte contains the address (02h) of the AR

register.Thedatainthethirdbytecontrolswhichregister

WCR (80h) or DR (00h) is being addressed (see Figure

5).

The last bit is the READ/WRITE bit and determines the

function to be performed. If it is a “1” a read command is

initiated and if it is a “0” a write is initiated. For the AR

register only write is allowed.

Slave Address Instruction Byte Description

After the Master sends a START condition and the slave

address byte, the DP7132 monitors the bus and

respondswithanacknowledgewhenitsaddressmatches

the transmitted slave address.

The first byte sent to the DP7132 from the master

processor is called the Slave/DP Address Byte. The

most significant five bits of the slave address are a

device type identifier. For the DP7132 these bits are

fixed at 01010 (refer to Table 2).

Table 1. Access Control Register

1st byte

2nd byte

AR address - 02h

3rd byte

WCR(80h) / DR(00h) selection

ST

0

1

0

1

0

A

0

1

0

A

1

0

A

SP

0

Table 2. Byte 1 Slave Address and Instruction Byte

Device Type Identifier

Slave Address

Read/Write

ID4

0

ID3

1

ID2

0

ID1

1

ID0

0

A1

X

A0

X

R/W

X

(MSB)

(LSB)

SLAVE

ADDRESS

AR REGISTER

ADDRESS

WCR/DR

SELECTION

S

T

A

R

T

& INSTRUCTION

S

T

O

P

BUS ACTIVITY:

MASTER

FIXED

SDA LINE

S

P

A

C

K

A

C

K

VARIABLE

C

K

Figure 5. Access Register Addressing Using 3 Bytes

Doc. No. MD-2124, Rev. E

8

Characteristics subject to change without notice

DP7132

Wiper Control Register (WCR) Description

The DP7132 contains a 7-bit Wiper Control Register

which is decoded to select one of the 128 switches along

its resistor array. The WCR is a volatile register and is

written with the contents of the nonvolatile Data Register

(DR) on power-up. The Wiper Control Register loses its

contents when the DP7132 is powered-down. The

contents of the WCR may be read or changed directly by

thehostusingaREAD/WRITEcommandafteraddressing

the WCR (see Table 1 to access WCR). Since the

DP7132 will only make use of the 7 LSB bits (The first

data bit, or MSB, is ignored) on write instructions and will

always come back as a “0” on read commands.

A write operation (see Table 3) requires a Start condition, followed by a valid slave address byte, a valid address byte

00h, a data byte and a STOP condition. After each of the three bytes the DP7132 responds with an acknowledge.

At this time the data is written only to volatile registers, then the device enters its standby state.

Table 3. WCR Write Operation

1st byte

2nd byte

3rd byte

AR address - 02h

WCR(80h) selection

ST

0

1

0

1

0

A

0

1

0

A

1

0

A

SP

slave address byte

WCR address - 00h

data byte

ST

0

1

0

1

0

X

An increment operation (see Table 4) requires a Start condition, followed by a valid increment address byte (01011),

a valid address byte 00h. After each of the two bytes, the DP7132 responds with an acknowledge. At this time if the

data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. Once the stop

is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper

position does not roll over but is limited to min and max positions.

Table 4. WCR Increment/Decrement Operation

1st byte

2nd byte

3rd byte

AR address - 02h

WCR(80h) selection

ST

0

1

0

1

0

A

0

1

0

A

1

0

A

SP

slave address byte

WCR address - 00h

increment (1) / decrement (0) bits

ST

0

1

0

1

0

A

0

A

1

0

Areadoperation(seeTable5)requiresaStartcondition,followedbyavalidslaveaddressbyteforwrite,avalidaddress

byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the DP7132

responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation

by issuing a STOP condition following the last bit of Data byte.

Table 5. WCR Read Operation

1st byte

2nd byte

3rd byte

AR address - 02h

WCR(80h) selection

ST

0

1

0

1

0

A

0

1

0

A

1

0

A

SP

slave address byte

WCR address - 00h

ST

0

1

0

1

0

1

A

0

slave address byte

data byte

0

1

0

X

SP

Characteristics subject to change without notice

Doc No. MD-2124, Rev. E

9

DP7132

Data Register (DR)

being performed. During the internal non-volatile write

cycle, the device ignores transitions at the SDA and SCL

pins, and the SDA output is at a high impedance state.

The WCR is also written during a write to DR. After a DR

WRITE is complete the DR and WCR will contain the

same wiper position.

The Data Register (DR) is a nonvolatile register and its

contents are automatically written to the Wiper Control

Register (WCR) on power-up. It can be read at any time

without effecting the value of the WCR. The DR, like the

WCR, only stores the 7 LSB bits and will report the MSB

bit as a “0”. Writing to the DR is performed in the same

fashionastheWCRexceptthatatimedelayofupto5ms

is experienced while the nonvolatile store operation is

To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the

following sequences.

A write operation (see Table 6) requires a Start condition, followed by a valid slave address byte, a valid address byte

00h, a data byte and a STOP condition. After each of the three bytes the DP7132 responds with an acknowledge.

At this time the data is written both to volatile and non-volatile registers, then the device enters its standby state.

Table 6. DR Write Operation

1st byte

2nd byte

3rd byte

AR address - 02h

DR(00h) selection

ST

0

1

0

1

0

A

0

1

0

A

0

A

SP

slave address byte

DR address - 00h

data byte

ST

0

1

0

1

0

A

0

A

X

A

SP

A read operation (see Table 7) requires a Start condition, followed by a valid slave address byte, a valid address byte

00h, a second Start and a second slave address byte for read. After each of the three bytes the DP7132 responds

with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing

a STOP condition following the last bit of Data byte.

Table 7. DR Read Operation

1st byte

2nd byte

3rd byte

AR address - 02h

DR(00h) selection

ST

0

1

0

1

0

A

0

1

0

A

0

A

SP

slave address byte

DR address - 00h

ST

0

1

0

1

0

1

A

0

slave address byte

data byte

0

1

0

X

SP

Characteristics subject to change without notice

Doc. No. MD-2124, Rev. E

10

DP7132

POTENTIOMETER OPERATION

Power-On

The DP7132 is a 128-position, digital potentiometer.

10k1 potentiometer ~791 is the resistance between

each wiper position. However in addition to the ~791 for

each resistive segment of the potentiometer, a wiper

resistanceoffsetmustbeconsidered. Table8showsthe

effect of this value and how it would appear on the wiper

terminal.

When

applying

power

to

the

DP7132,

V_CCmust be suplied prior to or simultaneously with V+.

At the sametime, the signals on R_H, R_Wand R_Lterminals

should not exceed V+. If V+ is applied before V_CC, The

electronic switches of the DP are powered in the

absence of the switch control signals, that could result in

multiple switches being turned on. This causes

unexpectedwipersettingsandpossiblecurrentoverload

of the potentiometer. When V_CCis applied the device

turns on at the mid-point wiper location (64) until the

wiperregistercanbeloadedwiththenonvolatilememory

location previously stored in the device. After the

nonvolatilememorydataisloadedintothewiperregister

the wiper location will change to the previously stored

wiper position.

This offset will appear in each of the DP7132 end-to-

end resistance values in the same way as the 10k1

example. However resistance between each wiper

position for the 50k1 version will be ~3951 and for the

100k1 version will be ~7901.

Table 8. Potentiometer Resistance and Wiper

Resistance Offset Effects

Typical R to R_LResistance for

Position

00

^W10k1 DP

At power-down, it is recommended to turn-off first the

signals on R_H, R_Wand R_L, followed by V+ and, after that,

V_CC, in order to avoid unexpected transmistions of the

wipper and uncontrolled current overload of the

potentiometer.

701 or

01 + 701

791 + 701

01

1491 or

5,0471 or

10,0701 or

63

4,9771 + 701

10,0001 + 701

127

The end-to-end nominal resistance of the potentiometer

has 128 contact points linearly distributed across the

total resistor. Each of these contact points is addressed

by the 7 bit wiper register which is decoded to select one

of these 128 contact points.

Typical R to R_HResistance for

Position

00

^W10k1 DP

10,0701 or

5,0471 or

1491 or

10,0001 + 701

4,9771 + 701

791 + 701

Each contact point generates a linear resistive value

between the 0 position and the 127 position. These

values can be determined by dividing the end-to-end

value of the potentiometer by 127. In the case of the

64

126

127

701 or

01 + 701

Doc No. MD-2124, Rev. E

11

Characteristics subject to change without notice

DP7132

PACKAGE OUTLINE DRAWING

MSOP 10-Lead 3.0 x 3.0mm (Z)

SYMBOL

MIN

NOM

MAX

1.10

0.15

0.95

0.27

0.23

3.10

5.05

3.10

A

A1

A2

b

0.00

0.75

0.17

0.13

2.90

4.75

2.90

0.05

0.85

c

D

3.00

4.90

E

E1

E

E1

e

3.00

0.50 BSC

0.60

L

0.40

0º

0.80

8º

L1

L2

e

0.95 REF

0.25 BSC

TOP VIEW

D

A2

A

DETAIL A

A1

e

b

c

SIDE VIEW

END VIEW

e

L2

L

L1

DETAIL A

Notes:

1. All dimensions are in millimeters. Angles in degrees.

2. Complies with JEDEC standard MO-187.

Characteristics subject to change without notice

Doc. No. MD-2124, Rev. E

12

DP7132

EXAMPLE OF ORDERING INFORMATION

Prefix

Device #

Suffix

DP

7132

Z

I

-10 – G

T3

Company ID

Product Number

Temperature Range

T: Tape & Reel

3: 3,000/Reel

7132

I = Industrial (-40$C to 85$C)

Resistance

Package

-10: 10k1

-50: 50k1

-00: 100k1

Z: MSOP

Lead Finish

G: NiPdAu (PPF)

Notes:

(1) All packages are RoHS-compliant (Lead-free, Halogen-free).

(2) The standard lead finish is NiPdAu.

(3) The device used in the above example is a DP7132ZI-10-GT3 (MSOP, Industrial Temperature range, 10k1, NiPdAu, Tape & Reel,

3,000/Reel).

(4) For additional package and temperature options, please contact your nearest COPAL ELECTRONICS Sales office.

Ordering Part Number

DP7132ZI-10-GT3

DP7132ZI-50-GT3

DP7132ZI-00-GT3

Doc No. MD-2124, Rev. E

13

Characteristics subject to change without notice

REVISION HISTORY

Date

Rev.

00

01

Reason

Initial Issue

Update Ordering Information

09/12/2005

01/18/2006

03/24/2006

02

Update Features

Update Description

Update Pin Drescription

Update Absolute Maximum Ratings

Update Recommended Operating Condictions

Update Ordering Information

Update Absolute Maximum Ratings

Update Reliability Characteristics

Update Potentiometer Operation

08/11/06

03

Update Title

Update Potentiometer Characteristics

Update D. C. Electrical Characteristics

Update Typical Performance Characteristics

Update Package Outline

Update Example of Ordering Information

11/01/06

04

E

Update Potentiometer Operation

Update Example of Ordering Information

03/13/2008

Update Package Outline Drawings

Change Document Number from 25092

NIDEC COPAL ELECTRONICS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

NIDEC COPAL ELECTRONICS CORP. product s are not de signe d, int e nde d, or aut horize d for use as compone nt s in syst e ms int e nde d for surgical implant int o t he body, or

ot he r applicat ions int e nde d t o support or sust ain life , or for any ot he r applicat ion in which t he failure of t he NIDEC COPAL ELECTRONICS CORP. product could cre at e a

sit uat ion where personal injury or deat h may occur.

NIDEC COPAL ELECTRONICS CORP. re se rve s t he right t o make change s t o or discont inue any product or se rvice de scribe d he re in wit hout not ice . Product s wit h dat a she e t s

labeled "Advance Informat ion" or "Preliminary" and ot her product s described herein may not be in product ion or offered for sale.

NIDEC COPAL ELECTRONICS CORP. advise s cust ome rs t o obt ain t he curre nt ve rsion of t he re le vant product informat ion be fore placing orde rs. Circuit diagrams illust rat e

t ypical semiconduct or applicat ions and may not be complet e.

NIDEC COPAL ELECTRONICS CORP.

Japan Head Office

Nishi-Shinjuku, Kimuraya Bldg.,

7-5-25 Nishi-Shinjuku, Shinjuku-ku, Tokyo 160-0023

Publication #: MD-2124

Phone: +81-3-3364-7055

Revison:

E

Fax: +81-3-3364-7098

Issue date:

03/13/08

www.nidec-copal-electronics.com


型号：	DP7132
厂家：	NIDEC COMPONENTS
描述：	16 Volt Digital Potentiometer
文件：	总14页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DP7132 [NIDEC]

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