PRMD16 [NEXPERIA]
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)Production;型号: | PRMD16 |
厂家: | Nexperia |
描述: | 50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)Production |
文件: | 总14页 (文件大小:282K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors
(RET)
14 September 2018
Product data sheet
1. General description
NPN/PNP Resistor-Equipped double Transistors (RET) in an ultra small DFN1412-6 (SOT1268)
leadless Surface-Mounted Device (SMD) plastic package.
2. Features and benefits
•
100 mA output current capability
•
•
•
•
•
•
Built-in bias resistors
Simplifies circuit design
Reduces component count
Reduces pick and place costs
Low package height of 0.5 mm
AEC-Q101 qualified
3. Applications
•
•
•
•
Digital applications
Cost-saving alternative to BC847/BC857 series in digital applications
Control of IC inputs
Switching loads
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor, for the PNP transistor with negative polarity
VCEO
collector-emitter
voltage
open base
-
-
50
V
IO
output current
DC current gain
bias resistor 1
bias resistor ratio
-
-
100
-
mA
hFE
R1
VCE = 5 V; IC = 5 mA; Tamb = 25 °C
Tamb = 25 °C
80
15.4
1.7
-
[1]
[1]
22
2.13
28.6
2.6
kΩ
R2/R1
[1] See section "Test information" for resistor calculation and test conditions.
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
5. Pinning information
Table 2. Pinning information
Pin
1
Symbol Description
Simplified outline
Graphic symbol
O1 I2
GND2
TR2
GND1
I1
GND (emitter) TR1
1
6
5
4
2
input (base) TR1
7
3
O2
output (collector) TR2
GND (emitter) TR2
input (base) TR2
R1
R2
2
4
GND2
I2
TR1
R2
8
5
3
R1
6
O1
output (collector) TR1
output (collector) TR1
output (collector) TR2
Transparent top view
7
O1
GND1
I1 O2
aaa-007379
DFN1412-6
(SOT1268)
8
O2
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
Description
Version
PRMD16
DFN1412-6
plastic thermal enhanced ultra thin small outline package; no
leads; 6 terminals; body: 1.4 mm x 1.2 mm x 0.47 mm
SOT1268
7. Marking
Table 4. Marking codes
Type number
Marking code
PRMD16
B7
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
2 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions
Per transistor, for the PNP transistor with negative polarity
Min
Max
Unit
VCBO
VCEO
VEBO
VI
collector-base voltage
open emitter
-
-
-
-
-
-
-
50
50
7
V
collector-emitter voltage open base
V
emitter-base voltage
input voltage
open collector
positive
V
40
-7
V
negative
V
IO
output current
100
325
mA
mW
Ptot
total power dissipation
Tamb ≤ 25 °C
Tamb ≤ 25 °C
[1]
[1]
Per device
Ptot
Tj
total power dissipation
junction temperature
ambient temperature
storage temperature
-
480
150
150
150
mW
°C
-
Tamb
Tstg
-55
-65
°C
°C
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
aaa-024487
500
P
tot
(mW)
400
300
200
100
0
-75
-25
25
75
125
amb
175
(°C)
T
FR4 PCB, standard footprint
Fig. 1. Per device: Power derating curve
©
PRMD16
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Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
3 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
9. Thermal characteristics
Table 6. Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor
Rth(j-a)
thermal resistance from in free air
junction to ambient
[1]
[1]
-
-
385
K/W
Per device
Rth(j-a)
thermal resistance from in free air
junction to ambient
-
-
261
K/W
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard footprint.
aaa-024488
3
10
duty cycle = 1
Z
th(j-a)
(K/W)
0.75
0.5
0.33
0.2
2
10
0.1
0.05
0.01
0.02
10
0
1
-5
10
-4
-3
-2
10
-1
2
3
10
10
10
1
10
10
10
t
(s)
p
FR4 PCB, standard footprint
Fig. 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
4 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
10. Characteristics
Table 7. Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Per transistor, for the PNP transistor with negative polarity
ICEO
collector-emitter cut-off VCE = 30 V; IB = 0 A; Tamb = 25 °C
-
-
-
-
-
-
1
µA
µA
nA
current
VCE = 30 V; IB = 0 A; Tj = 150 °C
50
100
ICBO
IEBO
collector-base cut-off
current
VCB = 50 V; IE = 0 A; Tamb = 25 °C
emitter-base cut-off
current
VEB = 5 V; IC = 0 A; Tamb = 25 °C
-
-
120
µA
hFE
DC current gain
VCE = 5 V; IC = 5 mA; Tamb = 25 °C
IC = 10 mA; IB = 0.5 mA; Tamb = 25 °C
80
-
-
-
-
VCEsat
collector-emitter
150
mV
saturation voltage
VI(off)
VI(on)
R1
off-state input voltage VCE = 5 V; IC = 100 µA; Tamb = 25 °C
on-state input voltage VCE = 0.3 V; IC = 2 mA; Tamb = 25 °C
-
0.8
1.1
22
0.5
-
V
2
V
bias resistor 1
Tamb = 25 °C
[1]
[1]
15.4
1.7
-
28.6
2.6
2.5
kΩ
R2/R1
CC
bias resistor ratio
collector capacitance
2.13
-
VCB = 10 V; IE = 0 A; ie = 0 A; f = 1 MHz;
Tamb = 25 °C
pF
pF
VCB = -10 V; IE = 0 A; ie = 0 A;
f = 1 MHz; Tamb = 25 °C
-
-
3
fT
transition frequency
VCE = 5 V; IC = 10 mA; f = 100 MHz;
Tamb = 25 °C
[2]
[2]
-
-
230
180
-
-
MHz
MHz
[1] See section "Test information" for resistor calculation and test conditions.
[2] Characteristics of built-in transistor.
aaa-021293
aaa-021294
3
10
0.1
0.60 mA
0.54 mA
I
0.48 mA
0.42 mA
C
(A)
(1)
(2)
h
FE
0.08
0.06
0.04
0.02
0
0.36 mA
(3)
0.30 mA
2
10
0.24 mA
0.18 mA
0.12 mA
10
I
= 0.06 mA
B
1
-1
10
2
1
10
10
0
1
2
3
4
5
I
(mA)
V
(V)
CE
C
VCE = 5 V
Tamb = 25 °C
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = -40 °C
Fig. 4. NPN transistor: Collector current as a function
of collector-emitter voltage; typical values
Fig. 3. NPN transistor: DC current gain as a function of
collector current; typical values
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
5 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
aaa-021336
aaa-021295
2
1
10
V
I(on)
(V)
V
CEsat
(V)
10
-1
10
(1)
(2)
(3)
(1)
(2)
(3)
1
-2
-1
10
10
-1
2
-1
2
10
1
10
10
10
1
10
10
I
(mA)
I (mA)
C
C
IC/IB = 10
VCE = 0.3 V
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = -40 °C
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 5. NPN transistor: Collector-emitter saturation
voltage as a function of collector current;
typical values
Fig. 6. NPN transistor: On-state input voltage as a
function of collector current; typical values
aaa-021296
aaa-021337
10
3
C
c
(pF)
V
I(off)
(V)
2
1
0
(1)
(2)
1
(3)
-1
10
-1
10
1
10
0
10
20
30
40
V
50
I
(mA)
(V)
CB
C
VCE = 5 V
f = 1 MHz; Tamb = 25 °C
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 8. NPN transistor: Collector capacitance as a
function of collector-base voltage; typical
values
Fig. 7. NPN transistor: Off-state input voltage as a
function of collector current; typical values
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
6 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
006aac757
aaa-021338
3
3
10
10
h
FE
(1)
(2)
f
T
(MHz)
2
10
(3)
2
10
10
10
1
-1
10
2
-1
-10
2
1
10
10
-1
-10
-10
I
(mA)
I (mA)
C
C
VCE = 5 V; Tamb = 25 °C
VCE = -5 V
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = -40 °C
Fig. 9. NPN transistor: Transition frequency as a
function of collector current; typical values of
built-in transistor
Fig. 10. PNP transistor: DC current gain as a function of
collector current; typical values
aaa-021339
aaa-021342
-0.1
-1
-0.90 mA
-0.81 mA
I
C
(A)
-0.72 mA
-0.63 mA
-0.45 mA
-0.08
V
CEsat
(V)
-0.54 mA
-0.06
-0.04
-0.02
0
-0.36 mA
-0.18 mA
-1
-10
-0.27 mA
(1)
(2)
(3)
I
= -0.09 mA
B
-2
-10
-1
2
0
-1
-2
-3
-4
-5
-10
-1
-10
-10
V
(V)
I (mA)
C
CE
Tamb = 25 °C
IC/IB = 10
(1) Tamb = 100 °C
(2) Tamb = 25 °C
(3) Tamb = -40 °C
Fig. 11. PNP transistor: Collector current as a function
of collector-emitter voltage; typical values
Fig. 12. PNP transistor: Collector-emitter saturation
voltage as a function of collector current;
typical values
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
7 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
aaa-021340
aaa-021341
2
-10
-10
V
I(on)
(V)
V
I(off)
(V)
(1)
(2)
(3)
-10
(1)
(2)
-1
(3)
-1
-1
-1
-10
-10
-1
2
-1
-10
-1
-10
-10
-10
-1
-10
I
(mA)
I (mA)
C
C
VCE = -0.3 V
VCE = -5 V
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
(1) Tamb = -40 °C
(2) Tamb = 25 °C
(3) Tamb = 100 °C
Fig. 13. PNP transistor: On-state input voltage as a
function of collector current; typical values
Fig. 14. PNP transistor: Off-state input voltage as a
function of collector current; typical values
aaa-021343
006aac763
3
4
10
C
c
(pF)
f
T
3
2
1
0
(MHz)
2
10
10
-1
-10
2
0
-10
-20
-30
-40
V
-50
(V)
-1
-10
-10
I (mA)
C
CB
f = 1 MHz; Tamb = 25 °C
VCE = -5 V; Tamb = 25 °C
Fig. 15. PNP transistor: Collector capacitance as a
function of collector-base voltage; typical
values
Fig. 16. PNP transistor: Transition frequency as a
function of collector current; typical values of
built-in transistor
©
PRMD16
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Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
8 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
11. Test information
Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC)
standard Q101 - Stress test qualification for discrete semiconductors, and is suitable for use in
automotive applications.
Resistor calculation
•
Calculation of bias resistor 1 (R1)
•
Calculation of bias resistor ratio (R2/R1)
n.c.
I
I
; I
I1 I2
R1
; I
I3 I4
R2
GND
aaa-020082
Fig. 17. NPN transistor: Resistor test circuit
n.c.
I
I
; I
I1 I2
R1
; I
I3 I4
R2
GND
aaa-020083
Fig. 18. PNP transistor: Resistor test circuit
Resistor test conditions
Table 8. Resistor test conditions
Per transistor; for the PNP transistor with negative polarity
R1 (kΩ)
R2 (kΩ)
Test conditions
II1
II2
140 μA
II3
II4
22
47
90 μA
-55 μA
-105 μA
©
PRMD16
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Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
9 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
12. Package outline
DFN1412-6: plastic thermal enhanced ultra thin small outline package; no leads;
6 terminals; body: 1.4 x 1.2 x 0.47 mm
SOT1268
(2×)
E
B
A
pin 1
index area
A
D
A
1
T
(6×)
detail X
C
Y
C
1
Y
E
L
1
(2×)
(6×)
4
5
3
2
e
e
e
e
1
b
(6×)
1
D
1
(2×)
1
6
V
C A B
pin 1
X
index area
0
1 mm
scale
L
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
b
D
D
1
E
E
e
e
T
V
Y
Y
1
1
1
1
min 0.44 0.00 0.15 1.35 0.43 1.15 0.32
0.145 0.10
0.20 1.40 0.48 1.20 0.37 0.5 0.35 0.195 0.16 0.1 0.05 0.05
0.50 0.04 0.25 1.45 0.53 1.25 0.42 0.245 0.22
nom
max
mm
Note
0.47
1. Dimension A is including plating thickness.
sot1268_po
References
Outline
version
IEC
European
projection
Issue date
JEDEC
- - -
JEITA
18-08-23
18-09-11
SOT1268
Fig. 19. Package outline DFN1412-6 (SOT1268)
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
10 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
13. Soldering
Footprint information for reflow soldering of DFN1412-6 package
SOT1268
1.6
1.4
1.3
0.3
0.2
0.25
0.5
0.3 0.35
0.27 0.37
1.71 1.51 1.41 0.71
0.17
0.43
0.17
1.23
occupied area
solder resist
solder paste
solder lands
Dimensions in mm
16-04-18
16-09-02
Issue date
sot1268_fr
Fig. 20. Reflow soldering footprint for DFN1412-6 (SOT1268)
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
11 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
14. Revision history
Table 9. Revision history
Data sheet ID
PRMD16 v.2
Modifications:
Release date
20180914
Data sheet status
Change notice
Supersedes
Product data sheet
-
PRMD16 v.1
•
Package outline drawing updated: Unit T added
PRMD16 v.1
20170729 Product data sheet
-
-
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
12 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
equipment, nor in applications where failure or malfunction of an Nexperia
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. Nexperia and its suppliers accept
no liability for inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
15. Legal information
Data sheet status
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Document status Product
Definition
[1][2]
status [3]
Applications — Applications that are described herein for any of these
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
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customer’s applications and products using Nexperia products in order to
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modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
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Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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specifications and product descriptions, at any time and without notice. This
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Suitability for use in automotive applications — This Nexperia product
has been qualified for use in automotive applications. Unless otherwise
agreed in writing, the product is not designed, authorized or warranted to
be suitable for use in life support, life-critical or safety-critical systems or
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
13 / 14
Nexperia
PRMD16
50 V, 100 mA NPN/PNP Resistor-Equipped double Transistors (RET)
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Quick reference data....................................................1
5. Pinning information......................................................2
6. Ordering information....................................................2
7. Marking..........................................................................2
8. Limiting values............................................................. 3
9. Thermal characteristics............................................... 4
10. Characteristics............................................................5
11. Test information..........................................................9
12. Package outline........................................................ 10
13. Soldering................................................................... 11
14. Revision history........................................................12
15. Legal information......................................................13
© Nexperia B.V. 2018. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 14 September 2018
©
PRMD16
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2018. All rights reserved
Product data sheet
14 September 2018
14 / 14
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