74LVC8T245PW.118 [NEXPERIA]
8-bit dual supply translating transceiver; 3-state;
| 型号： | 74LVC8T245PW.118 |
| 厂家： | 
Nexperia |
| 描述： | 8-bit dual supply translating transceiver; 3-state |
| 文件： | 总28页 (文件大小：831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
Rev. 3 — 12 December 2011
Product data sheet
1. General description
The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (pins An and Bn), a direction control input (DIR), an output enable input
(OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at
any voltage between 1.2 V and 5.5 V making the device suitable for translating between
any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and
DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows
transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The
output enable input (OE) can be used to disable the outputs so the buses are effectively
isolated.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a
valid logic level.
2. Features and benefits
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
60 Mbps (translate to 1.5 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78B Class II
24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 30 A maximum ICC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC8T245PW
74LVCH8T245PW
74LVC8T245BQ
74LVCH8T245BQ
40 C to +125 C
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
40 C to +125 C
DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
4. Functional diagram
B1
21
B2
20
B3
19
B4
18
B5
17
B6
16
B7
15
B8
14
V
V
CC(B)
CC(A)
22
OE
2
DIR
3
A1
4
5
6
7
8
9
10
A8
A2
A3
A4
A5
A6
A7
001aai472
Fig 1. Logic symbol
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
2 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
DIR
A1
OE
B1
V
CC(A)
V
CC(B)
to other seven channels
001aai473
Fig 2. Logic diagram (one channel)
5. Pinning information
5.1 Pinning
74LVC8T245
74LVCH8T245
terminal 1
index area
74LVC8T245
74LVCH8T245
2
3
23
22
21
20
19
18
17
16
15
14
DIR
A1
V
CC(B)
1
2
24
23
22
21
20
19
18
17
16
15
14
13
V
V
V
CC(A)
DIR
CC(B)
CC(B)
OE
B1
B2
B3
B4
B5
B6
B7
B8
4
A2
3
A1
A2
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
5
A3
4
6
A4
5
A3
7
A5
6
A4
8
A6
7
A5
9
A7
8
A6
(1)
10
11
A8
GND
9
A7
GND
10
11
12
A8
GND
GND
001aak437
Transparent top view
001aak436
(1) This is not a supply pin, the substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad
however if it is soldered the solder land should remain
floating or be connected to GND.
Fig 3. Pin configuration SOT355-1 (TSSOP24)
Fig 4. Pin configuration SOT815-1 (DHVQFN24)
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
3 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
5.2 Pin description
Table 2.
Symbol
VCC(A)
DIR
Pin description
Pin
Description
supply voltage A (An inputs/outputs, OE and DIR inputs are referenced to VCC(A)
1
)
2
direction control
data input or output
ground (0 V)
A1 to A8
GND[1]
GND[1]
GND[1]
B1 to B8
OE
3, 4, 5, 6, 7, 8, 9, 10
11
12
13
ground (0 V)
ground (0 V)
21, 20, 19, 18, 17, 16, 15, 14 data input or output
22
23
24
output enable input (active LOW)
VCC(B)
VCC(B)
supply voltage B (Bn inputs/outputs are referenced to VCC(B)
)
)
supply voltage B (Bn inputs/outputs are referenced to VCC(B)
[1] All GND pins must be connected to ground (0 V).
6. Functional description
Table 3.
Function table[1]
Supply voltage
VCC(A), VCC(B)
1.2 V to 5.5 V
1.2 V to 5.5 V
1.2 V to 5.5 V
GND[3]
Input
OE[2]
Input/output[3]
DIR[2]
An[2]
An = Bn
input
Z
Bn[2]
input
Bn = An
Z
L
L
L
H
X
X
H
X
Z
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2] The An inputs/outputs, DIR and OE input circuit is referenced to VCC(A); The Bn inputs/outputs circuit is referenced to VCC(B)
[3] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC(A)
VCC(B)
IIK
Parameter
Conditions
Min
0.5
0.5
50
0.5
50
0.5
0.5
-
Max
+6.5
+6.5
-
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
V
VI < 0 V
mA
V
[1]
VI
+6.5
-
IOK
output clamping current
output voltage
VO < 0 V
mA
V
[1][2][3]
[1]
VO
Active mode
VCCO + 0.5
+6.5
50
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B); per VCC pin
V
[2]
IO
output current
supply current
mA
mA
ICC
-
100
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
4 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Table 4.
Limiting values …continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
IGND
Parameter
Conditions
Min
100
65
-
Max
-
Unit
mA
C
ground current
per GND pin
Tstg
storage temperature
total power dissipation
+150
500
[4]
Ptot
Tamb = 40 C to +125 C
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For TSSOP24 package: Ptot derates linearly at 5.5 mW/K above 60 C.
For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VCC(A)
VCC(B)
VI
Recommended operating conditions
Parameter
Conditions
Min
Max
5.5
5.5
5.5
VCCO
5.5
+125
20
Unit
V
supply voltage A
supply voltage B
input voltage
1.2
1.2
V
0
V
[1]
[2]
VO
output voltage
Active mode
0
V
Suspend or 3-state mode
0
V
Tamb
ambient temperature
40
C
t/V
input transition rise and fall rate VCCI = 1.2 V
VCCI = 1.4 V to 1.95 V
-
-
-
-
-
ns/V
ns/V
ns/V
ns/V
ns/V
20
VCCI = 2.3 V to 2.7 V
VCCI = 3 V to 3.6 V
VCCI = 4.5 V to 5.5 V
20
10
5
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
9. Static characteristics
Table 6.
Typical static characteristics at Tamb = 25 C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
HIGH-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V
LOW-level output voltage VI = VIH or VIL
IO = 3 mA; VCCO = 1.2 V
Min
Typ
Max
Unit
[1]
VOH
VOL
II
-
1.09
-
V
[1]
[2]
-
-
0.07
-
-
V
input leakage current
DIR, OE input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V
1
A
[2]
[2]
IBHL
IBHH
bus hold LOW current
bus hold HIGH current
A or B port; VI = 0.42 V; VCCI = 1.2 V
A or B port; VI = 0.78 V; VCCI = 1.2 V
-
-
19
-
-
A
A
19
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
5 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Table 6.
Typical static characteristics at Tamb = 25 C …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
[2][3]
[2][3]
[1]
IBHLO
IBHHO
IOZ
bus hold LOW overdrive
current
A or B port; VCCI = 1.2 V
-
19
-
A
bus hold HIGH overdrive
current
A or B port; VCCI = 1.2 V
-
-
-
-
-
-
19
-
A
A
A
A
A
A
OFF-state output current
A or B port; VO = 0 V or VCCO
VCCO = 1.2 V to 5.5 V
;
-
-
-
-
-
1
1
1
1
1
[1]
suspend mode A port; VO = 0 V or VCCO
VCC(A) = 5.5 V; VCC(B) = 0 V
;
;
[1]
suspend mode B port; VO = 0 V or VCCO
VCC(A) = 0 V; VCC(B) = 5.5 V
IOFF
power-off leakage current A port; VI or VO = 0 V to 5.5 V;
VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V
CI
input capacitance
DIR, OE input; VI = 0 V or 3.3 V; VCC(A) = 3.3 V
-
-
3
-
-
pF
pF
CI/O
input/output capacitance
A and B port; VO = 3.3 V or 0 V;
VCC(A) = VCC(B) = 3.3 V
6.5
[1] VCCO is the supply voltage associated with the output port.
[2] CCI is the supply voltage associated with the data input port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH.
V
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
[1]
VIH
HIGH-level
data input
input voltage
VCCI = 1.2 V
0.8VCCI
0.65VCCI
1.7
-
-
-
-
-
0.8VCCI
0.65VCCI
1.7
-
-
-
-
-
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
DIR, OE input
2.0
2.0
0.7VCCI
0.7VCCI
VCCI = 1.2 V
0.8VCC(A)
0.65VCC(A)
1.7
-
-
-
-
-
0.8VCC(A)
0.65VCC(A)
1.7
-
-
-
-
-
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
2.0
2.0
0.7VCC(A)
0.7VCC(A)
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
6 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
[1]
VIL
LOW-level
data input
input voltage
VCCI = 1.2 V
-
-
-
-
-
0.2VCCI
0.35VCCI
0.7
-
-
-
-
-
0.2VCCI
0.35VCCI
0.7
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
DIR, OE input
0.8
0.8
0.3VCCI
0.3VCCI
VCCI = 1.2 V
-
-
-
-
-
0.2VCC(A)
0.35VCC(A)
0.7
-
-
-
-
-
0.2VCC(A)
0.35VCC(A)
0.7
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
VI = VIH
0.8
0.8
0.3VCC(A)
0.3VCC(A)
VOH
HIGH-level
output voltage
[2]
IO = 100 A;
VCCO 0.1
-
VCCO 0.1
-
V
VCCO = 1.2 V to 4.5 V
IO = 6 mA; VCCO = 1.4 V
IO = 8 mA; VCCO = 1.65 V
IO = 12 mA; VCCO = 2.3 V
IO = 24 mA; VCCO = 3.0 V
IO = 32 mA; VCCO = 4.5 V
VI = VIL
1.0
1.2
1.9
2.4
3.8
-
-
-
-
-
1.0
1.2
1.9
2.4
3.8
-
-
-
-
-
V
V
V
V
V
[2]
VOL
LOW-level
output voltage
IO = 100 A;
-
0.1
-
0.1
V
VCCO = 1.2 V to 4.5 V
IO = 6 mA; VCCO = 1.4 V
IO = 8 mA; VCCO = 1.65 V
IO = 12 mA; VCCO = 2.3 V
IO = 24 mA; VCCO = 3.0 V
IO = 32 mA; VCCO = 4.5 V
-
-
-
-
-
-
0.3
0.45
0.3
-
-
-
-
-
-
0.3
0.45
0.3
V
V
V
0.55
0.55
2
0.55
0.55
10
V
V
II
input leakage DIR, OE input; VI = 0 V to 5.5 V;
current VCCI = 1.2 V to 5.5 V
A
[1]
IBHL
bus hold LOW A or B port
current
VI = 0.49 V; VCCI = 1.4 V
15
25
-
-
-
-
-
10
20
-
-
-
-
-
A
A
A
A
A
VI = 0.58 V; VCCI = 1.65 V
VI = 0.70 V; VCCI = 2.3 V
VI = 0.80 V; VCCI = 3.0 V
VI = 1.35 V; VCCI = 4.5 V
45
45
100
100
80
100
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
7 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
[1]
[1][3]
[1][3]
IBHH
IBHLO
IBHHO
IOZ
bus hold HIGH A or B port
current
VI = 0.91 V; VCCI = 1.4 V
15
25
-
-
-
-
-
10
20
45
80
100
-
-
-
-
-
A
A
A
A
A
VI = 1.07 V; VCCI = 1.65 V
VI = 1.70 V; VCCI = 2.3 V
VI = 2.00 V; VCCI = 3.0 V
VI = 3.15 V; VCCI = 4.5 V
45
100
100
bus hold LOW A or B port
overdrive
current
VCCI = 1.6 V
VCCI = 1.95 V
VCCI = 2.7 V
VCCI = 3.6 V
VCCI = 5.5 V
125
200
300
500
900
-
-
-
-
-
125
200
300
500
900
-
-
-
-
-
A
A
A
A
A
bus hold HIGH A or B port
overdrive
VCCI = 1.6 V
125
200
300
500
900
-
-
-
125
200
300
500
900
-
-
A
A
A
A
A
A
current
VCCI = 1.95 V
VCCI = 2.7 V
-
-
-
VCCI = 3.6 V
-
-
-
VCCI = 5.5 V
-
[2]
[2]
OFF-state
A or B port; VO = 0 V or VCCO
;
2
10
output current VCCO = 1.2 V to 5.5 V
suspend mode A port;
VO = 0 V or VCCO; VCC(A) = 5.5 V;
VCC(B) = 0 V
-
-
-
-
2
2
2
2
-
-
-
-
10
10
10
10
A
A
A
A
[2]
suspend mode B port;
VO = 0 V or VCCO; VCC(A) = 0 V;
VCC(B) = 5.5 V
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 5.5 V;
VCC(A) = 0 V;
V
CC(B) = 1.2 V to 5.5 V
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V;
VCC(A) = 1.2 V to 5.5 V
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
8 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C
40 C to +125 C
Unit
Min
Max
Min
Max
[1]
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(A) = 5.5 V; VCC(B) = 0 V
-
-
15
15
-
-
-
20
20
-
A
A
A
VCC(A) = 0 V; VCC(B) = 5.5 V
2
4
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(B) = 0 V; VCC(A) = 5.5 V
-
2
-
15
-
-
4
-
20
-
A
A
A
VCC(B) = 5.5 V; VCC(A) = 0 V
15
20
A plus B port (ICC(A) + ICC(B));
IO = 0 A; VI = 0 V or VCCI
VCC(A), VCC(B) = 1.2 V to 5.5 V
-
-
25
50
-
-
30
75
A
A
ICC
additional
per input;
supply current VCC(A), VCC(B) = 3.0 V to 5.5 V
DIR and OE input; DIR or OE
input at VCC(A) 0.6 V;
A port at VCC(A) or GND;
B port = open
[4]
[4]
A port; A port at VCC(A) 0.6 V;
DIR at VCC(A); B port = open
-
-
50
50
-
-
75
75
A
A
B port; B port at VCC(B) 0.6 V;
DIR at GND; A port = open
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO / IBHHO when the input is in the range VIL to VIH.
[4] For non bus hold parts only (74LVC8T245).
74LVC_LVCH8T245
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
9 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
10. Dynamic characteristics
Table 8.
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.
Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 C[1]
Symbol Parameter
Conditions
VCC(B)
Unit
1.2 V
11.0
11.0
9.5
1.5 V
8.5
1.8 V
2.5 V
6.2
3.3 V
5.7
5.0 V
5.4
tpd
tdis
ten
propagation delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
7.4
9.5
ns
ns
ns
ns
ns
ns
10.0
9.5
9.1
8.9
8.9
disable time
enable time
9.5
7.8
9.5
9.5
9.5
10.2
13.5
13.6
8.2
6.7
7.3
6.4
13.5
10.3
13.5
8.9
13.5
7.5
13.5
7.1
13.5
7.0
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
Table 9.
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.
Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 C[1]
Symbol Parameter
Conditions
VCC(A)
Unit
1.2 V
11.0
11.0
9.5
1.5 V
10.0
8.5
1.8 V
2.5 V
9.1
3.3 V
8.9
5.0 V
8.8
tpd
tdis
ten
propagation delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
9.5
7.3
5.4
ns
ns
ns
ns
ns
ns
6.2
5.7
5.4
disable time
enable time
6.8
3.8
4.1
3.1
10.2
13.5
13.6
9.1
8.6
8.1
7.8
7.8
9.0
6.9
4.8
3.8
3.2
12.5
12.0
11.5
11.4
11.4
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
Table 10. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 C[1][2]
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VCC(A) and VCC(B)
Unit
1.8 V
2.5 V
3.3 V
5.0 V
CPD
power dissipation A port: (direction A to B);
1
1
1
2
pF
pF
capacitance
B port: (direction B to A)
A port: (direction B to A);
B port: (direction A to B)
13
13
13
13
[1] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = .
74LVC_LVCH8T245
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
10 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Table 11. Dynamic characteristics for temperature range 40 C to +85 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max
Min Max Min Max Min Max
VCC(A) = 1.5 V 0.1 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.7
0.9
1.5
2.4
0.4
1.8
27
27
30
34
34
36
1.7
0.9
1.5
2.4
0.4
1.8
23
25
30
33
34
34
1.3
0.8
1.5
1.9
0.4
1.5
18
23
30
15
34
18
1.0
0.7
1.5
1.7
0.4
1.2
15
23
30
14
34
15
0.8
0.7
1.4
1.3
0.4
0.9
13 ns
22 ns
30 ns
12 ns
34 ns
13 ns
disable time
enable time
VCC(A) = 1.8 V 0.15 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.7
0.9
1.5
2.4
0.4
1.8
25
23
30
33
24
34
1.7
0.9
1.5
2.4
0.4
1.8
21.9
23.8
29.6
32.2
24.0
32.0
1.3
0.8
1.5
1.9
0.4
1.5
9.2
1.0
0.7
1.5
1.7
0.4
1.2
7.4
0.8
0.7
1.4
1.3
0.4
0.9
7.1 ns
23.4 ns
29.2 ns
10.3 ns
23.7 ns
10.8 ns
23.6
29.4
13.1
23.8
16.0
23.4
29.3
12.0
23.7
12.6
disable time
enable time
VCC(A) = 2.5 V 0.2 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.5
1.2
1.4
2.3
1.0
1.7
23
18
1.5
1.2
1.4
2.3
1.0
1.7
21.4
9.3
1.2
1.0
1.4
1.8
1.0
1.5
9.0
9.1
0.8
1.0
1.4
1.7
1.0
1.2
6.2
8.9
0.6
0.9
1.4
0.9
1.0
1.0
4.8 ns
8.8 ns
9.0 ns
6.9 ns
10.9 ns
6.9 ns
disable time
9.0
31
9.0
9.0
9.0
29.6
10.9
28.2
11.0
10.9
12.9
9.3
10.9
9.4
enable time
10.9
32
VCC(A) = 3.3 V 0.3 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.5
0.8
1.6
2.1
0.8
1.8
23
15
1.5
0.8
1.6
2.1
0.8
1.8
21.2
7.2
1.1
0.8
1.6
1.7
0.8
1.4
8.8
6.2
0.8
0.7
1.6
1.5
0.8
1.1
6.3
6.1
8.2
8.6
8.1
8.5
0.5
0.6
1.6
0.8
0.8
0.9
4.4 ns
6.0 ns
8.2 ns
6.3 ns
8.1 ns
6.4 ns
disable time
8.2
30
8.2
8.2
29.0
8.1
10.3
8.1
enable time
8.1
31
27.7
12.4
VCC(A) = 5.0 V 0.5 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.5
0.7
0.3
2.0
0.7
1.5
22
13
1.5
0.7
0.3
2.0
0.7
1.5
21.4
7.0
1.0
0.4
0.3
1.6
0.7
1.3
8.8
4.8
5.4
9.7
6.4
11.4
0.7
0.3
0.3
1.4
0.7
1.0
6.0
4.5
5.4
8.0
6.4
8.1
0.4
0.3
0.3
0.7
0.7
0.9
4.2 ns
4.3 ns
5.4 ns
5.7 ns
6.4 ns
6.0 ns
disable time
5.4
30
5.4
28.7
6.4
enable time
6.4
31
27.6
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
11 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Table 12. Dynamic characteristics for temperature range 40 C to +125 C[1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V 5.0 V 0.5 V
Min Max Min
Max
Min Max Min Max Min Max
VCC(A) = 1.5 V 0.1 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.7
0.9
1.5
2.4
0.4
1.8
32
32
34
41
40
43
1.7
0.9
1.5
2.4
0.4
1.8
27
30
34
40
40
41
1.3
0.8
1.5
1.9
0.4
1.5
21
28
34
18
40
22
1.0
0.7
1.5
1.7
0.4
1.2
18
28
34
17
40
18
0.8
0.7
1.4
1.3
0.4
0.9
16 ns
26 ns
34 ns
15 ns
40 ns
16 ns
disable time
enable time
VCC(A) = 1.8 V 0.15 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.7
0.9
1.5
2.4
0.4
1.8
30
27
34
40
28
41
1.7
0.9
1.5
2.4
0.4
1.8
25.9
28.8
33.6
36.2
28
1.3
0.8
1.5
1.9
0.4
1.5
13.2
27.6
33.4
17.1
27.8
20
1.0
0.7
1.5
1.7
0.4
1.2
11.4
27.4
33.3
16.0
27.7
16.6
0.8
0.7
1.4
1.3
0.4
0.9
11.1 ns
27.4 ns
33.2 ns
14.3 ns
27.7 ns
14.8 ns
disable time
enable time
40
VCC(A) = 2.5 V 0.2 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.5
1.2
1.4
2.3
1.0
1.7
28
23
1.5
1.2
1.4
2.3
1.0
1.7
25.4
13.3
13
1.2
1.0
1.4
1.8
1.0
1.5
13
13.1
13
0.8
1.0
1.4
1.7
1.0
1.2
10.2
12.9
13
0.6
0.9
1.4
0.9
1.0
1.0
8.8 ns
12.8 ns
13 ns
10.9 ns
17.3 ns
11.2 ns
disable time
13
37
33.6
17.2
32.2
15
14.3
17.2
14.1
enable time
17.2
38
17.3
18.1
VCC(A) = 3.3 V 0.3 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.5
0.8
1.6
2.1
0.8
1.8
28
18
1.5
0.8
1.6
2.1
0.8
1.8
25.2
11.2
12.2
33
1.1
0.8
1.6
1.7
0.8
1.4
12.8
10.2
12.2
14.3
13.6
18.4
0.8
0.7
1.6
1.5
0.8
1.1
10.3
10.1
12.2
12.6
13.2
12.9
0.5
0.6
1.6
0.8
0.8
0.9
10.4 ns
10 ns
12.2 ns
10.3 ns
13.6 ns
10.9 ns
disable time
12.2
36
enable time
14.1
37
14.1
31.7
VCC(A) = 5.0 V 0.5 V
tpd
tdis
ten
propagation
delay
An to Bn
Bn to An
OE to An
OE to Bn
OE to An
OE to Bn
1.5
0.7
0.3
2.0
0.7
1.5
26
16
1.5
0.7
0.3
2.0
0.7
1.5
25.4
11
1.0
0.4
0.3
1.6
0.7
1.3
12.8
8.8
0.7
0.3
0.3
1.4
0.7
1.0
10
8.5
0.4
0.3
0.3
0.7
0.7
0.9
8.2 ns
8.3 ns
9.4 ns
9.7 ns
10.9 ns
10.7 ns
disable time
9.4
36
9.4
9.4
9.4
32.7
10.9
31.6
13.7
10.9
18.4
12
enable time
10.9
37
10.9
13.7
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH
.
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
12 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
11. Waveforms
V
I
V
An, Bn input
GND
M
t
t
PLH
PHL
V
OH
V
Bn, An output
M
V
OL
001aai475
Measurement points are given in Table 13.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. The data input (An, Bn) to output (Bn, An) propagation delay times
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aai474
Measurement points are given in Table 13.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
Table 13. Measurement points
Supply voltage
VCC(A), VCC(B)
1.2 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 5.5 V
Input[1]
Output[2]
VM
VM
VX
VOL + 0.1 V
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOH 0.1 V
VOH 0.15 V
VOH 0.3 V
VOL + 0.15 V
VOL + 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
74LVC_LVCH8T245
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
13 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 14.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance.
V
EXT = External voltage for measuring switching times.
Fig 7. Load circuitry for switching times
Table 14. Test data
Supply voltage
VCC(A), VCC(B)
1.2 V to 5.5 V
Input
VI[1]
Load
CL
VEXT
[3]
t/V[2]
RL
2 k
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
VCCI
1.0 ns/V
15 pF
open
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt 1.0 V/ns.
[3]
VCCO is the supply voltage associated with the output port.
74LVC_LVCH8T245
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
14 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
001aal268
001aal269
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
(1)
(1)
(2)
10
8
10
8
(2)
(3)
(3)
(4)
(5)
(6)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aal270
001aal271
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
10
8
10
8
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3)
VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6)
VCC(B) = 5.0 V.
Fig 8. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.2 V
74LVC_LVCH8T245
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©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
15 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
001aal272
001aal273
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
(1)
(2)
(1)
(2)
10
8
10
8
(3)
(4)
(5)
(6)
(3)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aal274
001aal275
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
10
8
10
8
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 9. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.5 V
74LVC_LVCH8T245
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
16 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
001aal276
001aal277
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
(1)
(1)
10
8
10
8
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aal278
001aal279
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
10
8
10
8
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 10. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 1.8 V
74LVC_LVCH8T245
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Nexperia B.V. 2017. All rights reserved
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17 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
001aal280
001aal281
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
(1)
(1)
10
8
10
8
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aal282
001aal283
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
10
8
10
8
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 11. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 2.5 V
74LVC_LVCH8T245
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Product data sheet
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74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
001aal284
001aal285
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
(1)
(1)
10
8
10
8
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aal286
001aal287
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
10
8
10
8
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5)
VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 12. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 3.3 V
74LVC_LVCH8T245
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74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
001aal288
001aal289
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
(1)
(1)
10
8
10
8
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aal290
001aal291
14
PHL
14
PLH
t
t
(ns)
12
(ns)
12
10
8
10
8
(1)
(2)
(3)
(4)
(5)
(6)
(1)
(2)
(3)
(4)
(5)
(6)
6
6
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4)
VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig 13. Typical propagation delay versus load capacitance; Tamb = 25 C; VCC(A) = 5 V
74LVC_LVCH8T245
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74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
13. Application information
13.1 Unidirectional logic level-shifting application
The circuit given in Figure 14 is an example of the 74LVC8T245; 74LVCH8T245 being
used in an unidirectional logic level-shifting application.
V
V
V
V
CC1
CC2
CC2
V
V
CC(B)
CC(A)
GND
An
DIR
74LVC8T245
74LVCH8T245
CC1
Bn
OE
system-1
system-2
001aak438
Schematic given for one channel.
Fig 14. Unidirectional logic level-shifting application
Table 15. Description unidirectional logic level-shifting application
Name
VCC(A)
GND
A
Function
VCC1
GND
OUT
IN
Description
supply voltage of system-1 (1.2 V to 5.5 V)
device GND
output level depends on VCC1 voltage
input threshold value depends on VCC2 voltage
the GND (LOW level) determines B port to A port direction
supply voltage of system-2 (1.2 V to 5.5 V)
The GND (LOW level) enables the output ports
B
DIR
VCC(B)
OE
DIR
VCC2
OE
74LVC_LVCH8T245
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8-bit dual supply translating transceiver; 3-state
13.2 Bidirectional logic level-shifting application
Figure 15 shows the 74LVC8T245; 74LVCH8T245 being used in a bidirectional logic
level-shifting application.
V
V
V
V
CC2
CC1
CC1
CC2
V
CC(A)
V
CC(B)
I/O-1
I/O-2
PULL-UP/DOWN
PULL-UP/DOWN
GND
A
DIR
74LVC8T245
74LVCH8T245
B
OE
OE
DIR CTRL
system-1
Schematic given for one channel.
system-2
001aak439
Pull-up or pull-down only needed for 74LVC8T245.
Fig 15. Bidirectional logic level-shifting application
Table 16 gives a sequence that will illustrate data transmission from system-1 to system-2
and then from system-2 to system-1.
Table 16. Description bidirectional logic level-shifting application[1]
State DIR CTRL OE
I/O-1
I/O-2
Description
1
2
H
H
L
output input
system-1 data to system-2
H
Z
Z
Z
system-2 is getting ready to send data to
system-1. I/O-1 and I/O-2 are disabled. The
bus-line state depends on bus hold.
3
L
H
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are
disabled. The bus-line state depends on bus
hold.
4
L
L
input
output system-2 data to system-1
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
13.3 Power-up considerations
The device is designed such that no special power-up sequence is required other than
GND being applied first.
Table 17. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
0 V
0
Unit
1.8 V
< 1
< 2
< 2
< 2
2
2.5 V
< 1
3.3 V
< 1
5.0 V
< 1
2
0 V
A
A
A
A
A
1.8 V
2.5 V
3.3 V
5.0 V
< 1
< 1
< 1
< 1
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
74LVC_LVCH8T245
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Product data sheet
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74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
14. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
12
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT355-1
MO-153
Fig 16. Package outline SOT355-1 (TSSOP24)
74LVC_LVCH8T245
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Nexperia B.V. 2017. All rights reserved
Product data sheet
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74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm
SOT815-1
D
B
A
A
A
E
1
c
detail X
terminal 1
index area
C
e
1
terminal 1
index area
y
y
v
M
C
C
A B
C
1
e
b
w
M
2
11
L
12
13
1
e
E
h
2
24
23
14
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
b
c
D
D
E
E
h
e
e
e
L
v
w
y
y
1
1
2
1
h
max.
0.05 0.30
0.00 0.18
5.6
5.4
4.25
3.95
3.6
3.4
2.25
1.95
0.5
0.3
mm
1
0.2
0.5
4.5
1.5
0.1
0.05 0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
03-04-29
SOT815-1
- - -
- - -
- - -
Fig 17. Package outline SOT815-1 (DHVQFN24)
74LVC_LVCH8T245
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Nexperia B.V. 2017. All rights reserved
Product data sheet
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74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
15. Abbreviations
Table 18. Abbreviations
Acronym
CDM
Description
Charged Device Model
Device Under Test
Human Body Model
Machine Model
DUT
HBM
MM
16. Revision history
Table 19. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC_LVCH8T245 v.3 20111212
Product data sheet
-
74LVC_LVCH8T245 v.2
Modifications:
• Legal pages updated.
74LVC_LVCH8T245 v.2 20110211
74LVC_LVCH8T245 v.1 20100111
Product data sheet
-
-
74LVC_LVCH8T245 v.1
-
Product data sheet
74LVC_LVCH8T245
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Product data sheet
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74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
malfunction of a Nexperia product can reasonably be expected
17.2 Definitions
to result in personal injury, death or severe property or environmental
damage. Nexperia accepts no liability for inclusion and/or use of
Nexperia products in such equipment or applications and
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
17.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — Nexperia products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
74LVC_LVCH8T245
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
26 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of
Nexperia’s specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies Nexperia for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond Nexperia’s
standard warranty and Nexperia’s product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
74LVC_LVCH8T245
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Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 12 December 2011
27 of 28
74LVC8T245; 74LVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
19. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Typical propagation delay characteristics . . 15
7
8
9
10
11
12
13
Application information. . . . . . . . . . . . . . . . . . 21
Unidirectional logic level-shifting application . 21
Bidirectional logic level-shifting application. . . 22
Power-up considerations . . . . . . . . . . . . . . . . 22
13.1
13.2
13.3
14
15
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 23
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
17.1
17.2
17.3
17.4
18
19
Contact information. . . . . . . . . . . . . . . . . . . . . 27
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 12 December 2011
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