74LVC573APW [NEXPERIA]
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction;型号: | 74LVC573APW |
厂家: | Nexperia |
描述: | Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-stateProduction 驱动 光电二极管 逻辑集成电路 |
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74LVC573A
Octal D-type transparent latch
with 5 V tolerant inputs/outputs; 3-state
Rev. 8 — 27 August 2021
Product data sheet
1. General description
The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch
enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches.
In this condition the latches are transparent, a latch output will change each time its corresponding
D-input changes. When LE is LOW the latches store the information that was present at the inputs
a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry
disables the output, preventing the potentially damaging backflow current through the device when
it is powered down.
2. Features and benefits
•
Wide supply voltage range from 1.2 to 3.6 V
•
•
•
•
•
•
•
Overvoltage tolerant inputs to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
High-impedance when VCC = 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
•
•
•
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
•
•
ESD protection:
•
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC573AD
74LVC573APW
74LVC573ABQ
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SO20
plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
TSSOP20
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
SOT764-1
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
4. Functional diagram
11
C1
1
EN1
1
2
19
1D
OE
2
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
5
6
7
18
17
16
15
14
3
4
5
6
7
8
9
8
9
13
12
LE
11
mna807
mna808
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
2
19
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
3
4
5
6
7
8
9
18
17
16
15
14
13
12
LATCH
1 to 8
3-STATE
OUTPUTS
LE
11
1
OE
mna809
Fig. 3. Functional diagram
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
2 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
D0
D1
D2
D3
D4
D5
D6
D7
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LATCH
1
LATCH
2
LATCH
3
LATCH
4
LATCH
5
LATCH
6
LATCH
7
LATCH
8
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE LE
LE
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna810
Fig. 4. Logic diagram
5. Pinning information
5.1. Pinning
74LVC573A
74LVC573A
1
2
20
19
18
17
16
15
14
13
12
11
1
20
V
OE
D0
V
OE
CC
CC
2
3
19
18
17
16
15
14
13
12
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
D0
D1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
3
D1
4
4
D2
D2
5
5
D3
D3
6
6
D4
D4
7
7
D5
D5
8
8
D6
D6
9
9
D7
D7
10
10
GND
GND
aaa-029010
aaa-029011
Fig. 5. Pin configuration SOT163-1 (SO20)
Fig. 6. Pin configuration SOT360-1 (TSSOP20)
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
3 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
74LVC573A
terminal 1
index area
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
(1)
GND
aaa-029012
Transparent top view
(1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered,
the solder land should remain floating or connected to GND.
Fig. 7. Pin configuration SOT764-1 (DHVQFN20)
5.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
OE
1
output enable input (active LOW)
latch enable input (active HIGH)
data input
LE
11
D0, D1, D2, D3, D4, D5, D6, D7
2, 3, 4, 5, 6, 7, 8, 9
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
19, 18, 17, 16, 15, 14, 13, 12
data output
GND
VCC
10
20
ground (0 V)
supply voltage
6. Functional description
Table 3. Functional table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high-impedance OFF-state
Operating modes
Input
Internal latch
Output
OE
L
LE
H
H
L
Dn
L
H
l
Qn
L
Enable and read register
(transparent mode)
L
L
H
L
H
L
Latch and read register
L
L
L
h
l
H
L
H
Z
Latch register and disable outputs H
H
L
L
h
H
Z
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
4 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-
Max
+6.5
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0
mA
V
VI
[1]
[2]
+6.5
±50
IOK
VO
IO
output clamping current
output voltage
VO > VCC or VO < 0
VO = 0 V to VCC
mA
V
-0.5
-
VCC + 0.5
±50
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
100
ground current
-100
-65
-
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[3]
mW
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SOT163-1 (SO20) package: Ptot derates linearly with 12.3 mW/K above 109 °C.
For SOT360-1 (TSSOP20) package: Ptot derates linearly with 10.0 mW/K above 100 °C.
For SOT764-1 (DHVQFN20) package: Ptot derates linearly with 12.9 mW/K above 111 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
3.6
-
Unit
V
VCC
supply voltage
1.65
1.2
0
-
-
-
-
-
-
-
-
functional
V
VI
input voltage
5.5
VCC
5.5
+125
20
V
VO
output voltage
output HIGH- or LOW-state
output 3-state
0
V
0
V
Tamb
ambient temperature
in free air
-40
0
°C
ns/V
ns/V
Δt/ΔV
input transition rise and fall rate
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
10
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
5 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
1.08
-
-
1.08
-
V
V
V
V
V
V
V
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
0.65VCC
-
-
-
-
-
-
-
-
0.65VCC
-
1.7
-
-
1.7
-
-
2.0
2.0
VIL
LOW-level
input voltage
-
-
-
-
0.12
0.35VCC
0.7
-
-
-
-
0.12
0.35VCC
0.7
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI = VIH or VIL
0.8
0.8
VOH
HIGH-level
output voltage
IO = -100 μA;
VCC - 0.2
-
-
VCC - 0.3
-
V
VCC = 1.65 V to 3.6 V
IO = -4 mA; VCC = 1.65 V
IO = -8 mA; VCC = 2.3 V
IO = -12 mA; VCC = 2.7 V
IO = -18 mA; VCC = 3.0 V
IO = -24 mA; VCC = 3.0 V
VI = VIH or VIL
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
V
V
V
V
V
VOL
LOW-level
output voltage
IO = 100 μA;
-
-
0.2
-
0.3
V
VCC = 1.65 V to 3.6 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
-
-
-
-
-
-
0.45
0.6
-
-
-
-
-
0.65
0.8
V
-
V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
VCC = 3.6 V; VI = 5.5 V or GND
-
-
0.4
0.6
V
0.55
±5
0.8
V
II
input leakage
current
±0.1
±20
μA
IOZ
IOFF
ICC
ΔICC
OFF-state
output current VO = 5.5 V or GND
VI = VIH or VIL; VCC = 3.6 V;
-
-
-
-
0.1
0.1
0.1
5
±5
±10
10
-
-
-
-
±20
±20
40
μA
μA
μA
μA
power-off
leakage current
VCC = 0 V; VI or VO = 5.5 V
supply current VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
additional
per input pin;
500
5000
supply current VCC = 2.7 V to 3.6 V;
VI = VCC - 0.6 V; IO = 0 A
CI
input
capacitance
VCC = 0 V to 3.6 V;
VI = GND to VCC
-
5.0
-
-
-
pF
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
©
74LVC573A
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
6 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 12.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tpd
propagation delay Dn to Qn; see Fig. 8
VCC = 1.2 V
[2]
[2]
[2]
[2]
-
16.0
7.8
4.1
4.1
3.4
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
2.1
1.5
1.5
1.5
16.3
8.0
7.2
6.2
2.1
1.5
1.5
1.5
18.8
9.2
9.0
8.0
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
LE to Qn; see Fig. 9
VCC = 1.2 V
-
16.0
7.7
4.1
3.7
3.4
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
2.0
1.5
1.5
1.5
16.0
7.8
7.5
6.5
2.0
1.5
1.5
1.5
18.4
9.1
9.5
8.5
VCC = 3.0 V to 3.6 V
OE to Qn; see Fig. 10
VCC = 1.2 V
ten
enable time
-
18.0
7.5
4.2
4.2
3.4
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.7
1.5
1.5
1.5
17.5
9.2
8.5
7.5
1.7
1.5
1.5
1.5
20.2
10.6
11.0
9.5
VCC = 3.0 V to 3.6 V
OE to Qn; see Fig. 10
VCC = 1.2 V
tdis
disable time
-
8.0
3.3
1.8
3.0
2.5
-
-
-
ns
ns
ns
ns
ns
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.0
0.3
1.5
1.5
10.1
5.7
6.5
6.0
1.0
0.3
1.5
1.5
11.6
6.6
8.5
7.5
VCC = 3.0 V to 3.6 V
LE HIGH; see Fig. 9
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
tW
tsu
th
pulse width
set-up time
hold time
5.0
4.0
3.2
3.2
-
-
-
-
-
-
5.0
4.0
3.2
3.2
-
-
-
-
ns
ns
ns
ns
-
VCC = 3.0 V to 3.6 V
Dn to LE; see Fig. 11
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
1.6
4.0
2.5
1.7
1.7
-
-
-
-
-
-
-
-
4.0
2.5
1.7
1.7
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
Dn to LE; see Fig. 11
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V
3.0
1.9
1.5
1.4
-
-
-
-
-
-
-
-
3.0
1.9
1.5
1.4
-
-
-
-
ns
ns
ns
ns
VCC = 3.0 V to 3.6 V
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
7 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tsk(0)
CPD
output skew time
VCC = 3.0 V to 3.6 V
[3]
[4]
-
-
1.0
-
1.5
ns
power dissipation per latch; VI = GND to VCC
capacitance
VCC = 1.65 V to 1.95 V
-
-
-
7.1
-
-
-
-
-
-
-
-
-
pF
pF
pF
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
10.3
13.2
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL
ten is the same as tPZL and tPZH
tdis is the same as tPLZ and tPHZ
.
.
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
Σ(CL × VCC 2 × fo) = sum of the outputs
10.1. Waveforms and test circuit
V
I
V
Dn input
M
GND
t
t
PLH
PHL
V
OH
V
Qn output
M
mna811
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 8. Input (Dn) to output (Qn) propagation delays
1/f
max
V
I
LE input
V
M
GND
t
W
t
t
PLH
PHL
V
OH
V
Qn output
M
mna812
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 9. Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays
©
74LVC573A
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
8 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
V
I
OE input
V
M
t
GND
t
PLZ
PZL
V
CC
Qn output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
Qn output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna813
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 10. 3-state enable and disable times
V
I
V
Dn input
M
GND
t
t
h
h
t
t
su
su
V
I
LE input
V
M
GND
mna814
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig. 11. Data set-up and hold times for the Dn input to the LE input
Table 8. Measurement points
Supply voltage
VCC
Input
VI
Output
VM
VM
VX
VY
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
0.5 × VCC
0.5 × VCC
0.5 × VCC
1.5 V
0.5 × VCC
0.5 × VCC
0.5 × VCC
1.5 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.15 V
VOL + 0.3 V
VOL + 0.3 V
VOH - 0.15 V
VOH - 0.15 V
VOH - 0.15 V
VOH - 0.3 V
VOH - 0.3 V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
1.5 V
1.5 V
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
9 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9. Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 12. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2 × VCC
2 × VCC
2 × VCC
2 × VCC
2 × VCC
tPHZ, tPZH
GND
1.2 V
VCC
VCC
VCC
2.7 V
2.7 V
≤ 2 ns
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
30 pF
30 pF
30 pF
50 pF
50 pF
1 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
open
GND
open
GND
open
GND
3.0 V to 3.6 V
open
GND
©
74LVC573A
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
10 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
11. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25 0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig. 13. Package outline SOT163-1 (SO20)
©
74LVC573A
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
11 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig. 14. Package outline SOT360-1 (TSSOP20)
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
12 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
SOT764-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
terminal 1
index area
e
C
1
v
w
C A
C
B
y
y
e
b
C
1
2
9
L
1
10
E
e
h
20
11
19
12
X
D
h
0
2.5
5 mm
scale
Dimensions (mm are the original dimensions)
(1) (1)
(1)
Unit
A
A
b
c
D
D
h
E
E
e
e
1
L
v
w
y
y
1
1
h
max 1.00 0.05 0.30
4.6 3.15 2.6 1.15
0.5
nom
min
mm
0.90 0.02 0.25 0.2 4.5 3.00 2.5 1.00 0.5 3.5 0.4 0.1 0.05 0.05 0.1
0.80 0.00 0.18 4.4 2.85 2.4 0.85 0.3
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot764-1_po
Issue date
References
Outline
version
European
projection
IEC
- - -
JEDEC
JEITA
- - -
03-01-27
14-12-12
SOT764-1
MO-241
Fig. 15. Package outline SOT764-1 (DHVQFN20)
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
13 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
12. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
CMOS
DUT
ESD
HBM
MM
Charged Device Model
Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
74LVC573A v.8
Modifications:
Release date
20210827
Data sheet status
Change notice Supersedes
- 74LVC573A v.7
Product data sheet
•
•
Section 1 and Section 2 updated.
Type number 74LVC573ADB (SOT339-1/SSOP20) removed.
74LVC573A v.7
Modifications:
20200330
Product data sheet 74LVC573A v.6
Table 4: Derating values for Ptot total power dissipation updated.
20180926 Product data sheet 74LVC573A v.5
-
•
74LVC573A v.6
Modifications:
-
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number 74LVC573ABX (SOT1045-2) removed.
Fig. 15: Package outline drawing SOT764-1 updated
74LVC573A v.5
Modifications:
20130219
Product data sheet
Product data sheet
-
74LVC573A v.4
•
74LVC573ABX added.
74LVC573A v.4
Modifications:
20121129
-
74LVC573A v.3
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage
ranges.
74LVC573A v.3
74LVC573A v.2
74LVC573A v.1
20031003
20030526
19980729
Product specification
Product specification
Product specification
-
-
-
74LVC573A v.2
74LVC573A v.1
-
©
74LVC573A
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
14 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
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Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
15 / 16
Nexperia
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................4
6. Functional description................................................. 4
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 8
11. Package outline........................................................ 11
12. Abbreviations............................................................14
13. Revision history........................................................14
14. Legal information......................................................15
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 27 August 2021
©
74LVC573A
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 8 — 27 August 2021
16 / 16
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