74LVC1T45GS [NEXPERIA]
Dual supply translating transceiver; 3-stateProduction;
| 型号： | 74LVC1T45GS |
| 厂家： | 
Nexperia |
| 描述： | Dual supply translating transceiver; 3-stateProduction |
| 文件： | 总30页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Rev. 9 — 10 February 2022
Product data sheet
1. General description
The 74LVC1T45; 74LVCH1T45 are single bit, dual supply transceivers with 3-state outputs
that enable bidirectional level translation. They feature two 1-bit input-output ports (A and B), a
direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can
be supplied at any voltage between 1.2 V and 5.5 V making the device suitable for translating
between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins A and DIR
are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission
from A to B and a LOW on DIR allows transmission from B to A.
The devices are fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the device
when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level,
both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH1T45 holds unused or floating data inputs at a valid logic
level.
2. Features and benefits
•
Wide supply voltage range:
•
•
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
•
•
High noise immunity
Maximum data rates:
•
•
•
•
•
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
•
•
•
•
•
•
•
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
±24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 16 μA maximum ICC
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
•
•
•
•
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
•
ESD protection:
•
•
HBM JESD22-A114F Class 3A exceeds 4000 V
CDM JESD22-C101E exceeds 1000 V
•
•
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1T45GW
74LVCH1T45GW
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
TSSOP6
plastic thin shrink small outline package; 6 leads; SOT363-2
body width 1.25 mm
74LVC1T45GM
74LVCH1T45GM
XSON6
XSON6
XSON6
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
SOT886
SOT1115
SOT1202
74LVC1T45GN
74LVCH1T45GN
extremely thin small outline package; no leads;
6 terminals; body 0.9 × 1.0 × 0.35 mm
74LVC1T45GS
74LVCH1T45GS
extremely thin small outline package; no leads;
6 terminals; body 1.0 × 1.0 × 0.35 mm
4. Marking
Table 2. Marking
Type number
Marking code[1]
74LVC1T45GW
74LVCH1T45GW
74LVC1T45GM
74LVCH1T45GM
74LVC1T45GN
74LVCH1T45GN
74LVC1T45GS
74LVCH1T45GS
V5
X5
V5
X5
V5
X5
V5
X5
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
5
DIR
DIR
3
A
A
4
B
B
V
V
CC(B)
CC(A)
V
V
CC(A)
CC(B)
001aag886
001aag885
Fig. 1. Logic symbol
Fig. 2. Logic diagram
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
2 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
6. Pinning information
6.1. Pinning
74LVC1T45
74LVCH1T45
74LVC1T45
74LVCH1T45
74LVC1T45
74LVCH1T45
V
1
2
3
6
5
4
V
CC(A)
GND
CC(B)
1
2
3
6
5
4
V
V
CC(B)
V
1
2
3
6
5
4
V
CC(B)
CC(A)
GND
CC(A)
GND
DIR
B
DIR
B
DIR
B
A
A
A
001aaj992
001aaj993
Transparent top view
Transparent top view
001aaj991
Fig. 3. Pin configuration SOT363-2 Fig. 4. Pin configuration SOT886
Fig. 5. Pin configuration SOT1115
and SOT1202 (XSON6)
(TSSOP6)
(XSON6)
6.2. Pin description
Table 3. Pin description
Symbol
Pin
1
Description
VCC(A)
GND
A
supply voltage port A and DIR
ground (0 V)
2
3
data input or output
data input or output
direction control
B
4
DIR
VCC(B)
5
6
supply voltage port B
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
Supply voltage
VCC(A), VCC(B)
1.2 V to 5.5 V
1.2 V to 5.5 V
GND [2]
Input
DIR
L
Input/output [1]
A
B
A = B
input
Z
input
B = A
Z
H
X
[1] The input circuit of the data I/O is always active.
[2] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
3 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-50
-0.5
-50
-0.5
-0.5
-
Max
+6.5
+6.5
-
Unit
V
VCC(A) supply voltage A
VCC(B) supply voltage B
V
IIK
input clamping current
VI < 0 V
mA
V
VI
input voltage
[1]
+6.5
-
IOK
VO
output clamping current
output voltage
VO < 0 V
mA
Active mode
[1] [2] [3]
[1]
VCCO + 0.5 V
Suspend or 3-state mode
VO = 0 V to VCCO
ICC(A) or ICC(B)
+6.5
±50
100
-
V
IO
output current
[2]
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-100
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[4]
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 6.5 V.
[4] For SOT363-2 (TSSOP6) package: Ptot derates linearly with 3.7 mW/K above 83 °C.
For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT1115 (XSON6) package: Ptot derates linearly with 3.2 mW/K above 71 °C.
For SOT1202 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
Min
Max
5.5
5.5
5.5
VCCO
5.5
+125
20
Unit
V
VCC(A) supply voltage A
VCC(B) supply voltage B
1.2
1.2
V
VI
input voltage
0
0
0
-40
-
V
VO
output voltage
Active mode
[1]
[2]
V
Suspend or 3-state mode
V
Tamb
ambient temperature
°C
Δt/ΔV
input transition rise and fall rate
VCCI = 1.2 V
ns/V
ns/V
ns/V
ns/V
ns/V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3 V to 3.6 V
VCCI = 4.5 V to 5.5 V
-
20
-
20
-
10
-
5
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
4 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
10. Static characteristics
Table 7. Typical static characteristics at Tamb = 25 °C
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). [1] [2]
Symbol Parameter
Conditions
Min
Typ
1.09
0.07
-
Max Unit
VOH
VOL
II
HIGH-level output voltage VI = VIH or VIL; IO = -3 mA; VCCO = 1.2 V
LOW-level output voltage VI = VIH or VIL; IO = 3 mA; VCCO = 1.2 V
-
-
-
-
-
V
V
input leakage current
DIR input; VI = 0 V to 5.5 V;
VCCI = 1.2 V to 5.5 V
±1
μA
IBHL
bus hold LOW current
bus hold HIGH current
A or B port; VI = 0.42 V; VCCI = 1.2 V
A or B port; VI = 0.78 V; VCCI = 1.2 V
A or B port; VCCI = 1.2 V
-
-
-
19
-19
19
-
-
-
μA
μA
μA
IBHH
IBHLO
bus hold LOW overdrive
current
[3]
[3]
IBHHO
IOZ
bus hold HIGH overdrive
current
A or B port; VCCI = 1.2 V
-
-
-
-
-
-
-19
-
-
±1
±1
±1
-
μA
μA
μA
μA
pF
pF
OFF-state output current
A or B port; VO = 0 V or VCCO
;
VCCO = 1.2 V to 5.5 V
IOFF
power-off leakage current A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V;
VCC(B) = 1.2 V to 5.5 V
-
B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V;
VCC(A) = 1.2 V to 5.5 V
-
CI
input capacitance
DIR input; VI = 0 V or 3.3 V;
VCC(A) = VCC(B) = 3.3 V
2.2
6.0
CI/O
input/output capacitance
A and B port; suspend mode;
-
VO = 3.3 V or 0 V; VCC(A) = VCC(B) = 3.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V). [1] [2]
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Max
Min
Max
VIH
HIGH-level
data input
input voltage
VCCI = 1.2 V
0.8VCCI
0.65VCCI
1.7
-
-
-
-
-
0.8VCCI
0.65VCCI
1.7
-
-
-
-
-
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
2.0
2.0
0.7VCCI
0.7VCCI
DIR input
VCCI = 1.2 V
0.8VCC(A)
0.65VCC(A)
1.7
-
-
-
-
-
0.8VCC(A)
0.65VCC(A)
1.7
-
-
-
-
-
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
2.0
2.0
0.7VCC(A)
0.7VCC(A)
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
5 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Max
Min
Max
VIL
LOW-level
data input
input voltage
VCCI = 1.2 V
-
-
-
-
-
0.2VCCI
0.35VCCI
0.7
-
-
-
-
-
0.2VCCI
0.35VCCI
0.7
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
0.8
0.8
0.3VCCI
0.3VCCI
DIR input
VCCI = 1.2 V
-
-
-
-
-
0.2VCC(A)
0.35VCC(A)
0.7
-
-
-
-
-
0.2VCC(A)
0.35VCC(A)
0.7
V
V
V
V
V
VCCI = 1.4 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VCCI = 3.0 V to 3.6 V
VCCI = 4.5 V to 5.5 V
0.8
0.8
0.3VCC(A)
0.3VCC(A)
VOH
HIGH-level
VI = VIH
output voltage
IO = -100 μA; VCCO = 1.2 V to 4.5 V
IO = -6 mA; VCCO = 1.4 V
VCCO - 0.1
1.0
-
-
-
-
-
-
VCCO - 0.1
1.0
-
-
-
-
-
-
V
V
V
V
V
V
IO = -8 mA; VCCO = 1.65 V
IO = -12 mA; VCCO = 2.3 V
IO = -24 mA; VCCO = 3.0 V
IO = -32 mA; VCCO = 4.5 V
1.2
1.2
1.9
1.9
2.4
2.4
3.8
3.8
VOL
LOW-level
VI = VIL
output voltage
IO = 100 μA; VCCO = 1.2 V to 4.5 V
IO = 6 mA; VCCO = 1.4 V
-
-
-
-
-
-
-
0.1
0.3
-
-
-
-
-
-
-
0.1
0.3
V
V
IO = 8 mA; VCCO = 1.65 V
IO = 12 mA; VCCO = 2.3 V
IO = 24 mA; VCCO = 3.0 V
IO = 32 mA; VCCO = 4.5 V
0.45
0.3
0.45
0.3
V
V
0.55
0.55
±2
0.55
0.55
±10
V
V
II
input leakage DIR input; VI = 0 V to 5.5 V;
current VCCI = 1.2 V to 5.5 V
μA
IBHL
bus hold LOW A or B port
current
VI = 0.49 V; VCCI = 1.4 V
15
25
-
-
-
-
-
10
20
-
-
-
-
-
μA
μA
μA
μA
μA
VI = 0.58 V; VCCI = 1.65 V
VI = 0.70 V; VCCI = 2.3 V
VI = 0.80 V; VCCI = 3.0 V
VI = 1.35 V; VCCI = 4.5 V
45
45
100
100
80
100
IBHH
bus hold HIGH A or B port
current
VI = 0.91 V; VCCI = 1.4 V
VI = 1.07 V; VCCI = 1.65 V
VI = 1.60 V; VCCI = 2.3 V
VI = 2.00 V; VCCI = 3.0 V
VI = 3.15 V; VCCI = 4.5 V
-15
-25
-
-
-
-
-
-10
-20
-
-
-
-
-
μA
μA
μA
μA
μA
-45
-45
-100
-100
-80
-100
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
6 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Max
Min
Max
IBHLO
bus hold LOW A or B port
overdrive
current
[3]
VCCI = 1.6 V
125
200
300
500
900
-
-
-
-
-
125
200
300
500
900
-
-
-
-
-
μA
μA
μA
μA
μA
VCCI = 1.95 V
VCCI = 2.7 V
VCCI = 3.6 V
VCCI = 5.5 V
IBHHO
bus hold HIGH A or B port
overdrive
current
[3]
VCCI = 1.6 V
-125
-200
-300
-500
-900
-
-
-
-125
-200
-300
-500
-900
-
-
μA
μA
μA
μA
μA
μA
VCCI = 1.95 V
VCCI = 2.7 V
-
-
-
VCCI = 3.6 V
-
-
-
VCCI = 5.5 V
-
IOZ
OFF-state
A or B port; VO = 0 V or VCCO
;
±2
±10
output current VCCO = 1.2 V to 5.5 V
IOFF
power-off
leakage
current
A port; VI or VO = 0 V to 5.5 V;
VCC(A) = 0 V; VCC(B) = 1.2 V to 5.5 V
-
-
±2
±2
-
-
±10
±10
μA
μA
B port; VI or VO = 0 V to 5.5 V;
VCC(B) = 0 V; VCC(A) = 1.2 V to 5.5 V
ICC
supply current A port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(A), VCC(B) = 1.65 V to 5.5 V
VCC(A) = 5.5 V; VCC(B) = 0 V
-
-
8
3
2
-
-
-
8
3
2
-
μA
μA
μA
μA
-
-
VCC(A) = 0 V; VCC(B) = 5.5 V
-2
-2
B port; VI = 0 V or VCCI; IO = 0 A
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(A), VCC(B) = 1.65 V to 5.5 V
VCC(B) = 5.5 V; VCC(A) = 0 V
-
-
8
3
2
-
-
-
8
3
2
-
μA
μA
μA
μA
-
-
VCC(B) = 0 V; VCC(A) = 5.5 V
-2
-2
A plus B port (ICC(A) + ICC(B)); IO = 0 A;
VI = 0 V or VCCI
VCC(A), VCC(B) = 1.2 V to 5.5 V
VCC(A), VCC(B) = 1.65 V to 5.5 V
-
-
16
4
-
-
16
4
μA
μA
ΔICC
additional
VCC(A), VCC(B) = 3.0 V to 5.5 V
supply current
A port; A port at VCC(A) - 0.6 V;
DIR at VCC(A); B port = open
[4]
[4]
-
-
50
50
-
-
75
75
μA
μA
DIR input; DIR at VCC(A) - 0.6 V;
A port at VCC(A) or GND;
B port = open
B port; B port at VCC(B) - 0.6 V;
DIR at GND; A port = open
-
50
-
75
μA
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
[3] To guarantee the node switches, an external driver must source/sink at least IBHLO/IBHHO when the input is in the range VIL to VIH.
[4] For non bus hold parts only (74LVC1T45).
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
7 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
11. Dynamic characteristics
Table 9. Typical dynamic characteristics at VCC(A) = 1.2 V and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.
Symbol Parameter
Conditions
VCC(B)
1.8 V
Unit
1.2 V
10.6
1.5 V
8.1
2.5 V
5.8
3.3 V
5.3
5.0 V
5.1
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
7.0
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B to A
10.6
9.5
8.5
8.3
8.2
HIGH to LOW
propagation delay
A to B
10.1
7.1
6.0
5.3
5.2
5.4
B to A
10.1
8.6
8.1
7.8
7.6
7.6
HIGH to OFF-state
propagation delay
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
9.4
9.4
9.4
9.4
9.4
9.4
12.0
9.4
9.0
7.8
8.4
7.9
LOW to OFF-state
propagation delay
7.1
7.1
7.1
7.1
7.1
7.1
9.5
7.8
7.7
6.9
7.6
7.0
OFF-state to HIGH
propagation delay
[1] 20.1
[1] 17.7
[1] 22.1
[1] 19.5
17.3
15.2
18.0
16.5
16.7
14.1
17.1
15.4
15.4
12.9
15.6
14.7
15.9
12.4
16.0
14.6
15.2
12.2
15.5
14.8
OFF-state to LOW
propagation delay
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4
Table 10. Typical dynamic characteristics at VCC(B) = 1.2 V and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for waveforms see Fig. 6 and Fig. 7.
Symbol Parameter
Conditions
VCC(A)
1.8 V
Unit
1.2 V
10.6
1.5 V
9.5
2.5 V
8.5
3.3 V
8.3
5.0 V
8.2
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
9.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
B to A
10.6
8.1
5.8
5.3
5.1
HIGH to LOW
propagation delay
A to B
10.1
8.6
8.1
7.8
7.6
7.6
B to A
10.1
7.1
6.0
5.3
5.2
5.4
HIGH to OFF-state
propagation delay
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
DIR to A
DIR to B
9.4
6.5
5.7
4.1
4.1
3.0
12.0
6.1
5.4
4.6
4.3
4.0
LOW to OFF-state
propagation delay
7.1
4.9
4.5
3.2
3.4
2.5
9.5
7.3
6.6
5.9
5.7
5.6
OFF-state to HIGH
propagation delay
[1] 20.1
[1] 17.7
[1] 22.1
[1] 19.5
15.4
14.4
13.2
15.1
13.6
13.5
11.4
13.8
11.7
11.7
9.9
11.0
11.7
9.5
10.7
10.7
9.4
OFF-state to LOW
propagation delay
11.9
11.7
10.6
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
8 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Table 11. Typical power dissipation capacitance at VCC(A) = VCC(B) and Tamb = 25 °C
Voltages are referenced to GND (ground = 0 V). [1][2]
Symbol Parameter
Conditions
VCC(A) and VCC(B)
Unit
1.8 V
2.5 V
3.3 V
5.5 V
CPD
power dissipation
capacitance
A port: (direction A to B);
B port: (direction B to A)
2
3
3
4
pF
pF
A port: (direction B to A);
B port: (direction A to B)
15
16
16
18
[1] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of the outputs.
[2] fi = 10 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.
Table 12. Dynamic characteristics for temperature range -40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for wave forms see Fig. 6 and Fig. 7.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
± 0.1 V
± 0.15 V
± 0.2 V
± 0.3 V
± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.8 21.3 2.4 17.6 2.0 13.5 1.7 11.8 1.6 10.5 ns
2.8 21.3 2.6 19.1 2.3 14.9 2.3 12.4 2.2 12.0 ns
2.6 19.3 2.2 15.3 1.8 11.8 1.7 10.9 1.7 10.8 ns
2.6 19.3 2.4 17.3 2.3 13.2 2.2 11.3 2.3 11.0 ns
3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 3.0 18.7 ns
3.5 24.8 3.5 23.6 3.0 11.0 3.3 11.3 2.8 10.3 ns
2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 2.4 11.4 ns
HIGH to LOW
propagation delay
HIGH to OFF-state DIR to A
propagation delay
DIR to B
LOW to OFF-state DIR to A
propagation delay
DIR to B
2.8 18.3 3.0 17.2 2.5
9.4
3.0 10.1 2.5
9.4 ns
21.4 ns
21.9 ns
21.3 ns
29.5 ns
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
39.6
32.7
44.1
38.0
-
-
-
-
36.3
29.0
40.9
34.0
-
-
-
-
24.3
24.9
24.2
30.5
-
-
-
-
22.5
23.2
22.6
29.6
-
-
-
-
DIR to B
OFF-state to LOW DIR to A
propagation delay
DIR to B
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
9 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
± 0.1 V
± 0.15 V
± 0.2 V
± 0.3 V
± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.65 V to 1.95 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.6 19.1 2.2 17.7 2.2
2.4 17.6 2.2 17.7 2.3 16.0 2.1 15.5 1.9 15.1 ns
2.4 17.3 2.0 14.3 1.6 8.5 1.8 7.1 1.7 7.0 ns
9.3
1.7
7.2
1.4
6.8 ns
HIGH to LOW
propagation delay
2.2 15.3 2.0 14.3 2.1 12.9 2.0 12.6 1.8 12.2 ns
2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 2.9 17.1 ns
HIGH to OFF-state DIR to A
propagation delay
DIR to B
3.2 24.1 3.2 21.9 2.7 11.5 3.0 10.3 2.5
8.2 ns
LOW to OFF-state DIR to A
propagation delay
2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 2.4 10.5 ns
DIR to B
2.5 17.6 2.6 16.0 2.2
9.2
2.7
8.4
2.4
6.4 ns
21.8 ns
17.3 ns
20.4 ns
24.1 ns
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
35.2
29.6
39.4
34.4
-
-
-
-
33.7
28.2
36.2
31.4
-
-
-
-
25.2
19.8
24.4
25.6
-
-
-
-
23.9
17.7
22.9
24.2
-
-
-
-
DIR to B
OFF-state to LOW DIR to A
propagation delay
DIR to B
VCC(A) = 2.3 V to 2.7 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.3 17.9 2.3 16.0 1.5
2.0 13.5 2.2 9.3 1.5
2.3 15.8 2.1 12.9 1.4
8.5
8.5
7.5
7.5
8.1
1.3
1.4
1.3
1.3
2.1
6.2
8.0
1.1
1.0
0.9
0.9
2.1
2.3
1.7
1.8
-
4.8 ns
7.5 ns
4.6 ns
6.2 ns
8.1 ns
6.9 ns
5.8 ns
5.3 ns
12.8 ns
10.6 ns
13.1 ns
12.7 ns
HIGH to LOW
propagation delay
5.4
1.8 11.8 1.9
2.1 8.1 2.1
8.5
8.1
1.4
2.1
7.0
HIGH to OFF-state DIR to A
propagation delay
8.1
DIR to B
3.0 22.5 3.0 21.4 2.5 11.0 2.8
9.3
LOW to OFF-state DIR to A
propagation delay
1.7
5.8
1.7
5.8
1.7
5.8
9.0
1.7
5.8
DIR to B
2.3 14.6 2.5 13.2 2.0
2.5
8.4
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
28.1
23.7
34.3
23.9
-
-
-
-
22.5
21.8
29.9
21.0
-
-
-
-
17.5
14.3
18.5
15.6
-
-
-
-
16.4
12.0
16.3
13.5
DIR to B
-
OFF-state to LOW DIR to A
propagation delay
-
DIR to B
-
VCC(A) = 3.0 V to 3.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.3 17.1 2.1 15.5 1.4
1.7 11.8 1.7 7.2 1.3
2.2 15.6 2.0 12.6 1.3
8.0
6.2
7.0
5.4
7.3
0.8
0.7
0.8
0.8
2.3
5.6
5.6
0.7
0.6
0.7
0.7
2.7
2.2
2.0
1.7
-
4.4 ns
5.4 ns
4.0 ns
4.5 ns
7.3 ns
6.3 ns
5.6 ns
4.9 ns
10.3 ns
10.0 ns
10.8 ns
11.3 ns
HIGH to LOW
propagation delay
5.0
1.7 10.9 1.8
2.3 7.3 2.3
7.1
7.3
1.3
2.3
5.0
HIGH to OFF-state DIR to A
propagation delay
7.3
DIR to B
2.9 18.0 2.9 16.5 2.3 10.1 2.7
8.6
LOW to OFF-state DIR to A
propagation delay
2.0
5.6
2.0
5.6
2.0
5.6
7.8
2.0
5.6
DIR to B
2.3 13.6 2.4 12.5 1.9
2.3
7.1
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
25.4
22.7
28.9
22.9
-
-
-
-
19.7
21.1
23.6
19.9
-
-
-
-
14.0
13.6
15.5
14.3
-
-
-
-
12.7
11.2
13.6
12.3
DIR to B
-
OFF-state to LOW DIR to A
propagation delay
-
DIR to B
-
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
10 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
± 0.1 V
± 0.15 V
± 0.2 V
± 0.3 V
± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 4.5 V to 5.5 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.2 16.6 1.9 15.1 1.0
1.6 10.5 1.4 6.8 1.0
2.3 15.3 1.8 12.2 1.0
7.5
4.8
0.7
0.7
0.7
0.7
1.7
2.7
1.0
2.3
-
5.4
4.4
4.5
4.0
5.4
8.0
3.7
7.0
11.4
9.1
12.0
9.9
0.5
0.5
0.5
0.5
1.7
2.5
0.9
1.8
-
3.9 ns
3.9 ns
3.5 ns
3.5 ns
5.4 ns
5.7 ns
3.7 ns
4.5 ns
8.4 ns
7.6 ns
9.2 ns
8.9 ns
HIGH to LOW
propagation delay
6.2
1.7 10.8 1.7
1.7 5.4 1.7
7.0
5.4
0.9
1.7
4.6
HIGH to OFF-state DIR to A
propagation delay
5.4
DIR to B
2.9 17.3 2.9 16.1 2.3
1.4 3.7 1.4 3.7 1.3
2.3 13.1 2.4 12.1 1.9
9.7
LOW to OFF-state DIR to A
propagation delay
3.7
DIR to B
7.4
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
23.6
20.3
28.1
20.7
-
-
-
-
18.9
18.8
23.1
17.6
-
-
-
-
12.2
11.2
14.3
11.6
DIR to B
-
-
OFF-state to LOW DIR to A
propagation delay
-
-
DIR to B
-
-
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4
Table 13. Dynamic characteristics for temperature range -40 °C to +125 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8; for wave forms see Fig. 6 and Fig. 7.
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V
± 0.1 V
1.8 V
± 0.15 V
2.5 V
± 0.2 V
3.3 V
± 0.3 V
5.0 V
± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.4 V to 1.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.5 23.5 2.1 19.4 1.8 14.9 1.5 13.0 1.4 11.6 ns
2.5 23.5 2.3 21.1 2.0 16.4 2.0 13.7 1.9 13.2 ns
2.3 21.3 1.9 16.9 1.6 13.0 1.5 12.0 1.5 11.9 ns
2.3 21.3 2.1 19.1 2.0 14.6 1.9 12.5 2.0 12.1 ns
2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 2.7 20.6 ns
3.1 27.3 3.1 26.0 2.7 12.1 2.9 12.5 2.5 11.4 ns
2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 2.1 12.6 ns
2.5 20.2 2.7 19.0 2.2 10.4 2.7 11.2 2.2 10.4 ns
HIGH to LOW
propagation delay
HIGH to OFF-state DIR to A
propagation delay
DIR to B
LOW to OFF-state DIR to A
propagation delay
DIR to B
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
43.7
36.1
48.6
41.9
-
-
-
-
40.1
32.0
45.1
37.5
-
-
-
-
26.8
27.5
26.7
33.6
-
-
-
-
24.9
25.6
25.0
32.6
-
-
-
-
23.6 ns
24.2 ns
23.5 ns
32.5 ns
DIR to B
OFF-state to LOW DIR to A
propagation delay
DIR to B
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
11 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
± 0.1 V
± 0.15 V
± 0.2 V
± 0.3 V
± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.65 V to 1.95 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.3 21.1 1.9 19.5 1.9 10.3 1.5
2.1 19.4 1.9 19.5 2.0 17.6 1.8 17.1 1.7 16.7 ns
2.1 19.1 1.8 15.8 1.4 9.4 1.6 7.9 1.5 7.7 ns
8.0
1.2
7.5 ns
HIGH to LOW
propagation delay
1.9 16.9 1.8 15.8 1.8 14.2 1.8 13.9 1.6 13.5 ns
2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 2.6 18.9 ns
HIGH to OFF-state DIR to A
propagation delay
DIR to B
2.8 26.6 2.8 24.1 2.4 12.7 2.7 11.4 2.2
9.1 ns
LOW to OFF-state DIR to A
propagation delay
2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 2.1 11.6 ns
DIR to B
2.2 19.4 2.3 17.6 1.9 10.2 2.4
9.3
2.1
7.4 ns
24.1 ns
19.1 ns
22.6 ns
26.6 ns
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
38.8
32.7
43.5
38.0
-
-
-
-
37.1
31.1
39.9
34.7
-
-
-
-
27.8
21.9
26.9
28.3
-
-
-
-
26.4
19.6
25.3
26.8
-
-
-
-
DIR to B
OFF-state to LOW DIR to A
propagation delay
DIR to B
VCC(A) = 2.3 V to 2.7 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.0 19.7 2.0 17.6 1.3
1.8 14.9 1.9 10.3 1.3
2.0 17.4 1.8 14.2 1.2
9.4
9.4
8.3
8.3
9.0
1.1
1.2
1.1
1.1
1.8
6.9
8.8
6.0
7.7
9.0
0.9
0.9
0.8
0.8
1.8
5.3 ns
8.3 ns
5.1 ns
6.9 ns
9.0 ns
7.6 ns
6.4 ns
5.9 ns
14.2 ns
11.7 ns
14.5 ns
14.1 ns
HIGH to LOW
propagation delay
1.6 13.0 1.7
1.8 9.0 1.8
9.4
9.0
1.2
1.8
HIGH to OFF-state DIR to A
propagation delay
DIR to B
2.7 24.8 2.7 23.6 2.2 12.1 2.5 10.3 2.0
LOW to OFF-state DIR to A
propagation delay
1.5
6.4
1.5
6.4
1.5
6.4
9.9
1.5
6.4
9.3
1.5
DIR to B
2.0 16.1 2.2 14.6 1.8
2.2
1.6
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
31.0
26.1
37.8
26.4
-
-
-
-
24.9
24.0
33.0
23.2
-
-
-
-
19.3
15.8
20.4
17.3
-
-
-
-
18.1
13.3
18.0
15.0
-
-
-
-
DIR to B
OFF-state to LOW DIR to A
propagation delay
DIR to B
VCC(A) = 3.0 V to 3.6 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
2.0 18.9 1.8 17.1 1.2
1.5 13.0 1.5 8.0 1.1
1.9 17.2 1.8 13.9 1.1
8.8
6.9
7.7
6.0
8.1
0.7
0.6
0.7
0.7
2.0
6.2
6.2
0.6
0.5
0.6
0.6
2.4
1.9
1.8
1.5
-
4.9 ns
6.0 ns
4.4 ns
5.0 ns
8.1 ns
7.0 ns
6.2 ns
5.4 ns
11.4 ns
11.1 ns
12.0 ns
12.5 ns
HIGH to LOW
propagation delay
5.5
1.5 12.0 1.6
2.0 8.1 2.0
7.9
8.1
1.1
2.0
5.5
HIGH to OFF-state DIR to A
propagation delay
8.1
DIR to B
2.6 19.8 2.6 18.2 2.0 11.2 2.4
9.5
LOW to OFF-state DIR to A
propagation delay
1.8
6.2
1.8
6.2
1.8
6.2
8.6
1.8
6.2
DIR to B
2.0 15.0 2.1 13.8 1.7
2.0
7.9
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
28.0
25.1
31.8
25.3
-
-
-
-
21.8
23.3
26.1
22.0
-
-
-
-
15.5
15.0
17.2
15.8
-
-
-
-
14.1
12.4
15.0
13.6
DIR to B
-
OFF-state to LOW DIR to A
propagation delay
-
DIR to B
-
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
12 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Symbol Parameter
Conditions
VCC(B)
Unit
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
± 0.1 V
± 0.15 V
± 0.2 V
± 0.3 V
± 0.5 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 4.5 V to 5.5 V
tPLH
tPHL
tPHZ
tPLZ
tPZH
tPZL
LOW to HIGH
propagation delay
A to B
B to A
A to B
B to A
1.9 18.3 1.7 16.7 0.9
1.4 11.6 1.2 7.5 0.9
2.0 16.9 1.6 13.5 0.9
8.3
5.3
6.9
5.1
6.0
0.6
0.6
0.6
0.6
1.5
6.0
4.9
0.4
0.4
0.4
0.4
1.5
2.2
0.8
1.6
-
4.3 ns
4.3 ns
3.9 ns
3.9 ns
6.0 ns
6.3 ns
4.1 ns
5.0 ns
9.3 ns
8.4 ns
10.2 ns
9.9 ns
HIGH to LOW
propagation delay
5.0
1.5 11.9 1.5
1.5 6.0 1.5
7.7
6.0
0.8
1.5
4.4
HIGH to OFF-state DIR to A
propagation delay
6.0
DIR to B
2.6 19.1 2.6 17.8 2.0 10.7 2.4
8.8
LOW to OFF-state DIR to A
propagation delay
1.2
4.1
1.2
4.1
1.1
4.1
8.2
0.9
4.1
DIR to B
2.0 14.5 2.1 13.4 1.7
2.0
7.7
OFF-state to HIGH DIR to A
propagation delay
[1]
[1]
[1]
[1]
-
-
-
-
26.1
22.4
31.0
22.9
-
-
-
-
20.9
20.8
25.5
19.5
-
-
-
-
13.5
12.4
15.8
12.9
-
-
-
-
12.6
10.1
13.2
11.0
DIR to B
-
OFF-state to LOW DIR to A
propagation delay
-
DIR to B
-
[1] tPZH and tPZL are calculated values using the formula shown in Section 13.4
11.1. Waveforms and test circuit
V
I
V
A, B input
M
GND
t
t
PLH
PHL
V
OH
B, A output
V
M
001aae967
V
OL
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. The data input (A, B) to output (B, A) propagation delay times
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
13 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
V
I
DIR input
V
M
t
GND
t
PLZ
PZL
V
CCO
output
V
LOW-to-OFF
OFF-to-LOW
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
V
M
OFF-to-HIGH
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae968
Measurement points are given in Table 14.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 7. Enable and disable times
Table 14. Measurement points
Supply voltage
VCC(A), VCC(B)
1.2 V to 1.6 V
1.65 V to 2.7 V
3.0 V to 5.5 V
Input [1]
Output [2]
VM
VM
VX
VY
0.5VCCI
0.5VCCI
0.5VCCI
0.5VCCO
0.5VCCO
0.5VCCO
VOL + 0.1 V
VOH - 0.1 V
VOH - 0.15 V
VOH - 0.3 V
VOL + 0.15 V
VOL + 0.3 V
[1] VCCI is the supply voltage associated with the data input port.
[2] VCCO is the supply voltage associated with the output port.
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
14 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 15.
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance;
VEXT = External voltage for measuring switching times.
Fig. 8. Test circuit for measuring switching times
Table 15. Test data
Supply voltage
VCC(A), VCC(B)
1.2 V to 5.5 V
Input
VI [1]
VCCI
Load
CL
VEXT
Δt/ΔV [2]
RL
2 kΩ
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ [3]
≤ 1.0 ns/V
15 pF
GND
2VCCO
[1] VCCI is the supply voltage associated with the data input port.
[2] dV/dt ≥ 1.0 V/ns
[3] VCCO is the supply voltage associated with the output port.
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
15 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
12. Typical propagation delay characteristics
001aai907
001aai908
14
PHL
(ns)
12
14
PLH
(ns)
12
t
t
(1)
(1)
10
8
10
8
(2)
(3)
(2)
(3)
(4)
(4)
(5)
(6)
6
6
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai909
001aai910
14
PHL
(ns)
12
14
PLH
(ns)
12
t
t
(1)
(1)
(2)
(3)
(4)
(2)
(3)
10
10
(5)
(6)
(4)
(5)
(6)
8
6
4
2
0
8
6
4
2
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 9. Typical propagation delay vs load capacitance; Tamb = 25 °C; VCC(A) = 1.2 V
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
16 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
001aai911
001aai912
14
14
PLH
(ns)
12
t
t
PHL
(ns)
12
(1)
10
8
10
8
(1)
(2)
(2)
(3)
6
6
(3)
(4)
(4)
(5)
(6)
4
4
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai913
001aai914
14
PHL
(ns)
12
14
PLH
(ns)
12
t
t
10
8
10
8
(1)
(1)
(2)
(3)
(4)
(2)
(3)
(4)
6
6
(5)
(6)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 10. Typical propagation delay vs load capacitance; Tamb = 25 °C; VCC(A) = 1.5 V
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
17 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
001aai915
001aai916
14
14
PLH
(ns)
12
t
t
PHL
(ns)
12
(1)
10
8
10
8
(1)
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai917
001aai918
14
PHL
(ns)
12
14
PLH
(ns)
12
t
t
10
8
10
8
(1)
(1)
(2)
(3)
(4)
(5)
(6)
6
6
(2)
(3)
(4)
(5)
(6)
4
4
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 11. Typical propagation delay vs load capacitance; Tamb = 25 °C; VCC(A) = 1.8 V
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
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18 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
001aai919
001aai920
14
14
PLH
(ns)
12
t
t
PHL
(ns)
12
(1)
10
8
10
8
(1)
(2)
(3)
(2)
(3)
6
6
(4)
(5)
(6)
4
4
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai921
001aai922
14
PHL
(ns)
12
14
PLH
(ns)
12
t
t
10
8
10
8
(1)
6
6
(1)
(2)
(3)
(2)
(3)
(4)
(5)
(6)
4
4
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 12. Typical propagation delay vs load capacitance; Tamb = 25 °C; VCC(A) = 2.5 V
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
19 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
001aai923
001aai924
14
14
PLH
(ns)
12
t
t
PHL
(ns)
12
10
8
10
8
(1)
(1)
(2)
(3)
(2)
(3)
6
6
4
4
(4)
(5)
(6)
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai925
001aai926
14
PHL
(ns)
12
14
PLH
(ns)
12
t
t
10
8
10
8
6
6
(1)
(1)
(2)
(3)
(2)
(3)
(4)
(5)
(6)
4
4
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 13. Typical propagation delay vs load capacitance; Tamb = 25 °C; VCC(A) = 3.3 V
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
20 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
001aai927
001aai928
14
14
PLH
(ns)
12
t
t
PHL
(ns)
12
10
8
10
8
(1)
(1)
(2)
(3)
(2)
(3)
6
6
4
4
(4)
(5)
(6)
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
a. HIGH to LOW propagation delay (A to B)
b. LOW to HIGH propagation delay (A to B)
001aai929
001aai930
14
PHL
(ns)
12
14
PLH
(ns)
12
t
t
10
8
10
8
6
6
(1)
(1)
(2)
(3)
(2)
(3)
4
4
(4)
(5)
(6)
(4)
(5)
(6)
2
2
0
0
0
5
10
15
20
25
30
(pF)
35
0
5
10
15
20
25
30
C (pF)
L
35
C
L
c. HIGH to LOW propagation delay (B to A)
d. LOW to HIGH propagation delay (B to A)
(1) VCC(B) = 1.2 V.
(2) VCC(B) = 1.5 V.
(3) VCC(B) = 1.8 V.
(4) VCC(B) = 2.5 V.
(5) VCC(B) = 3.3 V.
(6) VCC(B) = 5.0 V.
Fig. 14. Typical propagation delay vs load capacitance; Tamb = 25 °C; VCC(A) = 5.0 V
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
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21 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
13. Application information
13.1. Unidirectional logic level-shifting application
The circuit given in Fig. 15 is an example of the 74LVC1T45; 74LVCH1T45 being used in a
unidirectional logic level-shifting application.
74LVC1T45
74LVCH1T45
V
V
V
V
CC1
CC1
CC2
CC2
V
V
CC(B)
CC(A)
1
2
3
6
5
4
GND
A
DIR
B
system-1
system-2
001aaj994
Fig. 15. Unidirectional logic level-shifting application
Table 16. Description unidirectional logic level-shifting application
Pin
1
Name
VCC(A)
GND
A
Function Description
VCC1
GND
OUT
IN
supply voltage of system-1 (1.2 V to 5.5 V)
2
device GND
3
output level depends on VCC1 voltage
input threshold value depends on VCC2 voltage
the GND (LOW level) determines B port to A port direction
supply voltage of system-2 (1.2 V to 5.5 V)
4
B
5
DIR
DIR
6
VCC(B)
VCC2
13.2. Bidirectional logic level-shifting application
Fig. 16 shows the 74LVC1T45; 74LVCH1T45 being used in a bidirectional logic level-shifting
application. Since the device does not have an output enable pin, the system designer should take
precautions to avoid bus contention between system-1 and system-2 when changing directions.
74LVC1T45
74LVCH1T45
V
V
V
V
CC1
CC1
CC2
CC2
V
V
CC(B)
CC(A)
GND
A
1
2
3
6
5
4
I/O-1
I/O-2
DIR
B
PULL-UP/DOWN
PULL-UP/DOWN
DIR CTRL
system-1
system-2
001aaj995
Pull-up or pull-down only needed for 74LVC1T45.
Fig. 16. Bidirectional logic level-shifting application
©
74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
22 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Table 17 provides a sequence that illustrates data transmission from system-1 to system-2 and
then from system-2 to system-1.
Table 17. Description bidirectional logic level-shifting application
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
State
DIR CTRL I/O-1
I/O-2
input
Z
Description
1
2
H
H
output
Z
system-1 data to system-2
system-2 is getting ready to send data to
system-1. I/O-1 and I/O-2 are disabled. The
bus-line state depends on bus hold.
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 are still
disabled. The bus-line state depends on bus
hold.
input
output
system-2 data to system-1
13.3. Power-up considerations
The device is designed such that no special power-up sequence is required other than GND being
applied first.
Table 18. Typical total supply current (ICC(A) + ICC(B)
)
VCC(A)
VCC(B)
0 V
0
Unit
1.8 V
< 1
< 2
< 2
< 2
2
2.5 V
< 1
3.3 V
< 1
5.0 V
< 1
2
0 V
μA
μA
μA
μA
μA
1.8 V
2.5 V
3.3 V
5.0 V
< 1
< 1
< 1
< 1
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
< 2
13.4. Enable times
Calculate the enable times for the 74LVC1T45; 74LVCH1T45 using the following formulas:
•
•
•
•
tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR
bit is switched until an output is expected. For example, if the 74LVC1T45; 74LVCH1T45 initially
is transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled
before presenting it with an input. After the B port has been disabled, an input signal applied to it
appears on the corresponding A port after the specified propagation delay.
©
74LVC_LVCH1T45
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
23 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
14. Package outline
TSSOP6: plastic thin shrink small outline package; 6 leads; body width 1.25 mm
SOT363-2
D
B
E
A
X
c
(6x)
y
H
E
v
M
A
e
1
6
5
4
pin 1 index
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B
p
b
p
(6x)
detail X
e
e
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
(1)
(1)
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0
0.8 0.8
0.30 0.25 2.2 1.35
0.15 0.08 1.8 1.15
2.4 0.46
1.8 0.26
8°
0°
mm
0.15
0.65 1.3
0.3 0.1 0.1
0
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot363-2_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
21-12-15
21-12-16
SOT363-2
SC-88A
MO-203
Fig. 17. Package outline SOT363-2 (TSSOP6)
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Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4x
(2)
L
L
1
e
6
5
4
e
e
1
1
6x
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
b
D
E
e
e
L
L
1
1
1
max 0.5 0.04 0.25 1.50 1.05
0.35 0.40
0.30 0.35
0.27 0.32
nom
min
0.20 1.45 1.00 0.6
0.17 1.40 0.95
mm
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
sot886_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
MO-252
JEITA
04-07-22
12-01-05
SOT886
Fig. 18. Package outline SOT886 (XSON6)
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
25 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
b
3
(2)
(4×)
1
2
L
L
1
e
6
5
4
e
e
1
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 0.95 1.05
0.35 0.40
0.15 0.90 1.00 0.55 0.3 0.30 0.35
0.12 0.85 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1115_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1115
Fig. 19. Package outline SOT1115 (XSON6)
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
26 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
b
3
(2)
1
2
(4×)
L
L
1
e
6
5
4
e
e
1
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
0.15 1.00 1.00 0.55 0.35 0.30 0.35
0.12 0.95 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1202_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1202
Fig. 20. Package outline SOT1202 (XSON6)
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74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
27 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
15. Abbreviations
Table 19. Abbreviations
Acronym
Description
CDM
DUT
ESD
HBM
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
16. Revision history
Table 20. Revision history
Document ID
Release date
20220210
Data sheet status
Change notice Supersedes
74LVC_LVCH1T45 v.9
Modifications:
Product data sheet
-
74LVC_LVCH1T45 v.8
•
Package SOT363 (SC-88) changed to SOT363-2 (TSSOP6).
74LVC_LVCH1T45 v.8
Modifications:
20210610 Product data sheet 74LVC_LVCH1T45 v.7
-
•
•
Type numbers 74LVC1T45GF and 74LVCH1T45GF (SOT891 / XSON6) removed.
Section 8: Derating values for Ptot total power dissipation updated.
74LVC_LVCH1T45 v.7
Modifications:
20190319
Product data sheet
-
74LVC_LVCH1T45 v.6
•
•
The format of this data sheet has been redesigned to comply with the identity guidelines
of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74LVC_LVCH1T45 v.6
Modifications:
20120806
Product data sheet
-
74LVC_LVCH1T45 v.5
74LVC_LVCH1T45 v.4
•
Package outline drawing of SOT886 (Fig. 18) modified.
74LVC_LVCH1T45 v.5
Modifications:
20111219
Product data sheet
-
•
Legal pages updated.
74LVC_LVCH1T45 v.4
74LVC_LVCH1T45 v.3
74LVC_LVCH1T45 v.2
74LVC_LVCH1T45 v.1
20110927
20100819
20100119
20090511
Product data sheet
Product data sheet
Product data sheet
Product data sheet
-
-
-
-
74LVC_LVCH1T45 v.3
74LVC_LVCH1T45 v.2
74LVC_LVCH1T45 v.1
-
©
74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
28 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
17. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74LVC_LVCH1T45
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Product data sheet
Rev. 9 — 10 February 2022
29 / 30
Nexperia
74LVC1T45; 74LVCH1T45
Dual supply translating transceiver; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 3
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................8
11.1. Waveforms and test circuit.......................................13
12. Typical propagation delay characteristics..............16
13. Application information........................................... 22
13.1. Unidirectional logic level-shifting application............22
13.2. Bidirectional logic level-shifting application..............22
13.3. Power-up considerations......................................... 23
13.4. Enable times............................................................23
14. Package outline........................................................ 24
15. Abbreviations............................................................28
16. Revision history........................................................28
17. Legal information......................................................29
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 10 February 2022
©
74LVC_LVCH1T45
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Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 10 February 2022
30 / 30
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