74LV595D [NEXPERIA]
8-bit serial-in/serial-out or parallel-out shift register; 3-stateProduction;型号: | 74LV595D |
厂家: | Nexperia |
描述: | 8-bit serial-in/serial-out or parallel-out shift register; 3-stateProduction 光电二极管 输出元件 逻辑集成电路 触发器 |
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中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 5 — 29 September 2021
Product data sheet
1. General description
The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and
3-state outputs. Both the shift and storage register have separate clocks. The device features a
serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR
input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions
of the SHCP input. The data in the shift register is transferred to the storage register on a
LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register
will always be one clock pulse ahead of the storage register. Data in the storage register appears
at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs
to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the
registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface
inputs to voltages in excess VCC
.
2. Features and benefits
•
Wide supply voltage range from 1.0 V to 3.6 V
CMOS low power dissipation
Direct interface with TTL levels
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C
Has a shift register with direct clear
•
•
•
•
•
•
Output capability:
•
•
Parallel outputs; bus driver
Serial output; standard
•
•
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
•
ESD protection:
•
•
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
•
•
Multiple package options
Specified from -40 °C to 85 °C and -40 °C to 125 °C
3. Applications
•
•
Serial-to-parallel data conversion
Remote control holding register
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
-40 °C to +125 °C
Name
Description
Version
74LV595D
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74LV595PW
-40 °C to +125 °C
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
5. Functional diagram
13
EN3
12
C2
11
12
10
SHCP
SRG8
R
STCP
11
9
15
1
C1/
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
14
15
1
1D
2D
3
2
2
14
3
DS
3
4
4
5
5
6
6
7
Q7
7
MR
10
OE
9
13
mna552
mna553
Fig. 1. Logic symbol
Fig. 2. Logic symbol (IEEE/IEC)
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
9
12 STCP
13 OE
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q0
15
Q1 Q2 Q3 Q4 Q5 Q6 Q7
1
2
3
4
5
6
7
mna554
Fig. 3. Functional diagram
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
2 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
STAGE 0
Q
STAGES 1 TO 6
STAGE 7
D Q
DS
Q7S
D
D
Q
FF7
CP
FF0
CP
R
R
SHCP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
STCP
OE
mna555
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig. 4. Logic diagram
SHCP
DS
STCP
MR
OE
Q0
Z-state
Z-state
Q1
Z-state
Z-state
Q6
Q7
Q7S
mna556
Fig. 5. Timing diagram
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
3 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
6. Pinning information
6.1. Pinning
74LV595
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q1
Q2
V
CC
Q0
74LV595
Q3
DS
Q1
Q2
1
2
3
4
5
6
7
8
16 V
CC
15 Q0
Q4
OE
Q3
14 DS
Q5
STCP
SHCP
MR
Q4
13 OE
Q5
12 STCP
11 SHCP
10 MR
Q6
Q6
Q7
Q7
GND
Q7S
GND
9
Q7S
001aaj970
mla001
Fig. 6. Pin configuration SOT109-1 (SO16)
Fig. 7. Pin configuration SOT403-1 (TSSOP16)
6.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
ground (0 V)
GND
Q7S
MR
8
9
serial data output
10
11
12
13
14
16
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
SHCP
STCP
OE
DS
VCC
supply voltage
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
4 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
7. Functional description
Table 3. Function table
H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition;
X = don’t care; NC = no change; Z = high-impedance OFF-state.
Input
Output
Function
SHCP STCP OE
MR
L
DS
X
Q7S
L
Qn
NC
L
X
X
X
↑
X
↑
L
L
H
L
a LOW-state on MR only affects the shift register
empty shift register loaded into storage register
L
X
L
X
X
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state
H
H
Q6S
NC
logic HIGH-state shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X
↑
↑
↑
L
L
H
H
X
X
NC
QnS
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
Q6S
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Max
+4.6
±20
±50
Unit
V
VCC
IIK
supply voltage
-0.5
input clamping current
output clamping current
output current
VI < -0.5 V or VI > VCC + 0.5 V
VI < -0.5 V or VI > VCC + 0.5 V
-0.5 V < VO < VCC + 0.5 V
standard driver outputs
bus driver outputs
-
-
-
mA
mA
IOK
IO
25
35
50
70
mA
mA
mA
mA
mA
mA
°C
ICC
supply current
ground current
standard driver outputs
bus driver outputs
IGND
standard driver outputs
bus driver outputs
-50
-70
-65
-
Tstg
Ptot
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[1]
mW
[1] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
©
74LV595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
5 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
9. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max Unit
VCC
VI
supply voltage
1.0
3.3
3.6
VCC
VCC
V
V
V
input voltage
0
0
-
-
-
-
-
-
VO
output voltage
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
-
+125 °C
500 ns/V
200 ns/V
100 ns/V
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
-
-
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
0.9
1.4
2.0
-
Max
-
VIH
HIGH-level input
voltage
VCC = 1.2 V
0.9
1.4
2.0
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
VCC = 2.0 V
-
VCC = 2.7 V to 3.6 V
VCC = 1.2 V
-
VIL
LOW-level input
voltage
0.3
0.6
0.8
0.3
0.6
0.8
VCC = 2.0 V
-
-
VCC = 2.7 V to 3.6 V
-
-
VOH
HIGH-level output all outputs; VI = VIH or VIL;
voltage
IO = -100 μA
VCC = 1.2 V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V
-
1.2
2.0
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
1.8
2.5
2.8
2.4
1.8
2.5
2.8
2.2
2.7
3.0
standard outputs; VI = VIH or VIL;
IO = -6 mA; VCC = 3.0 V
2.82
bus outputs; VI = VIH or VIL;
IO = -8 mA; VCC = 3.0 V
2.4
2.82
-
2.2
-
V
VOL
LOW-level output all outputs; VI = VIH or VIL;
voltage
IO = 100 μA
VCC = 1.2 V
-
-
-
-
-
0
0
-
-
-
-
-
-
-
V
V
V
V
V
VCC = 2.0 V
VCC = 2.7 V
VCC = 3.0 V
0.2
0.2
0.2
0.4
0.2
0.2
0.2
0.5
0
0
standard driver outputs VCC = 3.0 V;
IO = 6 mA
0.25
bus driver outputs VCC = 3.0 V;
IO = 8 mA
-
-
0.20
-
0.4
1.0
-
-
0.5
1.0
V
II
input leakage
current
VCC = 3.6 V; VI = 5.5 V or GND
μA
©
74LV595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
6 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
IOZ
ICC
ΔICC
CI
OFF-state output VI = VIH or VIL; VO = VCC or GND;
-
-
-
-
-
5
20
500
-
-
10
μA
μA
μA
pF
current
VCC = 3.6 V
supply current
VCC = 3.6 V; VI = VCC or GND;
IO = 0 A
-
-
-
-
-
160
850
-
additional supply
current
per input pin; VCC = 2.7 V to 3.6 V;
VI = VCC - 0.6 V
input capacitance
3.5
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C.
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 13.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tpd
propagation delay
SHCP to Q7S; see Fig. 8
VCC = 1.2 V
[2]
-
-
-
-
-
95
32
24
15
18
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
61
45
-
75
55
-
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
STCP to Qn; see Fig. 9
VCC = 1.2 V
[3]
[2]
36
44
-
-
-
-
-
100
34
25
16
19
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
65
48
-
77
56
-
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
MR to Q7S; see Fig. 11
VCC = 1.2 V
[3]
38
45
-
-
-
-
-
85
29
21
14
16
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
56
41
-
66
49
-
VCC = 2.7 V
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
OE to Qn; see Fig. 12
VCC = 1.2 V
[3]
[4]
33
33
ten
enable time
disable time
-
-
-
-
85
29
21
16
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
56
41
33
66
49
39
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
OE to Qn; see Fig. 12
VCC = 1.2 V
[3]
[5]
tdis
-
-
-
-
65
24
18
14
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
40
32
26
49
37
30
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
[3]
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
7 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
tW
pulse width
SHCP, HIGH or LOW; see Fig. 8
VCC = 2.0 V
34
25
20
10
8
-
-
-
41
30
24
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
STCP, HIGH or LOW; see Fig. 9
VCC = 2.0 V
[3]
[3]
[3]
6
34
25
20
7
5
4
-
-
-
41
30
24
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
MR LOW; see Fig. 11
VCC = 2.0 V
34
25
20
10
8
-
-
-
41
30
24
-
-
-
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
DS to SHCP; see Fig. 10
VCC = 1.2 V
6
tsu
set-up time
-
40
14
10
8
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
26
19
15
31
23
18
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
SHCP to STCP; see Fig. 9
VCC = 1.2 V
[3]
[3]
[3]
[3]
-
40
14
10
8
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
26
19
15
31
23
18
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
DS to SHCP; see Fig. 10
VCC = 1.2 V
th
hold time
-
-10.0
-4.0
-3.0
-2.0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
5.0
5.0
5.0
5.0
5.0
5.0
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
MR to SHCP; see Fig. 11
VCC = 1.2 V
trec
recovery time
-
-35
-12.0
-9.0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
VCC = 2.0 V
5.0
5.0
5.0
5.0
5.0
5.0
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
-7.0
fmax
maximum frequency SHCP or STCP;
see Fig. 8 and Fig. 9
VCC = 2.0 V
VCC = 2.7 V
14.0
19.0
-
40.0
58.0
77
-
-
-
-
12
16
-
-
-
-
-
MHz
MHz
MHz
MHz
VCC = 3.3 V; CL = 15 pF
VCC = 3.0 V to 3.6 V
[3] 24.0
70.0
20
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
8 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Typ [1]
Max
Min
Max
CPD
power dissipation
capacitance
VI = GND to VCC; VCC = 3.0 V
[6]
-
115
-
-
-
pF
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPLH and tPHL
[3] Typical value measured at VCC = 3.3 V.
[4] ten is the same as tPZH and tPZL
[5] tdis is the same as tPHZ and tPLZ
.
.
.
[6] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + ∑(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑(CL × VCC 2 × fo) = sum of outputs.
11.1. Waveforms and test circuit
1/f
max
V
I
SHCP input
GND
V
M
t
W
t
t
PHL
PLH
V
OH
V
Q7S output
V
M
OL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig. 8. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and
maximum shift clock frequency
V
I
SHCP input
GND
V
M
t
1/f
max
su
V
I
STCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
Qn output
M
V
OL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig. 9. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width
and the shift clock to storage clock set-up time
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
9 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
V
I
V
SHCP input
M
GND
t
t
su
su
M
t
t
h
h
V
I
V
DS input
GND
V
OH
V
Q7S output
M
V
OL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig. 10. The data set-up and hold times for the serial data input (DS)
V
I
V
MR input
M
GND
t
t
rec
W
V
I
SHCP input
Q7S output
V
M
GND
t
PHL
V
OH
V
M
V
OL
mna561
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig. 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and
the master reset to shift clock (SHCP) recovery time
©
74LV595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
10 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
V
I
V
OE input
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
V
OL
X
t
t
PHZ
PZH
V
OH
V
Y
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
001aae821
Measurement points are given in Table 8.
VOL and VOH are typical output voltage drops that occur with the output load.
Fig. 12. Enable and disable times
Table 8. Measurement points
Supply voltage
Input
VM
Output
VM
VCC
VX
VY
VCC < 2.7 V
VCC ≥ 2.7 V
0.5VCC
1.5 V
0.5VCC
1.5 V
VOL + 0.1VCC
VOL + 0.3 V
VOH - 0.1VCC
VOH - 0.3 V
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
11 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig. 13. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
VCC
Input
VI
Load
CL
VEXT
tr, tf
RL
tPLH, tPHL
open
tPLZ, tPZL
2VCC
tPHZ, tPZH
GND
< 2.7 V
VCC
2.7 V
≤ 2.5 ns
≤ 2.5 ns
50 pF
50 pF
1 kΩ
1 kΩ
2.7 V to 3.6 V
open
2VCC
GND
©
74LV595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
12 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 14. Package outline SOT109-1 (SO16)
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74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
13 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 15. Package outline SOT403-1 (TSSOP16)
©
74LV595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
14 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
Machine Model
HBM
MM
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20210929 Product data sheet
Change notice Supersedes
- 74LV595 v.4
74LV595 v.5
Modifications:
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number 74LV595DB (SOT338-1/SSOP16) removed.
Section 1 and Section 2 updated.
Section 8: Derating values for Ptot total power dissipation updated.
74LV595 v.4
20160318
Type number 74LV595N (SOT38-4) removed.
20090421 Product data sheet
Product data sheet
-
74LV595 v.3
Modifications:
•
74LV595 v.3
-
74LV595 v.2
Modifications:
•
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
74LV595 v.2
74LV595 v.1
980402
970606
Product data sheet
Product data sheet
-
-
74LV595 v.1
-
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
15 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74LV595
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Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
16 / 17
Nexperia
74LV595
8-bit serial-in/serial-out or parallel-out shift register; 3-state
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................4
6.1. Pinning.........................................................................4
6.2. Pin description.............................................................4
7. Functional description................................................. 5
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................6
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit........................................ 9
12. Package outline........................................................ 13
13. Abbreviations............................................................15
14. Revision history........................................................15
15. Legal information......................................................16
© Nexperia B.V. 2021. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 29 September 2021
©
74LV595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2021. All rights reserved
Product data sheet
Rev. 5 — 29 September 2021
17 / 17
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