74LV165D [NEXPERIA]
8-bit parallel-in/serial-out shift registerProduction;型号: | 74LV165D |
厂家: | Nexperia |
描述: | 8-bit parallel-in/serial-out shift registerProduction |
文件: | 总16页 (文件大小:274K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74LV165
8-bit parallel-in/serial-out shift register
Rev. 9 — 5 September 2022
Product data sheet
1. General description
The 74LV165 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial
data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7
and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift
register asynchronously. When PL is HIGH data enters the register serially at DS. When the clock
enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH
on CE will disable the CP input. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess VCC
.
2. Features and benefits
•
Wide supply voltage range from 1.0 to 5.5 V
•
•
•
•
•
•
•
CMOS low power dissipation
Direct interface with TTL levels (2.7 V to 3.6 V)
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Optimized for low voltage applications: 1.0 V to 3.6 V
Synchronous parallel-to-serial applications
Synchronous serial input for easy expansion
Complies with JEDEC standards:
•
•
•
•
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
•
•
ESD protection:
•
•
HBM JESD22-A114F exceeds 2 kV
MM JESD22-A115-A exceeds 200 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
Description
Version
74LV165D
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
SOT403-1
74LV165PW -40 °C to +125 °C
TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
4. Functional diagram
SRG8
1
C2[LOAD]
G1[SHIFT]
15
≥ 1
10
C3/
1
2
DS
11
D0
10
11
12
13
14
3
3D
2D
2D
12
D1
13
D2
14
D3
3
D4
4
D5
5
9
7
D6
D7
PL
Q7
Q7
4
6
1
5
9
7
6
CP CE
15
2
mna985
aaa-008827
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
11 12 13 14 3
4
5
6
D0 D1 D2 D3 D4 D5 D6 D7
1
PL
10 DS
9
7
Q7
Q7
8-BIT SHIFT REGISTER
PARALLEL-IN/SERIAL-OUT
2
CP
CE
15
aaa-008826
Fig. 3. Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
DS
SD
SD
SD
SD
SD
Q
SD
SD
SD
CP
D
Q
D
Q
D
Q
D
Q
D
D
Q
D
Q
D
Q
Q7
Q7
CP
CP
FF1
RD
CP
FF2
RD
CP
FF3
RD
CP
FF4
RD
CP
CP
CP
FF7
FF0
FF5
FF6
CE
PL
Q
RD
RD
RD
RD
aaa-008828
Fig. 4. Logic diagram
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
2 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
5. Pinning information
5.1. Pinning
D package
SOT109-1 (SO16)
1
2
3
4
5
6
7
8
16
V
PL
CP
CC
PW package
SOT403-1 (TSSOP16)
15
14
13
12
11
10
9
CE
D3
D2
D1
D0
DS
Q7
D4
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PL
CP
V
CC
CE
D3
D2
D1
D0
DS
Q7
D5
D4
D6
D5
D6
D7
D7
Q7
Q7
GND
GND
aaa-035385
aaa-035386
5.2. Pin description
Table 2. Pin description
Symbol
Pin
1
Description
PL
parallel enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
complementary serial output from the last stage
ground (0 V)
CP
Q7
2
7
GND
Q7
8
9
serial output from the last stage
serial data input
DS
10
D0, D1, D2, D3, D4, D5, D6, D7
11, 12, 13, 14, 3, 4, 5, 6
parallel data inputs
CE
15
16
clock enable input (active LOW)
positive supply voltage
VCC
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
3 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
6. Functional description
Table 3. Function table
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care; ↑ = LOW-to-HIGH clock transition.
Operating modes
Inputs
Qn registers
Output
Q7
L
PL
L
CE
X
CP
X
X
↑
DS
X
X
l
D0 to D7
Q0
L
Q1 to Q6
Q7
H
parallel load
L
L to L
L
X
H
X
X
X
H
H to H
H
L
serial shift
H
H
H
L
L
q0 to q5
q0 to q5
q1 to q6
q6
q6
q6
q7
L
↑
h
H
q6
hold "do nothing"
H
X
X
q0
q7
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
serial shift
mna993
load
Fig. 5. Timing diagram
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
4 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). [1]
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
-0.5
input clamping current
input voltage
VI < -0.5 V or VI > VCC + 0.5 V
-
-0.5
-
20
mA
V
VI
+7
IOK
output clamping current
output current
VO > VCC or VO < 0
±50
±25
+50
-
mA
mA
mA
mA
°C
IO
-0.5 V < VO < VCC + 0.5 V
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-50
-65
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
1.0
0
Typ
Max
Unit
VCC
VI
supply voltage
3.3
5.5
VCC
VCC
+125
500
200
100
50
V
input voltage
-
-
-
-
-
-
-
V
VO
output voltage
0
V
Tamb
Δt/ΔV
ambient temperature
input transition rise and fall rate
-40
0
°C
VCC = 1.0 V to 2.0 V
VCC = 2.0 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 3.6 V to 5.5 V
ns/V
ns/V
ns/V
ns/V
0
0
0
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
5 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
0.9
1.4
2.0
Typ[1]
Max
Min
Max
VIH
HIGH-level
input voltage
VCC = 1.2 V
-
-
-
-
0.9
-
V
V
V
V
V
V
V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.2 V
-
1.4
-
-
2.0
-
0.7 × VCC
-
-
-
-
-
-
0.3
0.7 × VCC
-
0.3
VIL
LOW-level
input voltage
-
-
-
-
-
-
-
-
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
VI = VIH or VIL; IO = -100 μA
VCC = 1.2 V
0.6
0.6
0.8
0.8
0.3 × VCC
0.3 × VCC
VOH
HIGH-level
output voltage
-
1.2
2.0
2.7
3.0
4.5
-
VCC = 2.0 V
1.8
2.5
2.8
4.3
-
-
-
-
1.8
2.5
2.8
4.3
-
-
-
-
V
V
V
V
VCC = 2.7 V
VCC = 3.0 V
VCC = 4.5 V
standard outputs: VI = VIH or VIL
VCC = 3.0 V; IO = -6 mA
VCC = 4.5 V; IO = -12 mA
VI = VIH or VIL; IO = 100 μA
VCC = 1.2 V
2.40
3.60
2.82
4.20
-
-
2.20
3.50
-
-
V
V
VOL
LOW-level
output voltage
-
-
-
-
-
0
0
0
0
0
-
-
-
VCC = 2.0 V
0.2
0.2
0.2
0.2
1.8
2.5
2.8
4.3
0.2
0.2
0.2
0.2
V
V
V
V
VCC = 2.7 V
VCC = 3.0 V
VCC = 4.5 V
standard outputs: VI = VIH or VIL
VCC = 3.0 V; IO = 6 mA
VCC = 4.5 V; IO = 12 mA
-
-
-
0.25
0.35
-
0.40
0.55
±1
-
-
-
0.50
0.65
±1
V
V
II
input leakage VI = VCC or GND; VCC = 5.5 V
current
μA
ICC
ΔICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
-
-
-
20
500
-
-
-
-
160
850
-
μA
μA
pF
additional
VI = VCC – 0.6 V;
supply current VCC = 2.7 V to 3.6 V
input
3.5
capacitance
[1] Typical values are measured at Tamb = 25 °C.
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
6 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); for test circuit, see Fig. 11.
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
tpd
propagation delay CE, CP to Q7, Q7;
see Fig. 6 and Fig. 7
[2]
VCC = 1.2 V
-
-
-
-
-
-
115
38
27
22
18
15
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
61
43
36
-
76
54
45
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
PL to Q7, Q7; see Fig. 7
VCC = 1.2 V
[3]
[4]
24
30
-
-
-
-
-
-
110
35
24
20
18
14
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
56
39
33
-
70
49
41
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
D7 to Q7, Q7; see Fig. 8
VCC = 1.2 V
[3]
[4]
22
27
-
-
-
-
-
-
90
28
20
17
14
11
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
VCC = 2.0 V
45
32
27
-
56
40
33
-
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
[3]
[4]
18
22
tW
pulse width
CP input HIGH to LOW;
see Fig. 6
VCC = 2.0 V
34
25
20
15
10
8
-
-
-
-
41
30
24
18
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
PL input LOW; see Fig. 7
VCC = 2.0 V
[3]
[4]
7
5
34
25
20
15
10
8
-
-
-
-
41
30
24
18
-
-
-
-
ns
ns
ns
ns
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
PL to CP, CE; see Fig. 7
VCC = 1.2 V
[3]
[4]
7
5
trec
recovery time
-
40
15
11
10
7
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
24
18
17
12
30
23
21
15
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[4]
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
7 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
tsu
set-up time
DS to CP, CE; see Fig. 9
VCC = 1.2 V
-
-8
-2
-1
-1
0
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
22
16
13
9
26
19
15
10
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[4]
CE to CP, CP to CE;
see Fig. 9
VCC = 1.2 V
VCC = 2.0 V
-
20
7
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
22
16
13
9
26
19
15
10
VCC = 2.7 V
5
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
Dn to PL; see Fig. 10
VCC = 1.2 V
[3]
[4]
4
3
-
25
8
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
22
16
13
9
26
19
15
10
VCC = 2.7 V
6
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[4]
5
4
th
hold time
DS to CP, CE; Dn to PL;
see Fig. 9 and Fig. 10
VCC = 1.2 V
-
20
7
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
VCC = 2.0 V
22
16
13
9
26
19
15
10
VCC = 2.7 V
5
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
[3]
[4]
4
3
CE to CP, CP to CE;
see Fig. 9
VCC = 1.2 V
VCC = 2.0 V
-
-30
-8
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
5
5
5
5
5
5
5
5
VCC = 2.7 V
-6
VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
see Fig. 6
[3]
[4]
-5
-4
fmax
maximum
frequency
VCC = 2.0 V
14
19
24
-
40
60
65
78
75
-
-
-
-
-
12
16
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
VCC = 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 3.3 V; CL = 15 pF
VCC = 4.5 V to 5.5 V
[3]
[4]
36
30
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
8 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C
Unit
Min
Typ[1]
Max
Min
Max
CPD
power dissipation
capacitance
VI = GND to VCC
VCC = 3.3 V
;
[5]
-
35
-
-
-
pF
[1] Typical values are measured at Tamb = 25 °C.
[2] tpd is the same as tPHL and tPLH
.
[3] Typical values are measured at VCC = 3.3 V.
[4] Typical values are measured at VCC = 5.0 V.
[5] CPD is used to determine the dynamic power dissipation PD = CPD × VCC 2 × fi + Σ (CL × VCC 2 × fo) (PD in μW), where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ (CL × VCC 2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
10.1. Waveforms and test circuit
1/f
max
V
I
CP, CE input
V
M
GND
t
W
t
t
PHL
PLH
V
OH
V
Q7 or Q7 output
M
V
OL
aaa-008829
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig. 6. Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and
maximum clock frequency
V
I
V
PL input
M
GND
t
t
rec
W
V
I
CE, CP input
V
M
GND
t
PHL
V
OH
V
Q7 or Q7 output
M
V
OL
aaa-008830
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig. 7. Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock
(CP) and clock enable (CE) recovery time
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
9 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
V
I
V
D7 input
M
GND
t
t
PLH
PHL
V
OH
V
V
Q7 output
Q7 output
M
M
V
OL
t
t
PLH
PHL
V
OH
V
OL
aaa-008831
Measurement points are given in Table 8.
The changing to output assumes that internal Q6 is opposite state from Q7.
Fig. 8. Data input (Dn) to output (Q7 or Q7) propagation delays when PL is LOW
(1)
V
I
V
CP, CE input
M
GND
t
t
h
h
t
su
(L)
t
su
V
I
stable
V
DS input
M
GND
t
su
t
h
t
V
I
W
V
CP, CE input
M
GND
aaa-008832
Measurement points are given in Table 8.
(1) CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is
permitted to change for predictable output performance.
Fig. 9. Set-up and hold times
V
I
V
V
M
Dn input
GND
M
t
su
t
t
t
h
h
su
V
I
PL input
GND
V
V
M
M
aaa-008833
Measurement points are given in Table 8.
Fig. 10. Set-up and hold times from the data inputs (Dn) to the parallel load input (PL)
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
10 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
Table 8. Measurement points
Supply voltage
Input
Output
VM
VCC
VM
< 2.7 V
0.5 × VCC
1.5 V
0.5 × VCC
1.5 V
2.7 V to 3.6 V
≥ 4.5 V
0.5 × VCC
0.5 × VCC
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
EXT
R
V
CC
L
V
V
O
I
G
DUT
R
T
C
L
R
L
001aae331
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Fig. 11. Test circuit for measuring switching times
Table 9. Test data
Supply voltage
Input
VI
Load
VEXT
tr, tf
CL
RL
tPHL, tPLH
open
< 2.7 V
VCC
2.7 V
VCC
2.5 ns
2.5 ns
2.5 ns
50 pF
1 kΩ
1 kΩ
1 kΩ
2.7 V to 3.6 V
≥ 4.5 V
50 pF, 15 pF
50 pF
open
open
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
11 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 12. Package outline SOT109-1 (SO16)
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
12 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 13. Package outline SOT403-1 (TSSOP16)
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
13 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
12. Abbreviations
Table 10. Abbreviations
Acronym
CMOS
DUT
Description
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
Human Body Model
HBM
MM
Machine Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11. Revision history
Document ID
74LV165 v.9
Modifications:
Release date
20220905
Data sheet status
Change notice
Supersedes
Product data sheet
-
74LV165 v.8
•
Section 8: Maximum value for Tamb ambient temperature corrected to +125 °C.
74LV165 v.8
20210921 Product data sheet 74LV165 v.7
-
Modifications:
•
The format of this data sheet has been redesigned to comply with the identity guidelines of
Nexperia.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Section 7: Derating values for Ptot total power dissipation updated.
Type number 74LV165DB (SOT338-1/SSOP16) removed.
74LV165 v.7
20160309
Product data sheet
-
74LV165 v.6
Modifications:
•
Type number 74HC165N (SOT38-4) removed.
74LV165 v.6
20140219
Product data sheet
Product data sheet
-
-
-
74LV165 v.5
Modifications:
•
Typo corrected in Table 2
74LV165 v.5
20130909
74LV165 v.4
Modifications:
•
Typo corrected in the header of Table 6
20130830 Product data sheet
74LV165 v.4
74LV165_CNV_3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Family data added, see Table 6
74LV165_CNV_3
December 1998 Product specification
-
-
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
14 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
14. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
Trademarks
Suitability for use — Nexperia products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
15 / 16
Nexperia
74LV165
8-bit parallel-in/serial-out shift register
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................1
4. Functional diagram.......................................................2
5. Pinning information......................................................3
5.1. Pinning.........................................................................3
5.2. Pin description.............................................................3
6. Functional description................................................. 4
7. Limiting values............................................................. 5
8. Recommended operating conditions..........................5
9. Static characteristics....................................................6
10. Dynamic characteristics............................................ 7
10.1. Waveforms and test circuit........................................ 9
11. Package outline........................................................ 12
12. Abbreviations............................................................14
13. Revision history........................................................14
14. Legal information......................................................15
© Nexperia B.V. 2022. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 5 September 2022
©
74LV165
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2022. All rights reserved
Product data sheet
Rev. 9 — 5 September 2022
16 / 16
相关型号:
©2020 ICPDF网 联系我们和版权申明