74LV165APW [NEXPERIA]

8-bit parallel-in/serial-out shift registerProduction;


型号：	74LV165APW
厂家：	Nexperia
描述：	8-bit parallel-in/serial-out shift registerProduction 光电二极管逻辑集成电路触发器
文件：	总19页 (文件大小：805K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74LV165A

8-bit parallel-in/serial-out shift register

Rev. 4 — 28 March 2014

Product data sheet

1. General description

The 74LV165A is an 8-bit parallel-load or serial-in shift register with complementary serial

outputs (Q7 and Q7) available from the last stage. When the parallel-load input (PL) is

LOW, parallel data from the inputs D0 to D7 are loaded into the register asynchronously.

When input PL is HIGH, data enters the register serially at the input DS. It shifts one place

to the right (Q0 Q1 Q2, etc.) with each positive-going clock transition. This feature

allows parallel-to-serial converter expansion by tying the output Q7 to the input DS of the

succeeding stage.

The clock input is a gate-OR structure which allows one input to be used as an active

LOW clock enable input (CE) input. The pin assignment for the inputs CP and CE is

arbitrary and can be reversed for layout convenience. The LOW-to-HIGH transition of the

input CE should only take place while CP HIGH for predictable operation.

Schmitt-trigger action at all inputs, makes the circuit tolerant for slower input rise and fall

times. It is fully specified for partial-power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging current backflow through the device when it

is powered down.

2. Features and benefits

 Wide supply voltage range from 2.0 V to 5.5 V

 Synchronous parallel-to-serial applications

 Synchronous serial input for easy expansion

 Latch-up performance exceeds 250 mA

 CMOS LOW power consumption

 5.5 V tolerant inputs/outputs

 Direct interface with TTL levels (2.7 V to 3.6 V)

 Power-down mode

 Complies with JEDEC standards:

 JESD8-5 (2.3 V to 2.7 V)

 JESD8B/JESD36 (2.7 V to 3.6 V)

 JESD8-1A (4.5 V to 5.5 V)

 ESD protection:

 HBM JESD22-A114-A exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Specified from 40 C to +85 C

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

3. Ordering information

Table 1.

Type number Package

Temperature range Name

40 C to +85 C SO16

Ordering information

Description

Version

74LV165AD

plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74LV165APW 40 C to +85 C

TSSOP16 plastic thin shrink small outline package; 16 leads;

body width 4.4 mm

SOT403-1

4. Functional diagram

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Fig 2. IEC logic symbol

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Fig 3. Functional diagram

74LV165A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 March 2014

2 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

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Fig 4. Logic diagram

74LV165A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 March 2014

3 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

5. Pinning information

5.1 Pinning

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5.2 Pin description

Table 2.

Symbol

Pin description

Description

parallel enable input (active LOW)

clock input (LOW-to-HIGH edge-triggered)

complementary serial output from the last stage

ground (0 V)

GND

serial output from the last stage

serial data input

D0 to D7

11, 12, 13, 14, 3, 4, 5, 6

parallel data inputs

clock enable input (active LOW)

positive supply voltage

V_CC

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

4 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

6. Functional description

Table 3.

Function table^[1]

Operating modes

Inputs

Qn registers

Output



D0 to D7

Q1 to Q6

parallel load

L to L

H to H

serial shift

q0 to q5

q1 to q6



hold “do nothing”

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;

 = LOW-to-HIGH clock transition.

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Fig 6. Timing diagram

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

5 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)^[1]

Symbol

V_CC

I_IK

Parameter

Conditions

Min

0.5

Max

Unit

supply voltage

input clamping current

input voltage

V_I< 0 V

20

V_I

0.5

I_OK

output clamping current

output voltage

V_O> V_CCor V_O< 0

50

V_CC+ 0.5

V_O

0.5

power-down mode

0 V < V_O< V_CC

I_O

output current

25

+50

C

I_CC

I_GND

T_stg

P_tot

supply current

ground current

50

65

storage temperature

total power dissipation

+150

T_amb= 40 C to +85 C

SO16 package

[2]

[3]

500

TSSOP16 package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] _totderates linearly with 8 mW/K above 70 C.

[3] P_totderates linearly with 5.5 mW/K above 60 C.

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter

Conditions

Min

2.0

Typ

Max

5.5

Unit

V_CC

V_I

supply voltage

input voltage

5.5

V_O

output voltage

V_CC

+85

200

100

T_amb

t/V

ambient temperature

input transition rise and fall rate

40

C

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

ns/V

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

6 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

9. Static characteristics

Table 6.

Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions T_amb= 40 C to +85 C

Unit

Min

Typ

Max

V_IH

HIGH-level input voltage V_CC= 2.0 V

V_CC= 2.3 V to 2.7 V

1.5

0.7V_CC

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_CC= 2.0 V

0.7V_CC

V_IL

LOW-level input voltage

0.5

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

0.3V_CC

V_OH

HIGH-level output voltage V_I= V_IHor V_IL

I_O= 50 A; V_CC= 2.0 V to 5.5 V

V_CC 0.1

2.0

I_O= 2.0 mA; V_CC= 2.3 V

I_O= 6.0 mA; V_CC= 3.0 V

I_O= 12 mA; V_CC= 4.5 V

2.48

3.8

V_OL

LOW-level output voltage V_I= V_IHor V_IL

I_O= 50 A; V_CC= 2.0 V to 5.5 V

_O= 2.0 mA; V_CC= 2.3 V

0.10

0.40

0.44

0.55

1

I_O= 6.0 mA; V_CC= 3.0 V

I_O= 12 mA; V_CC= 4.5 V

I_I

input leakage current

V_I= V_CCor GND; V_CC= 5.5 V

0.01

0.05

0.2

A

I_OFF

I_CC

C_I

power-off leakage current V_Ior V_O= 5.5 V; V_CC= 0.0 V

5

supply current

V_I= V_CCor GND; I_O= 0 A; V_CC= 5.5 V

input capacitance

3.0

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

7 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

10. Dynamic characteristics

Table 7.

Dynamic characteristics

GND (ground = 0 V); for test circuit, see Figure 12

Symbol Parameter

Conditions

T_amb= 40 C to +85 C

Min Max

Typ^[1]

Unit

[2]

t_pd

propagation

delay

CE, CP to Q7, Q7; C_L= 15 pF; see Figure 7

and Figure 8

[3]

[4]

[5]

V_CC= 2.3 V to 2.7 V

V_CC= 3.0 V to 3.6 V

1.0

11.0

22.0

18.0

11.5

7.5

5.5

V_CC= 4.5 V to 5.5 V

PL to Q7, Q7; C_L= 15 pF; see Figure 8

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

1.0

11.5

8.0

23.5

18.5

11.5

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

5.5

D7 to Q7, Q7; C_L= 15 pF; see Figure 9

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

1.0

12.0

8.5

24.0

16.5

10.5

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

6.0

CE, CP to Q7, Q7; see Figure 7 and Figure 8

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

1.0

13.0

9.0

26.0

21.5

13.5

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

6.1

PL to Q7, Q7; see Figure 8

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

1.0

14.0

10.0

6.5

28.0

22.0

13.5

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

D7 to Q7, Q7; see Figure 9

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

1.0

14.0

10.0

6.5

28.0

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

12.5

t_W

pulse width

CP input HIGH to LOW; see Figure 7

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

9.0

7.0

4.0

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

PL input LOW; see Figure 8

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

13.0

9.0

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

6.0

t_rec

recovery time

PL to CP, CE; see Figure 8

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

8.5

6.0

4.0

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

8 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

Table 7.

Dynamic characteristics …continued

GND (ground = 0 V); for test circuit, see Figure 12

Symbol Parameter

Conditions

T_amb= 40 C to +85 C

Min Max

Typ^[1]

Unit

t_su

set-up time

DS to CP, CE; see Figure 10

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

6.0

4.0

7.0

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

CE to CP, CP to CE; see Figure 10

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

7.0

5.0

3.5

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

D7 to PL; see Figure 11

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

V_CC= 3.0 V to 3.6 V

8.5

5.0

V_CC= 4.5 V to 5.5 V

t_h

hold time

DS to CP, CE; PL to CP, CE; see Figure 10

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

0.5

Dn to PL; see Figure 11

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

0.5

1.0

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

f_max

maximum

frequency

CP input; C_L= 15 pF; see Figure 7

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

MHz

V_CC= 3.0 V to 3.6 V

115

165

V_CC= 4.5 V to 5.5 V

CP input; see Figure 7

V_CC= 2.3 V to 2.7 V

[3]

[4]

[5]

MHz

V_CC= 3.0 V to 3.6 V

V_CC= 4.5 V to 5.5 V

125

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

9 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

Table 7.

Dynamic characteristics …continued

GND (ground = 0 V); for test circuit, see Figure 12

Symbol Parameter

Conditions

T_amb= 40 C to +85 C

Min Max

Typ^[1]

Unit

[6]

C_PD

power

V_I= GND to V_CC; V_CC= 3.3 V

dissipation

capacitance

[1] Typical values are measured at T_amb= 25 °C and nominal V_CC

[2] t_pdis the same as t_PHLand t_PLH

[3] Typical values are measured at V_CC= 2.5 V.

[4] Typical values are measured at V_CC= 3.3 V.

[5] Typical values are measured at V_CC= 5.0 V.

[6] C_PDis used to determine the dynamic power dissipation P_D= C_PD V_CC² f_i+ (C_L V_CC² f_o) (P_Din W), where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

 (C_L V_CC² f_o) = sum of outputs;

C_L= output load capacitance in pF;

V_CC= supply voltage in V.

11. Waveforms

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Measurement points are given in Table 8.

The changing to output assumes that internal Q6 is opposite state from Q7.

Fig 7. Clock pulse (CP) and clock enable (CE) to output (Q7 or Q7) propagation delays, clock pulse width and

maximum clock frequency

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

10 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

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Measurement points are given in Table 8.

The changing to output assumes that internal Q6 is opposite state from Q7.

Fig 8. Parallel load (PL) pulse width, parallel load to output (Q7 or Q7) propagation delays, parallel load to clock

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Measurement points are given in Table 8.

The changing to output assumes that internal Q6 is opposite state from Q7.

Fig 9. Data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

11 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

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Measurement points are given in Table 8.

(1) CE may change only from HIGH-to-LOW while CP is LOW. The shaded areas indicate when the input is permitted to change for

predictable output performance.

Fig 10. Set-up and hold times

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Measurement points are given in Table 8.

Fig 11. Set-up and hold times from the data inputs (Dn) to the parallel load input (PL)

Table 8. Measurement points

Supply voltage

V_CC

Input

V_M

Output

V_M

2.0 V to 5.5 V

0.5V_CC

74LV165A

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Product data sheet

Rev. 4 — 28 March 2014

12 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

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Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig 12. Test circuit for measuring switching times

Table 9.

Test data

Supply voltage

Input

V_I

Load

V_EXT

t_r, t_f

C_L

R_L

t_PHL, t_PLH

open

2.0 V to 5.5 V

V_CC

3.0 ns

50 pF, 15 pF

1 k

74LV165A

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Product data sheet

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13 of 19

74LV165A

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8-bit parallel-in/serial-out shift register

12. Package outline

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74LV165A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 March 2014

14 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

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74LV165A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 March 2014

15 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

13. Abbreviations

Table 10. Abbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

Machine Model

TTL

Transistor-Transistor Logic

14. Revision history

Table 11. Revision history

Document ID

74LV165A v.4

Modifications:

Release date

20140328

Data sheet status

Change notice

Supersedes

Product data sheet

74LV165A v.3

• Minimum limit V_OHfor V_CC= 4.5 V corrected from 3.0 V to 3.8 V (errata) in Table 6 “Static

characteristics”

74LV165A v.3

Modifications:

74LV165A v.2

Modifications:

20140220

• Typo corrected in Table 2 “Pin description”

20130904 Product data sheet

Product data sheet

74LV165A v.2

74LV165A_CNV_1

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Family data added, see Section 9 “Static characteristics”

74LV165A_CNV_1

December 1990 Product specification

74LV165A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 March 2014

16 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nexperia.com.

Suitability for use — Nexperia products are not designed,

15.2 Definitions

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of a Nexperia product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. Nexperia and its suppliers accept no liability for

inclusion and/or use of Nexperia products in such equipment or

applications and therefore such inclusion and/or use is at the customer’s own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the Nexperia

product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the Nexperia product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Nexperia does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using Nexperia

products in order to avoid a default of the applications and

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no

responsibility for the content in this document if provided by an information

source outside of Nexperia.

the products or of the application or use by customer’s third party

customer(s). Nexperia does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall Nexperia be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Terms and conditions of commercial sale — Nexperia

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nexperia.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. Nexperia hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of Nexperia products by customer.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of Nexperia.

Right to make changes — Nexperia reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

74LV165A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 March 2014

17 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Nexperia’s specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies Nexperia for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond Nexperia’s

standard warranty and Nexperia’s product specifications.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

74LV165A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 28 March 2014

18 of 19

74LV165A

Nexperia

8-bit parallel-in/serial-out shift register

17. Contents

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

15.1

15.2

15.3

15.4

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 28 March 2014

74LV165APW [NEXPERIA]

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