74AXP2T45DC [NEXPERIA]

2-bit dual supply translating transceiver; 3-stateProduction;
74AXP2T45DC
型号: 74AXP2T45DC
厂家: Nexperia    Nexperia
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2-bit dual supply translating transceiver; 3-stateProduction

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74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Rev. 2 — 23 June 2022  
Product data sheet  
1. General description  
The 74AXP2T45 is a 2-bit, dual supply transceiver with 3-state outputs that enables bidirectional  
level translation. It features two 2-bit input-output ports (nA and nB), a direction control input  
(DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any  
voltage between 0.9 V and 5.5 V making the device suitable for translating between any of the low  
voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power supply sequencing is  
required and output glitches during power supply transitions are prevented using patented circuitry.  
As a result glitches will not appear on the outputs for supply transitions during power-up/down  
between 20 mV/μs and 5.5 V/s. Pins A and DIR are referenced to VCC(A) and pin B is referenced  
to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission  
from B to A.  
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry  
disables the output, preventing any damaging backflow current through the device when it is  
powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are  
in the high-impedance OFF-state.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 0.9 V to 5.5 V  
VCC(B): 0.9 V to 5.5 V  
Low input capacitance; CI = 1.4 pF (typical)  
Low output capacitance; CO = 4.4 pF (typical)  
Low dynamic power consumption; CPD = 11 pF (typical)  
Low static power consumption; ICC = 2 μA (25 °C maximum)  
High noise immunity  
Complies with JEDEC standard:  
JESD8-12 (1.1 V to 1.3 V; inputs)  
JESD8-11 (1.4 V to 1.6 V)  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD12-6 (4.5 V to 5.5 V)  
ESD protection:  
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2 kV  
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1 kV  
Latch-up performance exceeds 100 mA per JESD78D Class II  
Inputs accept voltages up to 5.5 V  
Low noise overshoot and undershoot < 10% of VCCO  
IOFF circuitry provides partial power-down mode operation  
Specified from -40 °C to +125 °C  
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74AXP2T45DC  
74AXP2T45GX  
-40 °C to +125 °C  
VSSOP8 plastic very thin shrink small outline package; 8 leads;  
body width 2.3 mm  
SOT765-1  
-40 °C to +125 °C  
X2SON8 plastic thermal enhanced extremely thin  
small outline package; no leads; 8 terminals;  
body 1.35 × 0.8 × 0.32 mm  
SOT1233-2  
4. Marking  
Table 2. Marking  
Type number  
Marking code[1]  
74AXP2T45DC  
74AXP2T45GX  
R5  
R5  
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.  
5. Functional diagram  
5
DIR  
DIR  
2
1A  
1A  
7
1B  
1B  
2B  
3
2A  
2A  
6
2B  
V
V
CC(B)  
CC(A)  
V
V
CC(B)  
CC(A)  
001aag577  
001aag578  
Fig. 1. Logic symbol  
Fig. 2. Logic diagram  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
2 / 26  
 
 
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
6. Pinning information  
6.1. Pinning  
74AXP2T45  
1
V
7
1B  
2B  
CC(A)  
8
V
CC(B)  
74AXP2T45  
1A  
2
6
1
2
3
4
8
7
6
5
V
V
CC(B)  
4
GND  
CC(A)  
1A  
1B  
2A  
3
5
DIR  
2A  
2B  
GND  
DIR  
aaa-029972  
Transparent top view  
aaa-029971  
Fig. 3. Pin configuration SOT765-1 (VSSOP8)  
Fig. 4. Pin configuration SOT1233-2 (X2SON8)  
6.2. Pin description  
Table 3. Pin description  
Symbol  
VCC(A)  
1A  
Pin  
1
Description  
supply voltage A (nA, and DIR are referenced to VCC(A)  
)
2
data input or output  
2A  
3
data input or output  
GND  
DIR  
4
ground (0 V)  
5
direction control  
2B  
6
data input or output  
1B  
7
data input or output  
VCC(B)  
8
supply voltage B (nB is referenced to VCC(B))  
7. Functional description  
Table 4. Function table  
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.  
Supply voltage  
VCC(A), VCC(B)  
0.9 V to 5.5 V  
0.9 V to 5.5 V  
GND[1]  
Input  
Input/output [1]  
DIR[2]  
nA[2]  
nA = nB  
input  
Z
nB[2]  
input  
nB = nA  
Z
L
H
X
[1] If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.  
[2] nA and DIR are referenced to VCC(A); nB is referenced to VCC(B)  
.
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
3 / 26  
 
 
 
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
8. Limiting values  
Table 5. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol  
VCC(A)  
VCC(B)  
IIK  
Parameter  
Conditions  
Min  
-0.5  
-0.5  
-20  
-0.5  
-20  
-0.5  
-0.5  
-
Max  
+6.5  
+6.5  
-
Unit  
V
supply voltage A  
supply voltage B  
input clamping current  
input voltage  
V
VI < 0 V  
mA  
V
VI  
[1]  
+6.5  
-
IOK  
output clamping current  
output voltage  
VO < 0 V  
mA  
VO  
Active mode  
[1][2][3]  
[1]  
VCCO + 0.5 V  
Suspend or 3-state mode  
VO = 0 V to VCCO  
ICC(A) or ICC(B); per VCC pin  
per GND pin  
+6.5  
±25  
100  
-
V
IO  
output current  
[2]  
mA  
mA  
mA  
°C  
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
ground current  
-100  
-65  
storage temperature  
total power dissipation  
+150  
Tamb = -40 °C to +125 °C  
For SOT765-1 package  
For SOT1233-2 package  
[4]  
[5]  
-
-
250  
300  
mW  
mW  
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.  
[2] VCCO is the supply voltage associated with the output port.  
[3] VCCO + 0.5 V should not exceed 6.5 V.  
[4] For SOT765-1 (VSSOP8) package: Ptot derates linearly with 4.9 mW/K above 99 °C.  
[5] For SOT1233-2 (X2SON8) package: Ptot derates linearly with 7.7 mW/K above 118 °C.  
9. Recommended operating conditions  
Table 6. Recommended operating conditions  
Symbol  
VCC(A)  
VCC(B)  
VI  
Parameter  
Conditions  
Min  
Max  
5.5  
5.5  
5.5  
VCCO  
5.5  
+125  
20  
Unit  
V
supply voltage A  
supply voltage B  
input voltage  
0.9  
0.9  
V
0
0
0
-40  
-
V
VO  
output voltage  
Active mode  
[1]  
[2]  
V
Suspend or 3-state mode  
V
Tamb  
ambient temperature  
°C  
Δt/ΔV  
input transition rise and fall rate VCCI = 0.9 V  
VCCI = 1.2 V  
ns/V  
ns/V  
ns/V  
ns/V  
ns/V  
ns/V  
-
20  
VCCI = 1.4 V to 1.95 V  
-
20  
VCCI = 2.3 V to 2.7 V  
VCCI = 3 V to 3.6 V  
VCCI = 4.5 V to 5.5 V  
-
20  
-
10  
-
8
[1] VCCO is the supply voltage associated with the output port.  
[2] VCCI is the supply voltage associated with the input port.  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
4 / 26  
 
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
10. Static characteristics  
Table 7. Static characteristics  
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
-40 °C to +125 °C  
Min  
+25 °C  
Max  
-40 °C to +85 °C -40 °C to +125 °C Unit  
Typ  
Max  
Max  
VIH  
HIGH-level  
input voltage  
nA, nB and DIR input  
VCCI = 0.9 V  
[1]  
0.7 × VCCI  
0.65 × VCCI  
1.6  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
VCCI = 1.1 V to 1.95 V  
VCCI = 2.3 V to 2.7 V  
VCCI = 3.0 V to 3.6 V  
VCCI = 4.5 V to 5.5 V  
nA, nB and DIR input  
VCCI = 0.9 V  
2.0  
0.7 × VCCI  
VIL  
LOW-level  
[1]  
input voltage  
-
-
-
-
-
-
-
-
-
-
0.3 × VCCI  
0.35 × VCCI  
0.7  
0.3 × VCCI  
0.35 × VCCI  
0.7  
0.3 × VCCI  
0.35 × VCCI  
0.7  
V
V
V
V
V
VCCI = 1.1 V to 1.95 V  
VCCI = 2.3 V to 2.7 V  
VCCI = 3.0 V to 3.6 V  
VCCI = 4.5 V to 5.5 V  
VI = VIH  
0.8  
0.8  
0.8  
0.3 × VCCI  
0.3 × VCCI  
0.3 × VCCI  
VOH  
HIGH-level  
[2]  
[3]  
output voltage  
IO = -0.1 mA; VCCO = 0.9 V to 5.5 V  
IO = -1.5 mA; VCCO = 1.1 V  
IO = -3 mA; VCCO = 1.4 V  
IO = -4.5 mA; VCCO = 1.65 V  
IO = -8 mA; VCCO = 2.3 V  
IO = -10 mA; VCCO = 3.0 V  
IO = -12 mA; VCCO = 4.5 V  
VCCO - 0.1  
0.825  
1.05  
1.2  
0.9  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
-
-
-
-
-
-
1.7  
2.2  
3.7  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
5 / 26  
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Symbol Parameter  
Conditions  
-40 °C to +125 °C  
Min  
+25 °C  
Max  
-40 °C to +85 °C -40 °C to +125 °C Unit  
Typ  
Max  
Max  
VOL  
LOW-level  
output voltage  
VI = VIL  
[2]  
[3]  
IO = 0.1 mA; VCCO = 0.9 V to 5.5 V  
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
0.1  
0.275  
0.35  
0.45  
0.7  
0.1  
0.275  
0.35  
0.45  
0.7  
0.1  
0.275  
0.35  
0.45  
0.7  
V
V
V
V
V
V
V
V
μA  
IO = 1.5 mA; VCCO = 1.1 V  
IO = 3 mA; VCCO = 1.4 V  
IO = 4.5 mA; VCCO = 1.65 V  
IO = 8 mA; VCCO = 2.3 V  
IO = 10 mA; VCCO = 3.0 V  
0.8  
0.8  
0.8  
IO = 8 mA; VCCO = 4.5 V  
0.5  
0.5  
0.5  
IO = 12 mA; VCCO = 4.5 V  
0.8  
0.8  
0.8  
II  
input leakage  
current  
DIR input; VI = 0 V to 5.5 V; VCCI = 0.9 V to 5.5 V  
±0.1  
±0.5  
±1  
IOZ  
OFF-state  
output current  
A or B port; VO = 0 V or VCCO; VCCO = 0.9 V to 5.5 V  
[2]  
[2]  
-
-
-
-
±0.1  
±0.1  
±0.5  
±0.5  
±2  
±2  
μA  
μA  
suspend mode A port; VO = 0 V or VCCO; VCC(A) = 5.5 V;  
VCC(B) = 0 V  
suspend mode B port; VO = 0 V or VCCO; VCC(A) = 0 V;  
VCC(B) = 5.5 V  
[2]  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1  
0.1  
±0.5  
0.5  
±2  
2
μA  
μA  
μA  
μA  
μA  
μA  
μA  
IOFF  
power-off  
DIR input; VI = 0 V to 5.5 V; VCC(A) = 0 V;  
leakage current VCC(B) = 0.9 V to 5.5 V  
A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V;  
VCC(B) = 0.9 V to 5.5 V  
0.1  
0.5  
2
B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V;  
VCC(A) = 0.9 V to 5.5 V  
0.1  
0.5  
2
ΔIOFF  
additional  
power-off  
leakage current  
DIR input; VI = 0 V or 5.5 V; VCC(A) = 0 V to 0.1 V;  
VCC(B) = 0.9 V to 5.5 V  
±0.1  
±0.1  
±0.1  
±0.5  
±0.5  
±0.5  
±2  
±2  
±2  
A port; VO = 0 V or 5.5 V; VCC(A) = 0 V to 0.1 V;  
VCC(B) = 0.9 V to 5.5 V; VI = 0 V or 5.5 V  
B port; VO = 0 V or 5.5 V; VCC(B) = 0 V to 0.1 V;  
VCC(A) = 0.9 V to 5.5 V; VI = 0 V or 5.5 V  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
6 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Symbol Parameter  
Conditions  
-40 °C to +125 °C  
Min  
+25 °C  
Max  
-40 °C to +85 °C -40 °C to +125 °C Unit  
Typ  
Max  
Max  
ICC  
supply current A port; VI = 0 V or VCCI; IO = 0 A  
VCC(A), VCC(B) = 0.9 V to 5.5 V  
VCC(A) = 5.5 V; VCC(B) = 0 V  
[1]  
-
-
-
-
-
-
2
2
5
5
13  
13  
±1  
μA  
μA  
μA  
VCC(A) = 0 V; VCC(B) = 5.5 V  
±0.1  
±0.4  
B port; VI = 0 V or VCCI; IO = 0 A  
VCC(A), VCC(B) = 0.9 V to 5.5 V  
VCC(B) = 5.5 V; VCC(A) = 0 V  
-
-
-
-
-
-
2
2
5
5
13  
13  
μA  
μA  
μA  
μA  
VCC(B) = 0 V; VCC(A) = 5.5 V  
-
±0.1  
100  
±0.4  
150  
±1  
ΔICC  
additional  
per input; other pins at VCCI or ground (0 V); IO = 0 A;  
[4]  
2
200  
supply current VCC(A), VCC(B) = 4.5 V to 5.5 V; VI = VCCI - 0.6 V  
[1] VCCI is the supply voltage associated with the control input or input port.  
[2] VCCO is the supply voltage associated with the output port.  
[3] Typical values for VOL and VOH are measured at VCCO is 0.9 V.  
[4] Typical values for ΔICC are measured at VCC(A), VCC(B) = 5 V.  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
7 / 26  
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Table 8. Typical total supply current ICC(A) at Tamb = 25 °C  
Voltages are referenced to GND (ground = 0 V).  
VCC(A)  
VCC(B)  
Unit  
0 V  
0.9 V  
0.01  
0.08  
0.10  
0.13  
0.16  
0.22  
0.29  
0.44  
1.2 V  
0.01  
0.08  
0.10  
0.13  
0.16  
0.22  
0.29  
0.44  
1.5 V  
0.01  
0.08  
0.10  
0.13  
0.16  
0.22  
0.29  
0.44  
1.8 V  
0.01  
0.08  
0.10  
0.13  
0.16  
0.22  
0.29  
0.44  
2.5 V  
0.01  
0.08  
0.10  
0.13  
0.16  
0.22  
0.29  
0.44  
3.3 V  
0.01  
0.08  
0.10  
0.13  
0.16  
0.22  
0.29  
0.44  
5.0 V  
0.01  
0.08  
0.10  
0.13  
0.16  
0.22  
0.29  
0.44  
0 V  
0.00  
0.01  
0.01  
0.01  
0.01  
0.01  
0.01  
0.01  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
0.9 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
5.0 V  
Table 9. Typical total supply current ICC(B) at Tamb = 25 °C  
Voltages are referenced to GND (ground = 0 V).  
VCC(A)  
VCC(B)  
Unit  
0 V  
0.9 V  
0.01  
0.08  
0.08  
0.08  
0.08  
0.08  
0.08  
0.08  
1.2 V  
0.01  
0.10  
0.10  
0.10  
0.10  
0.10  
0.10  
0.10  
1.5 V  
0.01  
0.13  
0.13  
0.13  
0.13  
0.13  
0.13  
0.13  
1.8 V  
0.01  
0.16  
0.16  
0.16  
0.16  
0.16  
0.16  
0.16  
2.5 V  
0.01  
0.22  
0.22  
0.22  
0.22  
0.22  
0.22  
0.22  
3.3 V  
0.01  
0.29  
0.29  
0.29  
0.29  
0.29  
0.29  
0.29  
5.0 V  
0.01  
0.44  
0.44  
0.44  
0.44  
0.44  
0.44  
0.44  
0 V  
0.00  
0.01  
0.01  
0.01  
0.01  
0.01  
0.01  
0.01  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
μA  
0.9 V  
1.2 V  
1.5 V  
1.8 V  
2.5 V  
3.3 V  
5.0 V  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
8 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
11. Dynamic characteristics  
Table 10. Typical dynamic characteristics at VCC(A) = 0.9 V and Tamb = 25 °C  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6.  
Symbol Parameter  
Conditions  
VCC(B)  
1.8 V  
16.5  
31  
Unit  
0.9 V  
40  
1.2 V  
22  
1.5 V  
18.5  
32  
2.5 V  
15  
3.3 V  
15  
5.0 V  
15  
tpd  
tdis  
ten  
propagation delay  
nA to nB  
nB to nA  
DIR to nA  
DIR to nB  
DIR to nA  
DIR to nB  
[1]  
[1]  
[1]  
[1]  
[1]  
[1]  
ns  
ns  
ns  
ns  
ns  
ns  
40  
33  
31  
31  
32  
disable time  
enable time  
34  
34  
34  
34  
34  
34  
34  
42  
30  
26  
26  
24  
25  
23  
82  
63  
58  
57  
55  
56  
55  
74  
56  
53  
51  
49  
49  
49  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
Table 11. Typical dynamic characteristics at VCC(B) = 0.9 V and Tamb = 25 °C  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6.  
Symbol Parameter  
Conditions  
VCC(A)  
1.8 V  
31  
Unit  
0.9 V  
40  
1.2 V  
33  
1.5 V  
32  
2.5 V  
31  
3.3 V  
31  
5.0 V  
32  
tpd  
tdis  
ten  
propagation delay  
nA to nB  
nB to nA  
DIR to nA  
DIR to nB  
DIR to nA  
DIR to nB  
[1]  
[1]  
[1]  
[1]  
[1]  
[1]  
ns  
ns  
40  
22  
18.5  
11  
16.5  
10  
15  
15  
15  
disable time  
enable time  
34  
16  
7.0  
27  
7.7  
27  
5.3 ns  
42  
31  
28  
28  
27  
42  
37  
ns  
ns  
ns  
82  
53  
47  
45  
42  
42  
74  
49  
43  
41  
38  
39  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
Table 12. Typical dynamic characteristics at Tamb = 25 °C  
[1][2] Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7.  
Symbol Parameter  
Conditions  
VCC(A) and VCC(B)  
0.9 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V  
Unit  
CPD  
power dissipation A port: (direction nA to nB);  
1.5  
1.6  
1.7  
1.8  
1.9  
2.2  
2.7 pF  
capacitance  
B port: (direction nB to nA)  
A port: (direction nB to nA);  
B port: (direction nA to nB)  
9.7  
10.2 10.3 10.4 10.7  
11  
11.9 pF  
CI  
input capacitance VI = 0 V or VCCI; VCCI = 0 V to 5.5 V 1.4  
1.4  
4.4  
1.4  
4.4  
1.4  
4.4  
1.4  
4.4  
1.4  
4.4  
1.4 pF  
4.4 pF  
CI/O  
input/output  
capacitance  
VO = 0 V; VCCO = 0 V  
4.4  
[1] CPD is used to determine the dynamic power dissipation (PD in μW).  
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = load capacitance in pF;  
VCC = supply voltage in V;  
N = number of inputs switching;  
Σ(CL × VCC 2 × fo) = sum of the outputs.  
[2] fi = 1 MHz; VI = GND to VCC; tr = tf = 1 ns; CL = 0 pF; RL = ∞ Ω.  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
9 / 26  
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Table 13. Dynamic characteristics for temperature range -40 °C to +85 °C  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6.  
Symbol Parameter Conditions  
VCC(B)  
1.8 V ± 0.15 V  
Unit  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5.0 V ± 0.5 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
tpd  
propagation nA to nB  
delay  
[1]  
VCC(A) = 1.2 V ± 0.1 V  
4.0  
3.5  
3.1  
2.8  
2.7  
2.7  
38  
33  
32  
31  
31  
31  
3.6  
3.0  
2.7  
2.4  
2.3  
2.2  
25  
21  
3.4  
2.8  
2.4  
2.1  
2.0  
1.9  
21  
16.5  
15  
3.1  
2.6  
2.2  
1.9  
1.8  
1.6  
16  
12.5  
11  
2.9  
2.4  
2.1  
1.7  
1.6  
1.4  
14.5  
10.5  
9.0  
2.7  
2.2  
1.9  
1.6  
1.4  
1.2  
14.5 ns  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
9.8  
8.2  
6.6  
5.8  
5.0  
ns  
ns  
ns  
ns  
ns  
19  
17.5  
17  
13.5  
13  
9.1  
8.5  
8.1  
7.5  
6.9  
16.5  
12.5  
6.4  
nB to nA  
VCC(A) = 1.2 V ± 0.1 V  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
4.0  
3.6  
3.4  
3.1  
2.9  
2.7  
38  
25  
3.5  
3.0  
2.8  
2.6  
2.4  
2.2  
33  
21  
3.1  
2.7  
2.4  
2.2  
2.1  
1.9  
32  
19  
2.8  
2.4  
2.1  
1.9  
1.7  
1.6  
31  
17.5  
13.5  
9.1  
2.7  
2.3  
2.0  
1.8  
1.6  
1.4  
31  
17  
2.7  
2.2  
1.9  
1.6  
1.4  
1.2  
31  
ns  
16.5 ns  
12.5 ns  
21  
16.5  
12.5  
10.5  
9.8  
15  
13  
16  
11  
8.5  
6.9  
5.8  
8.1  
6.4  
5.0  
ns  
ns  
ns  
14.5  
14.5  
9.0  
8.2  
7.5  
6.6  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
10 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Symbol Parameter Conditions  
VCC(B)  
1.8 V ± 0.15 V  
Unit  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5.0 V ± 0.5 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
ten  
enable time DIR to nA  
VCC(A) = 1.2 V ± 0.1 V  
[1]  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.3  
37.5  
29  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.3  
37.5  
29  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.3  
37.5  
29  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.3  
37.5  
29  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.3  
37.5  
29  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.3 ns  
37.5 ns  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
29  
19  
ns  
ns  
19  
19  
19  
19  
19  
17.3  
12  
17.3  
12  
17.3  
12  
17.3  
12  
17.3  
12  
17.3 ns  
12 ns  
DIR to nB  
VCC(A) = 1.2 V ± 0.1 V  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
8.9  
7.4  
7.1  
5.7  
6.2  
5.1  
58.3  
45.2  
42  
8.5  
6.9  
6.7  
5.3  
5.8  
4.6  
49.3  
32.5  
28.9  
25  
8.3  
6.7  
6.4  
5.0  
5.5  
4.3  
47  
8.0  
6.5  
6.2  
4.8  
5.3  
4.0  
45.8  
27.2  
23.9  
20.1  
18.6  
15.7  
7.8  
6.3  
6.1  
4.6  
5.1  
3.8  
45  
26.6  
23  
7.6  
6.1  
5.9  
4.5  
4.9  
3.6  
44.7 ns  
26 ns  
29.8  
26.2  
22.5  
21.2  
18.2  
22.5 ns  
18.4 ns  
17.1 ns  
13.9 ns  
37  
19  
37.2  
33.7  
23.8  
21  
17.7  
14.6  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
11 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Symbol Parameter Conditions  
VCC(B)  
1.8 V ± 0.15 V  
Unit  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5.0 V ± 0.5 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
tdis  
disable time DIR to nA  
VCC(A) = 1.2 V ± 0.1 V  
[1]  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31  
ns  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
17.8  
15.9  
12.9  
12.3  
9.6  
17.8  
15.9  
12.9  
12.3  
9.6  
17.8  
15.9  
12.9  
12.3  
9.6  
17.8  
15.9  
12.9  
12.3  
9.6  
17.8  
15.9  
12.9  
12.3  
9.6  
17.8 ns  
15.9 ns  
12.9 ns  
12.3 ns  
9.6  
ns  
DIR to nB  
VCC(A) = 1.2 V ± 0.1 V  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
5.6  
5.1  
4.7  
4.3  
4.2  
4.1  
36.8  
32.3  
30.9  
29  
4.8  
4.4  
4.0  
3.6  
3.5  
3.3  
27.9  
23.1  
21.5  
20  
5.1  
4.6  
4.3  
3.9  
3.7  
3.6  
26.7  
21.8  
20  
4.4  
3.8  
3.4  
3.0  
2.9  
2.7  
22.8  
17.6  
16  
5.1  
4.6  
4.2  
3.9  
3.7  
3.5  
23.5  
18.5  
15.5  
14.3  
13  
4.1  
3.6  
3.3  
2.9  
2.7  
2.5  
20.7 ns  
15.8 ns  
13.2 ns  
10.7 ns  
10.3 ns  
17.7  
16.7  
16.5  
14  
28.9  
27.8  
19  
12.6  
12.4  
18.9  
12.4  
9.4  
ns  
tt  
transition  
time  
nA, nB output  
VCC(A) = 1.1 V to 5.5 V  
1.0  
-
1.0  
-
1.0  
-
1.0  
-
1.0  
-
1.0  
-
ns  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
12 / 26  
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Table 14. Dynamic characteristics for temperature range -40 °C to +125 °C  
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 7; for waveforms see Fig. 5 and Fig. 6.  
Symbol Parameter Conditions  
VCC(B)  
1.8 V ± 0.15 V  
Unit  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5.0 V ± 0.5 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
tpd  
propagation nA to nB  
delay  
[1]  
VCC(A) = 1.2 V ± 0.1 V  
4.0  
3.5  
3.1  
2.8  
2.7  
2.7  
38  
33  
32  
31  
31  
31  
3.6  
3.0  
2.7  
2.4  
2.3  
2.2  
26  
22  
3.4  
2.8  
2.4  
2.1  
2.0  
1.9  
22  
17.5  
16  
3.1  
2.6  
2.2  
1.9  
1.8  
1.6  
17  
13.5  
12  
2.9  
2.4  
2.1  
1.7  
1.6  
1.4  
15  
11.5  
9.7  
8.1  
7.5  
6.9  
2.7  
2.2  
1.9  
1.6  
1.4  
1.2  
15  
ns  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
10.5 ns  
20  
9.4  
7.1  
6.3  
5.5  
ns  
ns  
ns  
ns  
18.5  
18  
14.5  
14  
9.8  
9.2  
8.8  
17.5  
13.5  
nB to nA  
VCC(A) = 1.2 V ± 0.1 V  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
4.0  
3.6  
3.4  
3.1  
2.9  
2.7  
38  
26  
22  
17  
15  
15  
3.5  
3.0  
2.8  
2.6  
2.4  
2.2  
33  
3.1  
2.7  
2.4  
2.2  
2.1  
1.9  
32  
20  
2.8  
2.4  
2.1  
1.9  
1.7  
1.6  
31  
18.5  
14.5  
9.8  
2.7  
2.3  
2.0  
1.8  
1.6  
1.4  
31  
18  
2.7  
2.2  
1.9  
1.6  
1.4  
1.2  
31  
ns  
22  
17.5 ns  
13.5 ns  
17.5  
13.5  
11.5  
10.5  
16  
14  
12  
9.2  
7.5  
6.3  
8.8  
6.9  
5.5  
ns  
ns  
ns  
9.7  
9.4  
8.1  
7.1  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
13 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Symbol Parameter Conditions  
VCC(B)  
1.8 V ± 0.15 V  
Unit  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5.0 V ± 0.5 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
ten  
enable time DIR to nA  
VCC(A) = 1.2 V ± 0.1 V  
[1]  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.6  
38  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.6  
38  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.6  
38  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.6  
38  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.6  
38  
9.6  
7.4  
6.7  
4.9  
5.3  
3.7  
67.6 ns  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
38  
ns  
30.2  
19.9  
17.9  
12.2  
30.2  
19.9  
17.9  
12.2  
30.2  
19.9  
17.9  
12.2  
30.2  
19.9  
17.9  
12.2  
30.2  
19.9  
17.9  
12.2  
30.2 ns  
19.9 ns  
17.9 ns  
12.2 ns  
DIR to nB  
VCC(A) = 1.2 V ± 0.1 V  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
8.9  
7.4  
7.1  
5.7  
6.2  
5.1  
58.6  
45.9  
42.5  
37.6  
37.5  
34.1  
8.5  
6.9  
6.7  
5.3  
5.8  
4.6  
49.8  
33.3  
30  
8.3  
6.7  
6.4  
5.0  
5.5  
4.3  
47.3  
30  
8.0  
6.5  
6.2  
4.8  
5.3  
4.0  
46  
7.8  
6.3  
6.1  
4.6  
5.1  
3.8  
45.5  
26.8  
24  
7.6  
6.1  
5.9  
4.5  
4.9  
3.6  
44.9 ns  
26.3 ns  
27.8  
24.5  
20.3  
18.9  
15.9  
27  
23  
ns  
25.2  
24.8  
21.5  
22.7  
21.5  
18.5  
19.2  
18  
18.5 ns  
17.3 ns  
14.8  
14  
ns  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
14 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Symbol Parameter Conditions  
VCC(B)  
1.8 V ± 0.15 V  
Unit  
1.2 V ± 0.1 V  
1.5 V ± 0.1 V  
2.5 V ± 0.2 V  
3.3 V ± 0.3 V  
5.0 V ± 0.5 V  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
tdis  
disable time DIR to nA  
VCC(A) = 1.2 V ± 0.1 V  
[1]  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31.2  
18  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31.2  
18  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31.2  
18  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31.2  
18  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31.2  
18  
4.9  
3.9  
4.0  
2.9  
3.5  
2.4  
31.2 ns  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
18  
16  
13  
ns  
ns  
ns  
16  
16  
16  
16  
16  
13  
13  
13  
13  
13  
12.4  
9.7  
12.4  
9.7  
12.4  
9.7  
12.4  
9.7  
12.4  
9.7  
12.4 ns  
9.7  
ns  
DIR to nB  
VCC(A) = 1.2 V ± 0.1 V  
VCC(A) = 1.5 V ± 0.1 V  
VCC(A) = 1.8 V ± 0.15 V  
VCC(A) = 2.5 V ± 0.2 V  
VCC(A) = 3.3 V ± 0.3 V  
VCC(A) = 5.0 V ± 0.5 V  
5.6  
5.1  
4.7  
4.3  
4.2  
4.1  
37  
4.8  
4.4  
4.0  
3.6  
3.5  
3.3  
28.3  
23.6  
22  
5.1  
4.6  
4.3  
3.9  
3.7  
3.6  
27.1  
22  
4.4  
3.8  
3.4  
3.0  
2.9  
2.7  
23.2  
18  
5.1  
4.6  
4.2  
3.9  
3.7  
3.5  
23.8  
18.7  
15.6  
14.4  
13.1  
12.5  
4.1  
3.6  
3.3  
2.9  
2.7  
2.5  
21  
16  
ns  
ns  
32.6  
31.1  
29.8  
29.1  
28  
20.1  
17.9  
16.9  
16.7  
16.1  
14.1  
12.9  
12.5  
13.4 ns  
10.9 ns  
10.4 ns  
20.2  
19.1  
19  
9.5  
ns  
tt  
transition  
time  
nA, nB output  
VCC(A) = 1.1 V to 5.5 V  
1.0  
-
1.0  
-
1.0  
-
1.0  
-
1.0  
-
1.0  
-
ns  
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH  
.
©
74AXP2T45  
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Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
15 / 26  
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
11.1. Waveforms and test circuit  
V
I
V
nA, nB input  
GND  
M
t
t
PLH  
PHL  
V
OH  
nB, nA output  
V
M
001aak114  
V
OL  
Measurement points are given in Table 15.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 5. The data input (nA, nB) to output (nB, nA) propagation delay times  
V
I
V
DIR input  
M
GND  
t
t
PZL  
PLZ  
V
CCO  
A output  
LOW-to-OFF  
OFF-to-LOW  
V
V
M
M
V
V
X
Y
V
OL  
t
t
PZH  
PHZ  
V
OH  
A output  
HIGH-to-OFF  
OFF-to-HIGH  
GND  
t
t
PZL  
PLZ  
PHZ  
V
CCO  
B output  
LOW-to-OFF  
OFF-to-LOW  
V
V
M
M
V
V
X
Y
V
OL  
t
t
PZH  
V
OH  
B output  
HIGH-to-OFF  
OFF-to-HIGH  
GND  
aaa-029961  
Measurement points are given in Table 15.  
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig. 6. Enable and disable times  
Table 15. Measurement points  
Supply voltage  
VCC(A), VCC(B)  
0.9 V to 1.6 V  
1.65 V to 2.7 V  
3.0 V to 5.5 V  
Input [1]  
Output [2]  
VM  
VM  
VX  
VY  
0.5 × VCCI  
0.5 × VCCI  
0.5 × VCCI  
0.5 × VCCO  
0.5 × VCCO  
0.5 × VCCO  
VOL + 0.1 V  
VOL + 0.15 V  
VOL + 0.3 V  
VOH - 0.1 V  
VOH - 0.15 V  
VOH - 0.3 V  
[1] VCCI is the supply voltage associated with the control input or input port.  
[2] VCCO is the supply voltage associated with the output port.  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
16 / 26  
 
 
 
 
 
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
t
W
V
I
90 %  
negative  
pulse  
V
V
V
M
M
10 %  
0 V  
t
t
r
f
t
t
f
r
V
I
90 %  
positive  
pulse  
V
M
M
10 %  
0 V  
t
W
V
EXT  
R
V
CC  
L
V
V
I
O
G
DUT  
R
T
C
L
R
L
001aae331  
Test data is given in Table 16.  
RL = Load resistance;  
CL = Load capacitance including jig and probe capacitance;  
RT = Termination resistance;  
VEXT = External voltage for measuring switching times.  
Fig. 7. Test circuit for measuring switching times  
Table 16. Test data  
Supply voltage  
VCC(A), VCC(B)  
0.9 V to 5.5 V  
Load  
CL  
Input  
tr, tf  
VEXT  
RL  
VI [1]  
tPLH, tPHL  
GND  
tPZH, tPHZ  
tPZL, tPLZ [2]  
5 pF  
10 kΩ  
≤3.0 ns  
VCCI  
GND  
2 × VCCO  
[1] VCCI is the supply voltage associated with the control input or input port.  
[2] VCCO is the supply voltage associated with the output port.  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
17 / 26  
 
 
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
11.2. Additional propagation delay versus load capacitance graphs  
aaa-029962  
aaa-029963  
6
8
6
4
2
0
t
pd  
(ns)  
(3)  
t
pd  
(ns)  
5
4
3
2
1
0
(3)  
(2)  
(1)  
(2)  
(1)  
0
20  
40  
60  
80  
C
100  
(pF)  
0
20  
40  
60  
80 100  
C (pF)  
L
L
Tamb = -40 °C to +125 °C  
For tPLH, tPHL, tPZH and tPZL  
(1) Minimum: VCCO = 5.5 V  
Tamb = -40 °C to +125 °C  
For tPLH, tPHL, tPZH and tPZL  
(1) Minimum: VCCO = 3.6 V  
(2) Typical: Tamb = 25 °C; VCCO = 5 V  
(3) Maximum: VCCO = 4.5 V  
(2) Typical: Tamb = 25 °C; VCCO = 3.3 V  
(3) Maximum: VCCO = 3 V  
Fig. 8. Additional propagation delay versus load  
capacitance  
Fig. 9. Additional propagation delay versus load  
capacitance  
aaa-029964  
aaa-029965  
10  
12  
t
pd  
(ns)  
t
(3)  
pd  
(ns)  
10  
8
(3)  
8
6
4
2
0
6
(2)  
(1)  
(2)  
4
(1)  
2
0
0
20  
40  
60  
80  
100  
(pF)  
0
20  
40  
60  
80  
100  
C (pF)  
L
C
L
Tamb = -40 °C to +125 °C  
For tPLH, tPHL, tPZH and tPZL  
(1) Minimum: VCCO = 2.7 V  
Tamb = -40 °C to +125 °C  
For tPLH, tPHL, tPZH and tPZL  
(1) Minimum: VCCO = 1.95 V  
(2) Typical: Tamb = 25 °C; VCCO = 2.5 V  
(3) Maximum: VCCO = 2.3 V  
(2) Typical: Tamb = 25 °C; VCCO = 1.8 V  
(3) Maximum: VCCO = 1.65 V  
Fig. 10. Additional propagation delay versus load  
capacitance  
Fig. 11. Additional propagation delay versus load  
capacitance  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
18 / 26  
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
aaa-029966  
aaa-029967  
16  
30  
t
pd  
(ns)  
t
pd  
(ns)  
(3)  
25  
(3)  
12  
20  
15  
10  
5
(2)  
(1)  
8
4
0
(2)  
(1)  
0
0
20  
40  
60  
80  
100  
(pF)  
0
20  
40  
60  
80  
100  
C (pF)  
L
C
L
Tamb = -40 °C to +125 °C  
For tPLH, tPHL, tPZH and tPZL  
(1) Minimum: VCCO = 1.6 V  
Tamb = -40 °C to +125 °C  
For tPLH, tPHL, tPZH and tPZL  
(1) Minimum: VCCO = 1.3 V  
(2) Typical: Tamb = 25 °C; VCCO = 1.5 V  
(3) Maximum: VCCO = 1.4 V  
(2) Typical: Tamb = 25 °C; VCCO = 1.2 V  
(3) Maximum: VCCO = 1.1 V  
Fig. 12. Additional propagation delay versus load  
capacitance  
Fig. 13. Additional propagation delay versus load  
capacitance  
aaa-029968  
32  
t
pd  
(ns)  
24  
16  
8
0
0
20  
40  
60  
80  
C
100  
(pF)  
L
Tamb = 25 °C; VCCO = 0.9 V  
For tPLH, tPHL, tPZH and tPZL  
Fig. 14. Additional propagation delay versus load capacitance  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
19 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
12. Application information  
12.1. Unidirectional logic level-shifting application  
The circuit given in Fig. 15 is an example of the 74AXP2T45 being used in an unidirectional logic  
level-shifting application.  
V
V
CC2  
CC1  
V
V
CC(B)  
CC(A)  
1A  
V
V
V
CC1  
CC1  
CC2  
CC2  
1
2
3
4
8
7
6
5
1B  
74AXP2T45  
2A  
2B  
DIR  
GND  
V
system-1  
system-2  
aaa-029973  
Fig. 15. Unidirectional logic level-shifting application  
Table 17. Unidirectional logic level-shifting application  
Pin  
1
Name  
VCC(A)  
1A  
Function  
VCC1  
OUT1  
OUT2  
GND  
DIR  
Description  
supply voltage of system-1 (0.9 V to 5.5 V)  
output level depends on VCC1 voltage  
output level depends on VCC1 voltage  
device GND  
2
3
2A  
4
GND  
DIR  
5
the GND (LOW level) determines B port to A port direction  
input threshold value depends on VCC2 voltage  
input threshold value depends on VCC2 voltage  
supply voltage of system-2 (0.9 V to 5.5 V)  
6
2B  
IN2  
7
1B  
IN1  
8
VCC(B)  
VCC2  
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74AXP2T45  
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Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
20 / 26  
 
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
12.2. Bidirectional logic level-shifting application  
Fig. 16 shows the 74AXP2T45 being used in a bidirectional logic level-shifting application. Since  
the device does not have an output enable (OE) pin, the system designer should take precautions  
to avoid bus contention between system-1 and system-2 when changing directions.  
V
V
V
V
CC2  
CC1  
CC1  
CC2  
V
V
CC(B)  
CC(A)  
1A  
I/O-1  
PULL-UP/DOWN  
PULL-UP/DOWN  
I/O-2  
1
2
3
4
8
7
6
5
1B  
74AXP2T45  
2A  
2B  
GND  
DIR  
DIR CTRL  
DIR CTRL  
system-1  
system-2  
aaa-029974  
System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.  
Fig. 16. Bidirectional logic level-shifting application  
Table 18 gives a sequence that will illustrate data transmission from system-1 to system-2 and then  
from system-2 to system-1.  
Table 18. Bidirectional logic level-shifting application [1] [2]  
State DIR CTRL I/O-1  
I/O-2  
input  
Z
Description  
1
2
H
H
output  
Z
system-1 data to system-2  
system-2 is getting ready to send data to system-1.  
I/O-1 and I/O-2 are disabled. The bus-line state  
depends on the pull-up or pull-down.  
3
4
L
L
Z
Z
DIR bit is set LOW. I/O-1 and I/O-2 still are disabled.  
The bus-line state depends on the pull-up or pull-down.  
input  
output  
system-2 data to system-1  
[1] System-1 and system-2 must use the same conditions, i.e., both pull-up or both pull-down.  
[2] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.  
12.3. Enable times  
Calculate the enable times for the 74AXP2T45 using the following formulas:  
Direction A to B:  
tPZL (DIR to B) = tPHL (A to B) + tPHZ (DIR to A)  
tPZH (DIR to B) = tPLH (A to B) + tPLZ (DIR to A)  
Direction B to A:  
tPZL (DIR to A) = tPHL (B to A) + tPHZ (DIR to B)  
tPZH (DIR to A) = tPLH (B to A) + tPLZ (DIR to B)  
In a bidirectional application, these enable times provide the maximum delay from the time  
the DIR bit is switched until an output is expected. For example, if the 74AXP2T45 initially is  
transmitting from A to B, then the DIR bit is switched, the B port of the device must be disabled  
before presenting it with an input. After the B port has been disabled, an input signal applied to it  
appears on the corresponding A port after the specified propagation delay.  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
21 / 26  
 
 
 
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
13. Package outline  
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm  
SOT765-1  
D
E
A
X
c
y
H
E
v
A
Z
5
8
Q
A
2
A
A
(A )  
3
1
pin 1 index  
θ
L
p
detail X  
1
4
L
e
w
b
p
0
5 mm  
scale  
Dimensions (mm are the original dimensions)  
A
(1)  
(2)  
(1)  
Unit  
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.  
max  
mm nom  
min  
0.15 0.85  
0.00 0.60  
0.27 0.23 2.1 2.4  
0.17 0.08 1.9 2.2  
3.2  
3.0  
0.40 0.21  
0.15 0.19  
0.4  
8°  
0°  
1
0.12  
0.5  
0.4  
0.2 0.08 0.1  
0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.  
sot765-1_po  
References  
Outline  
version  
European  
projection  
Issue date  
IEC  
JEDEC  
JEITA  
07-06-02  
16-05-31  
SOT765-1  
MO-187  
Fig. 17. Package outline SOT765-1 (VSSOP8)  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
22 / 26  
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
X2SON8: plastic thermal enhanced extremely thin small outline package; no leads;  
8 terminals; body 1.35 x 0.8 x 0.32 mm  
SOT1233-2  
C
Seating  
Plane  
X
y
C
A
B
D
E
A
A
3
u
C
A
detail X  
1
2x  
pin 1  
index area  
u
C
2x  
e
e
b
(6x)  
y
C
1
v
w
C
C
A
B
1
2
3
pin 1  
index area  
8
4
D
h
L
(6x)  
7
6
5
b
1
(6x)  
e
1
0
1 mm  
scale  
Dimensions (mm are the original dimensions)  
Unit  
A
A
A
b
b
D
D
h
E
e
e
L
u
v
w
y
y
1
1
3
1
1
max 0.35 0.04  
0.25  
0.20  
0.15  
0.27  
1.35 0.22 0.80 0.50 0.54 0.22 0.05 0.10 0.05 0.05 0.05  
0.17 0.17  
0.27  
0.10  
(Typ.)  
0.11  
(ref)  
nom  
min  
mm  
0.32 0.02  
0.30 0.00  
sot1233-2_po  
Issue date  
19-11-12  
References  
Outline  
version  
European  
projection  
IEC  
JEDEC  
- - -  
JEITA  
SOT1233-2  
Fig. 18. Package outline SOT1233-2 (X2SON8)  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
23 / 26  
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
14. Abbreviations  
Table 19. Abbreviations  
Acronym  
CDM  
Description  
Charged Device Model  
Device Under Test  
DUT  
ESD  
ElectroStatic Discharge  
Human Body Model  
HBM  
15. Revision history  
Table 20. Revision history  
Document ID  
74AXP2T45 v.2  
Modifications  
Release date  
20220623  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
74AXP2T45 v.1  
Package SOT1233 (X2SON8) changed to SOT1233-2 (X2SON8).  
74AXP2T45 v.1  
20200319 Product data sheet  
-
-
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
24 / 26  
 
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
injury, death or severe property or environmental damage. Nexperia and its  
suppliers accept no liability for inclusion and/or use of Nexperia products in  
such equipment or applications and therefore such inclusion and/or use is at  
the customer’s own risk.  
16. Legal information  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Data sheet status  
Document status Product  
Definition  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no representation  
or warranty that such applications will be suitable for the specified use  
without further testing or modification.  
[1][2]  
status [3]  
Objective [short]  
data sheet  
Development  
This document contains data from  
the objective specification for  
product development.  
Customers are responsible for the design and operation of their applications  
and products using Nexperia products, and Nexperia accepts no liability for  
any assistance with applications or customer product design. It is customer’s  
sole responsibility to determine whether the Nexperia product is suitable  
and fit for the customer’s applications and products planned, as well as  
for the planned application and use of customer’s third party customer(s).  
Customers should provide appropriate design and operating safeguards to  
minimize the risks associated with their applications and products.  
Preliminary [short]  
data sheet  
Qualification  
Production  
This document contains data from  
the preliminary specification.  
Product [short]  
data sheet  
This document contains the product  
specification.  
[1] Please consult the most recently issued document before initiating or  
completing a design.  
Nexperia does not accept any liability related to any default, damage, costs  
or problem which is based on any weakness or default in the customer’s  
applications or products, or the application or use by customer’s third party  
customer(s). Customer is responsible for doing all necessary testing for the  
customer’s applications and products using Nexperia products in order to  
avoid a default of the applications and the products or of the application or  
use by customer’s third party customer(s). Nexperia does not accept any  
liability in this respect.  
[2] The term 'short data sheet' is explained in section "Definitions".  
[3] The product status of device(s) described in this document may have  
changed since this document was published and may differ in case of  
multiple devices. The latest product status information is available on  
the internet at https://www.nexperia.com.  
Definitions  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those  
given in the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. Nexperia does not give any representations or  
warranties as to the accuracy or completeness of information included herein  
and shall have no liability for the consequences of use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is  
intended for quick reference only and should not be relied upon to contain  
detailed and full information. For detailed and full information see the relevant  
full data sheet, which is available on request via the local Nexperia sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of commercial sale — Nexperia products are  
sold subject to the general terms and conditions of commercial sale, as  
published at http://www.nexperia.com/profile/terms, unless otherwise agreed  
in a valid written individual agreement. In case an individual agreement is  
concluded only the terms and conditions of the respective agreement shall  
apply. Nexperia hereby expressly objects to applying the customer’s general  
terms and conditions with regard to the purchase of Nexperia products by  
customer.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
Nexperia and its customer, unless Nexperia and customer have explicitly  
agreed otherwise in writing. In no event however, shall an agreement be  
valid in which the Nexperia product is deemed to offer functions and qualities  
beyond those described in the Product data sheet.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
Disclaimers  
Limited warranty and liability — Information in this document is believed  
to be accurate and reliable. However, Nexperia does not give any  
representations or warranties, expressed or implied, as to the accuracy  
or completeness of such information and shall have no liability for the  
consequences of use of such information. Nexperia takes no responsibility  
for the content in this document if provided by an information source outside  
of Nexperia.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific Nexperia product is automotive qualified, the  
product is not suitable for automotive use. It is neither qualified nor tested in  
accordance with automotive testing or application requirements. Nexperia  
accepts no liability for inclusion and/or use of non-automotive qualified  
products in automotive equipment or applications.  
In no event shall Nexperia be liable for any indirect, incidental, punitive,  
special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal  
or replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards,  
customer (a) shall use the product without Nexperia’s warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
Nexperia’s specifications such use shall be solely at customer’s own risk,  
and (c) customer fully indemnifies Nexperia for any liability, damages or failed  
product claims resulting from customer design and use of the product for  
automotive applications beyond Nexperia’s standard warranty and Nexperia’s  
product specifications.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, Nexperia’s aggregate and cumulative liability towards customer  
for the products described herein shall be limited in accordance with the  
Terms and conditions of commercial sale of Nexperia.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Right to make changes — Nexperia reserves the right to make changes  
to information published in this document, including without limitation  
specifications and product descriptions, at any time and without notice. This  
document supersedes and replaces all information supplied prior to the  
publication hereof.  
Trademarks  
Suitability for use — Nexperia products are not designed, authorized or  
warranted to be suitable for use in life support, life-critical or safety-critical  
systems or equipment, nor in applications where failure or malfunction  
of an Nexperia product can reasonably be expected to result in personal  
Notice: All referenced brands, product names, service names and  
trademarks are the property of their respective owners.  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
25 / 26  
 
Nexperia  
74AXP2T45  
2-bit dual supply translating transceiver; 3-state  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................2  
4. Marking..........................................................................2  
5. Functional diagram.......................................................2  
6. Pinning information......................................................3  
6.1. Pinning.........................................................................3  
6.2. Pin description.............................................................3  
7. Functional description................................................. 3  
8. Limiting values............................................................. 4  
9. Recommended operating conditions..........................4  
10. Static characteristics..................................................5  
11. Dynamic characteristics.............................................9  
11.1. Waveforms and test circuit.......................................16  
11.2. Additional propagation delay versus load  
capacitance graphs............................................................ 18  
12. Application information........................................... 20  
12.1. Unidirectional logic level-shifting application............20  
12.2. Bidirectional logic level-shifting application..............21  
12.3. Enable times............................................................21  
13. Package outline........................................................ 22  
14. Abbreviations............................................................24  
15. Revision history........................................................24  
16. Legal information......................................................25  
© Nexperia B.V. 2022. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 23 June 2022  
©
74AXP2T45  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2022. All rights reserved  
Product data sheet  
Rev. 2 — 23 June 2022  
26 / 26  

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