74AUP1T00GW [NEXPERIA]
Low-power 2-input NAND gate with voltage-level translator;
| 型号： | 74AUP1T00GW |
| 厂家： | 
Nexperia |
| 描述： | Low-power 2-input NAND gate with voltage-level translator |
| 文件： | 总15页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
Rev. 1 — 23 November 2017
Product data sheet
1 General description
The 74AUP1T00 provides the single 2-input NAND function. This device ensures a
very low static and dynamic power consumption across the entire VCC range from
2.3 V to 3.6 V.
The 74AUP1T00 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
2 Features and benefits
• Wide supply voltage range from 2.3 V to 3.6 V
• High noise immunity
• ESD protection:
– HBM JESD22-A114F Class 3A exceeds 5000 V
– CDM JESD22-C101E exceeds 1000 V
• Low static power consumption; ICC = 1.5 μA (maximum)
• Latch-up performance exceeds 100 mA per JESD 78 Class II
• Inputs accept voltages up to 3.6 V
• Low noise overshoot and undershoot < 10 % of VCC
• IOFF circuitry provides partial power-down mode operation
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
3 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Temperature
range
Name
Description
Version
74AUP1T00GW -40 °C to +125 °C TSSOP5
74AUP1T00GX -40 °C to +125 °C X2SON5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
SOT1226
X2SON5: plastic thermal enhanced extremely
thin small outline package; no leads; 5 terminals;
body 0.8 × 0.8 × 0.35 mm
4 Marking
Table 2.ꢀMarking
Type number
Marking code [1]
74AUP1T00GW
74AUP1T00GX
5a
5a
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5 Functional diagram
1
2
B
A
B
1
2
&
Y
4
4
Y
A
aaa-027680
aaa-027681
aaa-027682
Figure 1.ꢀLogic symbol
Figure 2.ꢀIEC logic symbol
Figure 3.ꢀLogic diagram
6 Pinning information
6.1 Pinning
74AUP1T00
74AUP1T00
B
A
1
5
4
V
Y
CC
1
2
3
5
4
B
A
V
Y
CC
3
GND
2
GND
aaa-027685
Transparent top view
aaa-027684
Figure 4.ꢀPin configuration SOT353-1
Figure 5.ꢀPin configuration SOT1226 (X2SON5)
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
2 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
6.2 Pin description
Table 3.ꢀPin description
Symbol
Pin
1
Description
data input
B
A
2
data input
GND
Y
3
ground (0 V)
data output
supply voltage
4
VCC
5
7 Functional description
Table 4.ꢀFunction table [1]
Input
Output
A
L
B
L
Y
H
H
H
L
L
H
L
H
H
H
[1] H = HIGH voltage level;
L = LOW voltage level.
8 Limiting values
Table 5.ꢀLimiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-50
-0.5
-
Max
+4.6
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
[1]
VI
+4.6
-
IOK
VO
IO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
±20
50
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
-
storage temperature
total power dissipation
+150
250
[2]
Tamb = -40 °C to +125 °C
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP5 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K.
For X2SON5 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
3 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
9 Recommended operating conditions
Table 6.ꢀRecommended operating conditions
Symbol Parameter
Conditions
Min
2.3
0
Max
3.6
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
-40
+125
°C
10 Static characteristics
Table 7.ꢀStatic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 25 °C
Conditions
Min
Typ
Max
Unit
VT+
VT-
VH
positive-going threshold
VCC = 2.3 V to 2.7 V
0.60
0.75
0.35
0.50
-
-
-
-
1.10
1.16
0.60
0.85
V
V
V
V
voltage
VCC = 3.0 V to 3.6 V
negative-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
0.23
0.25
-
-
0.60
0.56
V
V
VCC = 3.0 V to 3.6 V
VOH
HIGH-level output voltage
VI = VT+ or VT-
IO = -20 μA; VCC = 2.3 V to 3.6 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
VI = VT+ or VT-
VCC - 0.1
2.05
1.9
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
2.72
2.6
VOL
LOW-level output voltage
IO = 20 μA; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.10
0.31
0.44
0.31
0.44
±0.1
±0.1
±0.1
V
V
V
V
V
II
input leakage current
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.2
μA
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
4 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
Symbol Parameter
Conditions
Min
Typ
0.8
1.7
Max
Unit
pF
CI
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
-
-
-
-
CO
pF
Tamb = -40 °C to +85 °C
VT+
VT-
VH
positive-going threshold
VCC = 2.3 V to 2.7 V
0.60
0.75
0.35
0.50
-
-
-
-
1.10
1.19
0.60
0.85
V
V
V
V
voltage
VCC = 3.0 V to 3.6 V
negative-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
0.10
0.15
-
-
0.60
0.56
V
V
VCC = 3.0 V to 3.6 V
VOH
HIGH-level output voltage
VI = VT+ or VT-
IO = -20 μA; VCC = 2.3 V to 3.6 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
VI = VT+ or VT-
VCC - 0.1
1.97
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
1.85
2.67
2.55
VOL
LOW-level output voltage
IO = 20 μA; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
V
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.5
V
V
V
V
II
input leakage current
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
1.5
μA
[1]
[2]
ΔICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
VCC = 3.0 V to 3.6 V; IO = 0 A
-
-
-
-
0.6
10
μA
μA
74AUP1T00
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
5 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = -40 °C to +125 °C
VT+
VT-
VH
positive-going threshold
VCC = 2.3 V to 2.7 V
0.60
0.75
0.33
0.46
-
-
-
-
1.10
1.19
0.64
0.85
V
V
V
V
voltage
VCC = 3.0 V to 3.6 V
negative-going threshold
voltage
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
hysteresis voltage
(VH = VT+ - VT-)
VCC = 2.3 V to 2.7 V
0.10
0.15
-
-
0.60
0.56
V
V
VCC = 3.0 V to 3.6 V
VOH
HIGH-level output voltage
VI = VT+ or VT-
IO = -20 μA; VCC = 2.3 V to 3.6 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
VI = VT+ or VT-
VCC - 0.11
1.77
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
1.67
2.40
2.30
VOL
LOW-level output voltage
IO = 20 μA; VCC = 2.3 V to 3.6 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
0.36
V
V
0.50
V
0.36
V
0.50
V
II
input leakage current
±0.75
±0.75
±0.75
μA
μA
μA
IOFF
ΔIOFF
power-off leakage current
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 2.3 V to 3.6 V
-
-
3.5
μA
[1]
[2]
ΔICC
additional supply current
VCC = 2.3 V to 2.7 V; IO = 0 A
VCC = 3.0 V to 3.6 V; IO = 0 A
-
-
-
-
1.8
18
μA
μA
[1] One input at 0.3 V or 1.1 V, other input at VCC or GND.
[2] One input at 0.45 V or 1.2 V, other input at VCC or GND.
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
6 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
11 Dynamic characteristics
Table 8.ꢀDynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7.
Symbol Parameter
Conditions
25 °C
-40 °C to +125 °C
Unit
Min
Typ [1]
Max
Min
Max
Max
(85 °C) (125 °C)
VCC = 2.3 V to 2.7 V; VI = 1.65 V to 1.95 V
[2]
[2]
[2]
[2]
[2]
tpd
propagation
delay
A, B to Y; see Figure 6
CL = 5 pF
1.9
2.4
2.8
3.8
3.4
3.9
4.4
5.6
5.3
6.0
6.6
8.0
0.5
1.0
1.0
1.5
6.8
7.9
7.5
8.7
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
8.7
9.6
CL = 30 pF
10.8
11.9
VCC = 2.3 V to 2.7 V; VI = 2.3 V to 2.7 V
tpd
propagation
delay
A, B to Y; see Figure 6
CL = 5 pF
1.4
1.9
2.3
3.4
3.2
3.8
4.3
5.5
5.3
6.0
6.6
8.0
0.5
1.0
1.0
1.5
6.0
7.1
6.6
7.9
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
7.9
8.7
CL = 30 pF
10.0
11.0
VCC = 2.3 V to 2.7 V; VI = 3.0 V to 3.6 V
tpd
propagation
delay
A, B to Y; see Figure 6
CL = 5 pF
1.2
1.6
2.1
3.1
3.0
3.5
4.0
5.2
4.8
5.5
6.1
7.5
0.5
1.0
1.0
1.5
5.5
6.5
7.4
9.5
6.1
7.2
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
8.2
CL = 30 pF
10.5
VCC = 3.0 V to 3.6 V; VI = 1.65 V to 1.95 V
tpd
propagation
delay
A, B to Y; see Figure 6
CL = 5 pF
1.9
2.3
2.6
3.4
2.8
3.4
3.8
5.0
3.9
4.7
5.3
6.8
0.5
1.0
1.0
1.5
8.0
8.5
9.1
9.8
9.0
9.4
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
10.1
10.8
CL = 30 pF
VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V
tpd
propagation
delay
A, B to Y; see Figure 6
CL = 5 pF
1.4
1.9
2.3
3.3
2.7
3.3
3.7
4.9
4.2
4.9
5.5
6.8
0.5
1.0
1.0
1.5
5.3
6.1
6.8
8.5
5.9
6.8
7.5
9.4
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
CL = 30 pF
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
7 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
Symbol Parameter
Conditions
25 °C
-40 °C to +125 °C
Unit
Min
Typ [1]
Max
Min
Max
Max
(85 °C) (125 °C)
VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V
[2]
tpd
propagation
delay
A, B to Y; see Figure 6
CL = 5 pF
1.0
1.6
2.0
3.0
2.6
3.2
3.7
4.8
4.3
5
0.5
1.0
1.0
1.5
4.7
5.7
6.2
7.8
5.2
6.3
6.9
8.6
ns
ns
ns
ns
CL = 10 pF
CL = 15 pF
5.6
6.9
CL = 30 pF
Tamb = 25 °C
CPD power
[3]
fi = 1 MHz; VI = GND to VCC
VCC = 2.3 V to 2.7 V
dissipation
-
-
4
5
-
-
-
-
-
-
-
-
pF
pF
capacitance
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC2 x fi x N + Σ(CL x VCC2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL x VCC2 x fo) = sum of the outputs.
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
8 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
11.1 Waveforms and test circuit
V
I
V
A, B input
GND
M
t
t
PHL
PLH
V
OH
V
Y output
M
mna612
V
OL
Measurement points are given in Table 9
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 6.ꢀInput A and B to output Y propagation delay times
Table 9.ꢀMeasurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
1.65 V to 3.6 V
tr = tf
2.3 V to 3.6 V
0.5 × VCC
0.5 × VI
≤ 3.0 ns
V
V
EXT
CC
5 kΩ
V
I
V
O
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Figure 7.ꢀTest circuit for measuring switching times
Table 10.ꢀTest data
Supply voltage
VCC
Load
VEXT
[1]
CL
RL
5 kΩ or 1 MΩ
tPLH, tPHL
open
tPZH, tPHZ
GND
tPZL, tPLZ
2.3 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ.
For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
9 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
12 Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
E
A
X
c
y
H
v
M
A
E
Z
5
4
A
2
A
(A )
3
A
1
θ
L
L
p
1
3
e
w
M
b
p
detail X
e
1
0
1.5
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
A
A
A
b
c
D
E
e
e
1
H
L
L
p
UNIT
θ
v
w
y
Z
1
2
3
p
E
max.
0.1
0
1.0
0.8
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
2.25
2.0
0.46
0.21
0.60
0.15
7°
0°
mm
1.1
0.65
1.3
0.425
0.3
0.1
0.1
0.15
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
00-09-01
03-02-19
SOT353-1
MO-203
SC-88A
Figure 8.ꢀPackage outline SOT353-1 (TSSOP5)
74AUP1T00
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
10 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
X2SON5: plastic thermal enhanced extremely thin small outline package; no leads;
5 terminals; body 0.8 x 0.8 x 0.35 mm
SOT1226
D
A
B
X
A
E
A
1
A
3
detail X
terminal 1
index area
e
C
B
A
v
w
C
C
b
y
y
C
1
1
2
terminal 1
index area
3
h
D
k
L
5
4
0
1 mm
scale
v
Dimensions
Unit
max 0.35 0.04 0.128 0.85 0.30 0.85 0.27
(1)
A
A
A
D
D
h
E
b
e
k
L
w
y
y
1
1
3
0.27
0.22
nom
min
0.80 0.25 0.80 0.22
0.040 0.75 0.20 0.75 0.17
mm
0.48
0.1 0.05 0.05 0.05
0.20 0.17
Note
1. Dimension A is including plating thickness.
2. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
sot1226_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
EIAJ
12-04-10
12-04-25
SOT1226
Figure 9.ꢀPackage outline SOT1226 (X2SON5)
74AUP1T00
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© Nexperia B.V. 2017. All rights reserved.
Product data sheet
Rev. 1 — 23 November 2017
11 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
13 Abbreviations
Table 11.ꢀAbbreviations
Acronym
CDM
Description
Charged Device Model
CMOS
DUT
Complementary Metal-Oxide Semiconductor
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
14 Revision history
Table 12.ꢀRevision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP1T00 v.1
20171123
Product data sheet
-
-
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Product data sheet
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12 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
15 Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.
systems or equipment, nor in applications where failure or malfunction
of an Nexperia product can reasonably be expected to result in personal
15.2 Definitions
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
Draft — The document is a draft version only. The content is still under
such equipment or applications and therefore such inclusion and/or use is at
internal review and subject to formal approval, which may result in
the customer’s own risk.
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Applications — Applications that are described herein for any of these
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or warranty that such applications will be suitable for the specified use
Short data sheet — A short data sheet is an extract from a full data sheet
without further testing or modification. Customers are responsible for the
with the same product type number(s) and title. A short data sheet is
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detailed and full information. For detailed and full information see the
applications or customer product design. It is customer’s sole responsibility
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customer’s applications and products planned, as well as for the planned
the full data sheet shall prevail.
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any liability related to any default, damage, costs or problem which is based
Nexperia and its customer, unless Nexperia and customer have explicitly
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15.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
Limited warranty and liability — Information in this document is believed
damage to the device. Limiting values are stress ratings only and (proper)
to be accurate and reliable. However, Nexperia does not give any
operation of the device at these or any other conditions above those
representations or warranties, expressed or implied, as to the accuracy
given in the Recommended operating conditions section (if present) or the
or completeness of such information and shall have no liability for the
Characteristics sections of this document is not warranted. Constant or
consequences of use of such information. Nexperia takes no responsibility
repeated exposure to limiting values will permanently and irreversibly affect
for the content in this document if provided by an information source outside
the quality and reliability of the device.
of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation -
lost profits, lost savings, business interruption, costs related to the removal
Terms and conditions of commercial sale — Nexperia products are
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damages are based on tort (including negligence), warranty, breach of
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contract or any other legal theory. Notwithstanding any damages that
concluded only the terms and conditions of the respective agreement shall
customer might incur for any reason whatsoever, Nexperia's aggregate and
apply. Nexperia hereby expressly objects to applying the customer’s general
cumulative liability towards customer for the products described herein shall
terms and conditions with regard to the purchase of Nexperia products by
customer.
be limited in accordance with the Terms and conditions of commercial sale of
Nexperia.
No offer to sell or license — Nothing in this document may be interpreted
Right to make changes — Nexperia reserves the right to make changes
or construed as an offer to sell products that is open for acceptance or
to information published in this document, including without limitation
the grant, conveyance or implication of any license under any copyrights,
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document supersedes and replaces all information supplied prior to the
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warranted to be suitable for use in life support, life-critical or safety-critical
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Product data sheet
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13 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
design and use of the product for automotive applications beyond Nexperia's
standard warranty and Nexperia's product specifications.
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications. In the event that customer
uses the product for design-in and use in automotive applications to
automotive specifications and standards, customer (a) shall use the product
without Nexperia's warranty of the product for such automotive applications,
use and specifications, and (b) whenever customer uses the product for
automotive applications beyond Nexperia's specifications such use shall be
solely at customer’s own risk, and (c) customer fully indemnifies Nexperia
for any liability, damages or failed product claims resulting from customer
Translations — A non-English (translated) version of a document is for
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15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
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Product data sheet
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14 / 15
Nexperia
74AUP1T00
Low-power 2-input NAND gate with voltage-level translator
Contents
1
2
General description ............................................ 1
Features and benefits .........................................1
3
4
5
6
6.1
6.2
7
8
9
10
11
11.1
12
13
14
15
Ordering information .......................................... 2
Marking .................................................................2
Functional diagram .............................................2
Pinning information ............................................ 2
Pinning ...............................................................2
Pin description ...................................................3
Functional description ........................................3
Limiting values ....................................................3
Recommended operating conditions ................4
Static characteristics ..........................................4
Dynamic characteristics .....................................7
Waveforms and test circuit ................................9
Package outline .................................................10
Abbreviations .................................................... 12
Revision history ................................................ 12
Legal information ..............................................13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© Nexperia B.V. 2017.
All rights reserved.
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 23 November 2017
Document identifier: 74AUP1T00
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