74AUP1G08GM [NEXPERIA]
Low-power 2-input AND gateProduction;型号: | 74AUP1G08GM |
厂家: | Nexperia |
描述: | Low-power 2-input AND gateProduction 栅 光电二极管 逻辑集成电路 触发器 |
文件: | 总18页 (文件大小:273K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74AUP1G08
Low-power 2-input AND gate
Rev. 11 — 12 July 2023
Product data sheet
1. General description
The 74AUP1G08 is a single 2-input AND gate. Schmitt-trigger action at all inputs makes the circuit
tolerant of slower input rise and fall times. This device ensures very low static and dynamic power
consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for
partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the
potentially damaging backflow current through the device when it is powered down.
2. Features and benefits
•
Wide supply voltage range from 0.8 V to 3.6 V
•
•
•
•
•
•
•
•
CMOS low power dissipation
High noise immunity
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Low static power consumption; ICC = 0.9 μA (maximum)
Complies with JEDEC standards:
•
•
•
•
•
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
•
ESD protection:
•
•
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
•
•
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Nexperia
74AUP1G08
Low-power 2-input AND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AUP1G08GW
74AUP1G08GM
74AUP1G08GN
74AUP1G08GS
74AUP1G08GX
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
XSON6
XSON6
XSON6
X2SON5
plastic extremely thin small outline package;
no leads; 6 terminals; body 1 × 1.45 × 0.5 mm
SOT886
extremely thin small outline package; no leads;
6 terminals; body 0.9 × 1.0 × 0.35 mm
SOT1115
SOT1202
SOT1226-3
extremely thin small outline package; no leads;
6 terminals; body 1.0 × 1.0 × 0.35 mm
plastic thermal enhanced extremely thin
small outline package; no leads; 5 terminals;
body 0.8 × 0.8 × 0.32 mm
4. Marking
Table 2. Marking
Type number
Marking code[1]
74AUP1G08GW
74AUP1G08GM
74AUP1G08GN
74AUP1G08GS
74AUP1G08GX
pE
pE
pE
pE
pE
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
A
1
2
1
2
B
A
&
4
Y
4
Y
B
mna113
mna114
mna221
Fig. 1. Logic symbol
Fig. 2. IEC logic symbol
Fig. 3. Logic diagram
©
74AUP1G08
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 11 — 12 July 2023
2 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
6. Pinning information
6.1. Pinning
GM package
SOT886 (XSON6)
GW package
SOT353-1 (TSSOP5)
B
A
1
2
3
6
5
V
CC
1
2
3
5
B
A
V
Y
CC
n.c.
Y
GND
4
4
GND
aaa-035733
Transparent top view
aaa-035731
GX package
SOT1226-3 (X2SON5)
GN package
SOT1115 (XSON6)
GS package
SOT1202 (XSON6)
B
1
5
V
CC
B
A
1
2
3
6
5
4
V
B
A
1
2
3
6
5
4
V
CC
CC
3
n.c.
Y
n.c.
Y
GND
GND
GND
2
4
Y
A
aaa-035735
aaa-035736
Transparent top view
aaa-035737
Transparent top view
Transparent top view
6.2. Pin description
Table 3. Pin description
Symbol
Pin
Description
TSSOP5 and X2SON5
XSON6
B
1
2
3
4
-
1
2
3
4
5
6
data input
A
data input
GND
Y
ground (0 V)
data output
not connected
supply voltage
n.c.
VCC
5
©
74AUP1G08
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 11 — 12 July 2023
3 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
7. Functional description
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
A
L
B
L
Y
L
L
L
H
L
H
L
H
H
H
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-50
-0.5
-50
-0.5
-
Max
+4.6
-
Unit
V
VCC
IIK
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
VI
[1]
[1]
+4.6
-
IOK
VO
IO
output clamping current
output voltage
VO < 0 V
mA
V
Active mode and Power-down mode
VO = 0 V to VCC
+4.6
±20
+50
-
output current
mA
mA
mA
°C
ICC
IGND
Tstg
Ptot
supply current
-
ground current
-50
-65
-
storage temperature
total power dissipation
+150
250
Tamb = -40 °C to +125 °C
[2]
mW
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT353-1 (TSSOP5) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT886 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT1115 (XSON6) package: Ptot derates linearly with 3.2 mW/K above 71 °C.
For SOT1202 (XSON6) package: Ptot derates linearly with 3.3 mW/K above 74 °C.
For SOT1226-3 (X2SON5) package: Ptot derates linearly with 3.0 mW/K above 67 °C.
9. Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
Conditions
Min
0.8
0
Max
3.6
Unit
V
VCC
VI
supply voltage
input voltage
output voltage
3.6
V
VO
Active mode
0
VCC
3.6
V
Power-down mode; VCC = 0 V
0
V
Tamb
ambient temperature
-40
0
+125
200
°C
ns/V
Δt/ΔV
input transition rise and fall rate
VCC = 0.8 V to 3.6 V
©
74AUP1G08
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 11 — 12 July 2023
4 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 25 °C
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input voltage VCC = 0.8 V
VCC = 0.9 V to 1.95 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.65 × VCC
-
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.6
-
2.0
-
VIL
LOW-level input voltage VCC = 0.8 V
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = -20 μA; VCC = 0.8 V to 3.6 V
IO = -1.1 mA; VCC = 1.1 V
IO = -1.7 mA; VCC = 1.4 V
IO = -1.9 mA; VCC = 1.65 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
VI = VIH or VIL
VCC - 0.1
0.75 × VCC
1.11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.32
2.05
1.9
2.72
2.6
VOL
LOW-level output
voltage
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.3 × VCC
0.31
V
V
V
0.31
V
0.31
V
0.44
V
0.31
V
0.44
V
II
input leakage current
±0.1
μA
μA
IOFF
power-off leakage
current
±0.2
ΔIOFF
ICC
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
-
-
±0.2
0.5
μA
μA
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
ΔICC
CI
additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V [1]
-
-
-
-
40
-
μA
pF
pF
input capacitance
output capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
0.8
1.7
CO
-
©
74AUP1G08
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 11 — 12 July 2023
5 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Tamb = -40 °C to +85 °C
VIH
HIGH-level input voltage VCC = 0.8 V
VCC = 0.9 V to 1.95 V
0.70 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
0.65 × VCC
-
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.6
-
2.0
-
VIL
LOW-level input voltage VCC = 0.8 V
-
-
-
-
0.30 × VCC
0.35 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
VOH
HIGH-level output
voltage
VI = VIH or VIL
IO = -20 μA; VCC = 0.8 V to 3.6 V
IO = -1.1 mA; VCC = 1.1 V
IO = -1.7 mA; VCC = 1.4 V
IO = -1.9 mA; VCC = 1.65 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
VI = VIH or VIL
VCC - 0.1
0.7 × VCC
1.03
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
1.30
1.97
1.85
2.67
2.55
VOL
LOW-level output
voltage
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.1
0.3 × VCC
0.37
V
V
V
0.35
V
0.33
V
0.45
V
0.33
V
0.45
V
II
input leakage current
±0.5
μA
μA
IOFF
power-off leakage
current
±0.5
ΔIOFF
ICC
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
-
-
-
-
±0.6
0.9
50
μA
μA
μA
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
ΔICC
additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V [1]
Tamb = -40 °C to +125 °C
VIH HIGH-level input voltage VCC = 0.8 V
0.75 × VCC
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.70 × VCC
-
1.6
-
2.0
-
VIL
LOW-level input voltage VCC = 0.8 V
-
-
-
-
0.25 × VCC
0.30 × VCC
0.7
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
0.9
©
74AUP1G08
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 11 — 12 July 2023
6 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VOH
HIGH-level output
VI = VIH or VIL
voltage
IO = -20 μA; VCC = 0.8 V to 3.6 V
VCC - 0.11
0.6 × VCC
0.93
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
V
V
V
V
V
V
V
IO = -1.1 mA; VCC = 1.1 V
IO = -1.7 mA; VCC = 1.4 V
IO = -1.9 mA; VCC = 1.65 V
IO = -2.3 mA; VCC = 2.3 V
IO = -3.1 mA; VCC = 2.3 V
IO = -2.7 mA; VCC = 3.0 V
IO = -4.0 mA; VCC = 3.0 V
1.17
1.77
1.67
2.40
2.30
VOL
LOW-level output
voltage
VI = VIH or VIL
IO = 20 μA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.11
0.33 × VCC
0.41
V
V
IO = 1.7 mA; VCC = 1.4 V
V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
0.39
V
0.36
V
IO = 3.1 mA; VCC = 2.3 V
0.50
V
IO = 2.7 mA; VCC = 3.0 V
0.36
V
IO = 4.0 mA; VCC = 3.0 V
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
±0.75
±0.75
μA
μA
IOFF
power-off leakage
current
ΔIOFF
ICC
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
-
-
-
-
±0.75
1.4
μA
μA
μA
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
ΔICC
additional supply current VI = VCC - 0.6 V; IO = 0 A; VCC = 3.3 V [1]
75
[1] One input at VCC - 0.6 V, other input at VCC or GND.
11. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 25 °C; CL = 5 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
[2]
-
17.0
5.1
3.7
3.0
2.4
2.2
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.6
1.6
1.3
1.1
1.0
10.8
6.5
5.2
4.0
3.5
©
74AUP1G08
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 11 — 12 July 2023
7 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
Symbol Parameter
Conditions
Min
Typ [1]
Max
Unit
Tamb = 25 °C; CL = 10 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
[2]
[2]
[2]
[3]
-
20.6
6.0
4.3
3.6
2.9
2.7
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.4
2.0
1.7
1.4
1.3
12.5
7.6
6.1
4.8
4.2
Tamb = 25 °C; CL = 15 pF
tpd propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
-
24.1
6.8
4.9
4.0
3.4
3.1
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.4
2.3
1.9
1.7
1.5
14.2
8.6
6.9
5.5
4.8
Tamb = 25 °C; CL = 30 pF
tpd propagation delay
A, B to Y; see Fig. 4
VCC = 0.8 V
-
34.4
9.1
6.4
5.3
4.5
4.2
-
ns
ns
ns
ns
ns
ns
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.6
3.4
2.6
2.3
2.2
19.4
11.5
9.1
7.2
6.2
Tamb = 25 °C
CPD power dissipation
capacitance
f = 1 MHz; VI = GND to VCC
VCC = 0.8 V
-
-
-
-
-
-
2.5
2.7
2.8
2.9
3.5
4.0
-
-
-
-
-
-
pF
pF
pF
pF
pF
pF
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1] All typical values are measured at nominal VCC
.
[2] tpd is the same as tPLH and tPHL
.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of the outputs.
©
74AUP1G08
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2023. All rights reserved
Product data sheet
Rev. 11 — 12 July 2023
8 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
Table 9. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 5
Symbol Parameter
Conditions
-40 °C to +85 °C
-40 °C to +125 °C Unit
Min
Max
Min
Max
CL = 5 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
[1]
[1]
[1]
[1]
2.1
1.5
1.3
1.0
0.9
11.7
7.5
6.1
4.8
4.3
2.1
1.5
1.3
1.0
0.9
12.9
8.3
6.7
5.3
4.8
ns
ns
ns
ns
ns
CL = 10 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
2.2
1.8
1.6
1.3
1.2
13.6
8.9
7.2
5.7
4.7
2.2
1.8
1.6
1.3
1.2
15.0
9.8
7.9
6.3
5.2
ns
ns
ns
ns
ns
CL = 15 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
3.1
2.1
1.8
1.6
1.5
15.7
10.1
8.2
3.1
2.1
1.8
1.6
1.5
17.3
11.2
9.0
ns
ns
ns
ns
ns
6.5
7.2
5.9
6.5
CL = 30 pF
tpd
propagation delay
A, B to Y; see Fig. 4
VCC = 1.1 V to 1.3 V
VCC = 1.4 V to 1.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
4.1
2.9
2.4
2.2
2.1
21.8
13.6
10.9
8.6
4.1
2.9
2.4
2.2
2.1
24.0
15.0
12.1
9.5
ns
ns
ns
ns
ns
7.5
8.3
[1] tpd is the same as tPLH and tPHL
.
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9 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
11.1. Waveforms and test circuit
V
I
V
A, B input
GND
M
t
t
PHL
PLH
V
OH
V
Y output
M
mna614
V
OL
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 4. The data input (A or B) to output (Y) propagation delays
Table 10. Measurement points
Supply voltage
VCC
Output
VM
Input
VM
VI
tr = tf
0.8 V to 3.6 V
0.5 × VCC
0.5 × VCC
VCC
≤ 3.0 ns
V
V
EXT
CC
5 kΩ
V
I
V
O
G
DUT
R
T
C
L
R
L
001aac521
Test data is given in Table 11.
Definitions for test circuit:
RL = Load resistance;
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator;
VEXT = External voltage for measuring switching times.
Fig. 5. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
VCC
Load
CL
VEXT
RL [1]
tPLH, tPHL
open
tPZH, tPHZ
tPZL, tPLZ
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ
GND
2 × VCC
[1] For measuring enable and disable times RL = 5 kΩ.
For measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ.
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Rev. 11 — 12 July 2023
10 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
12. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
B
E
A
X
c
(5x)
y
H
E
v
M
A
e
1
5
4
pin 1 index
A
A
2
A
1
1
2
3
A
3
θ
L
w
M B
p
b
p
(5x)
detail X
e
e
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
(1)
(1)
A
A
A
A
b
c
D
E
e
e
1
H
E
L
p
v
w
y
θ
1
2
3
p
max 1.1 0.1 1.0
0.8 0.8
0.30 0.25 2.2 1.35
0.15 0.08 1.8 1.15
2.4 0.46
1.8 0.26
8°
0°
mm
0.15
0.65 1.3
0.3 0.1 0.1
0
min
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
sot353-1_po
References
Outline
version
European
projection
Issue date
IEC
JEDEC
JEITA
21-12-15
21-12-16
SOT353-1
SC-88A
MO-203
Fig. 6. Package outline SOT353-1 (TSSOP5)
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Product data sheet
Rev. 11 — 12 July 2023
11 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4x
(2)
L
L
1
e
6
5
4
e
e
1
1
6x
(2)
A
A
1
D
E
terminal 1
index area
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
(1)
Unit
A
A
b
D
E
e
e
L
L
1
1
1
max 0.5 0.04 0.25 1.50 1.05
0.35 0.40
0.30 0.35
0.27 0.32
nom
min
0.20 1.45 1.00 0.6
0.17 1.40 0.95
mm
0.5
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
sot886_po
Issue date
References
Outline
version
European
projection
IEC
JEDEC
MO-252
JEITA
04-07-22
12-01-05
SOT886
Fig. 7. Package outline SOT886 (XSON6)
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Product data sheet
Rev. 11 — 12 July 2023
12 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
SOT1115
b
3
(2)
(4×)
1
2
L
L
1
e
6
5
4
e
e
1
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
scale
1 mm
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 0.95 1.05
0.35 0.40
0.15 0.90 1.00 0.55 0.3 0.30 0.35
0.12 0.85 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1115_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-07
SOT1115
Fig. 8. Package outline SOT1115 (XSON6)
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Product data sheet
Rev. 11 — 12 July 2023
13 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
SOT1202
b
3
(2)
1
2
(4×)
L
L
1
e
6
5
4
e
e
1
1
(2)
(6×)
A
1
A
D
E
terminal 1
index area
0
L
0.5
1 mm
scale
Dimensions
Unit
(1)
A
A
b
D
E
e
e
1
L
1
1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
0.15 1.00 1.00 0.55 0.35 0.30 0.35
0.12 0.95 0.95 0.27 0.32
mm nom
min
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
sot1202_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
JEITA
10-04-02
10-04-06
SOT1202
Fig. 9. Package outline SOT1202 (XSON6)
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Product data sheet
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Nexperia
74AUP1G08
Low-power 2-input AND gate
X2SON5: plastic thermal enhanced extremely thin small outline package; no leads;
5 terminals; body 0.8 x 0.8 x 0.32 mm
SOT1226-3
C
Seating Plane
y
C
X
5x
D
A
B
E
A
A
3
pin 1
index area
A
1
pin 1
e
index area
b
(4x)
y
v
w
C
C
A
B
C
1
1
2
L
(4x)
3
(6x)
5
4
0
1 mm
scale
v
Dimensions (mm are the original dimensions)
Unit
A
A
A
D
D
h
E
b
e
K
L
w
y
y
1
1
3
max 0.35 0.04
0.32 0.02
0.85 0.30 0.85 0.25
0.27
0.22
0.10
(Typ.)
0.80
0.80
0.20 0.50
0.25
nom
min 0.30 0.00
mm
0.1 0.05 0.05 0.05
0.75 0.20 0.75 0.15
0.20 0.17
EIAJ
sot1226-3_po
References
Outline
version
European
Issue date
projection
IEC
JEDEC
- - -
19-11-06
19-11-07
SOT1226-3
Fig. 10. Package outline SOT1226-3 (X2SON5)
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Product data sheet
Rev. 11 — 12 July 2023
15 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
13. Abbreviations
Table 12. Abbreviations
Acronym
Description
CDM
DUT
ESD
HBM
Charged Device Model
Device Under Test
ElectroStatic Discharge
Human Body Model
14. Revision history
Table 13. Revision history
Document ID
Release date Data sheet status
20230712 Product data sheet
Section 2: ESD specification updated according to the latest JEDEC standard.
20220113 Product data sheet 74AUP1G08 v.9
Section 1 and Section 2 updated.
Fig. 6: Package outline drawing for SOT353-1(TSSOP5) has changed
Product data sheet 74AUP1G08 v.8
Section 1 and Section 2 updated.
Type number 74AUP1G08GF (SOT891/XSON6) removed.
Product data sheet 74AUP1G08 v.7
Change notice Supersedes
74AUP1G08 v.11
Modifications:
- 74AUP1G08 v.10
•
74AUP1G08 v.10
Modifications:
-
•
•
74AUP1G08 v.9
Modifications:
20210805
-
•
•
74AUP1G08 v.8
Modifications:
20210421
-
•
•
SOT1226 (X2SON5) package changed to SOT1226-3 (X2SON5) package.
Table 5: Derating values for Ptot total power dissipation updated.
74AUP1G08 v.7
Modifications:
20171130
Product data sheet
-
74AUP1G08 v.6
•
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
Legal texts have been adapted to the new company name where appropriate.
74AUP1G08 v.6
Modifications:
20120622
Package outline drawing of SOT1226 modified.
20120412 Product data sheet
Product data sheet
-
74AUP1G08 v.5
74AUP1G08 v.4
•
74AUP1G08 v.5
Modifications:
-
•
•
Added type number 74AUP1G08GX (SOT1226)
Package outline drawing of SOT886 (Fig. 7) modified.
74AUP1G08 v.4
Modifications:
20111115
Product data sheet
-
74AUP1G08 v.3
•
Legal pages updated.
74AUP1G08 v.3
74AUP1G08 v.2
74AUP1G08 v.1
20101007
20060629
20050720
Product data sheet
Product data sheet
Product data sheet
-
-
-
74AUP1G08 v.2
74AUP1G08 v.1
-
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Rev. 11 — 12 July 2023
16 / 18
Nexperia
74AUP1G08
Low-power 2-input AND gate
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
without further testing or modification.
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
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and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
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liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
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Short data sheet — A short data sheet is an extract from a full data sheet
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intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
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sold subject to the general terms and conditions of commercial sale, as
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data sheet shall define the specification of the product as agreed between
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In no event shall Nexperia be liable for any indirect, incidental, punitive,
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In the event that customer uses the product for design-in and use in
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customer (a) shall use the product without Nexperia’s warranty of the
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whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
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Notwithstanding any damages that customer might incur for any reason
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to information published in this document, including without limitation
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Suitability for use — Nexperia products are not designed, authorized or
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Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
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Product data sheet
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Nexperia
74AUP1G08
Low-power 2-input AND gate
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Ordering information....................................................2
4. Marking..........................................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................3
7. Functional description................................................. 4
8. Limiting values............................................................. 4
9. Recommended operating conditions..........................4
10. Static characteristics..................................................5
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit.......................................10
12. Package outline........................................................ 11
13. Abbreviations............................................................16
14. Revision history........................................................16
15. Legal information......................................................17
© Nexperia B.V. 2023. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 12 July 2023
©
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Product data sheet
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18 / 18
相关型号:
74AUP1G08GM-H
IC AUP/ULP/V SERIES, 2-INPUT AND GATE, PDSO6, 1 X 1.45 MM, 0.50 MM HEIGHT, PLASTIC, MO-252, SOT-886, SON-6, Gate
NXP
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