74ALVCH16823DGG_技术文档

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable;

3-state

Rev. 3 — 1 February 2018

Product data sheet

1 General description

The 74ALVCH16823 is a 18-bit edge-triggered flip-flop featuring separate D-type inputs

for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold

data inputs which eliminate the need for external pull-up resistors to hold unused inputs.

The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock

(nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-

enable (nCE) input are provided for each total 9-bit section.

With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of

their individual nDn-inputs that meet the set-up and hold time requirements on the

LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching

the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go

LOW independently of the clock.

When nOE is LOW, the contents of the flip-flops are available at the outputs. When the

nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE

input does not affect the state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic

level.

2 Features and benefits

• Wide supply voltage range from 1.2 V to 3.6 V

• CMOS low-power consumption

• Direct interface with TTL levels

• Current drive ± 24 mA at 3.0 V

• MULTIBYTE flow-through standard pin-out architecture

• Low inductance multiple V_CCand GND pins for minimum noise and ground bounce

• Output drive capability 50 Ω transmission lines at 85°C

• All data inputs have bushold

• Complies with JEDEC standard no. 8-1A

• Complies with JEDEC standards:

– JESD8-5 (2.3 V to 2.7 V)

– JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

– CDM JESD22-C101E exceeds 1000 V

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

3 Ordering information

Table 1.ꢀOrdering information

Type number

Package

Temperature range Name

Description

Version

74ALVCH16823DGG −40 °C to +85 °C

TSSOP56 plastic thin shrink small outline package; 56 leads; SOT364-1

body width 6.1 mm

4 Functional diagram

2

EN1

R2

1OE

1MR

1CE

1CP

2OE

2MR

2CE

2CP

1

55

56

27

28

30

29

2MR

1MR

1OE

2OE

28

1

2

G3

3C4

27

EN5

R6

G7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

54

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

3

7C8

5

6

54

52

51

49

48

47

45

44

43

42

41

40

38

37

36

34

33

31

3

5

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

2D8

4D

1,2

1Q0

1Q1

1Q2

1Q3

1Q4

1Q5

1Q6

1Q7

1Q8

2Q0

2Q1

2Q2

2Q3

2Q4

2Q5

2Q6

2Q7

2Q8

8

9

6

10

12

13

14

15

16

17

19

20

21

23

24

26

8

9

10

12

13

14

15

16

17

19

20

21

23

24

26

8D

5,6

2CE

1CE

1CP

2CP

56

29

30

55

aaa-028141

001aad242

Figure 1.ꢀLogic symbol

Figure 2.ꢀIEC logic symbol

V

CC

data input

to internal circuit

001aad245

Figure 3.ꢀBushold circuit (one data input)

74ALVCH16823

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Product data sheet

Rev. 3 — 1 February 2018

2 / 18

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

5 Pinning information

5.1 Pinning

74ALVCH16823

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

1MR

1OE

1Q0

GND

1Q1

1Q2

1CP

1CE

1D0

GND

1D1

1D2

2

3

4

5

6

7

V

CC

8

1Q3

1Q4

1Q5

GND

1Q6

1Q7

1Q8

2Q0

2Q1

2Q2

GND

2Q3

2Q4

2Q5

1D3

1D4

1D5

GND

1D6

1D7

1D8

2D0

2D1

2D2

GND

2D3

2D4

2D5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

V

CC

2Q6

2Q7

GND

2Q8

2OE

2MR

2D6

2D7

GND

2D8

2CE

2CP

aaa-028142

Figure 5.ꢀPin configuration SOT364-1 (TSSOP56)

74ALVCH16823

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Product data sheet

Rev. 3 — 1 February 2018

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

5.2 Pin description

Table 2.ꢀPin description

Symbol

Description

1D0, 1D1, 1D2, 1D3, 1D4,

1D5, 1D6, 1D7, 1D8

54, 52, 51, 49, 48,

47, 45, 44, 43

data inputs

data outputs

data inputs

data outputs

1Q0, 1Q1, 1Q2, 1Q3, 1Q4,

1Q5, 1Q6, 1Q7, 1Q8

3, 5, 6, 8, 9,

10, 12, 13, 14

2D0, 2D1, 2D2, 2D3, 2D4,

2D5, 2D6, 2D7, 2D8

42, 41, 40, 38, 37,

36, 34, 33, 31

2Q0, 2Q1, 2Q2, 2Q3, 2Q4,

2Q5, 2Q6, 2Q7, 2Q8

15, 16, 17, 19, 20,

21, 23, 24, 26

1MR, 2MR

1OE, 2OE

1CP, 2CP

1CE, 2CE

GND

1, 28

master reset inputs (active-LOW)

output enable inputs (active LOW)

clock pulse inputs (active rising edge)

clock enable inputs (active-LOW)

ground (0 V)

2, 27

56, 29

55, 30

4, 11, 18, 25,

32, 39, 46, 53

V_CC

7, 22, 35, 50

supply voltage

6 Functional description

Table 3.ꢀFunction table ^[1]

Operating mode

Input

Output

nOE

nMR

L

nCE

X

nCP

X

nDn

nQn

L

clear

L

H

X

h

l

load and read data

H

L

↑

H

L

↑

L

hold

H

L

X

NC

Z

H

X

disable outputs

X

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

NC = no change;

X = don’t care;

Z = high-impedance OFF-state;

74ALVCH16823

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Product data sheet

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

7 Limiting values

Table 4.ꢀLimiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

Parameter

Conditions

Min

−0.5

−50

-

Max

+4.6

+5.5

V_CC+ 0.5

-

Unit

V

supply voltage

input voltage

[1]

V_I

For control pins

For data inputs

V

V_O

I_IK

output voltage

V

input clamping current

output clamping current

V_I< 0 V

mA

°C

I_OK

V_O> V_CCor V_O< 0 V

V_O= 0 V to V_CC

±50

I_{O(sink/source)}output sink or source current

-

±50

I_CC

supply current

-

100

I_GND

T_stg

P_tot

ground current

−100

−65

-

storage temperature

total power dissipation

+150

600

[2]

T_amb= −40 °C to +125 °C

mW

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] Above 55 °C the value of P_totderates linearly with 8 mW/K.

8 Recommended operating conditions

Table 5.ꢀRecommended operating conditions

Symbol Parameter

Conditions

Min

Max

Unit

V_CC

supply voltage

2.5 V range for maximum speed

performance at 30 pF output load

2.3

2.7

V

3.3 V range for maximum speed

performance at 50 pF output load

3.0

3.6

V

for low-voltage applications

for data inputs

1.2

0

3.6

V_CC

5.5

V_CC

+85

20

V

V_I

input voltage

V

for control inputs

0

V

V_O

output voltage

0

V

T_amb

Δt/ΔV

ambient temperature

input transition rise and fall rate

in free air

-40

-

°C

ns/V

V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

-

10

74ALVCH16823

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Product data sheet

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

9 Static characteristics

Table 6.ꢀStatic characteristics

At recommended operating conditions; T_amb= −40 °C to +85 °C; voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

V

V_IH

HIGH-level

V_CC= 1.2 V

V_CC

-

input voltage

V_CC= 1.8 V

0.7V_CC

0.9

1.2

1.5

-

V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_CC= 1.2 V

1.7

V

2.0

-

V

V_IL

LOW-level

input voltage

-

GND

0.2V_CC

0.7

0.8

V

V_CC= 1.8 V

0.9

1.2

1.5

V

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V to 3.6 V

V_I= V_IHor V_IL

V

V_OH

HIGH-level

output voltage

I_O= -100 μA; V_CC= 1.8 V to 3.6 V

I_O= -6 mA; V_CC= 1.8 V

I_O= -6 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.3 V

I_O= -18 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.7 V

I_O= -24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

V_CC- 0.2

V_CC

-

V

V_CC- 0.4 V_CC- 0.10

V_CC- 0.3 V_CC- 0.08

V_CC- 0.5 V_CC- 0.17

V_CC- 0.6 V_CC- 0.26

V_CC- 0.5 V_CC- 0.14

V_CC- 1.0 V_CC- 0.28

V_OL

LOW-level

output voltage

I_O= 100 μA; V_CC= 1.8 V to 3.6 V

I_O= 6 mA; V_CC= 1.8 V

I_O= 6 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 18 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

-

GND

0.09

0.07

0.15

0.23

0.14

0.27

0.1

0.20

0.30

0.20

0.40

0.60

0.40

0.55

5

V

I_I

input

leakage current

per control pin; V_CC= 1.8 V to 3.6 V;

V_I= 5.5 V or GND

μA

per data pin; V_CC= 1.8 V to 3.6 V;

V_I= V_CCor GND

-

0.1

5

μA

I_OZ

OFF-state

V_CC= 1.8 V to 2.7 V; V_I= V_IHor V_IL;

V_O= V_CCor GND

output current

V_CC= 2.7 V to 3.6 V; V_I= V_IHor V_IL;

V_O= V_CCor GND

10

I_CC

supply current

V_CC= 2.3 V to 3.6 V; V_I= V_CCor GND; I_O= 0 A

V_CC= 2.7 V to 3.6 V; V_I= V_CC- 0.6 V; I_O= 0 A

-

0.2

40

µA

μA

ΔI_CC

additional

150

750

supply current

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Product data sheet

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol Parameter

Conditions

Min

45

Typ^[1]

Max

Unit

μA

pF

I_BHL

I_BHH

I_BHLO

I_BHHO

C_I

bus hold LOW

current

V_CC= 2.3 V; V_I= 0.7 V

V_CC= 3.0 V; V_I= 0.8 V

V_CC= 2.3 V; V_I= 1.7 V

V_CC= 3.0 V; V_I= 2.0 V

V_CC= 2.7 V

-

75

150

bus hold HIGH

current

-45

-75

300

450

-300

-450

-

-175

bus hold LOW

overdrive current

-

V_CC= 3.0 V

-

bus hold HIGH

overdrive current

V_CC= 2.7 V

V_CC= 3.6 V

-

input capacitance

5.0

[1] All typical values are measured at T_amb= 25 °C.

10 Dynamic characteristics

Table 7.ꢀDynamic characteristics

At recommended operating conditions; T_amb= −40 °C to +85 °C; voltages are referenced to GND (ground = 0 V);

for test circuit see Figure 10

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

[2]

t_pd

propagation delay

nCP to nQn; see Figure 6

V_CC= 1.2 V

-

10.6

4.5

2.8

2.7

2.5

-

ns

V_CC= 1.8 V

1.5

1.0

7.5

4.9

4.3

3.7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nMR to nQn; see Figure 8

V_CC= 1.2 V

-

9.9

4.6

2.9

3.1

2.6

-

ns

V_CC= 1.8 V

1.5

1.0

7.4

5.0

4.6

4.0

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nOE to nQn; see Figure 9

V_CC= 1.2 V

[3]

t_en

enable time

-

10.4

4.4

2.8

3.1

2.5

-

ns

V_CC= 1.8 V

1.5

1.0

7.7

5.3

5.2

4.3

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

74ALVCH16823

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Product data sheet

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

[4]

t_dis

disable time

nOE to nQn; see Figure 9

V_CC= 1.2 V

-

6.7

3.3

2.2

3.1

2.8

-

ns

V_CC= 1.8 V

1.5

1.0

5.5

4.1

4.3

3.9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nDn to nCP; see Figure 7

V_CC= 1.8 V

t_su

set-up time

1.5

1.2

1.5

1.2

0.2

0.4

0.2

-

ns

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nCE to nCP; see Figure 7

V_CC= 1.8 V

2.0

1.8

1.9

1.5

-0.2

-0.1

-

ns

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nDn to nCP; see Figure 7

V_CC= 1.8 V

t_h

hold time

0.6

0.8

0.6

0.8

-0.2

-0.1

-0.2

0.0

-

ns

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nCE to nCP; see Figure 7

V_CC= 1.8 V

0.3

0.4

0.5

0.2

0.1

-

ns

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nCP HIGH or LOW; see Figure 6

V_CC= 1.8 V

t_W

pulse width

4.0

3.0

2.5

2.0

1.6

1.4

-

ns

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

nMR HIGH or LOW; see Figure 8

V_CC= 1.8 V

4.0

3.0

2.5

0.8

0.4

0.6

0.3

-

ns

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

74ALVCH16823

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Product data sheet

Rev. 3 — 1 February 2018

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Symbol Parameter

Conditions

Min

Typ^[1]

Max

Unit

t_rec

recovery time

nMR to nCP; see Figure 8

V_CC= 1.8 V

0.8

1.0

0.8

1.0

0.2

0.3

0.1

0.2

-

ns

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

f_max

maximum frequency nCP; see Figure 6

V_CC= 1.8 V

125

150

200

250

300

350

-

MHz

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

per latch; V_I= GND to V_CC

outputs enabled

[5]

C_PD

power dissipation

capacitance

-

16

10

-

pF

outputs disabled

[1] Typical values are measured at T_amb= 25 °C

Typical values for V_CC= 2.3 V to 2.7 V are measured at V_CC= 2.5 V.

Typical values for V_CC= 3.0 V to 3.6 V are measured at V_CC= 3.3 V.

[2] t_pdis the same as t_PLHand t_PHL

[3] t_enis the same as t_PZLand t_PZH

[4] t_disis the same as t_PLZand t_PHZ

.

[5] C_PDis used to determine the dynamic power dissipation (P_Din μW).

P_D= C_PD× V_CC²× f_i× N + ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in Volts;

N = total load switching outputs;

∑(C_L× V_CC²× f_o) = sum of outputs.

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Product data sheet

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

10.1 Waveforms and test circuit

1/f

max

V

I

nCP input

V

M

GND

t

W

t

PHL

PLH

V

OH

V

nQn output

M

001aaa256

V

OL

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Figure 6.ꢀPropagation delay clock input (nCP) to output (nQn), clock pulse (nCP) width and maximum clock (nCP)

frequency

V

I

input nDn,

nCE

V

M

GND

t

h(L)

su(H)

h(H)

su(L)

V

I

input nCP

V

M

GND

001aad401

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 7.ꢀData set-up and hold times for the nDn or nCE input to the nCP input

V

I

V

t

input nMR

GND

M

t

WL

rec

V

I

input nCP

GND

V

M

t

PHL

V

OH

V

output nQn

M

V

OL

001aad400

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Figure 8.ꢀMaster reset (nMR) pulse width, master reset (nMR) to output (nQn) propagation delay and master reset

(nMR) to clock (nCP) recovery time

74ALVCH16823

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Product data sheet

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74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

V

I

nOE input

V

M

t

GND

t

PLZ

PZL

V

CC

nQn output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

nQn output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aal795

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Figure 9.ꢀOFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays

Table 8.ꢀMeasurement points

V_CC

Input

V_I

Output

V_M

V_X

V_Y

< 2.7 V

≥ 2.7 V

V_CC

2.7 V

0.5 x V_CC

1.5 V

0.5 x V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH- 0.15 V

V_OH- 0.3 V

74ALVCH16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 1 February 2018

12 / 18

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

EXT

V

CC

R

L

V

O

I

PULSE

GENERATOR

DUT

R

T

C

L

R

L

001aae235

Test data is given in Table 9.

Definitions test circuit:

R_L= Load resistance;

C_L= Load capacitance including jig and probe capacitance;

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator;

V_EXT= External voltage for measuring switching times.

Figure 10.ꢀTest circuit for measuring switching times

Table 9.ꢀTest data

Input

V_CC

Load

R_L

V_EXT

V_I

t_r, t_f

C_L

t_PHZ, t_PZH

GND

t_PLZ, t_PZL

2 × V_CC

t_PLH, t_PHL

open

< 2.7 V

≥ 2.7 V

V_CC

2.7 V

≤ 2.0 ns

≤ 2.5 ns

500 Ω

30 pF

50 pF

GND

open

74ALVCH16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 1 February 2018

13 / 18

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

11 Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

E

D

A

X

c

H

v

M

A

y

E

Z

56

29

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

28

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

E

L

p

Q

v

w

y

Z

θ

1

2

3

p

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

mm

1.2

0.5

1

0.25

0.08

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Figure 11.ꢀPackage outline SOT364-1 (TSSOP56)

74ALVCH16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 1 February 2018

14 / 18

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

12 Abbreviations

Table 10.ꢀAbbreviations

Acronym

CMOS

DUT

Description

Complementary Metal-Oxide Semiconductor

Device Under Test

TTL

Transistor-Transistor Logic

13 Revision history

Table 11.ꢀRevision history

Document ID

Release date

20180201

Data sheet status

Change notice

Supersedes

74ALVCH16823 v.3

Modifications:

Product data sheet

-

74ALVCH16823 v.2

• The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Type number 74ALVCH16823DL (SOT371-1 / SSOP56) removed

74ALVCH16823 v.2

74ALVCH16823 v.1

19980729

Product specification

-

74ALVCH16823 v.1

-

74ALVCH16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 1 February 2018

15 / 18

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

14 Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nexperia.com.

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

14.2 Definitions

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

Draft — The document is a draft version only. The content is still under

such equipment or applications and therefore such inclusion and/or use is at

internal review and subject to formal approval, which may result in

the customer’s own risk.

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

Short data sheet — A short data sheet is an extract from a full data sheet

without further testing or modification. Customers are responsible for the

with the same product type number(s) and title. A short data sheet is

design and operation of their applications and products using Nexperia

intended for quick reference only and should not be relied upon to contain

products, and Nexperia accepts no liability for any assistance with

detailed and full information. For detailed and full information see the

applications or customer product design. It is customer’s sole responsibility

relevant full data sheet, which is available on request via the local Nexperia

to determine whether the Nexperia product is suitable and fit for the

sales office. In case of any inconsistency or conflict with the short data sheet,

customer’s applications and products planned, as well as for the planned

the full data sheet shall prevail.

application and use of customer’s third party customer(s). Customers should

provide appropriate design and operating safeguards to minimize the risks

associated with their applications and products. Nexperia does not accept

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

any liability related to any default, damage, costs or problem which is based

Nexperia and its customer, unless Nexperia and customer have explicitly

on any weakness or default in the customer’s applications or products, or

agreed otherwise in writing. In no event however, shall an agreement be

the application or use by customer’s third party customer(s). Customer is

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

responsible for doing all necessary testing for the customer’s applications

and products using Nexperia products in order to avoid a default of the

applications and the products or of the application or use by customer’s third

party customer(s). Nexperia does not accept any liability in this respect.

14.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

Limited warranty and liability — Information in this document is believed

damage to the device. Limiting values are stress ratings only and (proper)

to be accurate and reliable. However, Nexperia does not give any

operation of the device at these or any other conditions above those

representations or warranties, expressed or implied, as to the accuracy

given in the Recommended operating conditions section (if present) or the

or completeness of such information and shall have no liability for the

Characteristics sections of this document is not warranted. Constant or

consequences of use of such information. Nexperia takes no responsibility

repeated exposure to limiting values will permanently and irreversibly affect

for the content in this document if provided by an information source outside

the quality and reliability of the device.

of Nexperia. In no event shall Nexperia be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation -

lost profits, lost savings, business interruption, costs related to the removal

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

or replacement of any products or rework charges) whether or not such

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

damages are based on tort (including negligence), warranty, breach of

in a valid written individual agreement. In case an individual agreement is

contract or any other legal theory. Notwithstanding any damages that

concluded only the terms and conditions of the respective agreement shall

customer might incur for any reason whatsoever, Nexperia's aggregate and

apply. Nexperia hereby expressly objects to applying the customer’s general

cumulative liability towards customer for the products described herein shall

terms and conditions with regard to the purchase of Nexperia products by

customer.

be limited in accordance with the Terms and conditions of commercial sale of

Nexperia.

No offer to sell or license — Nothing in this document may be interpreted

Right to make changes — Nexperia reserves the right to make changes

or construed as an offer to sell products that is open for acceptance or

to information published in this document, including without limitation

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

74ALVCH16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 1 February 2018

16 / 18

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications. In the event that customer

uses the product for design-in and use in automotive applications to

automotive specifications and standards, customer (a) shall use the product

without Nexperia's warranty of the product for such automotive applications,

use and specifications, and (b) whenever customer uses the product for

automotive applications beyond Nexperia's specifications such use shall be

solely at customer’s own risk, and (c) customer fully indemnifies Nexperia

for any liability, damages or failed product claims resulting from customer

design and use of the product for automotive applications beyond Nexperia's

standard warranty and Nexperia's product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

14.4 Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74ALVCH16823

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 1 February 2018

17 / 18

Nexperia

74ALVCH16823

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

Contents

1

2

General description ............................................ 1

Features and benefits .........................................1

3

4

5

5.1

5.2

6

7

8

Ordering information .......................................... 2

Functional diagram .............................................2

Pinning information ............................................ 4

Pinning ...............................................................4

Pin description ...................................................5

Functional description ........................................5

Limiting values ....................................................6

Recommended operating conditions ................6

Static characteristics ..........................................7

Dynamic characteristics .....................................8

Waveforms and test circuit .............................. 11

Package outline .................................................14

Abbreviations .................................................... 15

Revision history ................................................ 15

Legal information ..............................................16

9

10

10.1

11

12

13

14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 1 February 2018

Document identifier: 74ALVCH16823


型号：	74ALVCH16823DGG
厂家：	Nexperia
描述：	18-bit bus-interface D-type flip-flop with reset and enable; 3-stateProduction 驱动光电二极管逻辑集成电路
文件：	总18页 (文件大小：213K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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