74ALVCH16601DGG [NEXPERIA]

18-bit universal bus transceiver (3-State)Production;


型号：	74ALVCH16601DGG
厂家：	Nexperia
描述：	18-bit universal bus transceiver (3-State)Production 光电二极管逻辑集成电路触发器
文件：	总15页 (文件大小：226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74ALVCH16601

18-bit universal bus transceiver; 3-state

Rev. 3 — 13 August 2018

Product data sheet

1. General description

The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data flow in each direction is controlled by

output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA)

inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is

LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When

OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance

state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB should

be tied to V_CCthrough a pullup resistor; the minimum value of the resistor is determined by the

current-sinking/current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

•

CMOS low power consumption

•

MultiByte flow-through standard pin-out architecture

Low inductance multiple V_CCand GND pins for minimum noise and ground bounce

Direct interface with TTL levels

Bus hold on data inputs

Output drive capability 50 Ω transmission lines at 85 °C

Current drive ±24 mA at 3.0 V

Complies with JEDEC standards:

•

JESD8-5 (2.3 V to 2.7 V)

JESD8B/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

CDM JESD22-C101E exceeds 1000 V

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range

Name

Description

Version

74ALVCH16601DGG −40 °C to +85 °C

TSSOP56

plastic thin shrink small outline package;

56 leads; body width 6.1 mm

SOT364-1

Nexperia

74ALVCH16601

18-bit universal bus transceiver; 3-state

4. Functional diagram

OEAB

EN1

CEAB

CPAB

LEAB

2C3

OEBA

CEBA

CPBA

LEBA

EN4

5C6

A10

B10

B11

B12

B13

B14

B15

B16

B17

A11

A12

A13

A14

A15

A10

A11

A12

A13

A14

A15

A16

A17

B10

B11

B12

B13

B14

B15

B16

B17

A16

A17

OEAB

OEBA

LEBA

CPBA

CEBA

LEAB

CPAB

CEAB

aaa-028853

aaa-028854

Fig. 1. Logic symbol

Fig. 2. IEC logic symbol

data input

to internal circuit

001aal733

Fig. 3. Bus hold circuit

74ALVCH16601

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Product data sheet

Rev. 3 — 13 August 2018

2 / 15

Nexperia

74ALVCH16601

18-bit universal bus transceiver; 3-state

CPBA

LEBA

CEBA

OEBA

CPAB

LEAB

CEAB

OEAB

18 identical channels

to 17 other channels

aaa-028855

Fig. 4. Logic diagram (one section)

74ALVCH16601

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Product data sheet

Rev. 3 — 13 August 2018

3 / 15

Nexperia

74ALVCH16601

18-bit universal bus transceiver; 3-state

5. Pinning information

5.1. Pinning

74ALVCH16601

OEAB

LEAB

CEAB

CPAB

GND

A10

A11

GND

A12

A13

A14

B10

B11

GND

B12

B13

B14

A15

A16

B15

B16

GND

A17

GND

B17

OEBA

LEBA

CPBA

CEBA

aaa-028856

Fig. 5. Pin configuration for TSSOP56 (SOT364-1)

74ALVCH16601

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Product data sheet

Rev. 3 — 13 August 2018

4 / 15

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74ALVCH16601

18-bit universal bus transceiver; 3-state

5.2. Pin description

Table 2. Pin description

Symbol

Description

A0, A1, A2, A3, A4, A5, A6, A7, A8,

3, 5, 6, 8, 9, 10, 12, 13, 14,

data inputs/outputs

A9, A10, A11, A12, A13, A14, A15, A16, A17 15, 16, 17, 19, 20, 21, 23, 24, 26

B0, B1, B2, B3, B4, B5, B6, B7, B8, 54, 52, 51, 49, 48, 47, 45, 44, 43,

B9, B10, B11, B12, B13, B14, B15, B16, B17 42, 41, 40, 38, 37, 36, 34, 33, 31

data outputs/inputs

OEAB, OEBA

LEAB, LEBA

CPBA, CPAB

CEBA, CEAB

1, 27

A to B / B to A output enable inputs

(active LOW)

2, 28

A to B / B to A latch enable inputs

(active HIGH)

30, 55

29, 56

B to A / A to B clock inputs

(active HIGH)

B to A / A to B clock enable inputs

(active LOW)

GND

V_CC

4, 11, 18, 25, 32, 39, 46, 53

7, 22, 35, 50

ground (0 V)

supply voltage

6. Functional description

Table 3. Function selection [1] [2]

Operating mode

Inputs

Outputs

CEAB

OEAB

LEAB

CPAB

Disabled

↑

Transparent

Hold

Clock data & Display

↑

Hold data & Display

[1] A-to-B data flow is shown; B-to-A flow is similar but uses CEBA, OEBA, LEBA, and CPBA.

[2] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the enable or clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the enable or clock transition;

X = don’t care;

NC = no change

↑ = LOW-to-HIGH enable or clock transition;

Z = high-impedance OFF-state.

74ALVCH16601

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Product data sheet

Rev. 3 — 13 August 2018

5 / 15

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74ALVCH16601

18-bit universal bus transceiver; 3-state

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

Parameter

Conditions

Min

-0.5

-50

Max

Unit

supply voltage

input voltage

+4.6

V_I

data inputs

[1]

V_CC+ 0.5 V

+4.6

V_CC+ 0.5 V

control inputs

V_O

I_IK

output voltage

input clamping current

output clamping current

V_I< 0 V

I_OK

V_O> V_CCor V_O< 0 V

±50

100

°C

I_{O (sink/source)}output sink or source current V_O= 0 V to V_CC

I_CC

supply current

I_GND

T_stg

P_tot

ground current

-100

−65

storage temperature

total power dissipation

+150

600

T_amb= −40 °C to +85 °C

[2]

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] For TSSOP56 packages: above 55 °C derate linearly with 8 mW/K.

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter

Conditions

Min

Max

Unit

V_CC

supply voltage

V_CC= 2.5 V:

2.3

2.7

for maximum speed performance at C_L= 30 pF

V_CC= 3.3 V:

3.0

3.6

for maximum speed performance at C_L= 50 pF

V_I

input voltage

V_CC

+85

V_O

output voltage

T_amb

Δt/ΔV

ambient temperature

in free air

−40

°C

input transition rise and fall rate V_CC= 2.3 V to 3.0 V

V_CC= 3.0 V to 3.6 V

ns/V

74ALVCH16601

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Product data sheet

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74ALVCH16601

18-bit universal bus transceiver; 3-state

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions. T_amb= −40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

1.7

2.0

Typ [1]

1.2

Max

Unit

V_IH

HIGH-level input

V_CC= 2.3 to 2.7 V

voltage

V_CC= 2.7 to 3.6 V

1.5

V_IL

LOW-level input

voltage

V_CC= 2.3 to 2.7 V

1.2

0.7

0.8

V_CC= 2.7 to 3.6 V

1.5

V_OH

HIGH-level output

voltage

V_I= V_IHor V_IL

I_O= -100 μA; V_CC= 2.3 V to 3.6 V

I_O= -6 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.3 V

I_O= -12 mA; V_CC= 2.7 V

I_O= -12 mA; V_CC= 3.0 V

I_O= -24 mA; V_CC= 3.0 V

V_I= V_IHor V_IL

V_CC- 0.2

V_CC

V_CC- 0.3 V_CC- 0.08

V_CC- 0.6 V_CC- 0.26

V_CC- 0.5 V_CC- 0.14

V_CC- 0.6 V_CC- 0.09

V_CC- 1.0 V_CC- 0.28

V_OL

LOW-level output

voltage

I_O= 100 μA; V_CC= 2.3 V to 3.6 V

I_O= 6 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.3 V

I_O= 12 mA; V_CC= 2.7 V

I_O= 24 mA; V_CC= 3.0 V

GND

0.07

0.15

0.14

0.27

0.1

0.20

0.40

0.70

0.40

0.55

I_I

input leakage current V_I= V_CCor GND; V_CC= 2.3 V to 3.6 V

μA

I_BHL

bus hold LOW

current

V_CC= 2.3 V; V_I= 0.7 V

V_CC= 3.0 V; V_I= 0.8 V

V_CC= 2.3 V; V_I= 1.7 V

V_CC= 3.0 V; V_I= 2.0 V

V_CC= 3.6 V

-45

-75

500

150

I_BHH

bus hold HIGH

current

-175

I_BHLO

I_BHHO

I_OZ

bus hold LOW

overdrive current

bus hold HIGH

overdrive current

V_CC= 3.6 V

-500

μA

OFF-state output

current

V_CC= 2.7 V to 3.6 V; V_I= V_IHor V_IL;

V_O= V_CCor GND

0.1

I_CC

supply current

V_CC= 2.3 to 3.6 V; V_I= V_CCor GND; I_O= 0 A

0.2

μA

ΔI_CC

additional supply

current

V_I= V_CC- 0.6 V; I_O= 0 A;

V_CC= 2.3 V to 3.6 V

150

750

C_I

input capacitance

4.0

8.0

C_I/O

input/output

capacitance

[1] All typical values are measured at T_amb= 25 °C.

74ALVCH16601

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Product data sheet

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74ALVCH16601

18-bit universal bus transceiver; 3-state

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). T_amb= −40 °C to +85 °C; For test circuit, see Fig. 10.

Symbol Parameter

Conditions

Min

Typ [1]

Max

Unit

t_pd

propagation delay

An to Bn; Bn to An; Fig. 6

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

[2]

1.0

3.1

2.8

5.2

4.7

4.2

V_CC= 3.0 V to 3.6 V

LEAB to Bn; LEBA to An; Fig. 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

3.6

3.4

3.1

6.2

5.4

4.9

V_CC= 3.0 V to 3.6 V

CPAB to Bn; CPBA to An; Fig. 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.0

3.4

3.5

3.1

5.9

5.8

5.0

V_CC= 3.0 V to 3.6 V

OEAB to Bn; OEBA to An; Fig. 8

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.3

t_en

t_dis

t_su

enable time

disable time

set-up time

1.1

3.1

3.3

2.8

5.3

6.1

5.2

V_CC= 3.0 V to 3.6 V

OEAB to Bn; OEBA to An; Fig. 8

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.1

1.4

2.8

3.3

3.2

4.9

4.8

4.4

V_CC= 3.0 V to 3.6 V

An to CPAB; Bn to CPBA; Fig. 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.2

2.3

2.4

2.1

−0.2

0.0

V_CC= 3.0 V to 3.6 V

An to LEAB; Bn to LEBA; Fig. 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

−0.2

1.3

1.2

1.1

0.1

−0.2

0.3

V_CC= 3.0 V to 3.6 V

CEAB to CPAB; CEBA to CPBA;

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

2.0

1.7

−0.4

−0.7

−0.2

V_CC= 3.0 V to 3.6 V

74ALVCH16601

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Product data sheet

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74ALVCH16601

18-bit universal bus transceiver; 3-state

Symbol Parameter

Conditions

Min

Typ [1]

Max

Unit

t_h

hold time

An to CPAB; Bn to CPBA; Fig. 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.2

1.1

1.0

0.3

V_CC= 3.0 V to 3.6 V

An to LEAB; Bn to LEBA; Fig. 9

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

−0.1

1.3

1.6

1.4

0.2

0.1

V_CC= 3.0 V to 3.6 V

CEAB to CPAB; CEBA to CPBA;

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

1.1

1.2

1.1

0.4

0.6

0.4

V_CC= 3.0 V to 3.6 V

LEAB HIGH; LEBA HIGH; Fig. 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

t_w

pulse width

3.3

1.6

0.7

0.9

V_CC= 3.0 V to 3.6 V

CPAB HIGH or LOW;

CPBA HIGH or LOW; Fig. 7

V_CC= 2.3 V to 2.7 V

V_CC= 2.7 V

3.3

2.0

1.2

0.9

V_CC= 3.0 V to 3.6 V

f_max

maximum frequency CPAB, CPBA; Fig. 7

V_CC= 2.3 V to 2.7 V

150

390

333

340

MHz

V_CC= 2.7 V

V_CC= 3.0 V to 3.6 V

C_PD

power dissipation

capacitance

per latch; V_I= GND to V_CC

outputs enabled

[3]

outputs disabled

[1] Typical values are measured at T_amb= 25 °C

Typical values for V_CC= 2.3 V to 2.7 V are measured at V_CC= 2.5 V

Typical values for V_CC= 3.0 V to 3.6 V are measured at V_CC= 3.3 V

[2] t_pdis the same as t_PHLand t_PLH

t_enis the same as t_PZHand t_PZL

t_disis the same as t_PHZand t_PLZ

;

[3] C_PDis used to determine the dynamic power dissipation (P_Din μW):

P_D= C_PDx V_CC²x f_ix N + ∑(C_Lx V_CC²x f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V;

N = number of inputs switching;

∑(C_Lx V_CC²x f_o) = sum of outputs.

74ALVCH16601

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Product data sheet

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74ALVCH16601

18-bit universal bus transceiver; 3-state

10.1. Waveforms and test circuit

An, Bn

input

GND

PHL

PLH

Bn, An

output

001aal734

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 6. The input An, Bn to output Bn, An propagation delays.

1/f

max

LEBA, LEAB

CPBA, CPAB

input

GND

PLH

PHL

An, Bn

output

aaa-028857

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 7. Latch enable input (LEAB, LEBA) and clock input (CPAB, CPBA) to output (Bn, An) propagation delays;

clock (CPAB, CPBA) pulse width and clock (CPAB, CPBA) maximum frequency

OEAB, OEBA

input

GND

PLZ

PZL

An, Bn output

LOW-to-OFF

OFF-to-LOW

PZH

PHZ

An, Bn output

HIGH-to-OFF

OFF-to-HIGH

GND

outputs

enabled

outputs

disabled

outputs

enabled

aaa-028033

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 8. 3-state enable and disable times.

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Product data sheet

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10 / 15

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74ALVCH16601

18-bit universal bus transceiver; 3-state

An, Bn

input

GND

CPAB, CPBA,

LEAB, LEBA

input

GND

aaa-028858

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig. 9. Data set-up and hold times for An and Bn inputs to LEAB, LEBA, CPAB or CPBA inputs.

Table 8. Measurement points

Supply voltage

V_CC

Input

V_I

Output

V_M

V_X

V_Y

2.3 V to 2.7 V

2.7 V

V_CC

0.5 V_CC

1.5 V

0.5 V_CC

1.5 V

V_OL+ 0.15 V

V_OL+ 0.3 V

V_OH- 0.15 V

V_OH- 0.3 V

2.7 V

3.0 V to 3.6 V

90 %

negative

pulse

10 %

0 V

90 %

positive

pulse

10 %

0 V

EXT

DUT

001aae331

Test data is given in Table 9.

Definitions for test circuit:

R_L= Load resistance.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

V_EXT= External voltage for measuring switching times.

Fig. 10. Test circuit for measuring switching times

Table 9. Test data

Supply voltage

V_CC

Input

V_I

Load

C_L

V_EXT

t_r, t_f

R_L

t_PLH, t_PHL

open

t_PLZ, t_PZL

t_PHZ, t_PZH

2.3 V to 2.7 V

2.7 V

V_CC

≤ 2.0 ns

≤ 2.5 ns

30 pF

50 pF

500 Ω

2 × V_CC

GND

2.7 V

open

3.0 V to 3.6 V

open

74ALVCH16601

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74ALVCH16601

18-bit universal bus transceiver; 3-state

11. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm

SOT364-1

(A )

pin 1 index

detail X

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

(1)

(2)

UNIT

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

14.1

13.9

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.5

0.1

1.2

0.5

0.25

0.08

0.1

0.25

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT364-1

MO-153

Fig. 11. Package outline SOT364-1 (TSSOP56)

74ALVCH16601

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74ALVCH16601

18-bit universal bus transceiver; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym

CDM

Description

Charged Device Model

CMOS

DUT

Complementary Metal-Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date

20180813

Data sheet status

Change notice

Supersedes

74ALVCH16601 v.3

Modifications:

Product data sheet

74ALVCH16601 v.2

•

The format of this data sheet has been redesigned to comply with the identity guidelines of

Nexperia.

Legal texts have been adapted to the new company name where appropriate.

74ALVCH16601 v.2

74ALVCH16601 v.1

19980924

19980831

Product specification

74ALVCH16601 v.1

74ALVCH16601

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13 / 15

Nexperia

74ALVCH16601

18-bit universal bus transceiver; 3-state

injury, death or severe property or environmental damage. Nexperia and its

suppliers accept no liability for inclusion and/or use of Nexperia products in

such equipment or applications and therefore such inclusion and/or use is at

the customer’s own risk.

14. Legal information

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Data sheet status

Document status Product

Definition

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

[1][2]

status [3]

Objective [short]

data sheet

Development

This document contains data from

the objective specification for

product development.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

any assistance with applications or customer product design. It is customer’s

sole responsibility to determine whether the Nexperia product is suitable

and fit for the customer’s applications and products planned, as well as

for the planned application and use of customer’s third party customer(s).

Customers should provide appropriate design and operating safeguards to

minimize the risks associated with their applications and products.

Preliminary [short]

data sheet

Qualification

Production

This document contains data from

the preliminary specification.

Product [short]

data sheet

This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

Nexperia does not accept any liability related to any default, damage, costs

or problem which is based on any weakness or default in the customer’s

applications or products, or the application or use by customer’s third party

customer(s). Customer is responsible for doing all necessary testing for the

customer’s applications and products using Nexperia products in order to

avoid a default of the applications and the products or of the application or

use by customer’s third party customer(s). Nexperia does not accept any

liability in this respect.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

Definitions

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. Nexperia does not give any representations or

warranties as to the accuracy or completeness of information included herein

and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the relevant

full data sheet, which is available on request via the local Nexperia sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

Nexperia and its customer, unless Nexperia and customer have explicitly

agreed otherwise in writing. In no event however, shall an agreement be

valid in which the Nexperia product is deemed to offer functions and qualities

beyond those described in the Product data sheet.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, Nexperia does not give any

representations or warranties, expressed or implied, as to the accuracy

or completeness of such information and shall have no liability for the

consequences of use of such information. Nexperia takes no responsibility

for the content in this document if provided by an information source outside

of Nexperia.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In no event shall Nexperia be liable for any indirect, incidental, punitive,

special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal

or replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Notwithstanding any damages that customer might incur for any reason

whatsoever, Nexperia’s aggregate and cumulative liability towards customer

for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale of Nexperia.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Right to make changes — Nexperia reserves the right to make changes

to information published in this document, including without limitation

specifications and product descriptions, at any time and without notice. This

document supersedes and replaces all information supplied prior to the

publication hereof.

Trademarks

Suitability for use — Nexperia products are not designed, authorized or

warranted to be suitable for use in life support, life-critical or safety-critical

systems or equipment, nor in applications where failure or malfunction

of an Nexperia product can reasonably be expected to result in personal

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

74ALVCH16601

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 13 August 2018

14 / 15

Nexperia

74ALVCH16601

18-bit universal bus transceiver; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................4

5.1. Pinning.........................................................................4

5.2. Pin description.............................................................5

6. Functional description................................................. 5

7. Limiting values............................................................. 6

8. Recommended operating conditions..........................6

9. Static characteristics....................................................7

10. Dynamic characteristics............................................ 8

10.1. Waveforms and test circuit...................................... 10

11. Package outline........................................................ 12

12. Abbreviations............................................................13

13. Revision history........................................................13

14. Legal information......................................................14

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 13 August 2018

74ALVCH16601

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 13 August 2018

15 / 15

74ALVCH16601DGG [NEXPERIA]

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