74ALVCH16501DGG [NEXPERIA]

18-bit universal bus transceiver; 3-stateProduction;
74ALVCH16501DGG
型号: 74ALVCH16501DGG
厂家: Nexperia    Nexperia
描述:

18-bit universal bus transceiver; 3-stateProduction

光电二极管 逻辑集成电路 触发器
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74ALVCH16501  
18-bit universal bus transceiver; 3-state  
Rev. 7 — 24 November 2021  
Product data sheet  
1. General description  
The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs.  
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB  
and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the  
transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held  
at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the  
LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is  
LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B  
but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH  
and OEBA is active LOW). This device is fully specified for partial power down applications using  
IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current  
through the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power dissipation  
Direct interface with TTL levels  
Current drive ±24 mA at VCC = 3.0 V  
Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in  
transparent, latched or clocked mode  
Bus hold on all data inputs  
Output drive capability 50 Ω transmission lines at 85 °C  
3-state non-inverting outputs for bus-oriented applications  
Latch-up performance exceeds 100 mA per JESD78 Class II Level B  
Complies with JEDEC standards:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
Specified from -40 °C to +85 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74ALVCH16501DGG -40 °C to +85 °C  
TSSOP56  
plastic thin shrink small outline package;  
56 leads; body width 6.1 mm  
SOT364-1  
 
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
4. Functional diagram  
1
OEAB  
EN1  
2C3  
C3  
55  
2
CPAB  
LEAB  
G2  
27  
30  
28  
OEBA  
CPBA  
LEBA  
EN4  
5C6  
C6  
A0  
3
B0  
B1  
54  
52  
51  
49  
48  
47  
45  
44  
43  
42  
41  
40  
38  
37  
36  
34  
33  
31  
A1  
5
G5  
A2  
6
B2  
A3  
B3  
3
54  
8
A0  
3D  
4
1
1
1
B0  
A4  
9
B4  
6D  
A5  
B5  
5
52  
51  
49  
48  
47  
45  
44  
43  
42  
41  
40  
38  
37  
36  
34  
33  
31  
10  
A1  
A2  
B1  
A6  
12  
B6  
6
B2  
A7  
B7  
8
13  
A3  
B3  
A8  
14  
B8  
9
A4  
B4  
A9  
B9  
10  
12  
13  
14  
15  
16  
17  
19  
20  
21  
23  
24  
26  
15  
A5  
B5  
A10  
16  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
A6  
B6  
A11  
17  
A7  
B7  
A12  
19  
A8  
B8  
A13  
20  
A9  
B9  
A14  
21  
A10  
A11  
A12  
A13  
A14  
A15  
A16  
A17  
B10  
B11  
B12  
B13  
B14  
B15  
B16  
B17  
A15  
23  
A16  
24  
A17  
26  
OEAB  
1
OEBA  
LEBA  
CPBA  
27  
28  
30  
LEAB  
2
CPAB  
55  
001aal718  
001aal717  
Fig. 1. Logic symbol  
Fig. 2. IEC logic symbol  
V
CC  
data input  
to internal circuit  
001aal733  
Fig. 3. Bus hold circuit  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
2 / 15  
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
OEAB  
CPBA  
LEBA  
CPAB  
LEAB  
OEBA  
C1  
1D  
C1  
1D  
B1  
A1  
C1  
1D  
C1  
1D  
18 IDENTICAL CHANNELS  
001aal719  
Fig. 4. Logic diagram  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
3 / 15  
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
5. Pinning information  
5.1. Pinning  
74ALVCH16501  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A0  
GND  
CPAB  
B0  
2
3
4
GND  
A1  
GND  
B1  
5
6
A2  
B2  
7
V
CC  
V
CC  
8
A3  
B3  
9
A4  
A5  
B4  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
B5  
GND  
A6  
GND  
B6  
A7  
B7  
A8  
B8  
A9  
B9  
A10  
A11  
GND  
A12  
A13  
A14  
B10  
B11  
GND  
B12  
B13  
B14  
V
CC  
V
CC  
A15  
A16  
B15  
B16  
GND  
A17  
GND  
B17  
OEBA  
LEBA  
CPBA  
GND  
001aal716  
Fig. 5. Pin configuration SOT364-1 (TSSOP56)  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
4 / 15  
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
5.2. Pin description  
Table 2. Pin description  
Symbol  
Pin  
1
Description  
OEAB  
output enable A-to-B input (active HIGH)  
latch enable A-to-B input  
data inputs or outputs  
LEAB  
2
A0 to A17  
3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17,  
19, 20, 21, 23, 24, 26  
GND  
4, 11, 18, 25, 29, 32, 39, 46, 53, 56  
ground (0 V)  
VCC  
7, 22, 35, 50  
positive supply voltage  
output enable B-to-A (active LOW)  
latch enable B-to-A  
OEBA  
LEBA  
CPBA  
B0 to B17  
27  
28  
30  
clock input B-to-A  
54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40,  
38, 37, 36, 34, 33, 31  
data inputs or outputs  
CPAB  
55  
clock input A-to-B  
6. Functional description  
Table 3. Function table  
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA, LEBA and CPBA.  
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the enable or clock transition;  
L = LOW voltage level; l = LOW voltage level one set-up time prior to the enable or clock transition;  
X = don’t care; Z = high-impedance OFF-state;  
↓ = HIGH-to-LOW clock transition; ↑ = LOW-to-HIGH clock transition.  
Inputs  
Output  
Operating mode  
OEAB  
LEAB  
CPAB  
An  
X
H
L
Bn  
Z
L
X
H
H
X
disabled  
H
H
H
H
H
H
H
H
X
H
L
transparent  
X
X
h
H
L
latch data and display  
clock data and display  
hold data and display  
X
l
L
L
L
L
h
H
L
l
H or L  
H or L  
X
X
H
L
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
5 / 15  
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
7. Limiting values  
Table 4. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
-0.5  
-50  
-0.5  
-0.5  
-
Max  
+4.6  
-
Unit  
V
VCC  
IIK  
supply voltage  
input clamping current  
input voltage  
VI < 0 V  
mA  
V
VI  
control inputs  
data inputs  
[1]  
[1]  
+4.6  
VCC + 0.5 V  
IOK  
VO  
output clamping current  
output voltage  
VO > VCC or VO < 0 V  
±50  
mA  
[1]  
-0.5  
-
VCC + 0.5 V  
IO  
output current  
VO = 0 V to VCC  
±50  
100  
-
mA  
ICC  
IGND  
Tstg  
Ptot  
supply current  
-
mA  
mA  
°C  
ground current  
-100  
-65  
-
storage temperature  
total power dissipation  
+150  
500  
Tamb = -40 °C to +85 °C  
mW  
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.  
8. Recommended operating conditions  
Table 5. Recommended operating conditions  
Symbol Parameter  
Conditions  
Min  
Typ  
Max Unit  
VCC  
supply voltage  
maximum speed performance  
CL = 30 pF  
2.3  
3.0  
1.2  
0
-
-
-
-
-
-
-
-
2.7  
3.6  
3.6  
VCC  
VCC  
+85  
20  
V
CL = 50 pF  
V
low-voltage applications  
V
VI  
input voltage  
V
VO  
output voltage  
0
V
Tamb  
Δt/ΔV  
ambient temperature  
input transition rise and fall rate  
in free air  
-40  
0
°C  
ns/V  
ns/V  
VCC = 2.3 V to 3.0 V  
VCC = 3.0 V to 3.6 V  
0
10  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
6 / 15  
 
 
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
9. Static characteristics  
Table 6. Static characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
Typ [1]  
Max  
Unit  
Tamb = -40 °C to +85 °C  
VIH  
HIGH-level input  
voltage  
VCC = 2.3 V to 2.7 V  
1.7  
2.0  
-
1.2  
1.5  
1.2  
1.5  
-
V
V
V
V
VCC = 2.7 V to 3.6 V  
-
VIL  
LOW-level input  
voltage  
VCC = 2.3 V to 2.7 V  
0.7  
0.8  
VCC = 2.7 V to 3.6 V  
-
VOH  
HIGH-level output  
voltage  
VI = VIH or VIL  
IO = -100 μA; VCC = 2.3 V to 3.6 V  
IO = -6 mA; VCC = 2.3 V  
IO = -12 mA; VCC = 2.3 V  
IO = -12 mA; VCC = 2.7 V  
IO = -12 mA; VCC = 3.0 V  
IO = -24 mA; VCC = 3.0 V  
VI = VIH or VIL  
VCC - 0.2  
VCC  
-
-
-
-
-
-
V
V
V
V
V
V
VCC - 0.3 VCC - 0.08  
VCC - 0.6 VCC - 0.26  
VCC - 0.5 VCC - 0.14  
VCC - 0.6 VCC - 0.09  
VCC - 1.0 VCC - 0.28  
VOL  
LOW-level output  
voltage  
IO = 100 μA; VCC = 2.3 V to 3.6 V  
IO = 6 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.3 V  
IO = 12 mA; VCC = 2.7 V  
IO = 24 mA; VCC = 3.0 V  
-
-
-
-
-
-
-
GND  
0.07  
0.15  
0.14  
0.27  
0.1  
0.20  
0.40  
0.70  
0.40  
0.55  
5
V
V
V
V
V
II  
input leakage current VI = VCC or GND; VCC = 2.3 V to 3.6 V  
μA  
μA  
IOZ  
OFF-state output  
current  
VI = VIH or VIL; VO = VCC or GND;  
VCC = 2.7 V to 3.6 V  
0.1  
10  
ICC  
supply current  
VCC = 2.3 V to 3.6 V; VI = VCC or GND;  
IO = 0 A  
-
-
0.2  
40  
μA  
μA  
ΔICC  
IBHL  
additional supply  
current  
per data I/O pin; VCC = 2.3 V to 3.6 V;  
VI = VCC - 0.6 V; IO = 0 A  
150  
750  
bus hold LOW current VCC = 2.3 V; VI = 0.7 V  
VCC = 3.0 V; VI = 0.8 V  
[2]  
[2]  
[2]  
[2]  
[2]  
45  
75  
-
150  
-
-
-
-
-
-
μA  
μA  
μA  
μA  
μA  
IBHH  
bus hold HIGH  
current  
VCC = 2.3 V; VI = 1.7 V  
VCC = 3.0 V; VI = 2.0 V  
VCC = 3.6 V  
-45  
-75  
500  
-175  
-
IBHLO  
IBHHO  
bus hold LOW  
overdrive current  
bus hold HIGH  
VCC = 3.6 V  
[2]  
-500  
-
-
μA  
overdrive current  
CI  
input capacitance  
-
-
4.0  
8.0  
-
-
pF  
pF  
CI/O  
input/output  
capacitance  
[1] All typical values are measured at Tamb = 25 °C.  
[2] Valid for data inputs of bus hold parts only.  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
7 / 15  
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
10. Dynamic characteristics  
Table 7. Dynamic characteristics  
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 10.  
Symbol Parameter  
Conditions  
Min  
Typ [1]  
Max  
Unit  
Tamb = -40 °C to +85 °C  
fmax  
maximum frequency  
see Fig. 8  
VCC = 2.3 V to 2.7 V  
[2]  
[3]  
150  
150  
150  
333  
340  
333  
-
-
-
MHz  
MHz  
MHz  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
tpd  
propagation delay  
An to Bn; Bn to An; see Fig. 6  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[4]  
[2]  
[3]  
1.0  
1.0  
-
2.8  
3.0  
3.0  
5.1  
4.2  
4.6  
ns  
ns  
ns  
LEAB, LEBA to Bn, An; see Fig. 8  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.1  
1.3  
-
3.5  
3.4  
3.6  
6.1  
4.8  
5.3  
ns  
ns  
ns  
CPAB, CPBA to Bn, An; see Fig. 8  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.0  
1.4  
-
3.3  
3.3  
3.4  
6.1  
4.9  
5.6  
ns  
ns  
ns  
ten  
enable time  
OEBA to An; see Fig. 7  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[4]  
[2]  
[3]  
1.3  
1.1  
-
2.8  
2.5  
3.3  
6.3  
5.0  
6.0  
ns  
ns  
ns  
OEAB to Bn; see Fig. 7  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.0  
1.0  
-
2.5  
2.4  
2.7  
5.8  
4.6  
5.3  
ns  
ns  
ns  
tdis  
disable time  
OEBA to An; see Fig. 7  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[4]  
[2]  
[3]  
1.3  
1.3  
-
2.5  
3.1  
3.3  
5.3  
4.2  
4.6  
ns  
ns  
ns  
OEAB to Bn; see Fig. 7  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.5  
1.4  
-
2.5  
2.9  
3.6  
6.2  
5.0  
5.7  
ns  
ns  
ns  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
8 / 15  
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
Symbol Parameter  
Conditions  
Min  
Typ [1]  
Max  
Unit  
tW  
pulse width  
set-up time  
hold time  
LEAB, LEBA HIGH; see Fig. 8  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
3.3  
3.3  
3.3  
0.8  
0.9  
0.7  
-
-
-
ns  
ns  
ns  
CPAB, CPBA HIGH or LOW; see Fig. 8  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
3.3  
3.3  
3.3  
2.0  
1.1  
1.4  
-
-
-
ns  
ns  
ns  
tsu  
An, Bn to CPAB, CPBA; see Fig. 9  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.7  
1.3  
1.4  
0.1  
-0.3  
-0.1  
-
-
-
ns  
ns  
ns  
An, Bn to LEAB, LEBA; see Fig. 9  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.1  
1.0  
1.0  
0.1  
0.3  
-
-
-
ns  
ns  
ns  
-0.2  
th  
An, Bn to CPAB, CPBA; see Fig. 9  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.7  
1.3  
1.6  
0.3  
0.4  
0.3  
-
-
-
ns  
ns  
ns  
An, Bn to LEAB, LEBA; see Fig. 9  
VCC = 2.3 V to 2.7 V  
VCC = 3.0 V to 3.6 V  
VCC = 2.7 V  
[2]  
[3]  
1.6  
1.2  
1.5  
0.3  
0.1  
0.1  
-
-
-
ns  
ns  
ns  
CPD  
power dissipation capacitance per buffer; VI = GND to VCC  
[5]  
outputs enabled  
outputs disabled  
-
-
21  
3
-
-
pF  
pF  
[1] All typical values are measured at Tamb = 25 °C.  
[2] Typical values are measured at VCC = 2.5 V.  
[3] Typical values are measured at VCC = 3.3 V.  
[4] tpd is the same as tPLH and tPHL  
ten is the same as tPZL and tPZH  
tdis is the same as tPLZ and tPHZ  
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).  
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:  
fi = input frequency in MHz;  
fo = output frequency in MHz;  
CL = output load capacitance in pF;  
VCC = supply voltage in Volts;  
N = total load switching outputs;  
Σ(CL × VCC 2 × fo) = sum of outputs.  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
9 / 15  
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
10.1. Waveforms and test circuit  
V
I
An, Bn  
input  
V
V
t
M
M
GND  
t
PHL  
PLH  
V
OH  
Bn, An  
output  
V
V
M
M
001aal734  
V
OL  
Measurement points are given in Table 8.  
VOL and VOH are typical output levels that occur with the output load.  
Fig. 6. Propagation delay, data input (An, Bn) to data output (Bn, An)  
V
I
OEAB, OEBA  
input  
V
V
M
M
t
GND  
t
PLZ  
PZL  
V
CC  
An, Bn output  
LOW-to-OFF  
OFF-to-LOW  
V
M
V
X
V
OL  
t
t
PZH  
PHZ  
V
OH  
V
Y
An, Bn output  
HIGH-to-OFF  
OFF-to-HIGH  
V
M
GND  
outputs  
enabled  
outputs  
disabled  
outputs  
enabled  
001aal721  
Measurement points are given in Table 8.  
VOL and VOH are typical output levels that occur with the output load.  
Fig. 7. 3-state output enable and disable times  
1 / f  
max  
V
LExx  
input  
CPxx  
input  
I
V
V
V
M
M
M
GND  
t
W
t
PLH  
t
PHL  
V
OH  
An, Bn  
output  
V
V
M
M
V
OL  
001aal720  
Measurement points are given in Table 8.  
VOL and VOH are typical output levels that occur with the output load.  
Fig. 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output,  
and pulse width  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
10 / 15  
 
 
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
V
I
An, Bn  
input  
V
V
V
M
V
M
M
M
GND  
t
su  
t
t
t
h
h
su  
V
I
CPxx, LExx  
input  
V
V
M
M
GND  
001aal722  
Measurement points are given in Table 8.  
Fig. 9. Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs)  
Table 8. Measurement points  
Supply voltage  
VCC  
Input  
VI  
Output  
VM  
VM  
VX  
VY  
1.2 V  
VCC  
VCC  
VCC  
2.7 V  
2.7 V  
0.5 × VCC  
0.5 × VCC  
0.5 × VCC  
1.5 V  
0.5 × VCC  
0.5 × VCC  
0.5 × VCC  
1.5 V  
VOL + 0.15 V  
VOL + 0.15 V  
VOL + 0.15 V  
VOL + 0.3 V  
VOL + 0.3 V  
VOH - 0.15 V  
VOH - 0.15 V  
VOH - 0.15 V  
VOH - 0.3 V  
VOH - 0.3 V  
1.8 V  
2.3 V to 2.7 V  
2.7 V  
3.0 V to 3.6 V  
1.5 V  
1.5 V  
V
EXT  
V
CC  
R
L
V
V
O
I
G
DUT  
R
T
C
L
R
L
mna616  
Test data is given in Table 9.  
Definitions for test circuit:  
RL = Load resistance.  
CL = Load capacitance includes jig and probe capacitance.  
RT = Termination resistance should be equal to Zo of pulse generator.  
VEXT = External voltage for measuring switching times.  
Fig. 10. Test circuit for measuring switching times  
Table 9. Test data  
Supply voltage  
VCC  
Input  
VI  
Load  
CL  
VEXT  
tr, tf  
RL  
tPLH, tPHL  
open  
tPLZ, tPZL  
2 × VCC  
2 × VCC  
2 × VCC  
2 × VCC  
2 × VCC  
tPHZ, tPZH  
GND  
1.2 V  
VCC  
VCC  
VCC  
2.7 V  
2.7 V  
≤ 2.0 ns  
≤ 2.0 ns  
≤ 2.0 ns  
2.5 ns  
2.5 ns  
30 pF  
30 pF  
30 pF  
50 pF  
50 pF  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
500 Ω  
1.8 V  
open  
GND  
2.3 V to 2.7 V  
2.7 V  
open  
GND  
open  
GND  
3.0 V to 3.6 V  
open  
GND  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
11 / 15  
 
 
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
11. Package outline  
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm  
SOT364-1  
E
D
A
X
c
H
v
M
A
y
E
Z
56  
29  
Q
A
2
(A )  
3
A
A
1
pin 1 index  
θ
L
p
L
detail X  
1
28  
w
M
b
e
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions).  
A
(1)  
(2)  
UNIT  
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.  
8o  
0o  
0.15  
0.05  
1.05  
0.85  
0.28  
0.17  
0.2  
0.1  
14.1  
13.9  
6.2  
6.0  
8.3  
7.9  
0.8  
0.4  
0.50  
0.35  
0.5  
0.1  
mm  
1.2  
0.5  
1
0.25  
0.08  
0.1  
0.25  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
99-12-27  
03-02-19  
SOT364-1  
MO-153  
Fig. 11. Package outline SOT364-1 (TSSOP56)  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
12 / 15  
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
12. Abbreviations  
Table 10. Abbreviations  
Acronym  
Description  
CMOS  
DUT  
ESD  
HBM  
MM  
Complementary Metal-Oxide Semiconductor  
Device Under Test  
ElectroStatic Discharge  
Human Body Model  
Machine Model  
TTL  
Transistor-Transistor Logic  
13. Revision history  
Table 11. Revision history  
Document ID  
Release date  
20211124  
Data sheet status  
Change notice Supersedes  
74ALVCH16501 v.7  
Modifications:  
Product data sheet  
-
74ALVCH16501 v.6  
Section 1 and Section 2 updated.  
Errata corrected in Table 4.  
74ALVCH16501 v.6  
Modifications:  
20190313  
Product data sheet  
-
74ALVCH16501 v.5  
The format of this data sheet has been redesigned to comply with the identity guidelines  
of Nexperia.  
Legal texts have been adapted to the new company name where appropriate.  
Type numbers 74ALVCH16501DL (SOT371-1) removed.  
74ALVCH16501 v.5  
Modifications:  
20120710  
Product data sheet  
-
74ALVCH16501 v.4  
Table 8 corrected (errata).  
74ALVCH16501 v.4  
Modifications:  
20111117  
Product data sheet  
-
74ALVCH16501 v.3  
Legal pages updated.  
74ALVCH16501 v.3  
74ALVCH16501 v.2  
74ALVCH16501 v.1  
20100402  
19980929  
19980929  
Product data sheet  
Product specification  
Product specification  
-
-
-
74ALVCH16501 v.2  
74ALVCH16501 v.1  
-
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
13 / 15  
 
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
injury, death or severe property or environmental damage. Nexperia and its  
suppliers accept no liability for inclusion and/or use of Nexperia products in  
such equipment or applications and therefore such inclusion and/or use is at  
the customer’s own risk.  
14. Legal information  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Data sheet status  
Document status Product  
Definition  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. Nexperia makes no representation  
or warranty that such applications will be suitable for the specified use  
without further testing or modification.  
[1][2]  
status [3]  
Objective [short]  
data sheet  
Development  
This document contains data from  
the objective specification for  
product development.  
Customers are responsible for the design and operation of their applications  
and products using Nexperia products, and Nexperia accepts no liability for  
any assistance with applications or customer product design. It is customer’s  
sole responsibility to determine whether the Nexperia product is suitable  
and fit for the customer’s applications and products planned, as well as  
for the planned application and use of customer’s third party customer(s).  
Customers should provide appropriate design and operating safeguards to  
minimize the risks associated with their applications and products.  
Preliminary [short]  
data sheet  
Qualification  
Production  
This document contains data from  
the preliminary specification.  
Product [short]  
data sheet  
This document contains the product  
specification.  
[1] Please consult the most recently issued document before initiating or  
completing a design.  
Nexperia does not accept any liability related to any default, damage, costs  
or problem which is based on any weakness or default in the customer’s  
applications or products, or the application or use by customer’s third party  
customer(s). Customer is responsible for doing all necessary testing for the  
customer’s applications and products using Nexperia products in order to  
avoid a default of the applications and the products or of the application or  
use by customer’s third party customer(s). Nexperia does not accept any  
liability in this respect.  
[2] The term 'short data sheet' is explained in section "Definitions".  
[3] The product status of device(s) described in this document may have  
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multiple devices. The latest product status information is available on  
the internet at https://www.nexperia.com.  
Definitions  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those  
given in the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
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data sheet shall define the specification of the product as agreed between  
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Limited warranty and liability — Information in this document is believed  
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representations or warranties, expressed or implied, as to the accuracy  
or completeness of such information and shall have no liability for the  
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Non-automotive qualified products — Unless this data sheet expressly  
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In no event shall Nexperia be liable for any indirect, incidental, punitive,  
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In the event that customer uses the product for design-in and use in  
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customer (a) shall use the product without Nexperia’s warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
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and (c) customer fully indemnifies Nexperia for any liability, damages or failed  
product claims resulting from customer design and use of the product for  
automotive applications beyond Nexperia’s standard warranty and Nexperia’s  
product specifications.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, Nexperia’s aggregate and cumulative liability towards customer  
for the products described herein shall be limited in accordance with the  
Terms and conditions of commercial sale of Nexperia.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Right to make changes — Nexperia reserves the right to make changes  
to information published in this document, including without limitation  
specifications and product descriptions, at any time and without notice. This  
document supersedes and replaces all information supplied prior to the  
publication hereof.  
Trademarks  
Suitability for use — Nexperia products are not designed, authorized or  
warranted to be suitable for use in life support, life-critical or safety-critical  
systems or equipment, nor in applications where failure or malfunction  
of an Nexperia product can reasonably be expected to result in personal  
Notice: All referenced brands, product names, service names and  
trademarks are the property of their respective owners.  
©
74ALVCH16501  
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Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
14 / 15  
 
Nexperia  
74ALVCH16501  
18-bit universal bus transceiver; 3-state  
Contents  
1. General description......................................................1  
2. Features and benefits.................................................. 1  
3. Ordering information....................................................1  
4. Functional diagram.......................................................2  
5. Pinning information......................................................4  
5.1. Pinning.........................................................................4  
5.2. Pin description.............................................................5  
6. Functional description................................................. 5  
7. Limiting values............................................................. 6  
8. Recommended operating conditions..........................6  
9. Static characteristics....................................................7  
10. Dynamic characteristics............................................ 8  
10.1. Waveforms and test circuit...................................... 10  
11. Package outline........................................................ 12  
12. Abbreviations............................................................13  
13. Revision history........................................................13  
14. Legal information......................................................14  
© Nexperia B.V. 2021. All rights reserved  
For more information, please visit: http://www.nexperia.com  
For sales office addresses, please send an email to: salesaddresses@nexperia.com  
Date of release: 24 November 2021  
©
74ALVCH16501  
All information provided in this document is subject to legal disclaimers.  
Nexperia B.V. 2021. All rights reserved  
Product data sheet  
Rev. 7 — 24 November 2021  
15 / 15  

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