74AHC595D
更新时间:2024-09-19 05:39:08
品牌:NEXPERIA
描述:8-bit serial-in/serial-out or parallel-out shift register with output latchesProduction
74AHC595D 概述
8-bit serial-in/serial-out or parallel-out shift register with output latchesProduction 移位寄存器
74AHC595D 规格参数
是否Rohs认证: | 符合 | 生命周期: | Active |
包装说明: | SOP, | Reach Compliance Code: | compliant |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.23 |
Is Samacsys: | N | 计数方向: | RIGHT |
系列: | AHC/VHC/H/U/V | JESD-30 代码: | R-PDSO-G16 |
JESD-609代码: | e4 | 长度: | 9.9 mm |
逻辑集成电路类型: | SERIAL IN PARALLEL OUT | 湿度敏感等级: | 1 |
位数: | 8 | 功能数量: | 1 |
端子数量: | 16 | 最高工作温度: | 125 °C |
最低工作温度: | -40 °C | 输出特性: | 3-STATE |
输出极性: | TRUE | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | SOP | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 峰值回流温度(摄氏度): | 260 |
传播延迟(tpd): | 20.1 ns | 认证状态: | Not Qualified |
座面最大高度: | 1.75 mm | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 2 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | AUTOMOTIVE | 端子面层: | Nickel/Palladium/Gold (Ni/Pd/Au) |
端子形式: | GULL WING | 端子节距: | 1.27 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | 30 |
触发器类型: | POSITIVE EDGE | 宽度: | 3.9 mm |
最小 fmax: | 90 MHz | Base Number Matches: | 1 |
74AHC595D 数据手册
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PDF下载74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with
output latches
Rev. 6 — 26 May 2020
Product data sheet
1. General description
The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and 3-state outputs. Both the shift and storage register have separate clocks. The device
features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous
reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH
transitions of the SHCP input. The data in the shift register is transferred to the storage register
on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the storage register. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes
the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect
the state of the registers. The 74AHCT595 features TTL compatible inputs. Both 74AHC595
and 74AHCT595 inputs are overvoltage tolerant. This feature allows the use of these devices as
translators in mixed voltage environments.
2. Features and benefits
•
Wide supply voltage range from 2.0 V to 5.5 V
•
•
•
•
•
•
Balanced propagation delays
All inputs have Schmitt-trigger action
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Input levels:
•
•
The 74AHC595 operates with CMOS input levels
The 74AHCT595 operates with TTL input levels
•
ESD protection:
•
•
•
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
•
•
•
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Applications
•
•
Serial-to-parallel data conversion
Remote control holding register
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
4. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
Description
Version
74AHC595D
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AHCT595D
74AHC595PW
74AHCT595PW
74AHC595BQ
74AHCT595BQ
TSSOP16
plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5 × 3.5 × 0.85 mm
SOT763-1
5. Functional diagram
14 DS
11 SHCP
10 MR
8-STAGE SHIFT REGISTER
Q7S
9
12 STCP
13 OE
8-BIT STORAGE REGISTER
3-STATE OUTPUTS
Q0
15
Q1 Q2 Q3 Q4 Q5 Q6 Q7
1
2
3
4
5
6
7
mna554
Fig. 1. Functional diagram
13
12
EN3
C2
11
12
10
11
SHCP
SRG8
STCP
R
9
15
1
C1/
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
14
15
1
1D
2D
3
2
2
14
3
DS
3
4
4
5
5
6
6
7
Q7
7
MR
10
OE
9
13
mna552
mna553
Fig. 2. Logic symbol
Fig. 3. IEC logic symbol
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
2 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
STAGE 0
Q
STAGES 1 TO 6
STAGE 7
D Q
DS
Q7S
D
D
Q
FF7
CP
FF0
CP
R
R
SHCP
MR
D
Q
D
Q
LATCH
CP
LATCH
CP
STCP
OE
mna555
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig. 4. Logic diagram
6. Pinning information
6.1. Pinning
74AHC595
74AHCT595
terminal 1
index area
2
3
4
5
6
7
15
14
13
12
11
10
Q2
Q0
Q3
Q4
Q5
Q6
Q7
DS
74AHC595
74AHCT595
OE
STCP
SHCP
MR
1
2
3
4
5
6
7
8
16
V
Q1
Q2
CC
(1)
GND
15
14
13
12
11
10
9
Q0
Q3
DS
Q4
OE
001aae483
Q5
STCP
SHCP
MR
Q6
Transparent top view
Q7
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
GND
Q7S
001aae538
Fig. 5. Pin configuration SOT109-1 (SO16) and
SOT403-1 (TSSOP16)
Fig. 6. Pin configuration SOT763-1 (DHVQFN16)
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
3 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
6.2. Pin description
Table 2. Pin description
Symbol
Pin
Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
15, 1, 2, 3, 4, 5, 6, 7
parallel data output
ground (0 V)
GND
Q7S
MR
8
9
serial data output
10
11
12
13
14
16
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
SHCP
STCP
OE
DS
VCC
supply voltage
7. Functional description
Table 3. Function table
H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
Control
Input Output
Function
SHCP STCP OE
MR
L
DS
X
Q7S
L
Qn
NC
L
X
X
X
↑
X
↑
L
L
H
L
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
L
X
L
X
X
L
X
L
Z
shift register clear; parallel outputs in high-impedance OFF-state
H
H
Q6S
NC
logic HIGH-level shifted into shift register stage 0. Contents of
all shift register stages shifted through, e.g. previous state of
stage 6 (internal Q6S) appears on the serial output (Q7S).
X
↑
↑
↑
L
L
H
H
X
X
NC
QnS
QnS
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
Q6S
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
4 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
SHCP
DS
STCP
MR
OE
Q0
Z-state
Z-state
Q1
Z-state
Z-state
Q6
Q7
Q7S
mna556
Fig. 7. Timing diagram
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
-0.5
-0.5
-20
-20
-25
-
Max
+7.0
+7.0
-
Unit
V
VCC
VI
supply voltage
input voltage
V
IIK
input clamping current
output clamping current
output current
VI < -0.5 V
[1]
[1]
mA
mA
mA
mA
mA
°C
IOK
IO
VO < -0.5 V or VO > VCC + 0.5 V
VO = -0.5 V to (VCC + 0.5 V)
+20
+25
+75
-
ICC
IGND
Tstg
Ptot
supply current
ground current
-75
-65
-
storage temperature
total power dissipation
+150
500
Tamb = -40 °C to +125 °C
[2]
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SOT109-1 (SO16) package: Ptot derates linearly with 12.4 mW/K above 110 °C.
For SOT403-1 (TSSOP16) package: Ptot derates linearly with 8.5 mW/K above 91 °C.
For SOT763-1 (DHVQFN16) package: Ptot derates linearly with 11.2 mW/K above 106 °C.
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
5 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
9. Recommended operating conditions
Table 5. Operating conditions
Symbol Parameter
Conditions
74AHC595
74AHCT595
Unit
Min
2.0
0
Typ
Max
5.5
Min
4.5
0
Typ
Max
5.5
VCC
VI
supply voltage
input voltage
5.0
5.0
V
V
V
-
5.5
-
5.5
VO
output voltage
ambient temperature
0
-
VCC
+125
100
20
0
-
VCC
Tamb
Δt/ΔV
-40
-
+25
-40
-
+25
+125 °C
input transition rise and fall rate VCC = 3.0 V to 3.6 V
VCC = 4.5 V to 5.5 V
-
-
-
-
-
ns/V
-
-
20
ns/V
10. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Typ
Max
Min
Max
Min
Max
74AHC595
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 3.0 V
VCC = 5.5 V
VCC = 2.0 V
VCC = 3.0 V
VCC = 5.5 V
VI = VIH or VIL
1.5
-
-
-
-
-
-
-
-
1.5
-
-
1.5
-
-
V
V
V
V
V
V
2.1
2.1
2.1
3.85
-
3.85
-
3.85
-
VIL
LOW-level
input voltage
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
-
-
-
0.5
0.9
1.65
VOH
HIGH-level
output voltage
IO = -50 μA; VCC = 2.0 V
1.9
2.9
2.0
3.0
4.5
-
-
-
-
-
-
1.9
2.9
-
-
-
-
-
1.9
2.9
-
-
-
-
-
V
V
V
V
V
IO = -50 μA; VCC = 3.0 V
IO = -50 μA; VCC = 4.5 V
IO = -4.0 mA; VCC = 3.0 V
IO = -8.0 mA; VCC = 4.5 V
4.4
4.4
4.4
2.58
3.94
2.48
3.80
2.40
3.70
-
VOL
LOW-level
VI = VIH or VIL
output voltage
IO = 50 μA; VCC = 2.0 V
IO = 50 μA; VCC = 3.0 V
IO = 50 μA; VCC = 4.5 V
IO = 4.0 mA; VCC = 3.0 V
IO = 8.0 mA; VCC = 4.5 V
-
-
-
-
-
-
0
0
0
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
-
-
-
-
-
-
0.1
0.1
V
V
V
V
V
0.1
0.1
0.1
0.36
0.36
0.1
0.44
0.44
1.0
0.55
0.55
-
II
input leakage VI = 5.5 V or GND;
-
2.0 μA
current
VCC = 0 V to 5.5 V
IOZ
ICC
CI
OFF-state
VI = VIH or VIL;
-
-
-
-
-
±0.25
4.0
-
-
-
±2.5
40
-
-
-
±10 μA
output current VO = VCC or GND; VCC = 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
80
10
μA
pF
input
3
10
10
capacitance
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
6 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
Symbol Parameter
Conditions
25 °C
Typ
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min
Max
Min
Max
Min
Max
74AHCT595
VIH
VIL
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
-
-
-
2.0
-
-
2.0
-
-
V
V
LOW-level
0.8
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = -50 μA
4.4
4.5
-
-
-
4.4
-
-
4.4
-
-
V
V
IO = -8.0 mA
3.94
3.80
3.70
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 50 μA
-
-
-
0
-
0.1
0.36
0.1
-
-
-
0.1
0.44
1.0
-
-
-
0.1
V
V
IO = 8.0 mA
0.55
II
input leakage VI = 5.5 V or GND;
-
2.0 μA
current
VCC = 0 V to 5.5 V
IOZ
ICC
ΔICC
OFF-state
VI = VIH or VIL;
-
-
-
-
-
-
±0.25
4.0
-
-
-
±2.5
40
-
-
-
±10 μA
output current VO = VCC or GND; VCC = 5.5 V
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
80
μA
additional
per input pin; VI = VCC - 2.1 V;
1.35
1.5
1.5 mA
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
CI
input
-
3
10
-
10
-
10
pF
capacitance
11. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 13.
Symbol Parameter Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min Typ [1] Max
Min
Max
Min
Max
74AHC595
tpd
propagation SHCP to Q7S; see Fig. 8
[2]
[2]
delay
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
STCP to Qn; see Fig. 9
-
-
-
-
5.7
7.7
4.0
5.4
13.0
16.5
8.2
1.0
1.0
1.0
1.0
15.0
18.5
9.4
1.0
1.0
1.0
1.0
16.5 ns
20.1 ns
10.5 ns
12.5 ns
10.0
11.4
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
-
-
-
5.9
7.7
4.2
5.5
11.9
15.4
7.4
1.0
1.0
1.0
1.0
13.5
17.0
8.5
1.0
1.0
1.0
1.0
15.0 ns
18.5 ns
9.5 ns
11.5 ns
9.0
10.5
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
7 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
Symbol Parameter Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min Typ [1] Max
Min
Max
Min
Max
tPHL
HIGH
MR to Q7S; see Fig. 11
to LOW
propagation
delay
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
-
-
-
5.9
7.4
4.4
5.6
12.8
16.3
8.0
1.0
1.0
1.0
1.0
13.7
17.2
9.1
1.0
1.0
1.0
1.0
15.0 ns
18.7 ns
10.0 ns
12.0 ns
10.0
11.1
ten
enable time OE to Qn; see Fig. 12
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
[4]
-
-
-
-
5.6
7.4
4.0
5.3
11.5
15.0
8.6
1.0
1.0
1.0
1.0
13.5
17.0
10.0
12.0
1.0
1.0
1.0
1.0
15.0 ns
18.5 ns
11.0 ns
13.0 ns
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
10.6
tdis
disable time OE to Qn; see Fig. 12
VCC = 3.0 V to 3.6 V; CL = 15 pF
VCC = 3.0 V to 3.6 V; CL = 50 pF
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
-
-
-
5.4
8.7
3.8
5.8
11.0
15.7
8.0
1.0
1.0
1.0
1.0
13.0
16.2
9.5
1.0
1.0
1.0
1.0
14.5 ns
17.5 ns
10.5 ns
12.0 ns
10.3
11.0
fmax
maximum
frequency
SHCP or STCP; see Fig. 8 and Fig. 9
VCC = 3.0 V to 3.6 V
80
125
170
-
-
60
-
-
40
90
-
-
MHz
VCC = 4.5 V to 5.5 V
130
110
MHz
tW
pulse width SHCP HIGH or LOW; see Fig. 8
VCC = 3.0 V to 3.6 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
STCP HIGH or LOW; see Fig. 9
VCC = 3.0 V to 3.6 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
MR LOW; see Fig. 11
VCC = 3.0 V to 3.6 V
5.0
5.0
-
-
-
-
5.0
5.0
-
-
5.0
5.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
tsu
set-up time DS to SHCP; see Fig. 10
VCC = 3.0 V to 3.6 V
3.5
3.0
-
-
-
-
3.5
3.0
-
-
3.5
3.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
SHCP to STCP; see Fig. 9
VCC = 3.0 V to 3.6 V
8.5
5.0
-
-
-
-
8.5
5.0
-
-
8.5
5.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
th
hold time
DS to SHCP; see Fig. 10
VCC = 3.0 V to 3.6 V
1.5
2.0
-
-
-
-
1.5
2.0
-
-
1.5
2.0
-
-
ns
ns
VCC = 4.5 V to 5.5 V
trec
recovery
time
MR to SHCP; see Fig. 11
VCC = 3.0 V to 3.6 V
3.0
2.5
-
-
-
-
-
-
3.0
2.5
-
-
-
-
3.0
2.5
-
-
-
-
ns
ns
pF
VCC = 4.5 V to 5.5 V
CPD
power
dissipation
capacitance
fi = 1 MHz; VI = GND to VCC
[5]
[6]
180
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Product data sheet
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8 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
Symbol Parameter Conditions
25 °C
-40 °C to
+85 °C
-40 °C to
+125 °C
Unit
Min Typ [1] Max
Min
Max
Min
Max
74AHCT595
tpd
propagation SHCP to Q7S; see Fig. 8
[2]
[2]
delay
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
STCP to Qn; see Fig. 9
-
-
3.8
5.2
8.2
1.0
1.0
9.0
1.0
1.0
10.0 ns
12.0 ns
10.0
11.0
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
MR to Q7S; see Fig. 11
-
-
4.0
5.3
7.4
9.0
1.0
1.0
8.5
1.0
1.0
9.5 ns
11.5 ns
10.5
tPHL
HIGH
to LOW
propagation
delay
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
-
-
4.6
5.8
8.2
1.0
1.0
9.5
1.0
1.0
10.5 ns
12.5 ns
10.5
11.5
ten
enable time OE to Qn; see Fig. 12
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
disable time OE to Qn; see Fig. 12
[3]
[4]
-
-
4.8
6.2
9.0
1.0
1.0
11.0
13.0
1.0
1.0
12.0 ns
14.5 ns
11.6
tdis
VCC = 4.5 V to 5.5 V; CL = 15 pF
VCC = 4.5 V to 5.5 V; CL = 50 pF
SHCP and STCP;
-
-
3.6
5.8
6.9
10.3
-
1.0
1.0
8.0
11.0
-
1.0
1.0
90
9.0 ns
12.0 ns
fmax
maximum
130
170
110
-
MHz
frequency VCC = 4.5 V to 5.5 V;
see Fig. 8 and Fig. 9
tW
pulse width SHCP HIGH or LOW;
5.0
5.0
5.0
3.0
5.0
2.0
3.0
-
-
-
-
-
-
-
-
-
-
5.0
5.0
5.0
3.0
5.0
2.0
3.0
-
-
-
-
-
-
-
-
-
5.0
5.0
5.0
3.0
5.0
2.0
3.0
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
pF
VCC = 4.5 V to 5.5 V; see Fig. 8
STCP HIGH or LOW;
VCC = 4.5 V to 5.5 V; see Fig. 9
-
MR LOW; VCC = 4.5 V to 5.5 V;
see Fig. 11
-
tsu
set-up time DS to SHCP; VCC = 4.5 V to 5.5 V;
see Fig. 10
-
SHCP to STCP; VCC = 4.5 V to 5.5 V;
see Fig. 9
-
th
hold time
DS to SHCP; VCC = 4.5 V to 5.5 V;
see Fig. 10
-
-
trec
CPD
recovery
time
MR to SHCP; VCC = 4.5 V to 5.5 V;
see Fig. 11
power
fi = 1 MHz; VI = GND to VCC
[5]
[6]
190
dissipation
capacitance
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH
[3] ten is the same as tPZL and tPZH
[4] tdis is the same as tPLZ and tPHZ
.
.
.
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
[6] All 9 outputs switching.
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74AHC_AHCT595
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
9 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
11.1. Waveforms and test circuit
1/f
max
V
I
SHCP input
GND
V
M
t
W
t
t
PHL
PLH
V
OH
V
Q7S output
V
M
OL
mna557
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 8. Shift clock pulse, maximum frequency and input to output propagation delays
V
I
SHCP input
GND
V
M
t
1/f
max
su
V
I
STCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
Qn output
M
V
OL
mna558
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 9. Storage clock to output propagation delays
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74AHC_AHCT595
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
10 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
V
I
V
SHCP input
M
GND
t
t
su
su
M
t
t
h
h
V
I
V
DS input
GND
V
OH
V
Q7S output
M
V
OL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 10. Data set-up and hold times
V
I
V
MR input
M
GND
t
t
rec
W
V
I
SHCP input
Q7S output
V
M
GND
t
PHL
V
OH
V
M
V
OL
mna561
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 11. Master reset to output propagation delays
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74AHC_AHCT595
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
11 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
V
I
V
OE input
M
GND
t
t
PZL
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
M
V
+ 0.3 V
V
OL
V
OL
t
t
PHZ
PZH
V
OH
- 0.3 V
OH
output
V
HIGH-to-OFF
OFF-to-HIGH
M
GND
outputs
enabled
outputs
enabled
outputs
disabled
mna450
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 12. Enable and disable times
Table 8. Measurement points
Type
Input
VM
Output
VM
74AHC595
0.5VCC
1.5 V
0.5VCC
0.5VCC
74AHCT595
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74AHC_AHCT595
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
12 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
V
V
CC
CC
V
I
V
O
R
L
S1
G
open
DUT
R
T
C
L
001aad983
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig. 13. Test circuit for measuring switching times
Table 9. Test data
Type
Input
VI
Load
S1 position
tPHL, tPLH
open
tr, tf
CL
RL
tPZH, tPHZ
GND
tPZL, tPLZ
VCC
74AHC595
VCC
3.0 V
≤ 3.0 ns
≤ 3.0 ns
15 pF, 50 pF
15 pF, 50 pF
1 kΩ
1 kΩ
74AHCT595
open
GND
VCC
©
74AHC_AHCT595
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
13 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
E
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.1
0.25
0.01
8o
0o
0.0100
0.0075
0.010 0.057
0.004 0.049
0.019
0.014
0.39
0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig. 14. Package outline SOT109-1 (SO16)
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74AHC_AHCT595
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Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
14 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
1
0.2
0.13
0.1
0.25
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig. 15. Package outline SOT403-1 (TSSOP16)
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
15 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
SOT763-1
B
A
D
A
A
1
E
c
detail X
terminal 1
index area
C
terminal 1
index area
e
1
y
y
e
b
v
M
C
C
A
B
C
1
w
M
2
7
L
1
8
9
E
h
e
16
15
10
D
h
X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
h
e
e
y
D
D
E
L
v
w
y
1
1
h
max.
0.05 0.30
0.00 0.18
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
0.3
mm
0.05
0.1
1
0.2
0.5
2.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
02-10-17
03-01-27
SOT763-1
- - -
MO-241
- - -
Fig. 16. Package outline SOT763-1 (DHVQFN16)
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74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
16 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
13. Abbreviations
Table 10. Abbreviations
Acronym
Description
CDM
CMOS
ESD
HBM
MM
Charged Device Model
Complementary Metal-Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11. Revision history
Document ID
Release date Data sheet status
20200526 Product data sheet
Change notice Supersedes
- 74AHC_AHCT595 v.5
74AHC_AHCT595 v.6
Modifications:
•
The format of this data sheet has been redesigned to comply with the identity
guidelines of Nexperia.
•
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 1 and Section 2 updated.
Fig. 7: Timing diagram updated with SHCP waveform.
Table 4: Derating values for Ptot total power dissipation updated.
Table 7: Propagation delay symbol and parameter corrected (Errata).
74AHC_AHCT595 v.5
Modifications:
20120704
Product data sheet
-
74AHC_AHCT595 v.4
•
Added GND in the pin configuration drawing DHVQFN16 (errata)
74AHC_AHCT595 v.4
74AHC_AHCT595 v.3
74AHC_AHCT595 v.2
74AHC_AHCT595 v.1
20090811
20080425
20060323
20000315
Product data sheet
Product data sheet
Product data sheet
Product specification
-
-
-
-
74AHC_AHCT595 v.3
74AHC_AHCT595 v.2
74AHC_AHCT595 v.1
-
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74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
17 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
injury, death or severe property or environmental damage. Nexperia and its
suppliers accept no liability for inclusion and/or use of Nexperia products in
such equipment or applications and therefore such inclusion and/or use is at
the customer’s own risk.
15. Legal information
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Data sheet status
Document status Product
Definition
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no representation
or warranty that such applications will be suitable for the specified use
[1][2]
status [3]
Objective [short]
data sheet
Development
This document contains data from
the objective specification for
product development.
without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia accepts no liability for
any assistance with applications or customer product design. It is customer’s
sole responsibility to determine whether the Nexperia product is suitable
and fit for the customer’s applications and products planned, as well as
for the planned application and use of customer’s third party customer(s).
Customers should provide appropriate design and operating safeguards to
minimize the risks associated with their applications and products.
Preliminary [short]
data sheet
Qualification
Production
This document contains data from
the preliminary specification.
Product [short]
data sheet
This document contains the product
specification.
[1] Please consult the most recently issued document before initiating or
completing a design.
Nexperia does not accept any liability related to any default, damage, costs
or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using Nexperia products in order to
avoid a default of the applications and the products or of the application or
use by customer’s third party customer(s). Nexperia does not accept any
liability in this respect.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have
changed since this document was published and may differ in case of
multiple devices. The latest product status information is available on
the internet at https://www.nexperia.com.
Definitions
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any representations or
warranties as to the accuracy or completeness of information included herein
and shall have no liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the relevant
full data sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of commercial sale — Nexperia products are
sold subject to the general terms and conditions of commercial sale, as
published at http://www.nexperia.com/profile/terms, unless otherwise agreed
in a valid written individual agreement. In case an individual agreement is
concluded only the terms and conditions of the respective agreement shall
apply. Nexperia hereby expressly objects to applying the customer’s general
terms and conditions with regard to the purchase of Nexperia products by
customer.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and customer have explicitly
agreed otherwise in writing. In no event however, shall an agreement be
valid in which the Nexperia product is deemed to offer functions and qualities
beyond those described in the Product data sheet.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no responsibility
for the content in this document if provided by an information source outside
of Nexperia.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific Nexperia product is automotive qualified, the
product is not suitable for automotive use. It is neither qualified nor tested in
accordance with automotive testing or application requirements. Nexperia
accepts no liability for inclusion and/or use of non-automotive qualified
products in automotive equipment or applications.
In no event shall Nexperia be liable for any indirect, incidental, punitive,
special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without Nexperia’s warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
Nexperia’s specifications such use shall be solely at customer’s own risk,
and (c) customer fully indemnifies Nexperia for any liability, damages or failed
product claims resulting from customer design and use of the product for
automotive applications beyond Nexperia’s standard warranty and Nexperia’s
product specifications.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards customer
for the products described herein shall be limited in accordance with the
Terms and conditions of commercial sale of Nexperia.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Right to make changes — Nexperia reserves the right to make changes
to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
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74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
18 / 19
Nexperia
74AHC595; 74AHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
Contents
1. General description......................................................1
2. Features and benefits.................................................. 1
3. Applications.................................................................. 1
4. Ordering information....................................................2
5. Functional diagram.......................................................2
6. Pinning information......................................................3
6.1. Pinning.........................................................................3
6.2. Pin description.............................................................4
7. Functional description................................................. 4
8. Limiting values............................................................. 5
9. Recommended operating conditions..........................6
10. Static characteristics..................................................6
11. Dynamic characteristics.............................................7
11.1. Waveforms and test circuit.......................................10
12. Package outline........................................................ 14
13. Abbreviations............................................................17
14. Revision history........................................................17
15. Legal information......................................................18
© Nexperia B.V. 2020. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 26 May 2020
©
74AHC_AHCT595
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 6 — 26 May 2020
19 / 19
74AHC595D 替代型号
型号 | 制造商 | 描述 | 替代类型 | 文档 |
74AHC595D | NXP | 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state | 功能相似 |
74AHC595D 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
74AHC595D,118 | NXP | 74AHC(T)595 - 8-bit serial-in/serial-out or parallel-out shift register SOP 16-Pin | 获取价格 | |
74AHC595D-Q100 | NXP | AHC/VHC/H/U/V SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16 | 获取价格 | |
74AHC595D-Q100 | NEXPERIA | 8-bit serial-in/serial-out or parallel-out shift register with output latches | 获取价格 | |
74AHC595D-T | NXP | IC AHC/VHC/H/U/V SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 3.90 MM, PLASTIC, MS-012, SOT109-1, SOP-16, Shift Register | 获取价格 | |
74AHC595PW | NXP | 8-bit serial-in/serial or parallel-out shift register with output latches; 3-state | 获取价格 | |
74AHC595PW | NEXPERIA | 8-bit serial-in/serial-out or parallel-out shift register with output latchesProduction | 获取价格 | |
74AHC595PW,118 | NXP | 74AHC(T)595 - 8-bit serial-in/serial-out or parallel-out shift register TSSOP 16-Pin | 获取价格 | |
74AHC595PW,653 | NXP | Serial In Parallel Out, AHC/VHC/H/U/V Series, 8-Bit, Right Direction, True Output, CMOS, PDSO16 | 获取价格 | |
74AHC595PW-Q100 | NEXPERIA | 8-bit serial-in/serial-out or parallel-out shift register with output latches | 获取价格 | |
74AHC595PW-T | NXP | IC AHC/VHC/H/U/V SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, 4.40 MM, PLASTIC, MO-153, SOT403-1, TSSOP-16, Shift Register | 获取价格 |
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