74AHC574D_技术文档

74AHC574; 74AHCT574

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

Rev. 02 — 24 January 2008

Product data sheet

1. General description

The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin

compatible with Low Power Schottky TTL (LSTTL). They are speciﬁed in compliance with

JEDEC standard no. 7A.

The 74AHC574; 74AHCT574 are octal D-type ﬂip-ﬂops featuring separate D-type inputs

for each ﬂip-ﬂop and 3-state outputs for bus oriented applications. A clock (CP) and an

output enable (OE) input are common to all ﬂip-ﬂops.

The 8 ﬂip-ﬂops will store the state of their individual D-inputs that meet the set-up and hold

times requirements on the LOW-to-HIGH CP transition.

When OE is LOW the contents of the 8 ﬂip-ﬂops are available at the outputs. When OE is

HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does

not affect the state of the ﬂip-ﬂops.

The 74AHC574; 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but

has non-inverting outputs. The 74AHC574; 74AHCT574 is functionally identical to

the 74AHC374; 74AHCT374, but has a different pinning.

2. Features

I Balanced propagation delays

I All inputs have a Schmitt-trigger action

I 3-state non-inverting outputs for bus orientated applications

I 8-bit positive, edge-triggered register

I Independent register and 3-state buffer operation

I Common 3-state output enable input

I For 74AHC574 only: operates with CMOS input levels

I For 74AHCT574 only: operates with TTL input levels

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range

−40 °C to +125 °C

Name

Description

Version

74AHC574D

SO20

plastic small outline package; 20 leads;

body width 7.5 mm

SOT163-1

74AHCT574D

74AHC574PW

74AHCT574PW

74AHC574BQ

74AHCT574BQ

−40 °C to +125 °C

TSSOP20

plastic thin shrink small outline package; 20 leads; SOT360-1

body width 4.4 mm

DHVQFN20 plastic dual in-line compatible thermal enhanced

very thin quad ﬂat package; no leads; 20 terminals;

body 2.5 × 4.5 × 0.85 mm

SOT764-1

4. Functional diagram

D0

D1

D2

D3

D4

D5

D6

D7

Q0

2

3

4

5

6

7

8

9

19

Q1 18

17

Q2

FF1

to

FF8

Q3 16

Q4 15

3-STATE

OUTPUTS

Q5

14

Q6 13

Q7 12

CP

OE

11

1

mna800

Fig 1. Functional diagram

D0

D1

D2

D3

D4

D5

D6

D7

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

CP

FF1

FF2

FF3

FF4

FF5

FF6

FF7

FF8

CP

OE

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

001aah077

Fig 2. Logic diagram

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

2 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

11

C1

1

EN

11

CP

2

19

1D

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

3

4

5

18

17

16

6

7

8

9

15

14

13

12

OE

1

mna798

mna446

Fig 3. Logic symbol

Fig 4. IEC logic symbol

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

3 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

5. Pinning information

5.1 Pinning

74AHC574

74AHCT574

terminal 1

index area

74AHC574

74AHCT574

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

D0

D1

D2

D3

D4

D5

D6

D7

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

1

2

20

19

18

17

16

15

14

13

12

11

OE

D0

V

CC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CP

3

D1

4

D2

5

D3

6

D4

(1)

GND

7

D5

8

D6

9

D7

001aah666

10

GND

001aah037

Transparent top view

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as a

supply pin or input.

Fig 5. Pin conﬁguration SO20, TSSOP20

Fig 6. Pin conﬁguration DHVQFN20

5.2 Pin description

Table 2.

Symbol

OE

Pin description

Description

1

3-state output enable input (active LOW)

data input

D[0:7]

GND

CP

2, 3, 4, 5, 6, 7, 8, 9

10

11

ground (0 V)

clock input (LOW-to-HIGH, edge triggered)

Q[0:7]

V_CC

19, 18, 17, 16, 15, 14, 13, 12 3-state ﬂip-ﬂop output

20 supply voltage

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

4 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

6. Functional description

Table 3.

Function table^[1]

Operating mode

Input

OE

L

Internal

ﬂip-ﬂop

Output

CP

↑

Dn

Qn

L

Load and read register

Load register and disable output

l

L

↑

h

l

H

L

H

Z

H

↑

H

↑

h

H

Z

[1] H = HIGH voltage level;

h = HIGH voltage level one setup time prior to the HIGH-to-LOW CP transition;

L = LOW voltage level;

l = LOW voltage level one setup time prior to the HIGH-to-LOW CP transition;

Z = high-impedance OFF-state;

↑ = LOW-to-HIGH clock transition.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

V_CC

V_I

Parameter

Conditions

Min

−0.5

−20

-

Max

+7.0

-

Unit

V

supply voltage

input voltage

V

[1]

I_IK

input clamping current

output clamping current

output current

V_I< −0.5 V

mA

°C

I_OK

V_O< −0.5 V or V_O> V_CC+ 0.5 V

V_O= −0.5 V to (V_CC+ 0.5 V)

±20

±25

75

I_O

-

I_CC

supply current

-

I_GND

T_stg

P_tot

ground current

−75

−65

-

storage temperature

total power dissipation

SO20 package

+150

T_amb= −40 °C to +125 °C

[2]

[3]

[4]

-

500

mW

TSSOP20 package

DHVQFN20 package

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] P_totderates linearly with 8 mW/K above 70 °C.

[3] P_totderates linearly with 5.5 mW/K above 60 °C.

[4] P_totderates linearly with 4.5 mW/K above 60 °C.

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

5 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

8. Recommended operating conditions

Table 5.

Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

74AHC574

74AHCT574

Unit

Min

2.0

0

Typ

Max

5.5

Min

4.5

0

Typ

Max

5.5

V_CC

V_I

supply voltage

input voltage

5.0

V

-

5.5

-

5.5

V_O

output voltage

ambient temperature

0

-

V_CC

+125

100

20

0

-

V_CC

T_amb

∆t/∆V

−40

-

+25

−40

-

+25

+125 °C

input transition rise

and fall rate

V_CC= 3.3 V ± 0.3 V

V_CC= 5.0 V ± 0.5 V

-

ns/V

-

20

9. Static characteristics

Table 6.

Static characteristics

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

For type 74AHC574

V_IH

HIGH-level

input voltage

V_CC= 2.0 V

1.5

-

1.5

-

1.5

-

V

V_CC= 3.0 V

2.1

V_CC= 5.5 V

3.85

-

3.85

-

3.85

-

V_IL

LOW-level

input voltage

V_CC= 2.0 V

-

0.5

0.9

1.65

-

0.5

0.9

1.65

-

0.5

0.9

1.65

V_CC= 3.0 V

V_CC= 5.5 V

V_OH

HIGH-level

V_I= V_IHor V_IL

output voltage

I_O= −50 µA; V_CC= 2.0 V

I_O= −50 µA; V_CC= 3.0 V

I_O= −50 µA; V_CC= 4.5 V

I_O= −4.0 mA; V_CC= 3.0 V

I_O= −8.0 mA; V_CC= 4.5 V

V_I= V_IHor V_IL

1.9

2.9

2.0

3.0

4.5

-

1.9

2.9

-

1.9

2.9

-

V

4.4

2.58

3.94

2.48

3.8

2.40

3.70

-

V_OL

LOW-level

output voltage

I_O= 50 µA; V_CC= 2.0 V

I_O= 50 µA; V_CC= 3.0 V

I_O= 50 µA; V_CC= 4.5 V

I_O= 4.0 mA; V_CC= 3.0 V

I_O= 8.0 mA; V_CC= 4.5 V

V_I= V_IHor V_IL;

-

0

-

0.1

-

0.1

-

0.1

V

0.1

V

0.36

±0.25

0.44

±2.5

0.55

±10.0

V

-

V

I_OZ

OFF-state

-

µA

output current V_O= V_CCor GND;

_CC= 5.5 V

V

I_I

input leakage V_I= 5.5 V or GND;

current _CC= 0 V to 5.5 V

-

0.1

4.0

-

1.0

40

-

©

2.0

80

µA

V

I_CC

supply current V_I= V_CCor GND; I_O= 0 A;

_CC= 5.5 V

V

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

6 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

Table 6.

Static characteristics …continued

Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ Max

Min

Max

Min

Max

C_I

input

capacitance

-

3.0

10

-

10

-

10

pF

C_O

output

-

4.0

-

capacitance

For type 74AHCT574

V_IH

HIGH-level

input voltage

V_CC= 4.5 V to 5.5 V

2.0

-

2.0

-

2.0

-

V

V_IL

LOW-level

0.8

input voltage

V_OH

HIGH-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= −50 µA

4.4

4.5

-

4.4

3.8

-

4.4

-

V

I_O= −8.0 mA

3.94

3.70

V_OL

LOW-level

output voltage

V_I= V_IHor V_IL; V_CC= 4.5 V

I_O= 50 µA

-

0

-

0.1

0.36

±0.25

-

0.1

-

0.1

0.55

±10.0

V

I_O= 8.0 mA

0.44

±2.5

V

I_OZ

OFF-state

per input pin; V_I= V_IHor V_IL;

-

µA

output current V_CC= 5.5 V; I_O= 0 A;

V_O= V_CCor GND;

other pins at V_CCor GND

I_I

input leakage V_I= 5.5 V or GND;

-

0.1

4.0

-

1.0

40

-

2.0

80

µA

mA

current

supply current V_I= V_CCor GND; I_O= 0 A;

_CC= 5.5 V

per input pin;

V_CC= 0 V to 5.5 V

I_CC

∆I_CC

V

additional

1.35

1.5

supply current V_I= V_CC− 2.1 V; I_O= 0 A;

other pins at V_CCor GND;

V

_CC= 4.5 V to 5.5 V

C_I

input

capacitance

-

3

10

-

10

-

10

-

pF

C_O

output

4.0

capacitance

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

7 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

10. Dynamic characteristics

Table 7.

Dynamic characteristics

GND = 0 V. For test circuit see Figure 10.

Symbol Parameter Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ^[1]Max Min

Max

Min

Max

For type 74AHC574

[2]

[1]

[2]

t_pd

propagation CP to Qn; see Figure 7

delay

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

C_L= 50 pF

-

6.5 13.2

9.3 16.7

1.0

15.5

19.0

1.0

16.5

21.0

ns

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.4

8.6

1.0

10.0

12.0

1.0

11.0

13.5

ns

C_L= 50 pF

6.2 10.6

t_en

enable time OE to Qn; see Figure 9

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

5.7 12.8

8.2 16.3

1.0

15.0

18.5

1.0

16.0

20.5

ns

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.2

9.0

1.0

10.5

12.5

1.0

11.5

14.0

ns

C_L= 50 pF

5.9 11.0

t_dis

f_max

t_W

disable time OE to Qn; see Figure 9

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

-

6.3 13.0

9.1 15.0

1.0

15.0

17.0

1.0

16.5

19.0

ns

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.3

9.0

1.0

10.5

11.5

1.0

11.5

13.0

ns

C_L= 50 pF

6.9 10.1

maximum

frequency

CP; see Figure 7

V_CC= 3.0 V to 3.6 V

C_L= 15 pF

80

50

125

75

-

65

45

-

65

45

-

MHz

C_L= 50 pF

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

130

85

180

115

-

110

75

-

110

75

-

MHz

C_L= 50 pF

pulse width CP; HIGH or LOW;

see Figure 7

V_CC= 3.0 V to 3.6 V;

C_L= 50 pF

5.0

-

5.0

-

5.0

-

ns

V_CC= 4.5 V to 5.5 V;

C_L= 50 pF

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

8 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

Table 7.

Dynamic characteristics …continued

GND = 0 V. For test circuit see Figure 10.

Symbol Parameter Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ^[1]Max Min

Max

Min

Max

t_su

set-up time Dn to CP; see Figure 8

V_CC= 3.0 V to 3.6 V;

C_L= 50 pF

3.5

3.0

-

3.5

3.0

-

3.5

3.0

-

ns

V_CC= 4.5 V to 5.5 V;

C_L= 50 pF

t_h

hold time

Dn to CP; see Figure 8

V_CC= 3.0 V to 3.6 V;

C_L= 50 pF

1.5

-

1.5

-

1.5

-

ns

pF

V_CC= 4.5 V to 5.5 V;

C_L= 50 pF

[3]

[2]

C_PD

power

dissipation

capacitance

C_L= 50 pF; f_i= 1 MHz;

V_I= GND to V_CC

10

For type 74AHCT574

t_pd

propagation CP to Qn; see Figure 7

delay

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

C_L= 50 pF

-

4.4

8.6

1.0

10.0

12.0

1.0

11.0

13.5

ns

6.3 10.6

t_en

enable time OE to Qn; see Figure 9

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.3

9.0

1.0

10.5

12.5

1.0

11.5

14.0

ns

C_L= 50 pF

6.1 11.0

[2]

t_dis

disable time OE to Qn; see Figure 9

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

-

4.3

9.0

1.0

10.5

11.5

1.0

11.5

13.0

ns

C_L= 50 pF

6.2 10.1

f_max

maximum

frequency

CP; see Figure 7

V_CC= 4.5 V to 5.5 V

C_L= 15 pF

130

85

180

115

-

110

75

-

110

75

-

MHz

C_L= 50 pF

t_W

pulse width CP; HIGH or LOW;

see Figure 7

V_CC= 4.5 V to 5.5 V;

C_L= 50 pF

5.0

3.0

-

5.5

3.5

-

5.5

3.5

-

ns

t_su

set-up time Dn to CP; see Figure 8

V_CC= 4.5 V to 5.5 V;

C_L= 50 pF

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

9 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

Table 7.

Dynamic characteristics …continued

GND = 0 V. For test circuit see Figure 10.

Symbol Parameter Conditions

25 °C

−40 °C to +85 °C −40 °C to +125 °C Unit

Min Typ^[1]Max Min

Max

Min

Max

t_h

hold time

Dn to CP; see Figure 8

V_CC= 4.5 V to 5.5 V;

C_L= 50 pF

1.5

-

1.5

-

1.5

-

ns

[3]

C_PD

power

per buffer;

12

pF

dissipation

C_L= 50 pF; f = 1 MHz;

capacitance V_I= GND to V_CC

[1] Typical values are measured at nominal supply voltage (V_CC= 3.3 V and V_CC= 5.0 V).

[2] t_pdis the same as t_PLHand t_PHL

t_enis the same as t_PZLand t_PZH

t_disis the same as t_PLZand t_PHZ

.

[3] C_PDis used to determine the dynamic power dissipation P_D(µW).

P_D= C_PD× V_CC²× f_i+ ∑ (C_L× V_CC²× f_o) where:

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

V_CC= supply voltage in V.

10.1 Waveforms

1/f

max

V

I

CP input

V

M

GND

t

W

t

PLH

PHL

V

OH

V

Qn output

M

mna802

V

OL

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 7. Propagation delay input (CP) to output (Qn), clock input (CP) pulse width and the maximum frequency

(CP)

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

10 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

V

I

V

CP input

M

GND

t

su

t

h

V

I

V

Dn input

M

GND

V

OH

V

Qn output

M

V

OL

mna803

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predicable output performance.

Fig 8. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times

V

I

OE input

V

M

GND

t

PZL

PLZ

V

CC

Qn output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PZH

PHZ

V

OH

V

Y

Qn output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aah078

Measurement points are given in Table 8.

V_OLand V_OHare typical voltage output levels that occur with the output load.

Fig 9. Enable and disable times

Table 8.

Type

Measurement points

Input

V_M

Output

V_M

V_X

V_Y

74AHC574

0.5V_CC

1.5 V

0.5V_CC

V_OL+ 0.3 V

V

_OH− 0.3 V

74AHCT574

V

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

11 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

f

r

V

I

90 %

positive

pulse

V

M

10 %

0 V

t

W

V

CC

V

CC

V

O

I

R

L

S1

PULSE

GENERATOR

open

DUT

R

T

C

L

001aad983

Test data is given in Table 9.

Deﬁnitions test circuit:

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

C_L= Load capacitance including jig and probe capacitance.

R_L= Load resistance.

S1 = Test selection switch.

Fig 10. Load circuitry for switching times

Table 9.

Type

Test data

Input

Load

S1 position

t_PHL, t_PLH

open

V_I

t_r, t_f

C_L

R_L

t_PZH, t_PHZ

GND

t_PZL, t_PLZ

V_CC

74AHC574

V_CC

3.0 V

3.0 ns

15 pF, 50 pF

1 kΩ

74AHCT574

open

GND

V_CC

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

12 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

11. Package outline

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A

X

c

y

H

E

v

M

A

Z

20

11

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

w

detail X

e

M

b

p

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

max.

(1)

UNIT

mm

A

b

c

D

E

e

H

L

Q

v

w

y

θ

1

2

3

p

E

p

Z

0.3

0.1

2.45

2.25

0.49

0.36

0.32

0.23

13.0

12.6

7.6

7.4

10.65

10.00

1.1

0.4

1.1

1.0

0.9

0.4

2.65

0.1

0.25

0.01

1.27

0.05

1.4

0.25 0.25

0.1

8^o

0^o

0.012 0.096

0.004 0.089

0.019 0.013 0.51

0.014 0.009 0.49

0.30

0.29

0.419

0.394

0.043 0.043

0.016 0.039

0.035

0.016

inches

0.055

0.01 0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT163-1

075E04

MS-013

Fig 11. Package outline SOT163-1 (SO20)

74AHC_AHCT574_2

©

Product data sheet

Rev. 02 — 24 January 2008

13 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm

SOT360-1

D

E

A

X

c

H

v

M

A

y

E

Z

11

20

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

1

10

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

6.6

6.4

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.5

0.2

mm

1.1

0.65

0.25

1

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT360-1

MO-153

Fig 12. Package outline SOT360-1 (TSSOP20)

74AHC_AHCT574_2

©

Product data sheet

Rev. 02 — 24 January 2008

14 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

20 terminals; body 2.5 x 4.5 x 0.85 mm

SOT764-1

B

A

D

A

1

E

c

detail X

terminal 1

index area

C

terminal 1

index area

e

1

y

e

b

v

M

C

A

B

C

1

w

M

2

9

L

1

10

E

h

e

20

11

19

12

D

h

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

(1)

UNIT

A

b

c

E

e

1

y

D

E

L

v

w

y

1

h

max.

0.05 0.30

0.00 0.18

4.6

4.4

3.15

2.85

2.6

2.4

1.15

0.85

0.5

0.3

mm

0.05

0.1

1

0.2

0.5

3.5

0.1

0.05

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

02-10-17

03-01-27

SOT764-1

- - -

MO-241

- - -

Fig 13. Package outline SOT764-1 (DHVQFN20)

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

15 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym

CDM

CMOS

DUT

Description

Charged-Device Model

Complementary Metal Oxide Semiconductor

Device Under Test

ESD

ElectroStatic Discharge

Human Body Model

HBM

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

74AHC_AHCT574_2 20080124

Product data sheet

-

74AHC_AHCT574_1

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Section 3: DHVQFN20 package added.

• Section 7: derating values added for DHVQFN20 package.

• Section 11: outline drawing added for DHVQFN20 package.

74AHC_AHCT574_1 19990616

Product speciﬁcation

-

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

16 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

14. Legal information

14.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nexperia.com.

malfunction of a Nexperia product can reasonably be expected

14.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. Nexperia accepts no liability for inclusion and/or use of

Nexperia products in such equipment or applications and

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. Nexperia does not give any

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. Nexperia makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local Nexperia sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — Nexperia products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nexperia.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by Nexperia. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

14.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable.However,Nexperiadoesnotgiveanyrepresentationsor

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — Nexperiareservestherighttomake

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

14.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — Nexperia products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

15. Contact information

For more information, please visit: http://www.nexperia.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nexperia.com

©

74AHC_AHCT574_2

Product data sheet

Rev. 02 — 24 January 2008

17 of 18

74AHC574; 74AHCT574

Nexperia

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

16. Contents

1

2

3

4

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

7

8

9

10

10.1

11

12

13

14

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

14.1

14.2

14.3

14.4

15

16

Contact information. . . . . . . . . . . . . . . . . . . . . 17

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 24 January 2008


型号：	74AHC574D
厂家：	Nexperia
描述：	Octal D-type flip-flop; positive-edge trigger; 3-stateProduction 驱动光电二极管逻辑集成电路
文件：	总18页 (文件大小：650K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

74AHC574D [NEXPERIA]

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