UPD8670CY [NEC]
CCD Sensor, 7400 Horiz pixels, 7400 Vert pixels, 1.50-2V, Rectangular, Through Hole Mount, CERAMIC, DIP-22;
| 型号： | UPD8670CY |
| 厂家： | 
NEC |
| 描述： | CCD Sensor, 7400 Horiz pixels, 7400 Vert pixels, 1.50-2V, Rectangular, Through Hole Mount, CERAMIC, DIP-22 传感器 图像传感器 CD |
| 文件： | 总28页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD8670A
7400 PIXELS CCD LINEAR IMAGE SENSOR
The µ PD8670A is a high sensitive and high-speed CCD (Charge Coupled Device) linear image sensor which changes
optical images to electrical signal.
The µ PD8670A is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the
photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits
and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.
FEATURES
• Valid photocell
: 7400 pixels
• Photocell pitch : 4.7 µ m
• Photocell size
• Resolution
• Data rate
: 4.7 × 4.7 µ m2
: 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side)
: 44 MHz MAX. (22 MHz/1 output)
• Output type
: 2 outputs in-phase operation, and out of phase also supported
• High sensitivity : 17.0 V/lx•s TYP. (Light source: Daylight color fluorescent lamp)
• Peak response wavelength : 550 nm (green)
• Low image lag : 1 % MAX.
• Drive clock level : CMOS output under +5 V operation
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
: +12 V
:
ORDERING INFORMATION
Part Number
Package
µ PD8670ACY
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17147EJ1V0DS00 (1st edition)
Date Published August 2004 NS CP (K)
Printed in Japan
2004
µPD8670A
DIFFERENCE BETWEEN µPD8670ACY AND µPD3747D
Part
Item
µ PD8670ACY
µ PD3747D
Referential
Page
Features
Output type
2 outputs out of phase or in phase
2 outputs in phase only
1
Sensitivity (Daylight
TYP. 17 V/lx•s
TYP. 19 V/lx•s
color fluorescent lamp)
Ordering information Package
32-pin plastic DIP
22-pin ceramic DIP (CERDIP)
Pin configuration
Block diagram
Input clock
φCP1, φCP2 separated,
φR1, φR2 separated,
φ2L1, φ2L2 separated
(Output: in/out of phase)
φCP common,
φR common,
4
3
φ2L common
Application circuit
21
(Output: in phase)
example
Equivalent circuit Tr.
2SA1206, 2SC1842
0 to +60°C
2SA1005, 2SC945
–25 to +55°C
Absolute maximum
ratings
Operating ambient
temperature
5
6
Storage temperature
Each clock amplitude
–40 to +70°C
–40 to +100°C
–
Recommended
Addition of specifications
(from 4.5 V to 5.8 V)
operating condition
Electrical
ADS, DSNU, DR1,
DR2
Change of specifications
–
characteristics
RF
TYP. 17 V/lx•s
TYP. 19 V/lx•s
RFTN
Addition of PRFTN, RFTN1,
RFTN2
Only RFTN
td
TYP. 13 ns
TYP. 14 ns
Addition of min. max.
σ bit, σ line, σ shot
Addition of condition (t6)
–
–
Input pin capacitance Capacitance
Change of specification
Addition of note
7
Timing chart
Operation
Addition of out-of-phase
timing chart
–
8, 9
t6
MIN. 5 ns
MIN. 0 ns
MIN. 0 ns
12, 14
t10
MIN. t3
t13, t16, t17
–
MAX. 10000 ns
–
14
15
19
24
Close point
Definitions
Change of specifications
Additional item
–
VOS, RFTN
Partial heating method
–
Recommended
350°C or blow, 3 seconds or less
300°C or blow, 3 seconds or less
soldering condition
Package drawing
Package
Cap
32-pin plastic DIP
Plastic cap 0.7t
2.45 0.3 mm
22-pin ceramic DIP (CERDIP)
Glass cap 0.7t
23
From CCD to bottom
of package
2.38 0.3 mm
From CCD to top of
cap
(2.0) mm
(1.95) mm
Remark TA = +25°C, VOD = 12 V
2
Data Sheet S17147EJ1V0DS
µPD8670A
BLOCK DIAGRAM
GND
31
φ
CP2
30
φ
R2
29
φ
2L2
28
φ
22
φ
12
23
24
V
OUT
2
32
CCD analog shift register
Transfer gate
(Even)
22
· · ·
· · ·
· · ·
· · ·
φ
TG
Transfer gate
CCD analog shift register
V
(Odd)
OUT
1
1
2
3
4
5
9
10
11
VOD
φ
CP1
φ
R1
φ
2L1
φ
11
φ
21
GND
3
Data Sheet S17147EJ1V0DS
µPD8670A
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
• µ PD8670ACY
Output signal 1 (Odd)
Output drain voltage
Reset feed-through level clamp clock 1
Reset gate clock 1
V
OUT
1
1
2
3
4
5
6
7
8
9
32
V
OUT
2
Output signal 2 (Even)
Ground
V
OD
31 GND
φ
CP1
R1
30
29
28
φ
φ
φ
CP2 Reset feed-through level clamp clock 2
φ
R2
Reset gate clock 2
Last stage shift register clock 2
Internal connection
Internal connection
No connection
Last stage shift register clock 1
Internal connection
Internal connection
No connection
φ
2L1
IC
2L2
27 IC
26 IC
25 NC
IC
NC
Shift register clock 1-1
Shift register clock 2-1
Ground
φ
11
24
23
22
φ
φ
φ
22
12
TG
Shift register clock 2-2
Shift register clock 1-2
Transfer gate clock
Internal connection
Internal connection
No connection
φ
21 10
GND 11
IC 12
Internal connection
Internal connection
No connection
21 IC
20 IC
19 NC
18 NC
17 NC
IC 13
NC
14
No connection
NC 15
NC 16
No connection
No connection
No connection
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
3.2
µ
µ
1.5 m
m
µ
Channel stopper
Aluminum
shield
4
Data Sheet S17147EJ1V0DS
µPD8670A
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter
Symbol
Ratings
−0.3 to +14.0
−0.3 to +8.0
−0.3 to +8.0
−0.3 to +8.0
−0.3 to +8.0
−0.3 to +8.0
0 to +60
Unit
V
Output drain voltage
VOD
Shift register clock voltage
Vφ 1, Vφ 2
Vφ 2L
Vφ R
V
Last stage shift register clock voltage
Reset gate clock voltage
V
V
Transfer gate clock voltage
Reset feed-through level clamp clock voltage
Operating ambient temperatureNote
Storage temperature
Vφ TG
Vφ CP
TA
V
V
°C
°C
Tstg
−40 to +70
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter
Output drain voltage
Symbol
Conditions
MIN.
11.4
4.5
TYP.
12.0
5.0
0
MAX.
12.6
5.5
Unit
V
VOD
Shift register clock high level
Vφ 1H, Vφ 2H
Vφ 1L, Vφ 2L
Vφ 2LH
V
Shift register clock low level
−0.3
4.5
+0.5
5.5
V
Last stage shift register clock high level
Last stage shift register clock low level
Reset gate clock high level
5.0
0
V
Vφ 2LL
−0.3
4.5
+0.5
5.5
V
Vφ RH
5.0
0
V
Reset gate clock low level
Vφ RL
−0.3
4.5
+0.5
5.5
V
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high level
Vφ CPH
Vφ CPL
5.0
0
V
−0.3
4.5
+0.5
5.5
V
Vφ TGH
Vφ TGL
5.0
0
V
Transfer gate clock low level
−0.3
4.0
+0.5
5.8
V
Shift register clock amplitude
Vφ 1_pp,
Vφ 2_pp
Vφ 2L_pp
Vφ R_pp
Vφ CP_pp
Vφ TG_pp
2fφ R
f < 10 MHz/ch
5.0
5.0
5.0
5.0
5.0
5.0
2
V
f ≥ 10 MHz/ch
4.5
5.8
V
Last stage shift register clock amplitude
Reset gate clock amplitude
4.5
5.8
V
4.5
5.8
V
Reset feed-through level clamp clock amplitude
Transfer gate clock amplitude
Data rate
4.5
5.8
V
4.5
5.8
V
1
44
MHz
5
Data Sheet S17147EJ1V0DS
µPD8670A
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, fφ R = 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Saturation voltage
Saturation exposure
Symbol
Vsat
Test Conditions
MIN.
1.5
−
TYP.
2.0
MAX.
−
Unit
V
SE
Daylight color fluorescent lamp
VOUT = 500 mV
0.10
5.0
−
lx•s
%
Photo response non-uniformity PRNU
−
10.0
6.0
28.0
420
0.3
20.4
1.0
5.7
15.0
−
Average dark signal
Dark signal non-uniformity
Power consumption
Output impedance
Response
ADS
DSNU
PW
Light shielding
−
1.0
mV
mV
mW
kΩ
V/lx•s
%
Light shielding
−
16.0
350
0.2
−
ZO
−
RF
Daylight color fluorescent lamp
VOUT = 500 mV
13.6
−
17.0
0.5
Image lag
Offset level Note 1
Output fall delay time Note 2
Total transfer efficiency
Register imbalance
Response peak
IL
VOS
td
3.7
11.0
94
0
4.7
V
VOUT = 500 mV
13.0
98
ns
TTE
RI
VOUT = 1 V, data rate = 44 MHz
VOUT = 500 mV
%
1.0
4.0
−
%
−
550
125
1000
+0.4
−0.4
+0.2
2.6
nm
times
times
V
Dynamic range
DR1
DR2
Vsat/DSNU
−
−
Vsat/σ bit, t6 ≥ 20 ns
−
−
Reset feed-through noise Note 1 PRFTN Light shielding, t4 = 5 ns
−
−
RFTN1
RFTN2
−1.0
−0.3
−
+0.2
+0.7
−
V
V
Random noise
Shot noise
σ bit
Light shielding,
bit clamp mode
Light shielding,
line clamp mode
t6 = 5 ns
t6 ≥ 20 ns
t6 ≥ 5 ns
mV
mV
mV
−
2.0
−
σ line
σ shot
−
8.0
−
VOUT = 500 mV,
bit clamp mode
t6 ≥ 5 ns
−
10.0
−
mV
Notes 1. Refer to 13 and 14 of DEFINITION OF CHARACTERISTIC ITEMS.
2. When the fall time of φ 2L (t2’) is the TYP. value (refer to TIMING CHART 5, 6). Note that VOUT1 and VOUT2 are
the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.
6
Data Sheet S17147EJ1V0DS
µPD8670A
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter
Symbol
Pin name
φ 11
Pin No.
9
MIN.
225
200
200
225
4
TYP.
250
220
220
250
5
MAX.
275
240
240
275
6
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Note
Shift register clock pin capacitance 1
Cφ 1
φ 12
23
10
24
5
Note
Shift register clock pin capacitance 2
Cφ 2
Cφ L
φ 21
φ 22
Last stage shift register clock pin capacitance
Reset gate clock pin capacitance
φ 2L1
φ 2L2
φ R1
28
4
4
5
6
Cφ R
4
5
6
φ R2
29
3
4
5
6
Reset feed-through level clamp clock pin capacitance
Cφ CP
φ CP1
φ CP2
φ TG
7
8
9
30
22
7
8
9
Transfer gate clock pin capacitance
Cφ TG
240
270
300
Note Cφ 1, Cφ 2 are equivalent capacitance with driving device, including the co-capacitance between φ1 and φ2.
Remark Pins 9 and 23 (φ11 and φ12), Pins 10 and 24 (φ21 and φ22) aren't each connected inside of the device.
7
Data Sheet S17147EJ1V0DS
TIMING CHART 1 (Bit clamp mode, Out of phase operation)
φ
TG
φ
11
21
φ
φ
2L1
R1
CP1
φ
φ
VOUT
1
φ
φ
12
22
φ
2L2
R2
CP2
φ
φ
VOUT
2
µ
Dummy cell
(32 pixels)
Optical black
(96 pixels)
Valid photocells
(7400 pixels)
Note
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
Note Set the
φ φ φ φ CP2 to low level during this period.
R1, R2, CP1 and
TIMING CHART 2 (Line clamp mode, Out of phase operation)
φ
TG
φ
11
21
φ
φ
2L1
R1
CP1
φ
φ
VOUT
1
φ
φ
12
22
φ
2L2
R2
CP2
φ
φ
VOUT
2
µ
Dummy cell
(32 pixels)
Optical black
(96 pixels)
Valid photocells
(7400 pixels)
Note
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
Note Set the
φ φ φ φ CP2 to low level during this period.
R1, R2, CP1 and
TIMING CHART 3 (Bit clamp mode, In phase operation)
φ
TG
φ
φ
11,
φ
12
22
21,
φ
φ
2L1, φ 2L2
φ
R1, φR2
φ
CP1, φ CP2
VOUT
1
VOUT2
Dummy cell
(32 pixels)
Optical black
(96 pixels)
Valid photocells
(7400 pixels)
Note
µ
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
Note Set the
φ φ φ φ CP2 to low level during this period.
R1, R2, CP1 and
TIMING CHART 4 (Line clamp mode, In phase operation)
φ
TG
φ
φ
11,
φ
12
22
21,
φ
φ
2L1, φ 2L2
φ
R1, φR2
φ
CP1, φ CP2
VOUT
1
VOUT2
Dummy cell
(32 pixels)
Optical black
(96 pixels)
Valid photocells
(7400 pixels)
Note
µ
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
Note Set the
φ φ φ φ CP2 to low level during this period.
R1, R2, CP1 and
µPD8670A
TIMING CHART 5 (Bit clamp mode)
t1
t2
90%
φ
φ
11
21
10%
90%
10%
t1'
t4
t2'
90%
10%
φ
2L1
t5
t8
t3
t6
t7
90%
10%
φ
R1
t9
t10
t11
90%
φ
CP1
10%
td
V
OUT
1
V
OS
10%
Symbol
t1, t2
MIN.
0
TYP.
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
−
−
−
−
−
−
−
−
−
t1’, t2’
t3
0
5
10
0
125
5
t4, t5
t6
5
125
125
5
t7
5
t8, t9
t10
0
0
125
250
t11
0
Caution This shows timing chart of VOUT1 side (φ11, φ21, φ2L1, φR1, φCP1, VOUT1). The timing chart of VOUT2
side (φ12, φ22, φ2L2, φR2, φCP2, VOUT2) is equal.
12
Data Sheet S17147EJ1V0DS
µPD8670A
TIMING CHART 6 (Line clamp mode)
t1
t2
90%
φ
φ
11
21
10%
90%
10%
t1'
t4
t2'
90%
10%
φ
2L1
t5
t3
t12
90%
10%
φ
R1
φ
CP1
"L"
td
V
OUT
1
V
OS
10%
Symbol
MIN.
0
TYP.
50
MAX.
Unit
ns
t1, t2
t1’, t2’
t3
−
−
−
−
−
0
5
ns
10
0
125
5
ns
t4, t5
t12
ns
5
250
ns
Caution This shows timing chart of VOUT1 side (φ11, φ21, φ2L1, φR1, φCP1, VOUT1). The timing chart of VOUT2
side (φ12, φ22, φ2L2, φR2, φCP2, VOUT2) is equal.
13
Data Sheet S17147EJ1V0DS
µPD8670A
TIMING CHART 7 (Bit clamp mode, Line clamp mode)
t14
t15
t13
90%
10%
φ
φ
TG
t16
90%
90%
11
φ
21,
φ
2L1
t4
t5
t17
90%
10%
t3
t6
φ
R1
t8
t9
t10
t7
t11
90%
10%
φ
CP1
Note
Note Set the φ R and φ CP to low level during this period.
Symbol
MIN.
10
0
TYP.
125
5
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t3
−
t4, t5
t6
−
5
125
125
5
−
t7
5
−
t8, t9
t10
0
−
0
125
250
1500
50
−
−
t11
0
t13
1000
0
10000
−
t14, t15
t16, t17
200
300
10000
Caution This shows timing chart of VOUT1 side (φ11, φ21, φ2L1, φR1, φCP1, VOUT1). The timing chart of VOUT2
side (φ12, φ22, φ2L2, φR2, φCP2, VOUT2) is equal.
14
Data Sheet S17147EJ1V0DS
µPD8670A
φ 11, φ 21 cross points
φ 11, φ 2L1 cross points
φ
φ
11
11
1.5 V or more
1.5 V or more
1.5 V or more
0 V or more
φ
φ
21
2L1
φ 12, φ 22 cross points
φ 12, φ 2L2 cross points
φ
φ
12
12
1.5 V or more
1.5 V or more
1.5 V or more
0 V or more
φ
φ
22
2L2
Remark Adjust cross points of (φ 11, φ 21), (φ 11, φ 2L1), (φ 12, φ 22) and (φ 12, φ 2L2) with input resistance of each pin.
φ 11, φ 12, φ 21, φ 22, φ 2L1, φ 2L2 clock width
0 ns or more
4.5 V
φ
φ
11,
21,
φ
φ
12,
22,
φ
2L1,
φ 2L2
0.5 V
0 ns or more
15
Data Sheet S17147EJ1V0DS
µPD8670A
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of
uniform illumination. This is calculated by the following formula.
∆x
x
PRNU (%) =
× 100
∆x: maximum of x
7400
j
− x
x
j
Σ
j = 1
x =
7400
: Output voltage of valid pixel number j
xj
V
OUT
x
Register dark
DC level
∆x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
7400
d
j
Σ
j = 1
7400
ADS (mV) =
dj: Dark signal of valid pixel number j
16
Data Sheet S17147EJ1V0DS
µPD8670A
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
DSNU (mV): maximum of d
j
− ADS j = 1 to 7400
d
j: Dark signal of valid pixel number j
V
OUT
ADS
Register dark
DC level
DSNU
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
φ
TG
Light
ON
OFF
V
OUT
V
1
VOUT
V
1
IL (%) =
× 100
OUT
V
9. Total transfer efficiency : TTE
The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by each
output.
TTE (%) = (1 − Vb / average output of all the valid pixels) × 100
Vb
V
V
V
a−1 : The last pixel output − 1 (Odd pixel: 7537th pixel)
a
b
: The last pixel output (Odd pixel: 7539th pixel)
: The spilt pixel output (Odd pixel: 7541st pixel)
V
a−1
Va
17
Data Sheet S17147EJ1V0DS
µPD8670A
10. Register imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
n
2
2
n
∑
(V2j – 1 – V2j)
j = 1
RI (%) =
× 100
n
1
n
∑
V
j
j = 1
n
: Number of valid pixels
Vj
: Output voltage of each pixel
11. Random noise : σ
Random noise σ is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines)
data sampling at dark (light shielding).
100
(V
i
– V)2
Σ
100
1
i = 1
, V =
V
i
σ
(mV) =
100 Σ
100
i = 1
Vi : A valid pixel output signal among all of the valid pixels
VOUT
V
1
2
line 1
line 2
V
V100
line 100
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
12. Shot noise : σ shot
Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data
sampling in the light. This includes the random noise.
The formula is the same with that of random noise.
18
Data Sheet S17147EJ1V0DS
µPD8670A
13. Offset level : VOS
DC level of output signal is defined as follows.
14. Reset feed-through noise and peak reset feed-through noise : RFTN and PRFTN
RTFN is switching noise of φR and φCP. Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are
defined as follows.
<1> Bit clamp operation
2L1
φ
R1
φ
CP1
RFTN2
PRFTN
V
OUT
1
RFTN1
V
OS
Caution This shows timing of VOUT1 side (φ2L1, φR1, φCP1, VOUT1). The definition of VOUT2 side (φ2L2,
φR2, φCP2, VOUT2) is equal.
<2> Line clamp operation
φ
2L1
φ
R1
φ
CP1
"L"
PRFTN
VOUT
1
RFTN1
V
OS
Caution This shows timing of VOUT1 side (φ2L1, φR1, φCP1, VOUT1). The definition of VOUT2 side (φ2L2,
φR2, φCP2, VOUT2) is equal.
19
Data Sheet S17147EJ1V0DS
µPD8670A
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25°C)
2
1
8
4
2
1
0.5
0.2
0.1
0.25
0.1
1
5
10
0
10
20
30
40
50
Storage Time (ms)
Operating Ambient Temperature TA (°C)
TOTAL SPECTRAL RESPONSE CHARACTERISTIC
(without infrared cut filter and heat absorbing filter) (T
A
= +25°C)
100
80
60
40
20
0
400
600
800
1000
1200
Wavelength (nm)
20
Data Sheet S17147EJ1V0DS
µPD8670A
APPLICATION CIRCUIT EXAMPLE
+12 V
µ
PD8670A
+5 V
0.1 µF 47 µF/25 V +5 V
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
B1
V
V
φ
OUT
1
V
OUT
2
B2
OD
GND
CP2
10
µ
F/16 V 0.1
CP1
µ
F
0.1 µF 10 µF/16 V
47 Ω
47 Ω
3
φ
CP1
R1
φ
φ
φ
φ
CP2
R2
47 Ω
47 Ω
47 Ω
47 Ω
4
φ
R1
φ
φ
R2
5
φ
2L1
φ
2L1
φ
2L2
IC
2L2
6
IC
7
IC
IC
8
NC
NC
2 Ω
2 Ω
2 Ω
2 Ω
9
φ
φ
11
21
φ
φ
11
21
φ
φ
22
12
φ
φ
22
12
10
11
12
13
14
15
16
GND
IC
φ
TG
IC
10 Ω
φ
TG
IC
IC
NC
NC
NC
NC
NC
NC
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Remark The inverters shown in the above application circuit example are the 74AC04.
21
Data Sheet S17147EJ1V0DS
µPD8670A
+12 V
B1, B2 EQUIVALENT CIRCUIT
+
µ
47 F/25 V
4.7 kΩ
110 Ω
2SC1842
47 Ω
CCD
2SA1206
VOUT
Output
1 kΩ
22
Data Sheet S17147EJ1V0DS
µPD8670A
PACKAGE DRAWING
µ
PD8670CY, µPD8670ACY
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) )
(Unit : mm)
55.2 0.5
54.8 0.5
1st valid pixel
1
3.2 0.3
32
17
16
1
4
46.7
4
2.0
12.6 0.5
4.1 0.5
10.16 0.20
4.55 0.5
1.02 0.15
2
(2.0)
3
2.45 0.3
0.25 0.05
(5.42)
4.21 0.5
0.46 0.1
2.54 0.25
+0.70
10.16
−0.20
Name
Dimensions
Refractive index
5
)
Plastic cap
52.2×6.4×0.8 (0.7
1.5
1 1st valid pixel
The center of the pin1
2 The surface of the CCD chip
3 The bottom of the package
4 Mirror finishied surface
The top of the cap
The surface of the CCD chip
5 Thickness of mirror finished surface
32C-1CCD-PKG10-2
23
Data Sheet S17147EJ1V0DS
µPD8670A
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to
consult with our sales offices.
Type of Through-hole Device
µ PD8670ACY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 350°C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic cap.
The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap
soiling and heat resistance. So the method cannot be guaranteed.
24
Data Sheet S17147EJ1V0DS
µPD8670A
NOTES ON HANDLING THE PACKAGES
1
DUST AND DIRT PROTECTING
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Ethyl Alcohol
Symbol
EtOH
MeOH
IPA
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
NMP
2
MOUNTING OF THE PACKAGE
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
3
4
OPERATE AND STORAGE ENVIRONMENTS
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
25
Data Sheet S17147EJ1V0DS
µPD8670A
[ NOTE ]
26
Data Sheet S17147EJ1V0DS
µPD8670A
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
27
Data Sheet S17147EJ1V0DS
µPD8670A
•
The information in this document is current as of August, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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