UPD78F0034BYGKA-9ET [NEC]
8-BIT SINGLE-CHIP MICROCONTROLLERS; 8位单芯片微控制器型号: | UPD78F0034BYGKA-9ET |
厂家: | NEC |
描述: | 8-BIT SINGLE-CHIP MICROCONTROLLERS |
文件: | 总90页 (文件大小:652K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD78F0034B is a member of the µPD780034A Subseries in the 78K/0 Series, and is equivalent to the
µPD780034A (expanded-specification product) but with flash memory in place of internal ROM.
The µPD78F0034BY is a member of the µPD780034AY Subseries, featuring flash memory in place of the internal
ROM of the µPD780034AY.
The µPD78F0034B(A) and 78F0034BY(A) are products to which a quality assurance program more stringent than
that used for the µPD78F0034B and 78F0034BY (standard models) is applied (NEC Electronics classifies these
products as "special" quality grade models).
The µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) incorporate flash memory, which can be
programmed and erased while mounted on the board.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual: U14046E
78K/0 Series Instruction User’s Manual: U12326E
FEATURES
•
•
•
•
Pin-compatible with mask ROM versions (except VPP pin)
Flash memory:
32 KBNote
Internal high-speed RAM: 1,024 bytesNote
Supply voltage: VDD = 1.8 to 5.5 V
Note The flash memory and internal high-speed RAM capacities can be changed with the memory size switching
register (IMS).
Remark For the differences between the flash memory and the mask ROM versions, refer to 4. DIFFERENCES
BETWEEN µPD78F0034B, 78F0034BY, AND MASK ROM VERSIONS.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U16369EJ1V0DS00 (1st edition)
Date Published January 2003 N CP(K)
Printed in Japan
©
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
ORDERING INFORMATION
Part Number
Package
Internal ROM
µPD78F0034BGB-8EU
µPD78F0034BGC-8BS
µPD78F0034BGK-9ET
µPD78F0034BF1-CN3
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
73-pin plastic FBGA (9 x 9)
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
73-pin plastic FBGA (9 x 9)
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
Flash memory
µPD78F0034BGB(A)-8EU
µPD78F0034BGC(A)-8BS
µPD78F0034BGK(A)-9ET
µPD78F0034BYGB-8EU
µPD78F0034BYGC-8BS
µPD78F0034BYGK-9ET
µPD78F0034BYF1-CN3
µPD78F0034BYGB(A)-8EU
µPD78F0034BYGC(A)-8BS
µPD78F0034BYGK(A)-9ET
QUALITY GRADE
Part Number
Package
Quality Grade
µPD78F0034BGB-8EU
µPD78F0034BGC-8BS
µPD78F0034BGK-9ET
µPD78F0034BF1-CN3
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
73-pin plastic FBGA (9 x 9)
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
73-pin plastic FBGA (9 x 9)
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
64-pin plastic TQFP (12 x 12)
Standard
Standard
Standard
Standard
Special
µPD78F0034BGB(A)-8EU
µPD78F0034BGC(A)-8BS
µPD78F0034BGK(A)-9ET
µPD78F0034BYGB-8EU
µPD78F0034BYGC-8BS
µPD78F0034BYGK-9ET
µPD78F0034BYF1-CN3
µPD78F0034BYGB(A)-8EU
µPD78F0034BYGC(A)-8BS
µPD78F0034BYGK(A)-9ET
Special
Special
Standard
Standard
Standard
Standard
Special
Special
Special
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
CORRESPONDENCE BETWEEN MASK ROM PRODUCTS AND FLASH MEMORY PRODUCTS
• µPD780024A, 780034A Subseries
Mask ROM Products
Flash Memory Products
Expanded-specification products of µPD780021A, 780022A, 780023A, 780024A
Expanded-specification products of µPD780031A, 780032A, 780033A, 780034A
µPD78F0034B
Conventional products of µPD780021A, 780022A, 780023A, 780024A
Conventional products of µPD780031A, 780032A, 780033A, 780034A
µPD78F0034A
Expanded-specification products of µPD780021A(A), 780022A(A), 780023A(A), 780024A(A)
Expanded-specification products of µPD780031A(A), 780032A(A), 780033A(A), 780034A(A)
µPD78F0034B(A)
µPD78F0034B(A)
Conventional products of µPD780021A(A), 780022A(A), 780023A(A), 780024A(A)
Conventional products of µPD780031A(A), 780032A(A), 780033A(A), 780034A(A)
Caution The µPD78F0034B(A)andconventionalproductsoftheµPD780021A(A), 780022A(A), 780023A(A),
780024A(A) and µPD780031A(A), 780032A(A), 780033A(A), and 780034A(A) differ in the operating
frequency ratings. When using the mask ROM versions in place of the flash memory versions,
take note of the power supply voltage and operating frequency used.
Remarks 1. The µPD78F0034B, 78F0034B(A) and 78F0034A differ in the operating frequency ratings and
communication mode of the flash memory programming. Refer to 5. DIFFERENCES BETWEEN
µPD78F0034B, 78F0034BY AND µPD78F0034A, 78F0034AY.
2. The expanded-specification products and conventional products of the mask ROM versions differ
in the operating frequency ratings. Refer to the data sheets of the products.
3. The special grade version of the µPD78F0034A is not provided (only the standard grade version
is provided).
• µPD780024AY, 780034AY Subseries
Mask ROM Products
µPD780021AY, 780022AY, 780023AY, 780024AY
Flash Memory Products
µPD78F0034AY
µPD78F0034BY
µPD780031AY, 780032AY, 780033AY, 780034AY
µPD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A)
µPD780031AY(A), 780032AY(A), 780033AY(A), 780034AY(A)
µPD78F0034BY(A)
Remarks 1. The µPD78F0034BY, 78F0034BY(A) and 78F0034AY differ in the communication mode of the flash
memory programming. Refer to 5. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND
µPD78F0034A, 78F0034AY.
2. The expanded-specification products of the µPD780024AY, 780034AY Subseries are not provided
(only the conventional products are provided).
3. The special grade version of the µPD78F0034A is not provided (only the standard grade version
is provided).
Data Sheet U16369EJ1V0DS
3
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
µ
EMI-noise reduced version of the PD78078
PD78054 with timer and enhanced external interface
ROMless version of the PD78078
PD78078Y with enhanced serial I/O and limited function
PD78054 with enhanced serial I/O
PD78054
PD78018F with UART and D/A converter, and enhanced I/O
PD780024A with expanded RAM
PD78075B
µ
µ
µ
100-pin
100-pin
100-pin
100-pin
80-pin
µ
PD78078
µ
µ
PD78078Y
PD78070A
PD78070AY
µ
µ
µ
PD780018AY
µ
PD780058
µ
µ
PD78058F
PD78054
µ
PD780058Y
PD78058FY
PD78054Y
µ
EMI-noise reduced version of the
µ
µ
µ
80-pin
80-pin
µ
µ
µ
µ
µ
PD780065
µ
µ
80-pin
PD780034A with timer and enhanced serial I/O
PD780024A with enhanced A/D converter
PD78018F with enhanced serial I/O
PD780078Y
PD780034AY
PD780024AY
µ
µ
64-pin
64-pin
64-pin
52-pin
52-pin
64-pin
PD780078
PD780034A
µ
µ
µ
µ
PD780024A
PD780034AS
PD780024AS
µ
µ
52-pin version of the PD780034A
52-pin version of the PD780024A
µ
EMI-noise reduced version of the PD78018F
µ
PD78014H
PD78018F
PD78083
µ
µ
µ
PD78018FY
Basic subseries for control
µ
64-pin
On-chip UART, capable of operating at low voltage (1.8 V)
42/44-pin
Inverter control
PD780988
64-pin
On-chip inverter control circuit and UART. EMI-noise reduced.
µ
VFD drive
µ
PD78044F with enhanced I/O and VFD C/D. Display output total: 53
For panel control. On-chip VFD C/D. Display output total: 53
PD78044F with N-ch open-drain I/O. Display output total: 34
Basic subseries for driving VFD. Display output total: 34
100-pin
80-pin
80-pin
80-pin
PD780208
PD780232
PD78044H
PD78044F
µ
µ
µ
µ
µ
LCD drive
78K/0
Series
µ
PD780344 with enhanced A/D converter
µ
PD780354Y
PD780344Y
100-pin
100-pin
120-pin
120-pin
120-pin
100-pin
100-pin
100-pin
PD780354
PD780344
µ
µ
µ
µ
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ
PD780338
PD780328
PD780318
µ
µ
µ
µ
µ
PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
PD780308Y
PD78064Y
µ
µ
PD78064 with enhanced SIO, and expanded ROM and RAM
PD780308
µ
µ
µ
µ
EMI-noise reduced version of the PD78064
PD78064B
PD78064
Basic subseries for driving LCDs, on-chip UART
µ
Bus interface supported
100-pin
80-pin
µ
µ
PD780948
PD78098B
On-chip CAN controller
µ
PD78054 with IEBusTM controller
80-pin
80-pin
80-pin
64-pin
PD780702Y
PD780703Y
PD780833Y
µ
µ
µ
On-chip IEBus controller
On-chip CAN controller
On-chip controller compliant with J1850 (Class 2)
Specialized for CAN controller function
PD780816
µ
Meter control
PD780958
100-pin
80-pin
µ
For industrial meter control
On-chip automobile meter controller/driver
For automobile meter driver. On-chip CAN controller
PD780852
µ
80-pin
PD780828B
µ
Remark VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are same.
4
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
The major functional differences among the subseries are listed below.
• Non-Y subseries
VDD
MIN.
Value
Function
ROM
Timer
8-Bit 10-Bit 8-Bit
Serial Interface
I/O
External
Expansion
√
Capacity
Subseries Name
(Bytes) 8-Bit 16-Bit Watch WDT A/D A/D D/A
Control µPD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch
µPD78078 48 K to 60 K
–
2 ch 3 ch (UART: 1 ch)
88 1.8 V
µPD78070A
–
61 2.7 V
µPD780058 24 K to 60 K 2 ch
µPD78058F 48 K to 60 K
µPD78054 16 K to 60 K
µPD780065 40 K to 48 K
µPD780078 48 K to 60 K
µPD780034A 8 K to 32 K
µPD780024A
3 ch (time-division UART: 1 ch) 68 1.8 V
3 ch (UART: 1 ch)
69 2.7 V
2.0 V
–
4 ch (UART: 1 ch)
3 ch (UART: 2 ch)
3 ch (UART: 1 ch)
60 2.7 V
52 1.8 V
51
2 ch
1 ch
–
8 ch
8 ch
–
–
4 ch
–
µPD780034AS
39
53
–
µPD780024AS
4 ch
8 ch
µPD78014H
2 ch
√
µPD78018F 8 K to 60 K
µPD78083 8 K to 16 K
–
–
–
1 ch (UART: 1 ch)
3 ch (UART: 2 ch)
33
–
Inverter µPD780988 16 K to 60 K 3 ch Note
1 ch
–
8 ch
–
–
47 4.0 V
√
control
VFD
drive
µPD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
–
2 ch
74 2.7 V
40 4.5 V
68 2.7 V
–
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
8 ch
µPD78044H 32 K to 48 K 2 ch 1 ch 1 ch
µPD78044F 16 K to 40 K
1 ch
2 ch
LCD
drive
µPD780354 24 K to 32 K 4 ch 1 ch 1 ch 1 ch
µPD780344
–
8 ch
–
8 ch
–
3 ch (UART: 1 ch)
66 1.8 V
–
–
µPD780338 48 K to 60 K 3 ch 2 ch
µPD780328
10 ch 1 ch 2 ch (UART: 1 ch)
54
62
70
µPD780318
µPD780308 48 K to 60 K 2 ch 1 ch
µPD78064B 32 K
8 ch
–
–
–
3 ch (time-division UART: 1 ch) 57 2.0 V
2 ch (UART: 1 ch)
µPD78064 16 K to 32 K
Bus
µPD780948 60 K
2 ch 2 ch 1 ch 1 ch 8 ch
1 ch
–
3 ch (UART: 1 ch)
79 4.0 V
69 2.7 V
√
interface µPD78098B 40 K to 60 K
2 ch
–
supported
µPD780816 32 K to 60 K
2 ch
12 ch
–
–
2 ch (UART: 1 ch)
2 ch (UART: 1 ch)
46 4.0 V
69 2.2 V
Meter
µPD780958 48 K to 60 K 4 ch 2 ch
–
1 ch
–
–
–
–
–
control
Dash-
board
control
µPD780852 32 K to 40 K 3 ch 1 ch 1 ch 1 ch 5 ch
µPD780828B 32 K to 60 K
–
3 ch (UART: 1 ch)
56 4.0 V
59
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
Data Sheet U16369EJ1V0DS
5
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
• Y subseries
ROM
Capacity
(Bytes)
VDD
MIN.
Value
Function
Subseries Name
Timer
8-Bit 10-Bit 8-Bit
Serial Interface
I/O
External
Expansion
√
8-Bit 16-Bit Watch WDT A/D A/D D/A
Control µPD78078Y 48 K to 60 K 4 ch 1 ch 1 ch 1 ch 8 ch
µPD78070AY
–
2 ch 3 ch (UART: 1 ch, I2C: 1 ch) 88 1.8 V
–
61 2.7 V
µPD780018AY 48 K to 60 K
µPD780058Y 24 K to 60 K 2 ch
µPD78058FY 48 K to 60 K
µPD78054Y 16 K to 60 K
µPD780078Y 48 K to 60 K
µPD780034AY 8 K to 32 K
µPD780024AY
–
3 ch (I2C: 1 ch)
88
2 ch 3 ch (time-division UART: 1 ch, I2C: 1 ch
3 ch (UART: 1 ch, I2C: 1 ch)
)
68 1.8 V
69 2.7 V
2.0 V
2 ch
1 ch
–
8 ch
–
–
–
4 ch (UART: 2 ch, I2C: 1 ch)
52 1.8 V
3 ch (UART: 1 ch, I2C: 1 ch) 51
8 ch
–
µPD78018FY 8 K to 60 K
2 ch (I2C: 1 ch)
53
–
–
LCD
drive
µPD780354Y 24 K to 32 K 4 ch 1 ch 1 ch 1 ch
µPD780344Y
–
8 ch
4 ch (UART: 1 ch,
I2C: 1 ch)
66 1.8 V
8 ch
–
µPD780308Y 48 K to 60 K 2 ch
µPD78064Y 16 K to 32 K
3 ch (time-division UART: 1 ch, I2C: 1 ch) 57 2.0 V
2 ch (UART: 1 ch, I2C: 1 ch)
Bus
µPD780701Y 60 K
µPD780703Y
3 ch 2 ch 1 ch 1 ch 16 ch
–
4 ch (UART: 1 ch, I2C: 1 ch)
67 3.5 V
interface
supported
µPD780833Y
65 4.5 V
Remark Functions other than the serial interface are common to both the Y and non-Y subseries.
6
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
OVERVIEW OF FUNCTIONS
Part Number
µPD78F0034B
µPD78F0034BY
Item
µPD78F0034B(A)
µPD78F0034BY(A)
Note 1
Internal
memory
Flash memory
32 KB
Note 1
High-speed RAM
1,024 bytes
64 KB
Memory space
General-purpose registers
Minimum instruction execution time
When main system
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip minimum instruction execution time cycle variable function
0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs 0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs
(@ 12 MHz operation, VDD = 4.5 to 5.5 V)
(@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
When subsystem
clock selected
122 µs (@ 32.768 kHz operation)
Instruction set
I/O ports
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
Total:
51
• CMOS input:
• CMOS I/O:
8
39
• N-ch open-drain I/O (5 V withstand voltage): 4
A/D converter
Serial interface
• 10-bit resolution × 8 channels
• Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V
• UART mode:
1 channel
• UART mode:
1 channel
• 3-wire serial I/O mode: 2 channels
• 3-wire serial I/O mode: 1 channel
• I C bus mode
2
(multimaster supporting): 1 channel
Timers
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• Watch timer:
• Watchdog timer:
1 channel
1 channel
Timer outputs
Clock output
3 (8-bit PWM output capable: 2)
• 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz,
1.25 MHz, 3 MHz, 6 MHz, 12 MHz
(@ 12 MHz operation with main system
clock)
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05
MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system
clock)
• 32.768 kHz (@ 32.768 kHz operation with • 32.768 kHz (@ 32.768 kHz operation with
subsystem clock)
subsystem clock)
Buzzer output
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz
(@ 12 MHz operation with main system clock) (@ 8.38 MHz operation with main system clock)
Vectored interrupt
sources
Maskable
Internal: 13, external: 5
Internal: 1
Non-maskable
Software
1
Test inputs
Internal: 1, external: 1
VDD = 1.8 to 5.5 V
TA = –40 to +85°C
Supply voltage
Operating ambient temperature
Package
• 64-pin plastic LQFP (10 x 10)
• 64-pin plastic LQFP (14 x 14)
• 64-pin plastic TQFP (12 x 12)
Note 2
• 73-pin plastic FBGA (9 x 9)
Notes 1. The capacities of the flash memory and the internal high-speed RAM can be changed with the memory
size switching register (IMS).
2. The special grade version of the 73-pin plastic FBGA (9 x 9) is not provided.
Data Sheet U16369EJ1V0DS
7
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ..............................................................................................
9
2. BLOCK DIAGRAM .......................................................................................................................... 12
3. PIN FUNCTIONS ............................................................................................................................. 13
3.1 Port Pins ................................................................................................................................................. 13
3.2 Non-Port Pins......................................................................................................................................... 14
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.................................................. 16
4. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY, AND MASK ROM VERSIONS ......... 19
5. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND µPD78F0034A, 78F0034AY ..... 21
6. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND µPD78F0034B(A), 78F0034BY(A) ..... 22
7. MEMORY SIZE SWITCHING REGISTER (IMS)............................................................................ 23
8. FLASH MEMORY PROGRAMMING .............................................................................................. 24
8.1 Selection of Communication Mode..................................................................................................... 24
8.2 Flash Memory Programming Functions............................................................................................. 26
8.3 Connection of Flashpro III/Flashpro IV .............................................................................................. 26
9. ELECTRICAL SPECIFICATIONS................................................................................................... 28
9.1 µPD78F0034B, 78F0034B(A) ................................................................................................................ 28
9.2 µPD78F0034BY, 78F0034BY(A) ............................................................................................................ 46
9.3 Timing Chart........................................................................................................................................... 64
10. PACKAGE DRAWINGS .................................................................................................................. 71
11. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 75
APPENDIX A. DEVELOPMENT TOOLS............................................................................................. 77
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 85
8
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
1. PIN CONFIGURATION (TOP VIEW)
•
•
64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (14 x 14)
• 64-pin plastic TQFP (12 x 12)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
P50/A8
P51/A9
1
P71/TI01
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P70/TI00/TO0
P03/INTP3/ADTRG
P02/INTP2
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
3
4
5
P01/INTP1
6
P00/INTP0
7
VSS1
8
X1
X2
VSS0
9
VDD0
10
11
12
13
14
15
16
VPP
P30
P31
XT1
XT2
P32/SDA0Note 1
P33/SCL0Note 1
P34/SI31Note 2
P35/SO31Note 2
RESET
AVDD
AVREF
P10/ANI0
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034BY, 78F0034BY(A) Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B, 78F0034B(A) Subseries.
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remark When the µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) are used in application fields
that require reduction of the noise generated from inside the microcontroller, the implementation of noise
reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting VSS0 and
VSS1 to different ground lines, is recommended.
Data Sheet U16369EJ1V0DS
9
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
• 73-pin plastic FBGA (9 x 9)
Top View
Bottom View
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
J H G F E D C B A
Index mark
Pin Name
Pin No
A1
A2
A3
A4
A5
A6
A7
A8
A9
B1
B2
B3
B4
B5
B6
B7
B8
B9
.
Pin Name
NC
Pin No
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
.
Pin No
E1
.
Pin Name
P57/A15
Pin No
G1
G2
G3
G4
G5
G6
G7
G8
G9
H1
H2
H3
H4
H5
H6
H7
H8
H9
.
Pin Name
Pin No
.
Pin Name
NC
P52/A10
P33/SCL0Note 1 J1
P32/SDA0Note 1 J2
P46/AD6
P44/AD4
P41/AD1
P67/ASTB
P65/WR
P74/PCL
NC
P53/A11
P45/AD5
P42/AD2
P64/RD
E2
VDD0
P36/SCK31Note2
NC
E3
P54/A12
P20/SI30
P21/SO30
P24/TxD0
VDD1
J3
J4
J5
J6
J7
J8
J9
E4
−
P25/ASCK0
NC
E5
−
P73/TI51/TO51 E6
P03/INTP3/ADTRG E7
−
P00/INTP0
XT1
P17/ANI7
P12/ANI2
P13/ANI3
NC
P16/ANI6
AVDD
P01/INTP1
VSS1
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
NC
X2
NC
P51/A9
P55/A13
P56/A14
P50/A8
NC
P30
P34/SI31Note 2
P35/SO31Note 2
P23/RxD0
P22/SCK30
AVSS
P47/AD7
P43/AD3
P40/AD0
P66/WAIT
P75/BUZ
P31
VSS0
−
−
−
−
−
P15/ANI5
P11/ANI1
P10/ANI0
AVREF
P72/TI50/TO51 D7
P02/INTP2
VPP
P14/ANI4
RESET
XT2
P71/TI01
D8
D9
P70/TI00/TO0
X1
Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034BY Subseries.
2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B Subseries.
Cautions 1. Connect the VPP pin directly to VSS0 or VSS1 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remarks 1. When the µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) are used in application
fieldsthatrequirereductionofthenoisegeneratedfrominsidethemicrocontroller, theimplementation
of noise reduction measures, such as supplying voltage to VDD0 and VDD1 individually and connecting
VSS0 and VSS1 to different ground lines, is recommended.
2. The special grade version of the 73-pin plastic FBGA (9 x 9) is not provided.
10
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A8 to A15:
AD0 to AD7:
ADTRG:
Address bus
Address/data bus
AD trigger input
Analog input
Asynchronous serial clock
Address strobe
Analog power supply
Analog reference voltage
Analog ground
Buzzer clock
External interrupt input
No connection
Port 0
P70 to P75:
PCL:
Port 7
Programmable clock
Read strobe
Reset
RD:
ANI0 to ANI7:
ASCK0:
RESET:
RxD0:
Receive data
ASTB:
SCK30, SCK31, SCL0: Serial clock
AVDD:
SDA0:
Serial data
Serial input
Serial output
AVREF:
SI30, SI31:
SO30, SO31:
AVSS:
BUZ:
TI00, TI01, TI50, TI51: Timer input
INTP0 to INTP3:
NC:
TO0, TO50, TO51:
TxD0:
Timer output
Transmit data
P00 to P03:
P10 to P17:
P20 to P25:
P30 to P36:
P40 to P47:
P50 to P57:
P64 to P67:
VDD0, VDD1:
VPP:
Power supply
Port 1
Programming power supply
Ground
Port 2
VSS0, VSS1:
WAIT:
Port 3
Wait
Port 4
WR:
Write strobe
Port 5
X1, X2:
Crystal (main system clock)
Crystal (subsystem clock)
Port 6
XT1, XT2:
Data Sheet U16369EJ1V0DS
11
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
2. BLOCK DIAGRAM
TI00/TO0/P70
16-bit timer/
event counter
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
P00 to P03
P10 to P17
P20 to P25
P30 to P36
P40 to P47
P50 to P57
P64 to P67
P70 to P75
TI01/P71
8-bit timer/
event counter 50
TI50/TO50/P72
8-bit timer/
event counter 51
TI51/TO51/P73
Watchdog timer
Watch timer
Flash
memory
(32 KB)
78K/0
CPU core
SI30/P20
SO30/P21
SCK30/P22
Serial
interface 30
SI31/P34
SO31/P35
SCK31/P36
Serial
interface 31Note 1
RAM
(1,024
bytes)
RxD0/P23
TxD0/P24
ASCK0/P25
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
UART0
SDA0/P32
SCL0/P33
I2C busNote 2
External access
RD/P64
WR/P65
ANI0/P10 to
ANI7/P17
AVDD
WAIT/P66
ASTB/P67
A/D converter
AVSS
AVREF
RESET
X1
INTP0/P00 to
INTP3/P03
System control
X2
Interrupt control
Buzzer output
XT1
XT2
BUZ/P75
PCL/P74
Clock output
control
VDD0
VDD1
VSS0
VSS1
VPP
Notes 1. Incorporated only in the µPD78F0034B and 78F0034B(A)
2. Incorporated only in the µPD78F0034BY and 78F0034BY(A)
12
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
Pin Name
I/O
Function
After Reset
Input
Alternate
Function
P00
I/O
Port 0
INTP0
4-bit I/O port.
P01
INTP1
Input/output can be specified in 1-bit units.
P02
INTP2
An on-chip pull-up resistor can be specified by software.
P03
INTP3/ADTRG
ANI0 to ANI7
P10 to P17
Input Port 1
8-bit input-only port.
Port 2
Input
Input
P20
I/O
SI30
6-bit I/O port.
P21
SO30
SCK30
RxD0
TxD0
ASCK0
–
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by software.
P22
P23
P24
P25
P30
I/O
Port 3
N-ch open-drain I/O port.
Input
7-bit I/O port.
LEDs can be driven directly.
P31
Input/output can be specified
in 1-bit units.
Note 1
P32
SDA0
Note 1
P33
SCL0
Note 2
P34
An on-chip pull-up resistor can be
specified by software.
SI31
Note 2
P35
SO31
Note 2
P36
SCK31
P40 to P47
I/O
I/O
I/O
Port 4
Input
Input
Input
AD0 to AD7
8-bit I/O port.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by software.
Interrupt request flag KRIF is set to 1 by falling edge detection.
P50 to P57
Port 5
A8 to A15
8-bit I/O port.
LEDs can be driven directly.
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by software.
P64
P65
P66
P67
Port 6
RD
4-bit I/O port.
WR
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by software.
WAIT
ASTB
Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034BY and 78F0034BY(A).
2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B and 78F0034B(A).
Data Sheet U16369EJ1V0DS
13
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.1 Port Pins (2/2)
Pin Name
I/O
Function
After Reset
Input
Alternate
Function
P70
P71
P72
P73
P74
P75
I/O
Port 7
TI00/TO0
TI01
6-bit I/O port.
Input/output can be specified in 1-bit units.
TI50/TO50
TI51/TO51
PCL
An on-chip pull-up resistor can be specified by software.
BUZ
3.2 Non-Port Pins (1/2)
Pin Name
I/O
Function
After Reset
Input
Alternate
Function
INTP0
INTP1
INTP2
INTP3
SI30
Input External interrupt request input by which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified.
P00
P01
P02
P03/ADTRG
P20
Input Serial interface serial data input.
Input
Note 1
SI31
P34
Note 2
SDA0
I/O
Serial interface serial data input/output
Input
Input
P32
SO30
Output Serial interface serial data output.
P21
Note 1
SO31
P35
SCK30
I/O
Serial interface serial clock input/output.
Input
P22
Note 1
SCK31
P36
Note 2
SCL0
P33
RxD0
TxD0
ASCK0
TI00
Input Serial data input for asynchronous serial interface.
Output Serial data output for asynchronous serial interface.
Input Serial clock input for asynchronous serial interface.
Input
Input
Input
Input
P23
P24
P25
Input External count clock input to 16-bit timer/event counter 0.
Capture trigger signal input to capture register 01 (CR01) of 16-bit timer/
event counter 0.
P70/TO0
TI01
Capture trigger signal input to capture register 00 (CR00) of 16-bit timer/
event counter 0.
P71
TI50
External count clock input to 8-bit timer/event counter 50.
External count clock input to 8-bit timer/event counter 51.
Output 16-bit timer/event counter 0 output.
P72/TO50
P73/TO51
P70/TI00
P72/TI50
P73/TI51
P74
TI51
TO0
Input
Input
TO50
TO51
PCL
8-bit timer/event counter 50 output (shared with 8-bit PWM output).
8-bit timer/event counter 51 output (shared with 8-bit PWM output).
Output Clock output (for trimming of main system clock and subsystem clock).
Output Buzzer output.
Input
Input
Input
BUZ
P75
AD0 to AD7
I/O
Lower address/data bus for extending memory externally.
P40 to P47
Notes 1. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B and 78F0034B(A).
2. SDA0 and SCL0 are incorporated only in the µPD78F0034BY and 78F0034BY(A).
14
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.2 Non-Port Pins (2/2)
Pin Name
I/O
Function
After Reset
Alternate
Function
A8 to A15
RD
Output Higher address bus for extending memory externally.
Output Strobe signal output for read operation of external memory.
Strobe signal output for write operation of external memory.
Input Inserting wait for accessing external memory.
Input
Input
P50 to P57
P64
WR
P65
WAIT
ASTB
Input
Input
P66
Output Strobe output which externally latches address information output to
ports 4 and 5 to access external memory.
P67
ANI0 to ANI7 Input A/D converter analog input.
Input
Input
–
P10 to P17
ADTRG
AVREF
AVDD
Input A/D converter trigger signal input.
P03/INTP3
Input A/D converter reference voltage input.
–
–
–
A/D converter analog power supply.
Set the voltage equal to VDD0 or VDD1.
–
AVSS
–
A/D converter ground potential.
–
–
Set the voltage equal to VSS0 or VSS1.
RESET
X1
Input System reset input.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Input Connecting crystal resonator for main system clock oscillation.
X2
–
XT1
XT2
VDD0
VSS0
VDD1
VSS1
VPP
Input Connecting crystal resonator for subsystem clock oscillation.
–
–
–
–
–
–
Positive power supply voltage for ports.
Ground potential of ports.
Positive power supply (except ports).
Ground potential (except ports).
Applying high-voltage for program write/verify. Connect to VSS0 or VSS1
in normal operation mode.
NCNote
–
Not internally connected. Leave open.
–
–
Note NC is incorporated only in the 73-pin plastic FBGA.
Data Sheet U16369EJ1V0DS
15
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output configuration of each type, refer to Figure 3-1 .
Table 3-1. Types of Pin I/O Circuits (1/2)
Pin Name
P00/INTP0
I/O Circuit Type
8-C
I/O
I/O
Recommended Connection of Unused Pins
Input: Independently connect to VSS0 or VSS1 via a
via a resistor.
P01/INTP1
Output: Leave open.
P02/INTP2
P03/INTP3/ADTRG
P10/ANI0 to P17/ANI7
P20/SI30
25
Input
I/O
Directly connect to VDD0, VDD1, VSS0, or VSS1.
8-C
5-H
8-C
Input: Independently connect to VDD0, VDD1, VSS0, or
VSS1 via a resistor.
P21/SO30
Output: Leave open.
P22/SCK30
P23/RxD0
P24/TxD0
5-H
8-C
P25/ASCK0
P30, P31
13-P
13-R
Input: Directly connect to VSS0 or VSS1.
Output: Leave open at low-level output.
Note 1
P32/SDA0
Note 1
P33/SCL0
Note 2
P34/SI31
8-C
5-H
8-C
5-H
Input: Independently connect to VDD0, VDD1, VSS0 or
VSS1 via a resistor.
Note 2
P35/SO31
Output: Leave open.
Note 2
P36/SCK31
P40/AD0 to P47/AD7
Input: Independently connect to VDD0 or VDD1 via a
resistor.
Output: Leave open.
P50/A8 to P57/A15
P64/RD
5-H
Input: Independently connect to VDD0, VDD1, VSS0, or
VSS1 via a resistor.
Output: Leave open.
P65/WR
P66/WAIT
P67/ASTB
P70/TI00/TO0
P71/TI01
8-C
5-H
P72/TI50/TO50
P73/TI51/TO51
P74/PCL
P75/BUZ
Notes 1. SDA0 and SCL0 are incorporated only in the µPD78F0034BY and 78F0034BY(A).
2. SI31, SO31, and SCK31 are incorporated only in the µPD78F0034B and 78F0034B(A).
16
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 3-1. Types of Pin I/O Circuits (2/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
–
RESET
XT1
2
Input
16
Directly connect to VDD0 or VDD1.
Leave open.
XT2
–
AVDD
AVREF
AVSS
VPP
–
Directly connect to VDD0 or VDD1.
Directly connect to VSS0 or VSS1.
Connect to VSS0 or VSS1.
Data Sheet U16369EJ1V0DS
17
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure 3-1. Pin I/O Circuits
TYPE 2
TYPE 13-R
IN/OUT
Data
Output disable
N-ch
IN
VSS0
Schmitt-triggered input with hysteresis characteristics
TYPE 5-H
TYPE 16
VDD0
Feedback
cut-off
Pullup
enable
P-ch
P-ch
VDD0
Data
P-ch
IN/OUT
Output
disable
N-ch
VSS0
XT1
XT2
Input
enable
TYPE 25
TYPE 8-C
VDD0
P-ch
N-ch
Pullup
enable
Comparator
P-ch
+
–
V
DD0
VSS0
Data
IN
P-ch
V
REF (threshold voltage)
IN/OUT
Input
enable
Output
disable
N-ch
VSS0
TYPE 13-P
IN/OUT
Data
Output disable
N-ch
V
SS0
Input
enable
18
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
4. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY, AND MASK ROM VERSIONS
The µPD78F0034B and 78F0034BY are products provided with a flash memory which enables writing, erasing,
and rewriting of programs with device mounted on the target system.
The functions of the µPD78F0034B and 78F0034BY (except the functions specified for flash memory) can be made
the same as those of the mask ROM versions by setting the memory size switching register (IMS).
Tables 4-1 and 4-2 show the differences between the µPD78F0034B, 78F0034BY and the mask ROM versions.
Table 4-1. Differences Between µPD78F0034B and Mask ROM Versions
Item
µPD78F0034B
Mask ROM Versions
Note
µPD780034A Subseries
µPD780024A Subseries
Internal ROM structure
Internal ROM capacity
Flash memory
Mask ROM
32 KB
µPD780031A: 8 KB
µPD780032A: 16 KB
µPD780033A: 24 KB
µPD780034A: 32 KB
µPD780021A: 8 KB
µPD780022A: 16 KB
µPD780023A: 24 KB
µPD780024A: 32 KB
Internal high-speed RAM capacity
1,024 bytes
µPD780031A: 512 bytes
µPD780032A: 512 bytes
µPD780021A: 512 bytes
µPD780022A: 512 bytes
µPD780033A: 1,024 bytes µPD780023A: 1,024 bytes
µPD780034A: 1,024 bytes µPD780024A: 1,024 bytes
Minimum instruction execution time
Minimum instruction execution time variable function incorporated
When main system clock is selected <µPD78F0034B and expanded-specification products of the mask ROM versions>
0.166 s/0.333 s/0.666 s/1.33 s/2.66 s (@ 12 MHz operation, VDD = 4.5 to 5.5 V)
µ
µ
µ
µ
µ
<Conventional products of the mask ROM versions>
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
When subsystem clock is selected 122 µs (32.768 kHz)
Clock output
<µPD78F0034B and expanded-specification products of the mask ROM versions>
• 93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz, 1.25 MHz, 3 MHz, 6 MHz, 12 MHz
(@ 12 MHz operation with main system clock)
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
<Conventional products of the mask ROM versions>
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system clock)
• 32.768 kHz (@ 32.768 kHz operation with subsystem clock)
Buzzer output
<µPD78F0034B and expanded-specification products of the mask ROM versions>
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz (@ 12 MHz operation with main system clock)
<Conventional products of the mask ROM versions>
•
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main system clock)
A/D converter resolution
10 bits
8 bits
Mask option specification of on-chip
pull-up resistor for pins P30 to P33
Not available
Available
IC pin
Not provided
Provided
Provided
VPP pin
Not provided
Electrical specifications,
Refer to the data sheet of individual products.
recommended soldering conditions
Note The µPD78F0034B can be used as the flash memory version of the µPD780024A Subseries.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then mass
producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
Data Sheet U16369EJ1V0DS
19
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 4-2. Differences Between µPD78F0034BY and Mask ROM Versions
Item
µPD78F0034BY
Mask ROM Versions
µPD780034AY Subseries µPD780024AY Subseries
Mask ROM
Note
Internal ROM structure
Internal ROM capacity
Flash memory
32 KB
µPD780031AY: 8 KB
µPD780032AY: 16 KB
µPD780033AY: 24 KB
µPD780034AY: 32 KB
µPD780021AY: 8 KB
µPD780022AY: 16 KB
µPD780023AY: 24 KB
µPD780024AY: 32 KB
Internal high-speed RAM capacity
1,024 bytes
µPD780031AY: 512 bytes
µPD780032AY: 512 bytes
µPD780021AY: 512 bytes
µPD780022AY: 512 bytes
µPD780033AY: 1,024 bytes µPD780023AY: 1,024 bytes
µPD780034AY: 1,024 bytes µPD780024AY: 1,024 bytes
Minimum instruction execution time
Minimum instruction execution time variable function incorporated
When main system clock is selected 0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs
(operation at 8.38 MHz, VDD = 4.0 to 5.5 V)
When subsystem clock is selected 122 µs (32.768 kHz)
Clock output
• 65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38 MHz
(@ 8.38 MHz operation with main system clock)
• 32.768 kHz
(@ 32.768 kHz operation with subsystem clock)
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz
(@ 8.38 MHz operation with main system clock)
A/D converter resolution
10 bits
8 bits
Mask option specification of on-chip
pull-up resistor for pins P30 and P31
Not available
Available
IC pin
Not provided
Provided
Provided
VPP pin
Not provided
Electrical specifications,
Refer to the data sheet of individual products.
recommended soldering conditions
Note The µPD78F0034BY can be used as the flash memory version of the µPD780024AY Subseries.
Caution There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then mass
producing it with the mask ROM version, be sure to conduct sufficient evaluations on the
commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
20
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
5. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND µPD78F0034A, 78F0034AY
Table 5-1 shows the differences between the µPD78F0034B and µPD78F0034A, and Table 5-2 shows differences
between the µPD78F0034BY and 78F0034AY.
Table 5-1. Differences Between µPD78F0034B and µPD78F0034A
Item
Guaranteed operating speed
(operating frequency)
µPD78F0034B
12 MHz (0.166 µs)
µPD78F0034A
8.38 MHz (0.238 µs)
4.5 to 5.5 V
4.0 to 5.5 V
3.0 to 5.5 V
2.7 to 5.5 V
1.8 to 5.5 V
8.38 MHz (0.238 µs)
8.38 MHz (0.238 µs)
5 MHz (0.4 µs)
8.38 MHz (0.238 µs)
5 MHz (0.4 µs)
5 MHz (0.4 µs)
1.25 MHz (1.6 µs)
1.25 MHz (1.6 µs)
Maximum instruction execution time
When main system clock is selected
Minimum instruction execution time variable function incorporated
0.166 µs/0.333 µs/0.666 µs/1.33 µs/2.66 µs
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs
(@ 12 MHz operation, VDD = 4.5 to 5.5 V)
(@ 8.38 MHz operation, VDD = 4.0 to 5.5 V)
When subsystem clock is selected
Clock output
122 µs (32.768 kHz)
•
93.75 kHz, 187.5 kHz, 375 kHz, 750 kHz,
1.25 MHz, 3 MHz, 6 MHz, 12 MHz (@ 12
MHz operation with main system clock)
•
65.5 kHz, 131 kHz, 262 kHz, 524 kHz,
1.05 MHz, 2.10 MHz, 4.19 MHz, 8.38
MHz (@ 8.38 MHz operation with main
system clock)
• 32.768 kHz (@ 32.768 kHz operation
with subsystem clock)
•
32.768 kHz (@ 32.768 kHz operation
with subsystem clock)
Buzzer output
1.46 kHz, 2.93 kHz, 5.86 kHz, 11.7 kHz
(@ 12 MHz operation with main system
clock)
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz
(@ 8.38 MHz operation with main system
clock)
Communication mode of flash memory
programming
•
•
•
3-wire serial I/O:
UART:
2 channelsNote
1 channel
•
•
•
3-wire serial I/O:
UART:
2 channelsNote
1 channel
Pseudo 3-wire serial I/O: 1 channel
Pseudo 3-wire serial I/O: 1 channel
Electrical specifications, recommended
soldering conditions
Refer to the data sheet of individual products.
Note The µPD78F0034B can use one channel (serial interface SIO30) as a handshake mode.
The µPD78F0034A cannot use a handshake mode.
Remark The operating frequency ratings of the µPD78F0034B and the expanded-specification products of the
mask ROM versions of the µPD780024A, 780034A Subseries are the same. The operating frequency
ratings of the µPD78F0034A and the conventional products of the mask ROM versions of the
µPD780024A, 780034A Subseries are the same.
Data Sheet U16369EJ1V0DS
21
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 5-2. Differences Between µPD78F0034BY and µPD78F0034AY
Item
Guaranteed operating speed
(operating frequency)
µPD78F0034BY
8.38 MHz (0.238 µs)
µPD78F0034AY
4.5 to 5.5 V
4.0 to 5.5 V
3.0 to 5.5 V
2.7 to 5.5 V
1.8 to 5.5 V
8.38 MHz (0.238 µs)
5 MHz (0.4 µs)
5 MHz (0.4 µs)
1.25 MHz (1.6 µs)
Maximum instruction execution time
When main system clock is selected
Minimum instruction execution time variable function incorporated
0.238 µs/0.48 µs/0.95 µs/1.91 µs/3.81 µs (@ 8.38 MHz operation, VDD =
4.0 to 5.5 V)
When subsystem clock is selected
Clock output
122 µs (32.768 kHz)
•
65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.10 MHz, 4.19 MHz,
8.38 MHz (@ 8.38 MHz operation with main system clock)
32.768 kHz (@ 32.768 kHz operation with subsystem clock)
•
Buzzer output
1.02 kHz, 2.05 kHz, 4.10 kHz, 8.19 kHz (@ 8.38 MHz operation with main
system clock)
Communication mode of flash memory
programming
•
•
•
3-wire serial I/O:
UART:
2 channelsNote
1 channel
•
•
•
3-wire serial I/O:
UART:
2 channelsNote
1 channel
Pseudo 3-wire serial I/O: 1 channel
Pseudo 3-wire serial I/O: 1 channel
Electrical specifications, recommended
soldering conditions
Refer to the data sheet of individual products.
Note The µPD78F0034BY can use one channel (serial interface SIO30) as a handshake mode.
The µPD78F0034AY cannot use a handshake mode.
Remark The operating frequency ratings of the µPD78F0034BY, 78F0034AY and the mask ROM versions of the
µPD780024AY, 780034AY Subseries are the same.
6. DIFFERENCES BETWEEN µPD78F0034B, 78F0034BY AND µPD78F0034B(A), 78F0034BY(A)
The µPD78F0034(A) and 78F0034BY(A) are products to which a quality assurance program more stringent than
that used for the µPD780034B and 780034BY (standard models) is applied (NEC Electronics classifies these products
as "special" quality grade models).
The µPD78F0034B, 78F0034BY and µPD78F0034B(A), 78F0034BY(A) only differ in the quality grade; there are
no differences in functions and electrical specifications.
Table 6-1. Differences Between µPD78F0034B, 78F0034BY and µPD78F0034B(A), 78F0034BY(A)
Item
µPD78F0034B, 78F0034BY
Standard
No differences.
µPD78F0034B(A), 78F0034BY(A)
Quality grade
Functions and electrical specifications
Special
22
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
7. MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used.
Bysettingmemorysizeswitchingregister(IMS), theinternalmemoryoftheµPD78F0034B, 78F0034BY, 78F0034B(A),
and 78F0034BY(A) can be mapped identically to that of a mask ROM version.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Caution The initial value of IMS is setting disabled (CFH). Be sure to set C8H or the value of the target
mask ROM version at the moment of initial setting.
Figure 7-1. Format of Memory Size Switching Register
7
6
5
4
0
3
2
1
0
Address
FFF0H
After reset
CFH
R/W
R/W
IMS RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
ROM3 ROM2 ROM1 ROM0 Selection of Internal ROM Capacity
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
0
8 KB
16 KB
24 KB
32 KB
Other than above
Setting prohibited
RAM2 RAM1 RAM0 Selection of Internal High-Speed RAM Capacity
0
1
1
1
0
0
512 bytes
1,024 bytes
Other than above
Setting prohibited
Table 7-1 shows the IMS set value to make the memory mapping the same as those of mask ROM versions.
Table 7-1. Set Value of Memory Size Switching Register
Target Mask ROM Versions
IMS Set Value
µPD780021A, 780021AY, 780031A, 780031AY
µPD780022A, 780022AY, 780032A, 780032AY
µPD780023A, 780023AY, 780033A, 780033AY
µPD780024A, 780024AY, 780034A, 780034AY
42H
44H
C6H
C8H
Data Sheet U16369EJ1V0DS
23
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8. FLASH MEMORY PROGRAMMING
Writing to flash memory can be performed without removing the memory from the target system (on board
programming). Writing is performed with the dedicated flash programmer (Flashpro III (part No.: FL-PR3 and PG-
FP3)/(Flashpro IV (part No.: FL-PR4 and PG-FP4)) connected to the host machine and the target system.
Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro III/
Flashpro IV.
Remark FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd.
8.1 Selection of Communication Mode
Writing to a flash memory is performed using Flashpro III/Flashpro IV in a serial communication. Select one of
the communication modes in Tables 8-1 and 8-2. The selection of the communication mode is made by using the
format shown in Figure 8-1. Each communication mode is selected by the number of VPP pulses shown in Tables
8-1 and 8-2.
Table 8-1. List of Communication Mode (µPD78F0034B)
Communication Mode
3-wire serial I/O
Channels
Pin Used
VPP Pulses
2
SI30/P20
0
1
3
SO30/P21
SCK30/P22
SI31/P34
SO31/P35
SCK31/P36
SI30/P20
SO30/P21
SCK30/P22
HS/P25
UART
1
1
RxD0/P23
TxD0/P24
8
Pseudo 3-wire serial I/O
P72/TI50/TO50
(serial clock input)
P71/TI01
12
(serial data output)
P70/TI00/TO0
(serial data input)
Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 8-1.
24
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 8-2. List of Communication Mode (µPD78F0034BY)
Communication Mode
3-wire serial I/O
Channels
Pin Used
VPP Pulses
1
SI30/P20
0
3
SO30/P21
SCK30/P22
SI30/P20
SO30/P21
SCK30/P22
HS/P25
2
I C bus
1
1
1
SDA0/P32
SCL0/P33
4
UART
RxD0/P23
TxD0/P24
8
Pseudo 3-wire serial I/O
P72/TI50/TO50
(serial clock input)
P71/TI01
12
(serial data output)
P70/TI00/TO0
(serial data input)
Caution Be sure to select a communication mode using the number of VPP pulses shown in Table 8-2.
Figure 8-1. Format of Communication Mode Selection
V
PP pulses
10 V
VDD
VPP
1
2
n
VSS
VDD
RESET
Flash write mode
VSS
Data Sheet U16369EJ1V0DS
25
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
8.2 Flash Memory Programming Functions
Operations such as writing to flash memory are performed by various command/data transmission and reception
operations according to the selected communication mode. Table 8-3 shows major functions of flash memory
programming.
Table 8-3. Major Functions of Flash Memory Programming
Function
Description
Used to stop write operation and detect transmission cycle.
Compares the entire memory contents with the input data.
Erases the entire memory contents.
Reset
Batch verify
Batch erase
Batch blank check
High-speed write
Checks the deletion status of the entire memory.
Performs write to the flash memory based on the write start address and the number of data
to be written (number of bytes).
Continuous write
Status
Performs continuous write based on the information input with high-speed write operation.
Used to confirm the current operating mode and operation end.
Oscillation frequency setting Sets the frequency of the resonator.
Erase time setting
Baud rate setting
Sets the memory erase time.
Sets the communication rate for UART mode
2
2
I C mode setting
Sets standard/high-speed mode for I C bus mode
Silicon signature read
Outputs the device name and memory capacity, and device block information.
8.3 Connection of Flashpro III/Flashpro IV
The connection of Flashpro III/Flashpro IV and the µPD78F0034B or 78F0034BY differs according to the
communication mode (3-wire serial I/O, UART, pseudo 3-wire serial I/O, and I2C bus). The connection for each
communication mode is shown in Figures 8-2 to 8-6, respectively.
Figure 6-2. Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode
µ
PD78F0034B,
µ
PD78F0034BY
Flashpro III/Flashpro IV
VPP
V
V
PP
VDD
RESET
SCK
DD0/VDD1/AVDD
RESET
SCK3n
SI3n
SO
SI
SO3n
GND
VSS0/VSS1/AVSS/AVREF
Remark µPD78F0034B: n = 0, 1
µPD78F0034BY: n = 0
26
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure 8-3. Connection of Flashpro III in 3-Wire Serial I/O Mode (Using Handshake)
µ
µ
PD78F0034B,
PD78F0034BY
Flashpro III/Flashpro IV
VPP
V
PP
VDD
RESET
SCK
SO
V
DD0/VDD1/AVDD
RESET
SCK30
SI30
SI
SO30
HS
HS (P25)
GND
VSS0/VSS1/AVSS/AVREF
Figure 8-4. Connection of Flashpro III/Flashpro IV for UART Mode
µ
PD78F0034B,
µ
Flashpro III/Flashpro IV
VPP
PD78F0034BY
V
PP
V
DD0/VDD1/AVDD
VDD
RESET
SO
RESET
RxD0
TxD0
SI
GND
VSS0/VSS1/AVSS/AVREF
Figure 8-5. Connection of Flashpro III/Flashpro IV for Pseudo 3-Wire Serial I/O Mode
µ
PD78F0034B,
µ
PD78F0034BY
Flashpro III/Flashpro IV
VPP
V
PP
V
DD0/VDD1/AVDD
VDD
RESET
SCK
SO
RESET
P72
(serial clock input)
P70
(serial data input)
SI
P71
(
serial data output)
GND
VSS0/VSS1/AVSS/AVREF
Figure 8-6. Connection of Flashpro III/Flashpro IV for I2C Bus Mode (µPD78F0034BY only)
Flashpro III/Flashpro IV
VPP
µ
PD78F0034BY
V
PP
VDD
VDD0/VDD1/AVDD
RESET
RESET
SCL0
SDA0
SO
SI
GND
VSS0/VSS1/AVSS/AVREF
Data Sheet U16369EJ1V0DS
27
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9. ELECTRICAL SPECIFICATIONS
9.1 µPD78F0034B, 78F0034B(A)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Conditions
Ratings
Unit
V
Supply voltage
–0.3 to +6.5
–0.3 to +10.5
VPP
Note 2
V
Note 1
AVDD
AVREF
AVSS
VI1
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
V
Note 1
Note 1
V
V
Input voltage
P00 to P03, P10 to P17, P20 to P25, P34 to P36,
P40 to P47, P50 to P57, P64 to P67, P70 to P75,
X1, X2, XT1, XT2, RESET
–0.3 to VDD + 0.3
V
VI2
VO
P30 to P33
N-ch open drain
–0.3 to +6.5
V
V
V
Note 1
Output voltage
–0.3 to VDD + 0.3
Analog input voltage VAN
P10 to P17
Per pin
Analog input pin
AVSS –0.3 to AVREF + 0.3Note 1
Note 1
and –0.3 to VDD + 0.3
Output current, high IOH
–10
–15
mA
mA
Total for P00 to P03, P40 to P47, P50 to P57,
P64 to P67, P70 to P75
Total for P20 to P25, P30 to P36
–15
20
mA
mA
Output current, low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
Per pin for P30 to P33, P50 to P57
30
50
mA
mA
Total for P00 to P03, P40 to P47, P64 to P67,
P70 to P75
Total for P20 to P25
Total for P30 to P36
Total for P50 to P57
During normal operation
20
100
mA
mA
mA
°C
100
Operating ambient
temperature
TA
–40 to +85
Storage
Tstg
–40 to +125
°C
temperature
Notes 1. 6.5 V or below
(Note 2 is explained on the following page.)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
28
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the
operating voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the
operating voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
VPP
1.8 V
0 V
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter Symbol
Input
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
capacitance
I/O
CIO
f = 1 MHz
P00 to P03, P20 to P25,
15
pF
capacitance
Unmeasured pins
returned to 0 V.
P34 to P36, P40 to P47,
P50 to P57, P64 to P67,
P70 to P75,
P30 to P33
20
pF
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
29
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Circuit
Resonator
Parameter
Oscillation
Conditions
MIN.
1.0
TYP.
MAX.
12.0
Unit
Ceramic
4.5 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 3.0 V
After VDD reaches
MHz
V
PP
resonator
frequency (fX)Note 1
1.0
1.0
8.38
5.0
4
X2
X1
C2
C1
Oscillation
ms
stabilization timeNote 2 oscillation voltage range
MIN.
1.0
12.0
Crystal
Oscillation
4.5 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 3.0 V
4.0 V ≤ VDD ≤ 5.5 V
MHz
V
PP
X2
X1
resonator
frequency (fX)Note 1
1.0
1.0
8.38
5.0
C2
C1
Oscillation
10
ms
stabilization timeNote 2 1.8 V ≤ VDD < 4.0 V
30
External
clock
X1 input
4.5 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 3.0 V
4.5 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 3.0 V
1.0
1.0
1.0
38
12.0
8.38
5.0
MHz
frequency (fX)Note 1
X2
X1
X1 input
500
500
500
ns
high-/low-level width
(tXH, tXL)
50
85
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
30
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
32
TYP. MAX.
Unit
kHz
Crystal
32.768
35
VPP
XT2 XT1
R2
Oscillation
resonator
Note 1
frequency (fXT)
Oscillation
C4
C3
4.0 V ≤ VDD ≤ 5.5 V
1.2
2
s
Note 2
stabilization time
1.8 V ≤ VDD
<
4.0 V
10
External
clock
32
12
38.5
kHz
µs
X1 input
XT2
XT1
Note 1
frequency (fXT)
15
X1 input high-/low-level
width (tXTH, tXTL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor to the same potential as VSS1.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U16369EJ1V0DS
31
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output current,
high
IOH
Per pin
All pins
–1
–15
10
mA
mA
mA
Output current,
low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
Per pin for P30 to P33, P50 to P57
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
Total for P20 to P25
15
20
mA
mA
mA
mA
mA
V
10
Total for P30 to P36
70
Total for P50 to P57
70
Input voltage,
high
VIH1
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
0.7VDD
0.8VDD
VDD
VDD
V
VIH2
VIH3
VIH4
VIH5
VIL1
P00 to P03, P20, P22, P23, P25, 2.7 V ≤ VDD ≤ 5.5 V
0.8VDD
0.85VDD
0.7VDD
0.8VDD
VDD – 0.5
VDD – 0.2
0.8VDD
0.9VDD
0
VDD
VDD
5.5
5.5
V
V
V
V
V
V
V
V
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
P30 to P33
(N-ch open-drain)
X1, X2
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
2.7 V ≤ VDD ≤ 5.5 V
VDD
VDD
VDD
XT1, XT2
VDD
Input voltage,
low
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
0.3VDD
1.8 V ≤ VDD < 2.7 V
0
0.2VDD
V
VIL2
VIL3
P00 to P03, P20, P22, P23, P25, 2.7 V ≤ VDD ≤ 5.5 V
0
0.2VDD
0.15VDD
0.3VDD
0.2VDD
0.1VDD
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
P34, P36, P70 to P73, RESET
P30 to P33
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
0
0
0
0
VIL4
X1, X2
0
0
0.2
VIL5
XT1, XT2
0
0.2VDD
0.1VDD
VDD
0
Output voltage,
high
VOH1
VOL1
4.0 V ≤ VDD ≤ 5.5 V, IOH = –1 mA
1.8 V ≤ VDD < 4.0 V, IOH = –100 µA
P30 to P33
VDD – 1.0
VDD – 0.5
VDD
Output voltage,
low
4.0 V ≤ VDD ≤ 5.5 V,
2.0
P50 to P57
IOL = 15 mA
0.4
2.0
P00 to P03, P20 to P25, P34 to P36, 4.0 V ≤ VDD ≤ 5.5 V,
P40 to P47, P64 to P67, P70 to P75 IOL = 1.6 mA
IOL = 400 µA
0.4
VOL2
0.5
V
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
32
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
ILIH1
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage
current, high
VIN = VDD
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
µA
ILIH2
ILIH3
ILIL1
X1, X2, XT1, XT2
P30 to P33
20
3
µA
µA
µA
VIN = 5.5 V
VIN = 0 V
Input leakage
current, low
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
ILIL2
ILIL3
ILOH
X1, X2, XT1, XT2
P30 to P33
–20
–3
3
µA
µA
µA
Output leakage
current, high
VOUT = VDD
VOUT = 0 V
VIN = 0 V,
Output leakage
current, low
ILOL
–3
µA
kΩ
Software pull-
up resistor
R
15
30
90
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
33
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
16
MAX.
32
Unit
mA
Note 2
Power supply
currentNote 1
IDD1
12.0 MHz
crystal oscillation
operating mode
VDD = 5.0 V ±10%Note 3
When A/D converter is
stopped
When A/D converter is
operatingNote 7
17
10.5
11.5
7
34
21
23
14
16
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
8.38 MHz
crystal oscillation
VDD = 5.0 V ±10%Note 3
When A/D converter is
stopped
operating mode
When A/D converter is
operatingNote 7
V
DD = 3.0 V + 10%Notes 3, 6 When A/D converter is
stopped
When A/D converter is
operatingNote 7
8
5.00 MHz
crystal oscillation
VDD = 3.0 V ±10%Note 3
VDD = 2.0 V ±10%Note 4
VDD = 5.0 V ±10%Note 3
VDD = 5.0 V ±10%Note 3
When A/D converter is
stopped
4.5
5.5
1
operating mode
When A/D converter is
operatingNote 7
11
2
When A/D converter is
stopped
When A/D converter is
operatingNote 7
2
6
IDD2
12.0 MHz
crystal oscillation
When peripheral functions
are stopped
2
4
HALT mode
When peripheral functions
are operating
8
8.38 MHz
crystal oscillation
When peripheral functions
are stopped
1.2
0.6
0.4
0.2
2.4
5
HALT mode
When peripheral functions
are operating
V
DD = 3.0 V + 10%Notes 3, 6 When peripheral functions
1.2
2.4
0.8
1.7
0.4
1.1
are stopped
When peripheral functions
are operating
5.00 MHz
crystal oscillation
VDD = 3.0 V ±10%Note 3
When peripheral functions
are stopped
HALT mode
When peripheral functions
are operating
VDD = 2.0 V ±10%Note 4
When peripheral functions
are stopped
When peripheral functions
are operating
IDD3
IDD4
32.768 kHz crystal oscillation
operating modeNote 5
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±10%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
VDD = 2.0 V ±10%
VDD = 5.0 V ±10%
VDD = 3.0 V ±10%
115
95
75
30
6
230
190
150
60
µA
µA
µA
µA
µA
µA
µA
µA
32.768 kHz crystal oscillation
HALT modeNote 5
18
2
10
IDD5
XT1 = VDD STOP mode
0.1
0.05
30
When feedback resistor is not used
10
VDD = 2.0 V ±10%
0.05
10
µA
34
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors
of ports).
2. IDD1 includes the peripheral operation current.
3. When the processor clock control register (PCC) is set to 00H.
4. When PCC is set to 02H.
5. When main system clock operation is stopped.
6. The values show the specifications when VDD = 3.0 to 3.3 V. The value in the TYP. column show the
specifications when VDD = 3.0 V.
7. Includes the current through the AVDD pin.
Data Sheet U16369EJ1V0DS
35
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
TCY
Operating with
0.166
0.238
0.4
16
16
µs
µs
(Min. instruction
execution time)
main system clock 3.0 V ≤ VDD ≤ 4.5 V
2.7 V ≤ VDD ≤ 3.0 V
16
µs
1.8 V ≤ VDD ≤ 2.7 V
1.6
16
µs
Note 1
Operating with subsystem clock
3.0 V ≤ VDD ≤ 5.5 V
103.9
122
125
µs
Note 2
TI00, TI01 input
high-/low-level
tTIH0, tTIL0
2/fsam+0.1
2/fsam+0.2
2/fsam+0.5
µs
Note 2
Note 2
2.7 V ≤ VDD < 3.0 V
µs
width
1.8 V ≤ VDD < 2.7 V
µs
TI50, TI51 input
frequency
fTI5
2.7 V ≤ VDD ≤ 5.5 V
0
0
4
MHz
kHz
ns
1.8 V ≤ VDD < 2.7 V
275
TI50, TI51 input
tTIH5, tTIL5
2.7 V ≤ VDD ≤ 5.5 V
100
1.8
high-/low-level
width
1.8 V ≤ VDD < 2.7 V
ns
Interrupt request tINTH, tINTL INTP0 to INTP3,
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
1
2
µs
µs
input high-/low-
P40 to P47
level width
RESET
tRSL
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
10
20
µs
µs
low-level width
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode
register 0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes
fsam = fX/8.
36
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
TCY vs. VDD (main system clock operation)
16.0
10.0
µ
5.0
Operation
guaranteed
range
2.0
1.6
1.0
0.4
0.238
0.166
0.1
5.5
0
1.0
2.0
3.0
4.0
4.5
Supply voltage VDD [V]
5.0
6.0
1.8
2.7
Data Sheet U16369EJ1V0DS
37
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
(1/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
20
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
6
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 54
(3 + 2n)tCY – 60
100
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 87
(3 + 2n)tCY – 93
Read data hold time
RD low-level width
0
tRDL1
(1.5 + 2n)tCY – 33
(2.5 + 2n)tCY – 33
tRDL2
Input time from RD↓ to WAIT↓
tRDWT1
tRDWT2
tWRWT
tWTL
tCY – 43
tCY – 43
Input time from WR↓ to WAIT↓
WAIT low-level width
tCY – 25
(0.5 + n)tCY + 10
(2 + 2n)tCY
Write data setup time
tWDS
60
Write data hold time
tWDH
6
(1.5 + 2n)tCY – 15
6
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 15
0.8tCY – 15
Delay time from RD↑ to ASTB↑ in
1.2tCY
external fetch
Hold time from RD↑ to address in
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
40
10
ns
ns
ns
ns
ns
60
0.8tCY – 15
0.8tCY
0.8tCY
1.2tCY + 30
2.5tCY + 25
2.5tCY + 25
tWTWR
Caution TCY can only be used when the MIN. value is 0.238 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
38
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
(2/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
10
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 108
(3 + 2n)tCY – 120
200
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 148
(3 + 2n)tCY – 162
Read data hold time
RD low-level width
0
tRDL1
(1.5 + 2n)tCY – 40
(2.5 + 2n)tCY – 40
tRDL2
Input time from RD↓ to WAIT↓
tRDWT1
tRDWT2
tWRWT
tWTL
tCY – 75
tCY – 60
Input time from WR↓ to WAIT↓
WAIT low-level width
tCY – 50
(0.5 + 2n)tCY + 10
(2 + 2n)tCY
Write data setup time
tWDS
60
10
Write data hold time
tWDH
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
(1.5 + 2n)tCY – 30
10
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 30
0.8tCY – 30
Delay time from RD↑ to ASTB↑ in
1.2tCY
external fetch
Hold time from RD↑ to address in
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
40
20
ns
ns
ns
ns
ns
120
0.8tCY – 30
0.5tCY
0.5tCY
1.2tCY + 60
2.5tCY + 50
2.5tCY + 50
tWTWR
Caution TCY can only be used when the MIN. value is 0.4 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
Data Sheet U16369EJ1V0DS
39
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
(3/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
120
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
20
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 233
(3 + 2n)tCY – 240
400
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 325
(3 + 2n)tCY – 332
Read data hold time
RD low-level width
0
tRDL1
(1.5 + 2n)tCY – 92
(2.5 + 2n)tCY – 92
tRDL2
Input time from RD↓ to WAIT↓
tRDWT1
tRDWT2
tWRWT
tWTL
tCY – 350
tCY – 132
tCY – 100
(2 + 2n)tCY
Input time from WR↓ to WAIT↓
WAIT low-level width
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
20
Write data hold time
tWDH
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
(1.5 + 2n)tCY – 60
20
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 60
0.8tCY – 60
Delay time from RD↑ to ASTB↑ in
1.2tCY
external fetch
Hold time from RD↑ to address in
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
40
40
ns
ns
ns
ns
ns
240
0.8tCY – 60
0.5tCY
0.5tCY
1.2tCY + 120
2.5tCY + 100
2.5tCY + 100
tWTWR
Caution TCY can only be used when the MIN. value is 1.6 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
40
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK3n... Internal clock output)
Parameter
SCK3n
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
666
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY1
cycle time
3.0 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.0 V
1.8 V ≤ VDD < 2.7 V
3.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 3.0 V
3.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 3.0 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.5 V
954
1600
3200
SCK3n high-/
low-level width
SI3n setup time
(to SCK3n↑)
tKH1, tKL1
tSIK1
tKCY1/2 – 50
tKCY1/2 – 100
100
150
300
SI3n hold time
(from SCK3n↑)
Delay time from
SCK3n↓ to SO3n
output
tKSI1
300
400
Note
tKSO1
C = 100 pF
4.5 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.5 V
200
300
Note C is the load capacitance of the SCK3n and SO3n output lines.
(b) 3-wire serial I/O mode (SCK3n... External clock input)
Parameter
SCK3n
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
666
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY2
cycle time
3.0 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.0 V
1.8 V ≤ VDD < 2.7 V
4.5 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.5 V
2.7 V ≤ VDD < 3.0 V
1.8 V ≤ VDD < 2.7 V
800
1600
3200
333
SCK3n high-/
low-level width
tKH2, tKL2
400
800
1600
100
SI3n setup time
(to SCK3n↑)
tSIK2
SI3n hold time
(from SCK3n↑)
Delay time from
SCK3n↓ to SO3n
output
tKSI2
4.5 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.5 V
300
400
ns
ns
ns
ns
Note
tKSO2
C = 100 pF
4.5 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.5 V
200
300
Note C is the load capacitance of the SO3n output line.
Remark n = 0, 1
Data Sheet U16369EJ1V0DS
41
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(c) UART mode (dedicated baud-rate generator output)
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
3.0 V ≤ VDD < 4.5 V
MIN.
TYP.
MAX.
Unit
bps
bps
Transfer rate
187500
131031
2.7 V ≤ VDD < 3.0 V
1.8 V ≤ VDD < 2.7 V
78125
39063
bps
bps
(d) UART mode (external clock input)
Parameter
ASCK0 cycle time
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
tKCY3
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
3200
400
ns
ns
ASCK0 high-/low-level width
Transfer rate
tKH3,
tKL3
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
800
ns
ns
1600
39063
19531
9766
bps
bps
bps
(e) UART mode (infrared data transfer mode)
Parameter
Symbol
Conditions
4.0 V ≤ VDD ≤ 5.5 V
MIN.
MAX.
Unit
bps
Transfer rate
131031
Allowable bit rate error
Output pulse width
Input pulse width
4.0 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD ≤ 5.5 V
±0.87
%
µs
µs
1.2
4/fX
0.24/fbrNote
Note fbr: Specified baud rate
42
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Resolution
Note
Overall error
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
4.0 V ≤ AVDD < 4.5 V
2.7 V ≤ AVDD < 4.0 V
1.8 V ≤ AVDD < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF ≤ 4.0 V
1.8 V ≤ AVREF < 2.7 V
±0.2
±0.3
±0.6
±0.4
±0.6
±1.2
96
%FSR
%FSR
%FSR
µs
Conversion time
Zero-scale error
tCONV
12
14
17
28
96
µs
96
µs
96
µs
Notes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVREF
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
LSB
LSB
V
Notes 1, 2
Full-scale error
Note 1
Integral linearity error
Differential linearity error
Analog input voltage
Reference voltage
VIAN
0
AVREF
1.8
20
V
Resistance between AVREF and AVSS RREF
During A/D conversion operation
40
kΩ
Notes 1. Excluding quantization error (±1/2 LSB).
2. Indicated as a ratio to the full-scale value (%FSR).
Remark When the µPD78F0034B is used as an 8-bit resolution A/D converter, the specifications are the same
as for the µPD780024A Subseries A/D converter.
Data Sheet U16369EJ1V0DS
43
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Remark The impedance of the analog input pins is shown below.
[Equivalent circuit]
R1
R2
ANIn
(n = 0 to 3)
C1
C2
C3
[Parameter value]
(TYP.)
C3
AVDD
2.7 V
4.5 V
R1
R2
C1
C2
12 kΩ
4 kΩ
8.0 kΩ
2.7 kΩ
3.0 pF
3.0 pF
3.0 pF
1.4 pF
2.0 pF
2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
VDDDR
IDDDR
Conditions
MIN.
1.6
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
Data retention supply current
Subsystem clock stop (XT1 = VDD)
and feed-back resistor disconnected
0.1
30
µA
Release signal set time
tSREL
tWAIT
0
µs
s
17
Oscillation stabilization wait time
Release by RESET
2 /fX
Release by interrupt request
Note
s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
44
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Programming Characteristics (T = +10 to +40°C, VDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
A
(1) Write erase characteristics
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
1.0
TYP.
10.0
MAX.
10.0
8.38
1.25
10.3
30
Unit
MHz
MHz
MHz
V
Operating frequency
fX
3.0 V ≤ VDD < 4.5 V
1.0
1.8 V ≤ VDD < 3.0 V
1.0
VPP supply voltage
VDD supply current
VPP2
IDD
During flash memory programming
9.7
When
10 MHz crystal
VPP = VPP2 oscillation
operating mode
VDD = 5.0 V±10%
mA
8.38 MHz crystal VDD = 5.0 V±10%
24
17
mA
mA
oscillation
VDD = 3.0 V±10%
operating mode
VPP supply current
IPP
When VPP = VPP2
100
0.201
20
mA
s
Step erase timeNote 1
Overall erase timeNote 2
Writeback timeNote 3
Ter
0.199
49.4
0.2
50
Tera
Twb
Cwb
When step erase time = 0.2 s
When writeback time = 50 ms
s/chip
ms
50.6
60
Number of writebacks per
writeback commandNote 4
Times
Number of erases/writebacks
Step write timeNote 5
Cerwb
Twr
16
52
Times
µs
48
48
50
Overall write time per wordNote 6
Number of rewrites per chipNote 7
Twrw
Cerwb
When step write time = 50 µs (1 word = 1 byte)
520
20
µs
1 erase + 1 write after erase = 1 rewrite
Times
Notes 1. The recommended setting value of the step erase time is 0.2 s.
2. The prewrite time before erasure and the erase verify time (writeback time) are not included.
3. The recommended setting value of the writeback time is 50 ms.
4. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step write time is 50 µs.
6. The actual write time per word is 100 µs longer. The internal verify time during or after a write is not
included.
7. When a product is first written after shipment, "erase → write" and "write only" are both taken as one
rewrite.
Example:
P: Write, E: Erase
Shipped product
→P→E→P→E→P: 3 rewrites
Shipped product →E→P→E→P→E→P: 3 rewrites
(2) Serial write operation characteristics
Parameter
Symbol
tPSRON
tDRPSR
tPSRRF
tRFCF
tCOUNT
tCH
Conditions
VPP high voltage
MIN.
1.0
10
TYP.
MAX.
Unit
µs
VPP set time
Set time from VDD↑ to VPP↑
Set time from VPP↑ to RESET↑
VPP count start time from RESET↑
Count execution time
VPP high voltage
VPP high voltage
µs
1.0
1.0
µs
µs
2.0
ms
µs
VPP counter high-level width
VPP counter low-level width
VPP counter noise elimination width
8.0
8.0
tCL
µs
tNFW
40
ns
Data Sheet U16369EJ1V0DS
45
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9.2 µPD78F0034BY, 78F0034BY(A)
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Conditions
Ratings
Unit
V
Supply voltage
–0.3 to +6.5
–0.3 to +10.5
VPP
Note 2
V
Note 1
AVDD
AVREF
AVSS
VI1
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
V
Note 1
Note 1
V
V
Input voltage
P00 to P03, P10 to P17, P20 to P25, P34 to P36,
P40 to P47, P50 to P57, P64 to P67, P70 to P75,
X1, X2, XT1, XT2, RESET
–0.3 to VDD + 0.3
V
VI2
VO
P30 to P33
N-ch open drain
–0.3 to +6.5
V
V
V
Note 1
Output voltage
–0.3 to VDD + 0.3
Analog input voltage VAN
P10 to P17
Per pin
Analog input pin
AVSS –0.3 to AVREF + 0.3Note 1
Note 1
and –0.3 to VDD + 0.3
Output current, high IOH
–10
–15
mA
mA
Total for P00 to P03, P40 to P47, P50 to P57,
P64 to P67, P70 to P75
Total for P20 to P25, P30 to P36
–15
mA
mA
Output current, low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
20
Per pin for P30 to P33, P50 to P57
30
50
mA
mA
Total for P00 to P03, P40 to P47, P64 to P67,
P70 to P75
Total for P20 to P25
Total for P30 to P36
Total for P50 to P57
During normal operation
20
100
mA
mA
mA
°C
100
Operating ambient
temperature
TA
–40 to +85
Storage
Tstg
–40 to +125
°C
temperature
Notes 1. 6.5 V or below
(Note 2 is explained on the following page.)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
46
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Notes 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (1.8 V) of the
operating voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (1.8 V) of the
operating voltage range of VDD (see b in the figure below).
1.8 V
V
DD
0 V
a
b
V
PP
1.8 V
0 V
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter Symbol
Input
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
CIN
f = 1 MHz
Unmeasured pins returned to 0 V.
capacitance
I/O
CIO
f = 1 MHz
P00 to P03, P20 to P25,
15
pF
capacitance
Unmeasured pins
returned to 0 V.
P34 to P36, P40 to P47,
P50 to P57, P64 to P67,
P70 to P75,
P30 to P33
20
pF
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
47
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Recommended
Circuit
Resonator
Parameter
Oscillation
Conditions
MIN.
TYP.
MAX.
8.38
Unit
4.0 V ≤ VDD ≤ 5.5 V
1.0
1.0
Ceramic
MHz
V
PP
X2
R1
X1
resonator
frequency (fX)Note 1
1.8 V ≤ VDD < 4.0 V
5.0
4
Oscillation
After VDD reaches
ms
C2
C1
stabilization timeNote 2 oscillation voltage range
MIN.
Crystal
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
1.0
1.0
8.38
5.0
10
MHz
ms
V
PP
X2
X1
resonator
frequency (fX)Note 1
C2
C1
Oscillation
stabilization timeNote 2 1.8 V ≤ VDD < 4.0 V
30
1.0
8.38
External
clock
X1 input
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
MHz
ns
X2
X1
frequency (fX)Note 1
1.0
50
85
5.0
500
500
X1 input
high-/low-level width
(tXH, tXL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS1.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. When the main system clock is stopped and the system is operating on the subsystem clock,
wait until the oscillation stabilization time has been secured by the program before switching
back to the main system clock.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacture for evaluation.
48
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Subsystem Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended Circuit
Parameter
Conditions
MIN.
32
TYP. MAX.
Unit
kHz
Crystal
32.768
35
VPP
XT2 XT1
R2
Oscillation
resonator
Note 1
frequency (fXT)
Oscillation
C4
C3
4.0 V ≤ VDD ≤ 5.5 V
1.2
2
s
Note 2
stabilization time
1.8 V ≤ VDD
<
4.0 V
10
External
clock
32
12
38.5
kHz
µs
X1 input
XT2
XT1
Note 1
frequency (fXT)
15
X1 input high-/low-level
width (tXTH, tXTL)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the
broken lines in the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor to the same potential as VSS1.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing power
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U16369EJ1V0DS
49
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output current,
high
IOH
Per pin
All pins
–1
–15
10
mA
mA
mA
Output current,
low
IOL
Per pin for P00 to P03, P20 to P25, P34 to P36,
P40 to P47, P64 to P67, P70 to P75
Per pin for P30 to P33, P50 to P57
Total for P00 to P03, P40 to P47, P64 to P67, P70 to P75
Total for P20 to P25
15
20
mA
mA
mA
mA
mA
V
10
Total for P30 to P36
70
Total for P50 to P57
70
Input voltage,
high
VIH1
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
0.7VDD
0.8VDD
VDD
VDD
V
VIH2
VIH3
VIH4
VIH5
VIL1
P00 to P03, P20, P22, P23, P25, 2.7 V ≤ VDD ≤ 5.5 V
0.8VDD
0.85VDD
0.7VDD
0.8VDD
VDD – 0.5
VDD – 0.2
0.8VDD
0.9VDD
0
VDD
VDD
5.5
5.5
V
V
V
V
V
V
V
V
V
P34, P36, P70 to P73, RESET
1.8 V ≤ VDD < 2.7 V
P30 to P33
(N-ch open-drain)
X1, X2
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
2.7 V ≤ VDD ≤ 5.5 V
VDD
VDD
VDD
XT1, XT2
VDD
Input voltage,
low
P10 to P17, P21, P24, P35,
P40 to P47, P50 to P57,
P64 to P67, P74, P75
0.3VDD
1.8 V ≤ VDD < 2.7 V
0
0.2VDD
V
VIL2
VIL3
P00 to P03, P20, P22, P23, P25, 2.7 V ≤ VDD ≤ 5.5 V
0
0.2VDD
0.15VDD
0.3VDD
0.2VDD
0.1VDD
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
V
P34, P36, P70 to P73, RESET
P30 to P33
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
0
0
0
0
VIL4
X1, X2
0
0
0.2
VIL5
XT1, XT2
0
0.2VDD
0.1VDD
VDD
0
Output voltage,
high
VOH1
VOL1
4.0 V ≤ VDD ≤ 5.5 V, IOH = –1 mA
1.8 V ≤ VDD < 4.0 V, IOH = –100 µA
P30 to P33
VDD – 1.0
VDD – 0.5
VDD
Output voltage,
low
4.0 V ≤ VDD ≤ 5.5 V,
2.0
P50 to P57
IOL = 15 mA
0.4
2.0
P00 to P03, P20 to P25, P34 to P36, 4.0 V ≤ VDD ≤ 5.5 V,
P40 to P47, P64 to P67, P70 to P75 IOL = 1.6 mA
IOL = 400 µA
0.4
VOL2
0.5
V
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins.
50
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
ILIH1
Conditions
MIN.
TYP.
MAX.
3
Unit
Input leakage
current, high
VIN = VDD
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
µA
ILIH2
ILIH3
ILIL1
X1, X2, XT1, XT2
P30 to P33
20
3
µA
µA
µA
VIN = 5.5 V
VIN = 0 V
Input leakage
current, low
P00 to P03, P10 to P17, P20 to P25,
P34 to P36, P40 to P47, P50 to P57,
P64 to P67, P70 to P75,
RESET
–3
ILIL2
ILIL3
ILOH
X1, X2, XT1, XT2
P30 to P33
–20
–3
3
µA
µA
µA
Output leakage
current, high
VOUT = VDD
VOUT = 0 V
VIN = 0 V,
Output leakage
current, low
ILOL
–3
µA
kΩ
Software pull-
up resistor
R
15
30
90
P00 to P03, P20 to P25, P34 to P36, P40 to P47,
P50 to P57, P64 to P67, P70 to P75
Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port
pins.
Data Sheet U16369EJ1V0DS
51
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Power supply
currentNote 1
Symbol
Conditions
MIN.
TYP.
10.5
MAX.
21
Unit
mA
Note 2
3
IDD1
8.38 MHz
VDD = 5.0 V ±10%Note
VDD = 3.0 V ±10%Note
VDD = 2.0 V ±10%Note
VDD = 5.0 V ±10%Note
VDD = 3.0 V ±10%Note
VDD = 2.0 V ±10%Note
When A/D converter is
stopped
crystal oscillation
operating mode
When A/D converter is
operatingNote 6
11.5
4.5
5.5
1
23
9
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
3
4
3
3
4
5.00 MHz
When A/D converter is
stopped
crystal oscillation
operating mode
When A/D converter is
operatingNote 6
11
2
When A/D converter is
stopped
When A/D converter is
operatingNote 6
2
6
IDD2
8.38 MHz
When peripheral functions
are stopped
1.2
2.4
5
crystal oscillation
HALT mode
When peripheral functions
are operating
5.00 MHz
When peripheral functions
are stopped
0.4
0.2
0.8
1.7
0.4
1.1
crystal oscillation
HALT mode
When peripheral functions
are operating
When peripheral functions
are stopped
When peripheral functions
are operating
IDD3
IDD4
IDD5
32.768 kHz crystal oscillation
operating modeNote 5
VDD = 5.0 V ±10%Note 2
VDD = 3.0 V ±10%Note 2
VDD = 2.0 V ±10%Note 3
VDD = 5.0 V ±10%Note 2
VDD = 3.0 V ±10%Note 2
VDD = 2.0 V ±10%Note 3
VDD = 5.0 V ±10%Note 2
VDD = 3.0 V ±10%Note 2
VDD = 2.0 V ±10%Note 3
115
95
230
190
150
60
µA
µA
µA
µA
µA
µA
µA
µA
µA
75
32.768 kHz crystal oscillation
HALT modeNote 5
30
6
18
2
10
XT1 = VDD STOP mode
0.1
0.05
0.05
30
When feedback resistor is not used
10
10
Notes 1. Total current through the internal power supply (VDD0, VDD1) (except the current through pull-up resistors
of ports).
2. IDD1 includes the peripheral operation current.
3. When the processor clock control register (PCC) is set to 00H.
4. When PCC is set to 02H.
5. When main system clock operation is stopped.
6. Includes the current through the AVDD pin.
52
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
0.238
0.4
TYP.
122
MAX.
16
Unit
µs
Cycle time
TCY
Operating with
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
(Min. instruction
execution time)
main system clock
16
µs
1.6
16
µs
Note 1
Operating with subsystem clock
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 5.5 V
103.9
125
µs
Note 2
TI00, TI01 input
high-/low-level
tTIH0, tTIL0
2/fsam+0.1
µs
Note 2
Note 2
2/fsam+0.2
µs
width
2/fsam+0.5
µs
TI50, TI51 input
frequency
fTI5
0
0
4
MHz
kHz
ns
275
TI50, TI51 input
high-/low-level
width
tTIH5, tTIL5
100
1.8 V ≤ VDD < 2.7 V
1.8
1
ns
µs
µs
Interrupt request tINTH, tINTL INTP0 to INTP3,
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
input high-/low-
P40 to P47
level width
2
RESET
tRSL
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
10
20
µs
µs
low-level width
Notes 1. Value when the external clock is used. When a crystal resonator is used, it is 114 µs (MIN.).
2. Selection of fsam = fX, fX/4, fX/64 is possible using bits 0 and 1 (PRM00, PRM01) of prescaler mode register
0 (PRM0). However, if the TI00 valid edge is selected as the count clock, the value becomes fsam = fX/8.
Data Sheet U16369EJ1V0DS
53
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
TCY vs. VDD (main system clock operation)
16.0
10.0
µ
5.0
Operation
guaranteed
range
2.0
1.6
1.0
0.4
0.238
0.1
5.5
0
1.0
2.0
3.0
4.0
5.0
6.0
1.8
2.7
Supply voltage VDD [V]
54
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 4.0 to 5.5 V)
(1/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
20
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
6
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 54
(3 + 2n)tCY – 60
100
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 87
(3 + 2n)tCY – 93
Read data hold time
RD low-level width
0
tRDL1
tRDL2
tRDWT1
tRDWT2
tWRWT
tWTL
(1.5 + 2n)tCY – 33
(2.5 + 2n)tCY – 33
Input time from RD↓ to WAIT↓
tCY – 43
tCY – 43
Input time from WR↓ to WAIT↓
WAIT low-level width
tCY – 25
(0.5 + n)tCY + 10
(2 + 2n)tCY
Write data setup time
tWDS
60
Write data hold time
tWDH
6
(1.5 + 2n)tCY – 15
6
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 15
0.8tCY – 15
Delay time from RD↑ to ASTB↑ in
1.2tCY
external fetch
Hold time from RD↑ to address in
tRDADH
0.8tCY – 15
1.2tCY + 30
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
40
10
ns
ns
ns
ns
ns
60
0.8tCY – 15
0.8tCY
0.8tCY
1.2tCY + 30
2.5tCY + 25
2.5tCY + 25
tWTWR
Caution TCY can only be used when the MIN. value is 0.238 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
Data Sheet U16369EJ1V0DS
55
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 2.7 to 4.0 V)
(2/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
10
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 108
(3 + 2n)tCY – 120
200
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 148
(3 + 2n)tCY – 162
Read data hold time
RD low-level width
0
tRDL1
(1.5 + 2n)tCY – 40
(2.5 + 2n)tCY – 40
tRDL2
Input time from RD↓ to WAIT↓
tRDWT1
tRDWT2
tWRWT
tWTL
tCY – 75
tCY – 60
Input time from WR↓ to WAIT↓
WAIT low-level width
tCY – 50
(0.5 + 2n)tCY + 10
(2 + 2n)tCY
Write data setup time
tWDS
60
10
Write data hold time
tWDH
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
(1.5 + 2n)tCY – 30
10
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 30
0.8tCY – 30
Delay time from RD↑ to ASTB↑ in
1.2tCY
external fetch
Hold time from RD↑ to address in
tRDADH
0.8tCY – 30
1.2tCY + 60
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
40
20
ns
ns
ns
ns
ns
120
0.8tCY – 30
0.5tCY
0.5tCY
1.2tCY + 60
2.5tCY + 50
2.5tCY + 50
tWTWR
Caution TCY can only be used when the MIN. value is 0.4 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
56
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(2) Read/write operation (TA = –40 to +85°C, VDD = 1.8 to 2.7 V)
(3/3)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Conditions
MIN.
0.3tCY
120
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
20
Input time from address to data
tADD1
tADD2
tRDAD
tRDD1
tRDD2
tRDH
(2 + 2n)tCY – 233
(3 + 2n)tCY – 240
400
Output time from RD↓ to address
Input time from RD↓ to data
0
(2 + 2n)tCY – 325
(3 + 2n)tCY – 332
Read data hold time
RD low-level width
0
tRDL1
(1.5 + 2n)tCY – 92
(2.5 + 2n)tCY – 92
tRDL2
Input time from RD↓ to WAIT↓
tRDWT1
tRDWT2
tWRWT
tWTL
tCY – 350
tCY – 132
tCY – 100
(2 + 2n)tCY
Input time from WR↓ to WAIT↓
WAIT low-level width
(0.5 + 2n)tCY + 10
Write data setup time
tWDS
60
20
Write data hold time
tWDH
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
(1.5 + 2n)tCY – 60
20
Delay time from ASTB↓ to RD↓
Delay time from ASTB↓ to WR↓
2tCY – 60
0.8tCY – 60
Delay time from RD↑ to ASTB↑ in
1.2tCY
external fetch
Hold time from RD↑ to address in
tRDADH
0.8tCY – 60
1.2tCY + 120
ns
external fetch
Write data output time from RD↑
Write data output time from WR↓
Hold time from WR↑ to address
Delay time from WAIT↑ to RD↑
Delay time from WAIT↑ to WR↑
tRDWD
tWRWD
tWRADH
tWTRD
40
40
ns
ns
ns
ns
ns
240
0.8tCY – 60
0.5tCY
0.5tCY
1.2tCY + 120
2.5tCY + 100
2.5tCY + 100
tWTWR
Caution TCY can only be used when the MIN. value is 1.6 µs.
Remarks 1. tCY = TCY/4
2. n indicates the number of waits.
3. CL = 100 pF (CL is the load capacitance of the AD0 to AD7, A8 to A15, RD, WR, WAIT, and ASTB
pins.)
Data Sheet U16369EJ1V0DS
57
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(3) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK30... Internal clock output)
Parameter
SCK30
Symbol
Conditions
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
MIN.
954
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY1
cycle time
1600
3200
SCK30 high-/
low-level width
SI30 setup time
(to SCK30↑)
tKH1, tKL1
tSIK1
tKCY1/2 – 50
tKCY1/2 – 100
100
150
300
SI3n hold time
tKSI1
400
(from SCK30↑)
Note
Delay time from
SCK30↓ to SO30
output
tKSO1
C = 100 pF
300
ns
Note C is the load capacitance of the SCK30 and SO30 output lines.
(b) 3-wire serial I/O mode (SCK30... External clock input)
Parameter
SCK30
Symbol
Conditions
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tKCY2
cycle time
1600
3200
400
SCK30 high-/
low-level width
tKH2, tKL2
800
1600
100
SI30 setup time
tSIK2
tKSI2
tKSO2
(to SCK30↑)
SI30 hold time
400
ns
ns
(from SCK30↑)
Note
Delay time from
SCK30↓ to SO30
output
C = 100 pF
300
Note C is the load capacitance of the SO30 output line.
58
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(c) UART mode (dedicated baud-rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
131031
78125
39063
Unit
bps
bps
bps
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
(d) UART mode (external clock input)
Parameter
ASCK0 cycle time
Symbol
Conditions
MIN.
800
TYP.
MAX.
Unit
ns
tKCY3
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1600
ns
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
3200
400
ns
ns
ASCK0 high-/low-level width
Transfer rate
tKH3,
tKL3
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
800
ns
ns
1600
39063
19531
9766
bps
bps
bps
(e) UART mode (infrared data transfer mode)
Parameter
Transfer rate
Symbol
Conditions
4.0 V ≤ VDD ≤ 5.5 V
MIN.
MAX.
Unit
131031
±0.87
bps
%
Allowable bit rate error
Output pulse width
4.0 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD ≤ 5.5 V
1.2
4/fX
0.24/fbrNote
µs
Input pulse width
4.0 V ≤ VDD ≤ 5.5 V
µs
Note fbr: Specified baud rate
Data Sheet U16369EJ1V0DS
59
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(f) I2C bus mode
Parameter
Symbol
Standard Mode
High-Speed Mode
Unit
MIN.
MAX.
100
–
MIN.
0
MAX.
SCL0 clock frequency
fCLK
tBUF
0
400
kHz
Bus free time
4.7
1.3
–
µs
(between stop and start condition)
Hold timeNote 1
tHD:STA
tLOW
4.0
4.7
4.0
4.7
5.0
0Note 2
250
–
–
0.6
–
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
pF
SCL0 clock low-level width
SCL0 clock high-level width
Start/restart condition setup time
Data hold time CBUS compatible master
I2C bus
–
1.3
–
tHIGH
–
–
0.6
–
–
tSU:STA
tHD:DAT
0.6
–
–
–
–
0Note 2
0.9Note 3
–
Data setup time
tSU:DAT
tR
–
100Note 4
SDA0 and SCL0 signal rise time
SDA0 and SCL0 signal fall time
Stop condition setup time
Spike pulse width controlled by input filter
Capacitive load per each bus line
1,000
300
–
20 + 0.1CbNote 5
300
300
–
tF
–
20 + 0.1CbNote 5
tSU:STO
tSP
4.0
–
0.6
0
–
50
Cb
–
400
–
400
Notes 1. In the start condition, the first clock pulse is generated after this hold time.
2. To fill in the undefined area of the SCL0 falling edge, it is necessary for the device to internally provide
at least 300 ns of hold time for the SDA0 signal (which is VIHmin. of the SCL0 signal).
3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time tHD:DAT
needs to be fulfilled.
4. The high-speed mode I2C bus is available in a standard mode I2C bus system. At this time, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU:DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the next data bit to the SDA0 line before the SCL0 line is released (tRmax. + tSU:DAT
= 1,000 + 250 = 1,250 ns by standard mode I2C bus specification).
5. Cb: Total capacitance per one bus line (unit: pF)
60
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Resolution
Note
Overall error
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
4.0 V ≤ AVDD < 4.5 V
2.7 V ≤ AVDD < 4.0 V
1.8 V ≤ AVDD < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
1.8 V ≤ AVREF < 2.7 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF ≤ 4.0 V
1.8 V ≤ AVREF < 2.7 V
±0.2
±0.3
±0.6
±0.4
±0.6
±1.2
96
%FSR
%FSR
%FSR
µs
Conversion time
Zero-scale error
tCONV
12
14
17
28
96
µs
96
µs
96
µs
Notes 1, 2
±0.4
±0.6
±1.2
±0.4
±0.6
±1.2
±2.5
±4.5
±8.5
±1.5
±2.0
±3.5
AVREF
AVDD
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
LSB
LSB
V
Notes 1, 2
Full-scale error
Note 1
Integral linearity error
Differential linearity error
Analog input voltage
Reference voltage
VIAN
0
AVREF
1.8
20
V
Resistance between AVREF and AVSS RREF
During A/D conversion operation
40
kΩ
Notes 1. Excluding quantization error (±1/2 LSB).
2. Indicated as a ratio to the full-scale value (%FSR).
Remark When the µPD78F0034BY is used as an 8-bit resolution A/D converter, the specifications are the same
as for the µPD780024AY Subseries A/D converter.
Data Sheet U16369EJ1V0DS
61
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Remark The impedance of the analog input pins is shown below.
[Equivalent circuit]
R1
R2
ANIn
(n = 0 to 3)
C1
C2
C3
[Parameter value]
(TYP.)
C3
AVDD
2.7 V
4.5 V
R1
R2
C1
C2
12 kΩ
4 kΩ
8.0 kΩ
2.7 kΩ
3.0 pF
3.0 pF
3.0 pF
1.4 pF
2.0 pF
2.0 pF
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
VDDDR
IDDDR
Conditions
MIN.
1.6
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
Data retention supply current
Subsystem clock stop (XT1 = VDD)
and feed-back resistor disconnected
0.1
30
µA
Release signal set time
tSREL
tWAIT
0
µs
s
17
Oscillation stabilization wait time
Release by RESET
2 /fX
Release by interrupt request
Note
s
Note Selection of 212/fX and 214/fX to 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation
stabilization time select register (OSTS).
62
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Programming Characteristics (T = +10 to +40°C, VDD = 1.8 to 5.5 V, VSS = AVSS = 0 V)
A
(1) Write erase characteristics
Parameter
Symbol
Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
1.0
TYP.
10.0
MAX.
10.0
8.38
1.25
10.3
30
Unit
MHz
MHz
MHz
V
Operating frequency
fX
3.0 V ≤ VDD < 4.5 V
1.0
1.8 V ≤ VDD < 3.0 V
1.0
VPP supply voltage
VDD supply current
VPP2
IDD
During flash memory programming
9.7
When
10 MHz crystal
VPP = VPP2 oscillation
operating mode
VDD = 5.0 V±10%
mA
8.38 MHz crystal VDD = 5.0 V±10%
24
17
mA
mA
oscillation
VDD = 3.0 V±10%
operating mode
VPP supply current
IPP
When VPP = VPP2
100
0.201
20
mA
s
Step erase timeNote 1
Overall erase timeNote 2
Writeback timeNote 3
Ter
0.199
49.4
0.2
50
Tera
Twb
Cwb
When step erase time = 0.2 s
When writeback time = 50 ms
s/chip
ms
50.6
60
Number of writebacks per
writeback commandNote 4
Times
Number of erases/writebacks
Step write timeNote 5
Cerwb
Twr
16
52
Times
µs
48
48
50
Overall write time per wordNote 6
Number of rewrites per chipNote 7
Twrw
Cerwb
When step write time = 50 µs (1 word = 1 byte)
520
20
µs
1 erase + 1 write after erase = 1 rewrite
Times
Notes 1. The recommended setting value of the step erase time is 0.2 s.
2. The prewrite time before erasure and the erase verify time (writeback time) are not included.
3. The recommended setting value of the writeback time is 50 ms.
4. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step write time is 50 µs.
6. The actual write time per word is 100 µs longer. The internal verify time during or after a write is not
included.
7. When a product is first written after shipment, "erase → write" and "write only" are both taken as one
rewrite.
Example:
P: Write, E: Erase
Shipped product
→P→E→P→E→P: 3 rewrites
Shipped product →E→P→E→P→E→P: 3 rewrites
(2) Serial write operation characteristics
Parameter
Symbol
tPSRON
tDRPSR
tPSRRF
tRFCF
tCOUNT
tCH
Conditions
VPP high voltage
MIN.
1.0
10
TYP.
MAX.
Unit
µs
VPP set time
Set time from VDD↑ to VPP↑
Set time from VPP↑ to RESET↑
VPP count start time from RESET↑
Count execution time
VPP high voltage
VPP high voltage
µs
1.0
1.0
µs
µs
2.0
ms
µs
VPP counter high-level width
VPP counter low-level width
VPP counter noise elimination width
8.0
8.0
tCL
µs
tNFW
40
ns
Data Sheet U16369EJ1V0DS
63
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
9.3 Timing Chart
AC Timing Test Point (Excluding X1, XT1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Point of test
Clock Timing
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
IL4 (MAX.)
X1 input
V
1/fXT
t
XTL
t
XTH
V
IH5 (MIN.)
IL5 (MAX.)
XT1 input
V
TI Timing
t
TIL0
t
TIH0
TI00, TI01
1/fTI5
t
TIL5
t
TIH5
TI50, TI51
64
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Interrupt Request Input Timing
t
INTL
t
INTH
INTP0 to INTP3
RESET Input Timing
t
RSL
RESET
Data Sheet U16369EJ1V0DS
65
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Read/Write Operation
External fetch (no wait):
A8 to A15
Higher 8-bit address
t
ADD1
Hi-Z
Lower 8-bit
address
AD0 to AD7
Instruction code
t
RDAD
RDD1
t
ADS
t
t
ADH
t
RDADH
RDAST
t
ASTH
t
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
External fetch (wait insertion):
A8 to A15
Higher 8-bit address
Hi-Z
t
ADD1
Lower 8-bit
address
AD0 to AD7
Instruction code
t
RDAD
t
ADS
t
RDADH
t
ADH
t
RDD1
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
WAIT
t
RDWT1
t
WTL
t
WTRD
66
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
External data access (no wait):
A8 to A15
Higher 8-bit address
t
ADD2
Hi-Z
Hi-Z
Lower 8-bit
address
AD0 to AD7
Read data
Write data
t
RDAD
t
ADS
t
RDD2
t
ADH
t
ASTH
t
RDH
ASTB
RD
t
RDWD
t
ASTRD
t
RDL2
t
WDS
t
WDH
WRADH
t
t
WRWD
WR
t
ASTWR
t
WRL1
External data access (wait insertion):
A8 to A15
Higher 8-bit address
Read data
t
ADD2
Hi-Z
Hi-Z
Lower 8-bit
address
Write data
AD0 to AD7
t
RDAD
t
ADH
t
ADS
t
RDH
t
ASTH
t
RDD2
ASTB
RD
t
ASTRD
t
RDWD
t
RDL2
t
WDS
t
WDH
t
WRWD
WR
t
ASTWR
t
WRL1
t
WRADH
WAIT
t
WTL
t
WTRD
t
RDWT2
t
WTL
t
WRWT
t
WTWR
Data Sheet U16369EJ1V0DS
67
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK3n
SI3n
t
SIKm
t
KSIm
Input data
t
KSOm
SO3n
Output data
Remarks 1. m = 1, 2
2. µPD78F0034B and 78F0034B(A):
n = 0, 1
3. µPD78F0034BY and 78F0034BY(A): n = 0
UART mode (external clock input):
KCY3
t
t
KL3
tKH3
ASCK0
I2C bus mode (µPD78F0034BY only):
t
LOW
t
R
SCL0
SDA0
t
F
t
HD:DAT
t
HIGH
SU:DAT
t
SU:STA
t
HD:STA
t
SP
t
SU:STO
t
HD:STA
t
t
BUF
Stop
Start
Restart
condition
Stop
condition
condition condition
68
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Data Retention Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
V
DD
V
DDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(Interrupt request)
tWAIT
Data Sheet U16369EJ1V0DS
69
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Flash Memory Write Mode Set Timing
VDD
0 V
VDD
tDRPSR
tRFCF
tCH
VPPH
VPP VPPL
0 V
tCL
tPSRON tPSRRF
tCOUNT
VDD
RESET (input)
0 V
70
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
10. PACKAGE DRAWINGS
64-PIN PLASTIC LQFP (10x10)
A
B
detail of lead end
48
49
33
32
S
P
T
C
D
R
L
U
64
1
17
Q
16
F
G
J
M
H
I
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
12.0±0.2
10.0±0.2
10.0±0.2
12.0±0.2
1.25
K
S
1.25
0.22±0.05
0.08
M
N
S
J
0.5 (T.P.)
1.0±0.2
0.5
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.4
0.1±0.05
+4°
3°
R
−3°
S
T
1.5±0.10
0.25
U
0.6±0.15
S64GB-50-8EU-2
Remark The package and material of ES products are the same as mass produced products.
71
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
64-PIN PLASTIC LQFP (14x14)
A
B
48
49
33
32
detail of lead end
S
P
C
D
T
R
L
64
17
16
U
1
Q
F
G
J
M
H
I
ITEM MILLIMETERS
A
B
C
D
F
17.2±0.2
14.0±0.2
14.0±0.2
17.2±0.2
1.0
K
S
G
1.0
+0.08
0.37
H
−0.07
N
S
M
I
J
0.20
0.8 (T.P.)
1.6±0.2
0.8
K
L
NOTE
+0.03
0.17
M
Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
−0.06
N
P
Q
0.10
1.4±0.1
0.127±0.075
+4°
3°
R
−3°
S
T
1.7 MAX.
0.25
U
0.886±0.15
P64GC-80-8BS
Remark The package and material of ES products are the same as mass produced products.
72
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
64-PIN PLASTIC TQFP (12x12)
A
B
detail of lead end
48
33
32
49
S
P
T
C
D
R
L
U
Q
64
17
16
1
F
G
J
M
H
I
ITEM MILLIMETERS
A
B
C
D
F
14.0±0.2
12.0±0.2
12.0±0.2
14.0±0.2
1.125
K
S
G
1.125
+0.06
0.32
H
−0.10
M
I
0.13
J
K
L
0.65 (T.P.)
1.0±0.2
0.5
N
S
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
+0.03
0.17
M
−0.07
N
P
Q
0.10
1.0
0.1±0.05
+4°
3°
R
−3°
1.1±0.1
0.25
S
T
U
0.6±0.15
P64GK-65-9ET-3
Remark The package and material of ES products are the same as mass produced products.
73
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
73-PIN PLASTIC FBGA (9x9)
D
w
S
A
ZE
ZD
A
9
8
7
6
5
4
3
2
1
B
E
J H G F E D C B A
INDEX MARK
w S B
A
A2
y1
S
e
(UNIT:mm)
ITEM DIMENSIONS
S
D
E
9.00±0.10
9.00±0.10
0.20
w
A
1.28±0.10
0.35±0.06
0.93
y
A1
S
A1
A2
e
M
φ
φ
x
b
S A B
0.80
+0.05
0.50
b
–0.10
x
0.08
0.10
0.20
1.30
y
y1
ZD
ZE
1.30
P73F1-80-CN3
Remark The external dimensions and materials of the ES version are the same as those of the mass-produced
version.
74
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
11. RECOMMENDED SOLDERING CONDITIONS
The µPD78F0034B, 78F0034BY, 78F0034B(A), and 78F0034BY(A) should be soldered and mounted under
the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
Table 11-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD78F0034BGB-8EU:
µPD78F0034BGB(A)-8EU: 64-pin plastic LQFP (10 x 10)
µPD78F0034BYGB-8EU: 64-pin plastic LQFP (10 x 10)
µPD78F0034BYGB(A)-8EU: 64-pin plastic LQFP (10 x 10)
64-pin plastic LQFP (10 x 10)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-107-2
VP15-107-2
–
Count: Two times or less,
Note
Exposure limit: 7 days
(after 7 days, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less,
Note
Exposure limit: 7 days
(after 7 days, prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD78F0034BGC-8BS:
µPD78F0034BGC(A)-8BS: 64-pin plastic LQFP (14 x 14)
µPD78F0034BYGC-8BS: 64-pin plastic LQFP (14 x 14)
µPD78F0034BYGC(A)-8BS: 64-pin plastic LQFP (14 x 14)
64-pin plastic LQFP (14 x 14)
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-00-2
VP15-00-2
WS60-00-1
–
Count: Two times or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
75
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Table 11-1. Surface Mounting Type Soldering Conditions (2/2)
(3) µPD78F0034BGK-9ET:
64-pin plastic TQFP (12 x 12)
µPD78F0034BGK(A)-9ET: 64-pin plastic TQFP (12 x 12)
µPD78F0034BYGK-9ET:
64-pin plastic TQFP (12 x 12)
µPD78F0034BYGK(A)-9ET: 64-pin plastic TQFP (12 x 12)
Soldering Method
Infrared reflow
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-107-2
VP15-107-2
WS60-107-1
–
Count: Two times or less,
Note
Exposure limit: 7 days
(after 7 days, prebake at 125°C for 10 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Two times or less,
Note
Exposure limit: 7 days
(after 7 days, prebake at 125°C for 10 hours)
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Time: 10 seconds max.,
Count: Once, Preheating temperature: 120°C max. (package surface temperature),
Note
Exposure limit: 7 days
(after 7 days, prebake at 125°C for 10 hours)
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(4) µPD78F0034BF1-CN3: 73-pin plastic FBGA (9 x 9)
µPD78F0034BYF1-CN3: 73-pin plastic FBGA (9 x 9)
Soldering Method
Soldering Conditions
Recommended
ConditionSymbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),
Count: Three times or less,
IR60-203-3
Exposure limit: 3 daysNote (after that, prebake at 125°C for 20 hours)
VPS
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less,
VP15-203-3
Exposure limit: 3 daysNote (after that, prebake at 125°C for 20 hours)
Note After opening the dry pack, store it at 25°C or less and 65%RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
76
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD780034B, 780034BY.
Also refer to (6) Cautions on Using Development Tools.
(1) Software Package
SP78K0
CD-ROM in which various software tools for 78K/0 development are integrated in one
package
(2) Language Processing Software
RA78K0
Assembler package common to 78K/0 Series
C compiler package common to 78K/0 Series
Device file for µPD780034A, 780034AY Subseries
C compiler library source file common to 78K/0 Series
CC78K0
DF780034
CC78K0-L
(3) Flash Memory Writing Tools
Flashpro III (FL-PR3, PG-FP3)
Flashpro IV (FL-PR4, PG-FP4)
Flash programmer dedicated to microcontrollers with on-chip flash memory
FA-64GB-8EU
FA-64GC-8BS-A
FA-64GK-9ET
Adapter for flash memory writing used connected to the Flashpro III/Flashpro IV.
• FA-64GB-8EU: 64-pin plastic LQFP (GB-8EU type)
• FA-64GC-8BS-A: 64-pin plastic LQFP (GC-8BS type)
FA-73F1-CN3-A
• FA-64GK-9ET:
64-pin plastic TQFP (GK-9ET type)
• FA-73F1-CN3-A: 73-pin plastic FBGA (F1-CN3 type)
77
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(4) Debugging Tools
• When using in-circuit emulator IE-78K0-NS
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
IE-78K0-NS-PA
IE-70000-98-IF-C
IE-70000-CD-IF-A
IE-70000-PC-IF-C
IE-70000-PCI-IF-A
IE-780034-NS-EM1
NP-64GC
Power supply unit for IE-78K0-NS
Performance board to enhance and expand the functions of IE-78K0-NS
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
PC card and interface cable when using notebook PC as host machine (PCMCIA socket supported)
TM
Adapter required when using IBM PC/AT
or compatible as host machine (ISA bus supported)
Adapter required when using PC in which PCI bus is incorporated as host machine
Emulation board to emulate µPD780034A, 780034AY Subseries
Emulation probe for 64-pin plastic LQFP (GC-8BS type)
NP-64GC-TQ
NP-H64GC-TQ
NP-64GK
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
NP-H64GK-TQ
NP-H64GB-TQ
Emulation probe for 64-pin plastic LQFP (GB-8EU type)
Emulation probe for 73-pin plastic FBGA (F1-CN3 type)
Note
NP-73F1-CN3
EV-9200GC-64
TGC-064SAP
TGK-064SBW
TGB-064SDP
Conversion socket to connect the NP64GC and a target system board on which a 64-pin plastic LQFP
(GC-8BS type) can be mounted.
Conversion adapter to connect the NP-64GC-TQ or NP-H64GC-TQ and a target system board on
which a 64-pin plastic LQFP (GC-8BS type) can be mounted
Conversion adapter to connect the NP-64GK or NP-H64GK-TQ and a target system on which a 64-
pin plastic TQFP (GK-9ET type) can be mounted
Conversion socket to connect the NP-H64GB-TQ and a target system board on which a 64-pin
plastic LQFP (GB-8EU type) can be mounted
CSICE73A0909N01,
LSPACK73A0909N01,
CSSOCKET73A0909N01
ID78K0-NS
Conversion socket to connect the NP-73F1-CN3 and a target system board on which a 73-pin plastic
FBGA (F1-CN3 type) can be mounted
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
Device file for µPD780034A, 780034AY Subseries
DF780034
Note The conversion socket (CSICE73A0909N01, LSPACK73A0909N01, or CSSOCKET73A0909N01) is supplied
with the emulation probe (NP-73F1-CN3).
78
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
• When using in-circuit emulator IE-78001-R-A
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
IE-70000-PC-IF-C
IE-70000-PCI-IF-A
IE-780034-NS-EM1
IE-78K0-R-EX1
EP-78240GC-R
EP-78012GK-R
EV-9200GC-64
Adapter required when using PC-9800 series as host machine (excluding notebook PCs) (C bus supported)
Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus supported)
Adapter required when using PC in which PCI bus is incorporated as host machine
Emulation board to emulate µPD780034A, 780034AY Subseries
Emulation probe conversion board necessary when using IE-780034-NS-EM1 on IE-78001-R-A
Emulation probe for 64-pin plastic LQFP (GC-8BS type)
Emulation probe for 64-pin plastic TQFP (GK-9ET type)
Conversion socket to connect the EP-78240GC-R and a target system board on which a 64-pin
plastic LQFP (GC-8BS type) can be mounted
TGK-064SBW
Conversion adapter to connectthe EP-78012GK-R and a target system board on which a 64-pin plastic
TQFP (GK-9ET type) can be mounted
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
DF780034
System simulator common to 78K/0 Series
Device file for µPD780034A, 780034AY Subseries
(5) Real-Time OS
RX78K0
Real-time OS for 78K/0 Series
Caution The 64-pin plastic LQFP (GB-8EU type) and 73-pin plastic FBGA (F1-CN3 type) do not support
the IE-78001-R-A.
79
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
(6) Cautions on Using Development Tools
• The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780034.
• The CC78K0 and RX78K0 are used in combination with the RA78K0 and the DF780034.
• FL-PR3, FL-PR4, FA-64GC-8BS-A, FA-64GB-8EU, FA-64GK-9ET, FA-73F1-CN3-A, NP-64GC, NP-64GC-
TQ, NP-H64GC-TQ, NP-64GK, NP-H64GK-TQ, NP-H64GB-TQ, and NP-73F1-CN3 are products made by
Naito Densei Machida Mfg. Co., Ltd. (+81-45-475-4191).
• TGC-064SAP, TGK-064SBW, TGB-064SDP, CSICE73A0909N01, LSPACK73A0909N01, and
CSSOCKET73A0909N01 are products made by TOKYO ELETECH CORPORATION.
Contact: Daimaru Kogyo, Ltd.
Tokyo Electronic Division (+81-3-3820-7112)
Osaka Electronic Division (+81-6-6244-6672)
• For third-party development tools, see the Single-chip Microcontroller Development Tool Selection Guide
(U11069E).
• The host machines and OSs supporting each software are as follows.
Host Machine
[OS]
PC
EWS
PC-9800 series [Japanese WindowsTM
IBM PC/AT and compatibles
]
HP9000 series 700TM [HP-UXTM
]
SPARCstationTM [SunOSTM, SolarisTM
]
Software
RA78K0
CC78K0
ID78K0-NS
ID78K0
[Japanese/English Windows]
Note
√
√
√
Note
√
√
√
√
–
–
–
√
SM78K0
RX78K0
Note
√
Note DOS-based software
80
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Socket Drawing (EV-9200GC-64) and Footprints
Figure A-1. EV-9200GC-64 Drawing (For Reference Only)
A
B
M
N
E
O
F
EV-9200GC-64
1
P
No.1 pin index
G
H
I
EV-9200GC-64-G0
ITEM
A
MILLIMETERS
18.8
14.1
14.1
18.8
4-C 3.0
0.8
INCHES
0.74
B
0.555
0.555
0.74
C
D
E
4-C 0.118
0.031
0.236
0.622
0.728
0.236
0.622
0.728
0.315
0.307
0.098
0.079
F
G
H
I
6.0
15.8
18.5
6.0
J
K
15.8
18.5
8.0
L
M
N
O
P
7.8
2.5
2.0
Q
R
S
1.35
0.053
+0.004
–0.005
±
0.35 0.1
0.014
2.3
1.5
0.091
0.059
T
81
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Figure A-2. EV-9200GC-64 Footprints (For Reference Only)
G
J
K
L
C
B
A
EV-9200GC-64-P1E
ITEM
MILLIMETERS
INCHES
0.768
A
B
C
D
E
F
G
H
I
19.5
14.8
±
0.583
0.8 0.02 × 15=12.0 0.05 0.031+0.002
–0.001 × 0.591=0.472
–0.002
+0.003
±
0.8 0.02 × 15=12.0 0.05 0.031+0.002
–0.001 × 0.591=0.472
–0.002
+0.003
±
±
14.8
19.5
0.583
0.768
0.236
0.236
0.197
+0.004
±
6.00 0.08
–0.003
+0.004
–0.003
±
6.00 0.08
+0.001
–0.002
±
0.5 0.02
+0.001
±
J
2.36 0.03
0.093
0.087
0.062
–0.002
+0.004
–0.005
±
2.2 0.1
K
L
+0.001
–0.002
±
1.57 0.03
DimensionsofmountpadforEV-9200andthatfortargetdevice
(QFP)maybedifferentinsomeparts.Fortherecommended
mountpaddimensionsforQFP,referto"SEMICONDUCTOR
DEVICE MOUNTING TECHNOLOGY MANUAL"
(C10535E).
Caution
82
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Adapter Drawing (TGC-064SAP)
Figure A-3. TGC-064SAP Drawing (For Reference Only)
A
B
I
J
K
C
S
Protrusion height
T
D
E F G H
Q R
M
N
L
O
P
V
W
d
U
j
i
X
Z
c
b
a
Y
ITEM MILLIMETERS
INCHES
0.556
ITEM MILLIMETERS
INCHES
0.073
A
B
C
D
E
F
14.12
0.8x15=12.0
0.8
a
b
c
d
e
f
1.85
3.5
0.031x0.591=0.472
0.031
0.138
0.079
2.0
e g
f
h
0.813
6.0
0.236
20.65
10.0
0.394
0.25
13.6
1.2
0.010
12.4
0.488
0.535
G
H
I
14.8
0.583
g
h
i
0.047
17.2
0.677
1.2
0.047
C 2.0
9.05
C 0.079
0.356
2.4
0.094
j
2.7
0.106
J
K
L
5.0
0.197
TGC-064SAP-G0E
13.35
1.325
1.325
16.0
0.526
M
N
O
P
Q
R
S
T
0.052
0.052
0.630
20.65
12.5
0.813
0.492
17.5
0.689
4-
φ
1.3
4-φ0.051
1.8
0.071
U
V
W
X
Y
Z
φ
φ
φ
3.55
0.9
φ
φ
φ
0.140
0.035
0.012
0.3
(19.65)
7.35
(0.667)
0.289
0.047
1.2
note: Product by TOKYO ELETECH CORPORATION.
83
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Conversion Adapter Drawing (TGK-064SBW)
Figure A-4. TGK-064SBW Drawing (For Reference Only) (Unit: mm)
A
L
B
K
X
C
M
S
V
Q
G F E D
H I
J
W
R
N
O
P
a
Z
e
Y
k
j
h
d
i
c
b
g
f
ITEM MILLIMETERS
INCHES
0.724
ITEM MILLIMETERS
INCHES
φ
φ
0.012
A
B
C
D
E
F
18.4
a
b
c
d
e
f
0.3
0.65x15=9.75
0.65
0.026x0.591=0.384
0.026
1.85
3.5
0.073
0.138
0.079
0.154
0.052
0.052
0.232
0.031
0.094
0.106
0.305
2.0
7.75
10.15
12.55
14.95
0.65x15=9.75
11.85
18.4
0.400
3.9
0.494
1.325
1.325
5.9
G
H
I
0.589
g
h
i
0.026x0.591=0.384
0.467
0.8
J
0.724
j
2.4
k
2.7
K
L
C 2.0
12.45
10.25
7.7
C 0.079
0.490
TGK-064SBW-G1E
M
N
O
P
Q
R
S
T
0.404
0.303
10.02
14.92
11.1
0.394
0.587
0.437
1.45
0.057
1.45
0.057
φ
φ
4- 1.3
4- 0.051
U
V
W
X
Y
Z
1.8
5.0
0.071
0.197
φ
φ
5.3
0.209
4-C 1.0
4-C 0.039
φ
φ
φ
φ
3.55
0.9
0.140
0.035
note: Product by TOKYO ELETECH CORPORATION.
84
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
U14046E
µPD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual
µPD780021A, 780022A, 780023A, 780024A, 780021AY, 780022AY, 780023AY, 780024AY Data Sheet
µPD780021A(A), 780022A(A), 780023A(A), 780024A(A), 780021AY(A), 780022AY(A), 780023AY(A),
780024AY(A) Data Sheet
U14042E
U15131E
µPD780031A, 780032A, 780033A, 780034A, 780031AY, 780032AY, 780033AY, 780034AY Data Sheet
µPD780031A(A), 780032A(A), 780033A(A), 780034A(A), 780031AY(A), 780032AY(A), 780033AY(A),
780034AY(A) Data Sheet
U14044E
U15132E
µPD78F0034A, 78F0034AY Data Sheet
U14040E
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A) Data Sheet
78K/0 Series User’s Manual Instruction
This document
U12326E
Documents Related to Development Software Tools (User’s Manuals)
Document Name
Document No.
U14445E
U14446E
U11789E
U14297E
U14298E
U15373E
RA78K0 Assembler Package
Operation
Language
Structured Assembly Language
Operation
CC78K0 C Compiler
Language
SM78K Series System Simulator Ver. 2.30 or Later
Operation (Windows Based)
External Part User Open Interface Specifications U15802E
ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based)
U15185E
U11537E
U11536E
U14610E
RX78K0 Real-time OS
Fundamentals
Installation
Project Manager Ver. 3.12 or Later (Windows Based)
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
85
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name
Document No.
U13731E
IE-78K0-NS In-Circuit Emulator
IE-78K0-NS-A In-Circuit Emulator
IE-780034-NS-EM1 Emulation Board
IE-78001-R-A In-Circuit Emulator
IE-78K0-R-EX1 In-Circuit Emulator
U14889E
U14642E
U14142E
To be prepared
Documents Related to Flash Memory Writing
Document Name
Document No.
U13502E
PG-FP3 Flash Memory Programmer User’s Manual
PG-FP4 Flash Memory Programmer User’s Manual
U15260E
Other Related Documents
Document Name
Document No.
X13769E
SEMICONDUCTORS SELECTION GUIDE - Products & Packages -
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C10983E
C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
86
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
[MEMO]
87
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Note: Purchase of NEC Electronics I2C components conveys a license under the Philips I2C Patent Rights to
use these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
FIP and IEBus are trademarks of NEC Electronics Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/or
other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
88
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
800-366-9782
Fax: 2886-9022/9044
Fax: 408-588-6130
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
• Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-244 58 45
800-729-9288
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 040-244 45 80
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Fax: 0211-65 03 327
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Fax: 091-504 28 60
Fax: 021-6841-1137
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 02-2719-5951
Fax: 01-30-67 58 99
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
Fax: 6250-3583
J02.11
89
Data Sheet U16369EJ1V0DS
µPD78F0034B, 78F0034BY, 78F0034B(A), 78F0034BY(A)
•
The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号:
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