UPD78011HCWA-XXX [NEC]
8-BIT, MROM, MICROCONTROLLER, PDIP64, 0.750 INCH, SHRINK, PLASTIC, DIP-64;
| 型号： | UPD78011HCWA-XXX |
| 厂家： | 
NEC |
| 描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP64, 0.750 INCH, SHRINK, PLASTIC, DIP-64 时钟 光电二极管 外围集成电路 |
| 文件： | 总66页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
Compared to the µPD78011H, 78012H, 78013H, and 78014H (standard models), the µPD78011H(A), 78012H(A),
78013H(A), and 78014H(A) employ a stricter quality-assurance program. (NEC calls this quality grade “special grade”).
The µPD78011H(A), 78012H(A), 78013H(A), and 78014H(A) are the products in the µPD78014H subseries within the
78K/0 series.
Compared with the older µPD78018F subseries, this subseries reduces the EMI (Electro Magnetic Interface) noise
generated from the microcontroller.
Functions are described in detail in the following User's Manual, which should be read when carring out design
work.
µPD78014H Subseries User's Manual: Planned to publish
78K/0 Series User’s Manual – Instruction: IEU-1372
FEATURES
•
•
Low EMI noise model
Large on-chip ROM & RAM
Item
Program
Data Memory
Memory
(ROM)
Internal High-
Internal
Package
Product Name
Speed RAM
512 bytes
Buffer RAM
µPD78011H(A)
µPD78012H(A)
µPD78013H(A)
µPD78014H(A)
8K bytes
32 bytes
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 14 mm)
16K bytes
24K bytes
32K bytes
1024 bytes
•
•
•
•
•
•
•
External memory expansion space : 64K bytes
Instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs)
I/O ports: 53 (N-ch open-drain : 4)
8-bit resolution A/D converter : 8 channels
Serial interface : 2 channels
Timer : 5 channels
Supply voltage : VDD = 1.8 to 5.5 V
APPLICATION FIELD
Control unit of automotive, gas leak breaker, and safety devices, etc.
The information in this document is subject to change without notice.
Document No. U12174EJ1V0DS00 (1st edition)
Date Published March 1997 N
Printed in Japan
1997
©
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
ORDERING INFORMATION
Part Number
Package
µPD78011HCW(A)-×××
µPD78011HGC(A)-×××-AB8
µPD78012HCW(A)-×××
µPD78012HGC(A)-×××-AB8
µPD78013HCW(A)-×××
µPD78013HGC(A)-×××-AB8
µPD78014HCW(A)-×××
µPD78014HGC(A)-×××-AB8
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 14 mm)
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 14 mm)
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 14 mm)
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14 × 14 mm)
Remark ××× indicates ROM code No.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
2
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
78K/0 Series Expansion
The following shows the 78K/0 Series products development. Subseries name are shown inside frames.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
EMI-noise reduced version of
µ
PD78078
PD78075B
PD78078
µPD78075BY
µPD78078Y
µ
µ
100-pin
100-pin
100-pin
100-pin
80-pin
A timer was added to the PD78054 and external interface was enhanced
µ
µPD78070A
PD780018Note
PD780058
µPD78070AY
PD780018YNote
PD780058YNote
µPD78058FY
µ
ROM-less version of the PD78078
Serial I/O of the
Serial I/O of the
µ
µ
PD78078 was enhanced and the function is limited.
PD78054 was enhanced and EMI-noise was reduced.
µ
µ
µ
µ
EMI-noise reduced version of the PD78054
µ
µPD78058F
PD78054
80-pin
µ
UART and D/A converter were enhanced to the PD78014 and I/O was enhanced
80-pin
PD78054Y
PD780034Y
PD780024Y
µ
µ
µ
µ
PD780034
µ
A/D converter of the
µ
PD780024 was enhanced
64-pin
PD780024
64-pin
64-pin
µ
µ
Serial I/O of the PD78018F was added and EMI-noise was reduced.
µ
EMI-noise reduced version of PD78018F
µ
PD78014H
PD78018F
PD78014
Low-voltage (1.8 V) operation version of the PD78014, with larger selection of ROM and RAM capacities
µ
64-pin
µ
µ
PD78018FY
PD78014Y
µ
µ
µ
µ
µ
An A/D converter and 16-bit timer were added to the PD78002
µ
64-pin
An A/D converter was added to the PD78002
µ
PD780001
64-pin
µPD78002Y
Basic subseries for control
PD78002
PD78083
64-pin
On-chip UART, capable of operating at low voltage (1.8 V)
42/44-pin
Inverter control
µ
A/D converter of the PD780924 was enhanced
64-pin
64-pin
PD780964
µ
On-chip inverter control circuit and UART. EMI-noise was reduced.
PD780924
µ
FIPTM drive
The I/O and FIP C/D of the
The I/O and FIP C/D of the
µ
µ
PD78044F were enhanced, Display output total: 53
PD78044H were enhanced, Display output total: 48
100-pin
100-pin
80-pin
PD780208
PD780228
PD78044H
µ
µ
µ
78K/0
Series
µ
An N-ch open drain I/O was added to the PD78044F, Display output total: 34
Basic subseries for driving FIP, Display output total: 34
80-pin
PD78044F
µ
LCD drive
100-pin
100-pin
100-pin
PD780308
PD78064B
µ
PD780308Y
PD78064Y
µ
µ
The SIO of the µPD78064 was enhanced, and ROM, RAM capacity increased
µ
EMI-noise reduced version of the PD78064
µ
µ
PD78064
Basic subseries for driving LCDs, On-chip UART
IEBusTM supported
µ
An IEBus controller was added to the PD78054
80-pin
64-pin
µPD78098
LV
µPD78P0914
On-chip PWM output, LV digital code decoder, and Hsync counter
Note Under planning
3
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
The following lists the main functional differences between subseries products.
Function
Timer
ROM
8-bit 10-bit 8-bit
A/D A/D D/A
VDD MIN.
Value
External
Serial Interface
I/O
88
Capacity
Expansion
Subseries Name
8-bit 16-bit Watch WDT
Control µPD78075B 32K-40K
4ch 1ch 1ch 1ch 8ch
–
2ch 3ch (UART: 1ch)
1.8 V
µPD78078
48K-60K
–
µPD78070A
61
2.7 V
µPD780018 48K-60K
µPD780058 24K-60K
µPD78058F 48K-60K
–
2ch (time division 3-wire: 1ch) 88
2ch
2ch 3ch (time division UART: 1ch) 68
1.8 V
2.7 V
2.0 V
1.8 V
3ch (UART: 1ch)
69
51
53
µPD78054
16K-60K
µPD780034 8K-32K
µPD780024
–
8ch
–
–
3ch (UART: 1ch,
time division 3-wire: 1ch)
8ch
µPD78014H
2ch
1.8 V
2.7 V
µPD78018F 8K-60K
µPD78014
8K-32K
µPD780001 8K
–
–
1ch
–
1ch
39
53
33
47
–
–
µPD78002
µPD78083
8K-16K
–
8ch
–
1ch (UART: 1ch)
2ch (UART: 2ch)
1.8 V
2.7 V
Inverter µPD780964 8K-32K
3ch Note
–
1ch
8ch
–
–
–
control
µPD780924
8ch
FIP
µPD780208 32K-60K
µPD780228 48K-60K
µPD78044H 32K-48K
µPD78044F 16K-40K
µPD780308 48K-60K
µPD78064B 32K
2ch 1ch 1ch 1ch 8ch
3ch
–
2ch
1ch
74
72
68
2.7 V
4.5 V
2.7 V
–
–
drive
–
–
2ch 1ch 1ch
2ch
LCD
drive
2ch 1ch 1ch 1ch 8ch
–
–
3ch (time division UART: 1ch) 57
2ch (UART: 1ch)
1.8 V
2.0 V
µPD78064
µPD78098
16K-32K
32K-60K
IEBus
2ch 1ch 1ch 1ch 8ch
–
–
2ch 3ch (UART: 1ch)
69
54
2.7 V
4.5 V
supported
LV
µPD78P0914 32K
6ch
–
–
1ch 8ch
–
2ch
Note 10-bit timer: 1 channel
4
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
OVERVIEW OF FUNCTION
Item
µPD78011H(A)
µPD78012H(A)
µPD78013H(A)
µPD78014H(A)
Product Name
ROM
8K bytes
16K bytes
24K bytes
32K bytes
High-speed
512 bytes
1024 bytes
Internal
memory
RAM
Buffer RAM
32 bytes
64K bytes
Memory space
General-purpose registers
Instruction cycle
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip instruction execution time cycle modification function
When main system
clock selected
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (at 10.0 MHz operation)
When subsystem
clock selected
122 µs (at 32.768 kHz operation)
Instruction set
• 16-bit operation
• Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, boolean operation)
• BCD correction, etc.
I/O ports
Total
: 53
: 02
: 47
• CMOS input
• CMOS I/O
• N-channel open-drain I/O
(15 V withstand voltage)
: 04
A/D converter
Serial interface
Timer
• 8-bit resolution × 8 channels
• Operable over a wide power supply voltage range: AVDD = 1.8 to 5.5 V
• 3-wire serial I/O/SBI /2-wire serial I/O mode selectable: 1 channel
• 3-wire serial I/O mode (on-chip max. 32 bytes automatic data transmit/receive function): 1 channel
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter
• Watch timer
: 2 channels
: 1 channel
: 1 channel
• Watchdog timer
Timer output
Clock output
3 (14-bit PWM output × 1)
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock: 10.0 MHz
operation), 32.768 kHz (at subsystem clock: 32.768 kHz operation)
Buzzer output
2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock: 10.0 MHz operation)
Maskable
Vectored
interrupt
sources
Internal : 8, External : 4
Internal : 1
Non-maskable
Software
1
Internal : 1, External : 1
Test input
VDD = 1.8 to 5.5 V
TA = –40 to +85°C
Supply voltage
Operating ambient
temperature
Package
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QFP (14 × 14 mm)
5
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
TABLE OF CONTENTS
1. PIN CONFIGURATION (Top View) ......................................................................................................... 7
2. BLOCK DIAGRAM ................................................................................................................................... 10
3. PIN FUNCTIONS ...................................................................................................................................... 11
3.1 PORT PINS ........................................................................................................................................................ 11
3.2 OTHER PORTS ................................................................................................................................................. 12
3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ................................................ 14
4. MEMORY SPACE .................................................................................................................................... 16
5. PERIPHERAL HARDWARE FUNCTION FEATURES ............................................................................ 17
5.1 PORTS ............................................................................................................................................................... 17
5.2 CLOCK GENERATOR....................................................................................................................................... 18
5.3 TIMER/EVENT COUNTER ................................................................................................................................ 19
5.4 CLOCK OUTPUT CONTROL CIRCUIT ............................................................................................................ 21
5.5 BUZZER OUTPUT CONTROL CIRCUIT........................................................................................................... 21
5.6 A/D CONVERTER.............................................................................................................................................. 22
5.7 SERIAL INTERFACES ...................................................................................................................................... 23
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS.............................................................................. 25
6.1 INTERRUPT FUNCTIONS................................................................................................................................. 25
6.2 TEST FUNCTIONS ............................................................................................................................................ 28
7. EXTERNAL DEVICE EXPANSION FUNCTIONS ................................................................................... 29
8. STANDBY FUNCTIONS........................................................................................................................... 29
9. RESET FUNCTIONS ................................................................................................................................ 29
10. INSTRUCTION SET ................................................................................................................................. 30
11. ELECTRICAL SPECIFICATIONS ............................................................................................................ 33
12. PACKAGE DRAWINGS ........................................................................................................................... 57
13. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 59
APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 60
APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 62
6
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
1. PIN CONFIGURATION (Top View)
• 64-Pin Plastic Shrink DIP (750 mil)
µPD78011HCW(A)-×××, 78012HCW(A)-×××, 78013HCW(A)-×××, 78014HCW(A)-×××
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
P31/TO1
P32/TO2
P33/TI1
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVREF
2
AVDD
3
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVSS
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P04/XT1
XT2
P34/TI2
P35/PCL
P36/BUZ
P37
IC
X1
X2
V
SS
V
DD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0/TI0
RESET
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P63
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P62
P61
P60
P57/A15
P56/A14
V
SS
Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly.
2. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an applica-
tion where the noise generated from the microcontroller must be reduced, connect the AVDD pin
to a power supply of the same voltage as VDD.
3. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an
application where the noise generated from the microcontroller must be reduced, connect AVSS
pin to a ground line separate from VSS.
7
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
• 64-Pin Plastic QFP (14 × 14 mm)
µPD78011HGC(A)-×××-AB8, 78012HGC(A)-×××-AB8, 78013HGC(A)-×××-AB8, 78014HGC(A)-×××-AB8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P11/ANI1
P10/ANI0
AVSS
2
3
4
P04/XT1
XT2
5
6
IC
7
X1
8
X2
V
SS
9
VDD
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
10
11
12
13
14
15
16
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0/TI0
RESET
P67/ASTB
P66/WAIT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Cautions 1. Always connect the IC (Internally Connected) pin to VSS directly.
2. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an applica-
tion where the noise generated from the microcontroller must be reduced, connect the AVDD pin
to a power supply of the same voltage as VDD.
3. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an
application where the noise generated from the microcontroller must be reduced, connect AVSS
pin to a ground line separate from VSS.
8
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
A8-A15
AD0-AD7
ANI0-ANI7
ASTB
: Address Bus
: Address/Data Bus
: Analog Input
: Address Strobe
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
: Busy
P60-P67
PCL
: Port 6
: Programmable Clock
: Read Strobe
: Reset
RD
RESET
SB0, SB1
SCK0, SCK1
SI0, SI1
SO0, SO1
STB
AVDD
: Serial Bus
AVREF
: Serial Clock
: Serial Input
AVSS
BUSY
: Serial Output
: Strobe
BUZ
: Buzzer Clock
: Internally Connected
: Interrupt from Peripherals
: Port 0
IC
TI0-TI2
TO0-TO2
VDD
: Timer Input
INTP0-INTP3
P00-P04
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
: Timer Output
: Power Supply
: Ground
: Port 1
VSS
: Port 2
WAIT
: Wait
: Port 3
WR
: Write Strobe
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
: Port 4
X1, X2
XT1, XT2
: Port 5
9
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
2. BLOCK DIAGRAM
TO0/P30
P00
16-bit TIMER/
EVENT COUNTER
PORT0
TI0/INTP0/P00
P01-P03
P04
TO1/P31
TI1/P33
8-bit TIMER/
EVENT COUNTER 1
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
78K/0
CPU CORE
ROM
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SERIAL
INTERFACE 0
SI1/P20
SO1/P21
SCK1/P22
STB/P23
AD0/P40-
AD7/P47
SERIAL
INTERFACE 1
A8/P50-
A15/P57
BUSY/P24
EXTERNAL
ACCESS
RAM
RD/P64
ANI0/P10-
ANI7/P17
WR/P65
WAIT/P66
ASTB/P67
A/D CONVERTER
AVREF
RESET
X1
INTP0/P00-
INTP3/P03
INTERRUPT
CONTROL
SYSTEM
CONTROL
X2
XT1
XT2
BUZZER OUTPUT
BUZ/P36
PCL/P35
CLOCK OUTPUT
CONTROL
V
DD
VSS AVDD AVSS IC
Remark Internal ROM & RAM capacity varies depending on the product.
10
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Dual-
Pin Name
P00
I/O
Function
On Reset
Input
Function Pin
Port 0
Input
INTP0/TI0
Input only
5-bit I/O port
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up
resistor can be used by software.
Input
Input/
P01
P02
P03
P04
INTP1
output
INTP2
INTP3
Note 1
Input
Input only
Input
Input
XT1
Port 1
Input/
P10 to P17
ANI0 to ANI7
8-bit input/output port.
output
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
Note 2
by software.
Input
Input/
P20
Port 2
SI1
output
8-bit input/output port.
P21
SO1
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used
by software.
P22
SCK1
STB
P23
P24
BUSY
SI0/SB0
SO0/SB1
SCK0
TO0
P25
P26
P27
Input
Input/
Port 3
P30
output
8-bit input/output port.
P31
TO1
Input/output can be specified in 1-bit units.
When used as an input port, on-chip pull-up resistor can be used
by software.
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
Input/
P40 to P47
Port 4
Input
AD0 to AD7
output
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, on-chip pull-up resistor can be used
by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Notes 1. When using the P04/XT1 pin as an input port pin, set bit 6 (FRC) of the processor clock control register
(PCC) to 1 (do not use the internal feedback resistor of the subsystem clock oscillation circuit).
2. When using the P10/ANI0 through P17/ANI7 pins as the analog input pins of the A/D converter, the internal
pull-up resistors are automatically not used.
11
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
3.1 PORT PINS (2/2)
Dual-
Pin Name
I/O
Function
On Reset
Input
Function Pin
Port 5
P50 to P57
Input/
A8 to A15
8-bit input/output port.
LED can be driven directly.
output
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by
software.
P60
P61
P62
P63
P64
P65
P66
P67
Input
Input/
Port 6
N-ch open-drain input/output port.
output
8-bit input/output port.
On-chip pull-up resistor can be
Input/output can be specified
specified by mask option.
bit-wise.
LED can be driven directly.
RD
When used as an input port, on-chip
pull-up resistor can be used by soft-
ware.
WR
WAIT
ASTB
Caution Do not manipulate the pins multiplexed with a port pin as follows during A/D conversion; otherwise,
the rated total error during A/D conversion may not be satisfied.
<1> Rewriting the contents of the output latch when the pin is used as an output port pin.
<2> Changing the output level of the pin used as an output pin even when the pin is not used as a
port pin.
3.2 OTHER PORTS (1/2)
Dual-
Pin Name
INTP0
I/O
Function
On Reset
Input
Function Pin
P00/TI0
P01
Input
External interrupt request input by which the effective edge (rising
edge, falling edge, or both rising edge and falling edge) can be
specified.
INTP1
INTP2
INTP3
SI0
P02
P03
Falling edge detection external interrupt request input.
Serial interface serial data input.
Input
Input
Input
Input
Input
P25/SB0
P20
SI1
SO0
P26/SB1
P21
Output
Serial interface serial data output.
SO1
SB0
Input
Serial interface serial data input/output.
Serial interface serial clock input/output.
P25/SI0
P26/SO0
P27
/output
SB1
Input
SCK0
SCK1
STB
/output
P22
Serial interface automatic transmit/receive strobe output.
Serial interface automatic transmit/receive busy input.
Input
Input
Output
Input
P23
BUSY
P24
12
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
3.2 OTHER PORTS (2/2)
Dual-
Function Pin
On Reset
Input
Pin Name
TI0
I/O
Function
External count clock input to 16-bit timer (TM0).
External count clock input to 8-bit timer (TM1).
External count clock input to 8-bit timer (TM2).
Input
P00/INTP0
P33
TI1
TI2
P34
Output
16-bit timer (TM0) output (multiplexed with 14-bit PWM output).
8-bit timer (TM1) output.
Input
TO0
P30
TO1
P31
8-bit timer (TM2) output.
TO2
P32
Input
Input
PCL
Clock output (for main system clock, subsystem clock trimming).
Buzzer output.
Output
Output
P35
BUZ
P36
Input
AD0 to AD7
Low-order address/data bus at external memory expansion.
P40 to P47
Input
/output
Input
Input
A8 to A15
RD
High-order address bus at external memory expansion.
External memory read operation strobe signal output.
External memory write operation strobe signal output.
Wait insertion at external memory access.
Output
Output
P50 to P57
P64
WR
P65
Input
Input
WAIT
ASTB
Input
P66
Strobe output which latches the address information output at port 4 and
port 5 to access external memory.
Output
P67
ANI0 to ANI7
AVREF
AVDD
AVSS
RESET
X1
A/D converter analog input.
Input
—
P10 to P17
Input
Input
—
A/D converter reference voltage input.
—
—
—
—
—
—
P04
—
—
—
—
—
A/D converter analog power supply (multiplexed with a port power pin).
A/D converter ground potential (multiplexed with a port ground pin).
System reset input.
—
—
—
—
—
Input
Input
—
Main system clock oscillation crystal connection.
X2
XT1
Subsystem clock oscillation crystal connection.
Input
—
Input
—
XT2
VDD
Positive power supply (except port pins).
Ground potential (except port pins).
—
—
—
—
VSS
—
IC
Internal connection. Connected to VSS directly.
—
Cautions 1. The AVDD pin is multiplexed with an A/D converter power pin and a port power pin. In an applica-
tion where the noise generated from the microcontroller must be reduced, connect the AVDD pin
to a power supply of the same voltage as VDD.
2. The AVSS pin is multiplexed with an A/D converter ground pin and a port ground pin. In an
application where the noise generated from the microcontroller must be reduced, connect AVSS
pin to a ground line separate from VSS.
13
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
3.3 PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin
Input/output
Circuit Type
Pin Name
I/O
Recommended Connection when Not Used
P00/INTP0/TI0
P01/INTP1
P02/INTP2
P03/INTP3
P04/XT1
2
Input
Connected to VSS .
8-D
Input/output
Individually connected to VSS via resistor.
16
Input
Connected to VDD or VSS.
P10/ANI0 to P17/ANI7
P20/SI1
11-C
8-D
5-J
Input/output
Individually connected to VDD or VSS via resisitor.
P21/SO1
P22/SCK1
P23/STB
8-D
5-J
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
8-D
10-C
5-J
P31/TO1
P32/TO2
P33/TI1
8-D
5-J
P34/TI2
P35/PCL
P36/BUZ
P37
P40/AD0 to P47/AD7
P50/A8 to P57/A15
P60 to P63
P64/RD
5-O
5-J
Individually connected to VDD via resistor.
Individually connected to VDD or VSS via resistor.
Individually connected to VDD via resistor.
Individually connected to VDD or VSS via resistor.
13-I
5-J
P65/WR
P66/WAIT
P67/ASTB
RESET
2
Input
—
—
XT2
16
—
Leave open.
AVREF
Connected to VSS .
Connected to VDD .
Connected to VSS .
Connected to VSS directly.
AVDD
AVSS
IC
14
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 3-1. Pin Input/Output Circuits
Type 2
Type 10-C
pullup
AVDD
P-ch
enable
IN
AVDD
P-ch
data
IN / OUT
open drain
output disable
N-ch
AVSS
Schmitt-Triggered Input with Hysteresis Characteristic
Type 5-J
Type 11-C
AVDD
AVDD
P-ch
pullup
enable
pullup
enable
P-ch
AVDD
data
P-ch
AVDD
P-ch
IN / OUT
data
N-ch
output
disable
Comparator
P-ch
N-ch
IN / OUT
AVSS
+
output
disable
N-ch
AVSS
–
AVSS
REF (Threshold Voltage)
V
input
enable
input
enable
Type 5-O
Type 13-I
AVDD
AVDD
Mask
Option
pullup
enable
IN / OUT
P-ch
data
AVDD
P-ch
N-ch
AVSS
output disable
data
AVDD
IN / OUT
output
disable
RD
P-ch
N-ch
AVSS
Middle-High Voltage Input Buffer
Type 8-D
Type 16
AVDD
feedback
cut-off
pullup
enable
P-ch
P-ch
AVDD
P-ch
data
IN / OUT
output
disable
N-ch
AVSS
XT1
XT2
15
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
4. MEMORY SPACE
The memory map of the µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) is shown in Figure 4-1.
Figure 4-1. Memory Map
FFFFH
Special Function Registers
(SFR) 256 × 8 Bits
FF00H
FEFFH
General-Purpose Registers
32 × 8 Bits
FEE0H
FEDFH
Internal High-Speed RAMNote
mmmmH
nnnnH
mmmmH–1
Use Prohibited
Program Area
CALLF Entry Area
Program Area
FAE0H
FADFH
Data
1000H
0FFFH
Buffer RAM 32 × 8 Bits
Memory
Space
FAC0H
FABFH
Use Prohibited
0800H
07FFH
FA80H
FA7FH
Program
Memory
Space
0080H
007FH
External Memory
nnnnH+1
nnnnH
CALLT Table Area
Vector Table Area
0040H
003FH
Internal ROMNote
0000H
0000H
Note Internal ROM and internal high-speed RAM capacities vary depending on the product (see the table below).
Internal High-Speed RAM
Intenal ROM End Address
Start Address
mmmmH
Product Name
nnnnH
FD00H
µPD78011H(A)
µPD78012H(A)
µPD78013H(A)
µPD78014H(A)
1FFFH
3FFFH
5FFFH
7FFFH
FB00H
16
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 PORTS
The I/O port has the following three types
• CMOS input (P00, P04)
:
2
• CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67)
• N-ch open-drain input/output(15V withstand voltage) (P60 to P63)
: 47
:
4
Total
: 53
Table 5-1. Functions of Ports
Port Name
Port 0
Pin Name
Function
P00, P04
Dedicated Input port
P01 to P03
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
Input/output ports. Input/output can be specified in 8-bit units.
When used as an input port, pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
LED can be driven directly.
Port 1
Port 2
Port 3
Port 4
P10 to P17
P20 to P27
P30 to P37
P40 to P47
Port 5
Port 6
P50 to P57
P60 to P63
P64 to P67
N-ch open-drain input/output port. Input/output can be specified bit-wise.
On-chip pull-up resistor can be specified by mask option.
LED can be driven directly.
Input/output ports. Input/output can be specified bit-wise.
When used as an input port, pull-up resistor can be used by software.
17
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
5.2 CLOCK GENERATOR
There are two types of clock generator: main system clock and subsystem clock.
The instruction exection time can be changed.
• 0.4µs/0.8µs/1.6µs/3.2µs/6.4µs (Main system clock: at 10.0 MHz operation)
• 122µs (Subsystem clock: at 32.768 KHz operation)
Figure 5-1. Clock Generator Block Diagram
Watch Timer
Clock Output
Function
XT1/P04
Subsystem
Clock
Osicillator
fXT
XT2
Prescaler
Main
X1
X2
fX
Clock to
Peripheral
Hardware
System
Clock
Prescaler
Osicillator
fX
fX
fX
fX
2
22
23
24
STOP
Wait
Control
Circuit
Standby
Control
Circuit
CPU Clock
(fCPU)
Selector
INTP0
Sampling Clock
18
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
5.3 TIMER/EVENT COUNTER
The following five channels are incorporated in the timer/event counter.
• 16-bit timer/event counter
• 8-bit timer/event counter
• Watch timer
: 1 channel
: 2 channels
: 1 channel
: 1 channel
• Watchdog timer
Table 5-2. Types and Functions of Timer/Event Counter
8-bit Timer/Event
Counter
16-bit Timer/Event
Counter
Watch Timer
Watchdog Timer
Type
Interval timer
1 channel
1 channel
1 output
1 output
1 input
1 output
2
2 channels
1 channel
1 channel
Externanal event counter
Timer output
2 channels
–
–
–
–
–
1
1
–
–
–
–
–
1
–
Functions
2 outputs
PWM output
–
Pulse width mesurement
Sqare wave output
Interrupt request
Test input
–
2 outputs
2
–
–
Figure 5-2. 16-bit Timer/Enent Counter Block Diagram
Internal Bus
16-Bit Compare
Register (CR00)
INTTM0
PWM
Pulse
Output
Control
Circuit
Output
Control
Circuit
Match
TO0/P30
fX/2
fX/22
fX/23
16-Bit Timer
Register (TM0)
Selector
Edge
Detection
Circuit
Selector
Clear
TI0/INTP0/P00
INTP0
16-Bit Capture
Register (CR01)
Internal Bus
19
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 5-3. 8-bit Timer/Enent Counter Block Diagram
Internal Bus
INTIM1
8-Bit Compare
Register (CR10)
8-Bit Compare
Register (CR20)
Output
Control
Circuit
TO2/P32
INTTM2
Selector
Match
fX/22–fX/210
8-Bit Timer
Register 1 (TM1)
Selector
Selector
fX/212
8-Bit Timer
Register 2 (TM2)
Selector
TI1/P33
Clear
Clear
fX/22–fX/210
Selector
fX/212
TI2/P34
Output
Control
Circuit
TO1/P31
Internal Bus
Figure 5-4. Watch Timer Block Diagram
fW
214
Selector
5-Bit Counter
fX/28
fXT
fW
Selector
INTWT
Prescaler
Selector
fW
213
fW
24
fW
25
fW
fW
27
fW
28
fW
29
26
Selector
INTTM3
20
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 5-5. Watchdog Timer Block Diagram
fX
24
Prescaler
fX
26
fX
27
fX
28
fX
29
fX
210
fX
212
fX
25
INTWDT
Maskable
Interrupt Request
Control
Circuit
Selector
RESET
8-Bit Counter
INTWDT
Non-Maskable
Interrupt Request
5.4 CLOCK OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for clock output.
• 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation)
• 32.768 kHz (Subsystem clock: at 32.768 kHz operation)
Figure 5-6. Clock Output Control Block Diagram
fX/23
fX/24
fX/25
Synchronization
Circuit
Output Control
Circuit
fX/26
PCL/P35
Selector
fX/27
fX/28
fXT
5.5 BUZZER OUTPUT CONTROL CIRCUIT
The clock with the following frequencies can be output for buzzer output.
• 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation)
Figure 5-7. Buzzer Output Control Block Diagram
fX/210
fX/211
fX/212
Output Control
Circuit
BUZ/P36
Selector
21
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
5.6 A/D CONVERTER
The A/D converter has on-chip eight 8-bit resolution channels.
There are the following two method to start A/D conversion.
• Hardware starting
• Software starting
Figure 5-8. A/D Converter Block Diagram
Series Resistor String
AVDD
Sample & Hold Circuit
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
AVREF
Voltage Comparator
Tap
Selector
Selector
Succesive Approximation
Register (SAR)
AVSS
Falling
Edge
Detector
Control
Circuit
INTAD
INTP3
INTP3/P03
A/D Conversion
Result Register (ADCR)
Internal Bus
Caution Do not manipulate the pins multiplexed with a port pin (refer to 3.1 PORT PINS) during A/D conversion;
otherwise, the rated total error during A/D conversion may not be satisfied.
<1> Rewriting the contents of the output latch when the pin is used as an output port pin.
<2> Changing the output level of the pin used as an output pin even when the pin is not used as a port
pin.
22
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
5.7 SERIAL INTERFACES
There are two on-chip clocked serial interfaces as follows.
• Serial Interface channel 0
• Serial Interface channel 1
Table 5-3. Type and Function of Serial Interface
Function
3-wire serial I/O mode
Serial Interface Channel 0
Serial Interface Channel 1
O (MSB/LSB-first switchable)
O (MSB/LSB-first switchable)
3-wire serial I/O mode with automatic data transmit/
receive function
–
O (MSB/LSB-first switchable)
SBI (Serial Bus Interface) mode
2-wire serial I/O mode
O (MSB-first)
O (MSB-first)
–
–
Figure 5-9. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25
SO0/SB1/P26
Output
Latch
Serial I/O Shift
Register 0 (SIO0)
Selector
Selector
Busy/Acknowledge
Output Circuit
Bus Release/Command/
Acknowledge Detection
Circuit
Interrupt
Request
Signal
INTCSI0
SCK0/P27
Serial Clock Counter
Generator
fx/22–fx/29
TO2
Serial Clock
Control Circuit
Selector
23
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 5-10. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data Transmit/
Receive Address Pointer
(ADTP)
Buffer RAM
Serial I/O Shift Register 1 (SIO1)
SI1/P20
SO1/P21
STB/P23
Handshake
Control
Circuit
BUSY/P24
Interrupt Request
Signal Generator
INTCSI1
Serial Clock Counter
SCK1/P22
fX/22 – fX/29
TO2
Selector
Serial Clock Control Circuit
24
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS
There are the 14 interrupt sources of 3 different kind as shown below.
• Non-maskable
• Maskable
:
1
: 12
• Software
:
1
Table 6-1. Interrupt Source List
Interrupt Source
Default
Internal/
External
Vector Table
Address
Basic
Note 1
Interrupt Type
Non-maskable
Maskable
Priority
Configuratin
Name
Trigger
Note 2
Type
–––
0
INTWDT Watchdog timer overflow (with watchdog
timer mode 1 selected)
Internal
0004H
(A)
(B)
INTWDT Watchdog timer overflow (with interval
timer mode selected)
1
2
3
4
5
6
7
INTP0
INTP1
INTP2
INTP3
Pin input edge detection
External
0006H
0008H
000AH
000CH
000EH
0010H
0012H
(C)
(D)
INTCSI0 Serial interface channel 0 transfer end
INTCSI1 Serial interface channel 1 transfer end
Internal
(B)
INTTM3 Reference time interval signal from
watch timer
8
9
INTTM0 16 bit timer/event counter match signal
generation
0014H
0016H
0018H
INTTM1 8-bit timer/event counter 1 match signal
generation
10
INTTM2 8-bit timer/event counter 2 match signal
generation
11
INTAD
BRK
A/D converter conversion end
BRK instruction execution
001AH
003EH
Software
–––
–
(E)
Notes 1. The default pririty is the priority applicable when more than one maskable interrupt is generated. 0 is the highest
priority and 11, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) on the next page.
25
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Figure 6-1. Basic Interrupt Function Configuration (1/2)
(A) Internal Non-Maskable Interrupt
Internal Bus
Vector Table
Address
Generator
Interrupt
Request
Priority Control
Circuit
Standby Release
Signal
(B) Internal Maskable Interrupt
Internal Bus
PR
ISP
MK
IE
Vector Table
Priority Control
Circuit
Address
Interrupt
Request
IF
Generator
Standby Release
Signal
(C) External Maskable Interrupt (INTP0)
Internal Bus
MK
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
PR
ISP
IE
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
Sampling
Clock
IF
Standby Release
Signal
26
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
Figure 6-1. Basic Interrupt Function Configuration (2/2)
(D) External Maskable Interrupt (Except INTP0)
Internal Bus
MK
External Interrupt
Mode Register
(INTM0)
PR
ISP
IE
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
Edge
Detector
IF
Standby Release
Signal
(E) Software Interrupt
Internal Bus
Vector Table
Address
Generator
Priority Control
Circuit
Interrupt
Request
IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority spcification flag
27
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
6.2 TEST FUNCTIONS
There are two test functions as shown in Table 6-2.
Table 6-2. Test Source List
Test Source
Trigger
Internal/External
Name
INTWT
INTPT4
Watch timer overflow
Internal
External
Port 4 falling edge detection
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Standby Release
Signal
Test
Input
IF
IF : Test input flag
MK : Test mask flag
28
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion function is used to connect external devices to areas other than the internal ROM, RAM
and SFR.
Ports 4 to 6 are used for connection with external devices.
8. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current dissipation.
• HALT mode
: The CPU operating clock is stopped. The average consumption current can be reduced by intermittent
operation in combination with the normal operat ing mode.
• STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock
is stopped, so that the system operates withultra-low power consumption using only the subsystem
clock.
Figure 8-1. Standby Functions
CSS=1
Main System
Clock Operation
Subsystem Clock
OperationNote
CSS=0
HALT
Instruction
STOP
Instruction
HALT
Instruction
Interrupt
Request
Interrupt
Request
Interrupt
Request
STOP Mode
(Main system clock
oscillation stopped)
HALT Mode
(Clock supply to CPU is
stopped, oscillation)
HALT ModeNote
(Clock supply to CPU is
stopped, oscillation)
Note The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the
subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used.
Caution When the main system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be switched again to the main system clock after the oscillation stabilization
time is secured by the program by the program.
9. RESET FUNCTIONS
There are the following two reset methods.
• External reset input by RESET pin.
• Internal reset by watchdog timer runaway time detection.
29
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
10. INSTRUCTION SET
(1) 8-Bit Instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL,
RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand
[HL+byte]
Note
#byte
A
r
sfr
saddr !addr16 PSW
[DE]
[HL]
[HL+B] $adder16
[HL+C]
1
None
1st Operand
A
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
ROL
RORC
ROLC
ADDC ADDC
SUB SUB
SUBC SUBC
ADDC ADDC
SUB SUB
SUBC SUBC
XOR
CMP
AND
OR
AND
OR
AND
OR
AND
OR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
r1
DBNZ
DBNZ
sfr
MOV MOV
sadder
MOV MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!adder16
PSW
MOV
MOV MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL+byte]
[HL+B]
MOV
[HL+C]
X
C
MULU
DIVUW
Note Except r=A
30
µPD78011H(A), 78012H(A), 78013FH(A), 78014H(A)
(2) 16-Bit Instruction
MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#byte
AX
rp Note
saddrp
MOVW
!addr16
MOVW
SP
None
MOVW
AX
rp
ADDW
MOVW
XCHW
MOVW
SUBW
CMPW
MOVW
MOVWNote
INCW, DECW
PUSH, POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp=BC, DE, HL.
(3) Bit Manipulation Instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand
1st Operand
A.bit
A.bit
sfr.bit
saddr.bit
PWS.bit
[HL].bit
CY
$addr16
BT
None
MOV1
SET1
CLR1
BF
BTCLR
sfr.bit
MOV1
MOV1
MOV1
MOV1
BT
SET1
CLR1
BF
BTCLR
saddr.bit
PSW.bit
[HL].bit
CY
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
MOV1
AND1
OR1
MOV1
MOV1
MOV1
MOV1
SET1
CLR1
NOT1
AND1
OR1
AND1
OR1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
31
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(4) Call Instruction/Branch Instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
2nd Operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
1st Operand
Basic instruction
BR
CALL, BR
BR, BC, BNC,
BZ, BNZ
Compound instruction
BT, BF, BTCLR,
DBNZ
(5) Other Instruction
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
32
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Symbol
Test Conditions
Rating
Unit
Supply voltage
VDD
AVDD
AVREF
AVSS
–0.3 to + 7.0
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to + 0.3
V
V
V
V
Input voltage
P00 to P04, P10 to P17, P20 to P27, P30 to P37
P40 toP47, P50 to P57, P64 to P67, X1, X2, XT2
VI1
–0.3 to VDD + 0.3
V
VI2
VO
P60 to P67
Open-drain
–0.3 to +16
V
V
Output voltage
–0.3 to VDD + 0.3
Analog input
voltage
VAN
P10 to P17
1 pin
Analog input pin
AVSS –0.3 to AVREF + 0.3
V
Output
current high
–10
–15
–15
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IOH
P10 to P17, P20 to P27, P30 to P37 total
P01 to P03, P40 to P47, P50 to P57, P60 to P67 total
Peak value
Output
current low
1 pin
rms
15
P40 to P47, P50 to P55 total
Peak value
rms
100
70
P01 to P03, P56, P57,
P60 to P67 total
P01 to P03,
Peak value
rms
100
70
IOLNote
Peak value
rms
50
P64 to P67 total
20
P10 to P17, P20 to P27, P30 to P37 Peak value
total rms
50
20
Operating ambient
temperature
–40 to +85
°C
°C
TA
Storage
–65 to +150
Tstg
temperature
Note rms should be calculated as follows: [rms] = [peak value] × √duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or
even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions which
ensure that the absolute maximum ratings are not exceeded.
33
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Capacitance ( TA = 25 °C, VDD = VSS = 0 V )
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
Input capacitance
I/O capacitance
CIN
f = 1 MHz Unmeasured pins returned to 0 V
P01 to P03, P10 to P17,
f = 1 MHz Unmeasured P20 to P27, P30 toP37,
pins returned to 0 V P40 toP47, P50 to P57,
P64 to P67
15
pF
pF
CIO
P60 to P63
20
Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics ( TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Recommended
Circuit
Resonator
Ceramic
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
1
1
10
5
Oscillator
MHz
X1
X2
IC
resonator
Note 1
frequency (fX)
R1
Oscillation
After VDD reaches oscil-
lator voltage range MIN.
C2
C1
ms
4
Note 2
stabilization time
Crystal
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
VDD = 4.5 to 5.5 V
1
1
10
5
Oscillator
MHz
X1
C1
X2
IC
resonator
Note 1
Note 2
frequency (fX)
Oscillation
10
30
C2
X2
ms
stabilization time
External
clock
X1 input
1.0
45
10.0
500
Note 1
MHz
frequency (fX)
X1
X1 input
high/low level width
(tXH , tXL)
ns
µ
PD74HCU04
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wirinin the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
● Wiring should be as short as possible.
● Wiring should not cross other signal lines.
● Wiring should not be placed close to a varying high current.
● The potential of the oscillator capacitor ground should be the same as VSS.
● Do not ground wiring to a ground pattern in which a high current flows.
● Do not fetch a signal from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be switched again to the main system clock after the oscillation stabilization
time is secured by the program.
34
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Recommended
Circuit
Test Conditions
Parameter
Oscillator
MIN.
32
TYP.
MAX.
35
Unit
kHz
Resonator
Crystal
32.768
1.2
XT1 XT2
IC
Note 1
frequency (fXT)
resonator
R2
VDD = 4.5 to 5.5 V
2
Oscillation
C3
C4
s
Note 2
stabilization time
10
XT1 input
External
clock
100
15
32
5
kHz
Note 1
frequency (fXT)
XT2
XT1
XT1 input
high/low level width
µs
(tXTH , tXTL)
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
● Wiring should be as short as possible.
● Wiring should not cross other signal lines.
● Wiring should not be placed close to a varying high current.
● The potential of the oscillator capacitor ground should be the same as VSS.
● Do not ground wiring to a ground pattern in which a high current flows.
● Do not fetch a signal from the oscillator.
2. The subsystem clock oscillation circuit is a circuit with a low amplification level,more prone to
misoperation due to noise than the main system clock.
Particular care is therefore required with the wiring method when the subsystem clock is used.
35
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter Symbol Test Conditions
P10-P17, P21, P23, P30-P32, VDD = 2.7 to 5.5 V
MIN.
TYP.
MAX.
Unit
V
Input voltage VIH1
high
0.7 VDD
VDD
P35-P37, P40-P47, P50-P57,
P64-67
0.8 VDD
VDD
V
VIH2
VIH3
VIH4
VIH5
P00-P03, P20, P22, P24-P27, P33, VDD = 2.7 to 5.5 V
P34, RESET
0.8 VDD
0.85 VDD
0.7 VDD
0.8 VDD
VDD – 0.5
VDD – 0.2
0.8 VDD
0.9 VDD
0.9 VDD
0
VDD
VDD
V
V
V
V
V
V
V
V
V
V
P60-P63
VDD = 2.7 to 5.5 V
15
(N-ch open-drain)
X1, X2
15
VDD = 2.7 to 5.5 V
VDD
VDD
XT1/P04, XT2
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
VDD = 2.7 to 5.5 V
VDD
VDD
Note
VDD
Input voltage VIL1
low
P10-P17, P21, P23, P30-P32,
P35-P37, P40-P47, P50-P57,
P64-67
0.3 VDD
0
0.2 VDD
V
VIL2
VIL3
P00-P03, P20, P22, P24-P27, P33, VDD = 2.7 to 5.5 V
P34, RESET
0
0.2 VDD
0.15 VDD
0.3 VDD
0.2 VDD
0.1 VDD
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
0
P60-P63
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
0
0
0
VIL4
VIL5
X1, X2
VDD = 2.7 to 5.5 V
0
0
0.2
XT1/P04, XT2
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
1.8 V ≤ VDD < 2.7 V
0
0.2 VDD
0.1 VDD
0.1 VDD
0
Note
0
Output
VOH1
VOL1
VDD = 4.5 to 5.5 V, IOH = –1 mA
IOH = –100 µA
VDD – 1.0
VDD – 0.5
voltage high
Output
P50 to P57, P60 to P63
VDD = 4.5 to 5.5 V,
IOL = 15 mA
0.4
2.0
0.4
voltage low
P01 to P03, P10 to P17, P20 to P27
P30 to P37, P40 to P47, P64 to P67
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
V
V
V
VOL2
VOL3
VDD = 4.5 to 5.5 V, open-drain
0.2 VDD
0.5
pulled-up (R = 1 KΩ)
IOL = 400 µA
Note When using XT1/P04 as P04, input the inverse of P04 to XT2 using an inverter.
Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
36
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter Symbol Test Conditions
P00 to P03, P10 to P17,
MIN.
TYP.
MAX.
3
Unit
Input leakage ILIH1
current high
VIN = VDD
µA
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, RESET
X1, X2, XT1/P04, XT2
P60 to P63
ILIH2
ILIH3
20
80
–3
µA
µA
µA
VIN = 15 V
VIN = 0 V
Input leakege ILIL1
current low
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
P40 to P47, P50 to P57,
P60 to P67, RESET
X1, X2, XT1/P04, XT2
P60 to P63
ILIL2
ILIL3
–20
µA
µA
µA
Note
–3
Output leakage ILOH1
current high
VOUT = VDD
3
Output leakage ILOL
current low
VOUT = 0 V
–3
90
90
µA
kΩ
kΩ
Mask option
pull-up resister
Software
R1
VIN = 0 V, P60 to P63
20
15
40
40
R2
VIN = 0 V, P01 to P03, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P60 to P67
pull-up resister
Note For P60-P63, if pull-up resistor is not provided (specifiable by mask option) a low-level input leak current of –200
µA (MAX.) flows only during the 3 clocks (no-wait time) after an instruction has been executed to read out port 6 (P6)
or port mode register 6 (PM6). Outside the period of 3 clocks following execution a read-out instruction, the current
is –3 µA (MAX.).
Remark The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
37
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
DC Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
Supply
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Note 2
Note 3
Note 2
Note 3
Note 3
Note 3
Note 4
Note 3
Note 3
Note 4
IDD1
10.00 MHz crystal
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.0 V ± 10 %
VDD = 5.0 V ± 10 %
9.0
1.3
2.0
1.0
60
18.0
2.6
4.0
2.0
120
70
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Note 1
current
oscillation operation mode
10.00 MHz crystal
IDD2
IDD3
oscillation HALT mode
32.768 kHz crystal
Note 4
oscillation operation mode
35
24
48
IDD4
IDD5
IDD6
32.768 kHz crystal
25
50
oscillation HALT mode
5
15
2
10
XT1 = VDD
1
30
STOP mode when using feedback VDD = 3.0 V ± 10 %
0.5
0.3
0.1
0.05
0.05
10
Note 4
Note 4
resistor
VDD = 2.0 V ± 10 %
VDD = 5.0 V ± 10 %
VDD = 3.0 V ± 10 %
VDD = 2.0 V ± 10 %
10
XT1 = VDD
30
STOP mode when not using
feedback resistor
10
10
Notes 1. Current flowing into the VDD and AVDD pins. However, the current flowing into the A/D converter and internal pull-
up resistors is not included.
2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H)
3. When operating at low-speed mode (when the PCC is set to 04H)
4. When main system clock stopped.
38
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
AC Characteristics
(1) Basic Operation (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
Operating on main system clock
MIN.
TYP.
122
MAX.
Unit
Cycle time
TCY
3.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 3.5 V
1.8 V ≤ VDD < 2.7 V
0.4
64
64
µs
µs
(Min. instruction
execution time)
0.8
2.0
40
64
µs
Operating on subsystem clock
3.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 3.5 V
1.8 V ≤ VDD < 2.7 V
VDD = 4.5 to 5.5 V
125
µs
Note
Note
Note
TI0 input
tTIH0
tTIL0
2/fsam+0.1
2/fsam+0.2
2/fsam+0.5
0
µs
frequency
µs
µs
TI1, TI2 input fTI1
frequency
4
MHz
kHz
0
275
TI1, TI2 input tTIH1
high/low-level tTIL1
width
VDD = 4.5 to 5.5 V
100
1.8
ns
µs
Note
Note
Note
Interrupt input tINTH
INTP0
3.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 3.5 V
1.8 V ≤ VDD < 2.7 V
VDD = 2.7 to 5.5 V
2/fsam+0.1
2/fsam+0.2
2/fsam+0.5
10
µs
µs
µs
µs
µs
µs
µs
high/low-level
width
tINTL
INTP1-INTP3, KR0-KR7
VDD = 2.7 to 5.5 V
20
RESET low
level width
tRSL
10
20
Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible
between fX/2N+1, fX/64 and fx/128 (when N= 0 to 4).
39
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
TCY vs VDD (At main system clock operation)
60.0
Operation Guaranteed
Range
10.0
5.0
µ
1.0
0.5
0.1
3.5
5.5
0
1.0
2.0
3.0
4.0
5.0
6.0
1.8
2.7
Supply voltage VDD [V]
40
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(2) Read/Write Operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Test Conditions
MIN.
0.5tCY
0.5tCY–30
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
Data input time from address
tADD1
tADD2
tRDD1
tRDD2
tRDH
(2.5+2n)tCY–50
(3+2n)tCY–100
(1+2n)tCY–25
Data input time from RD↓
(2.5+2n)tCY–100
Read data hold time
RD low-level width
0
tRDL1
(1.5+2n)tCY–20
(2.5+2n) tCY–20
tRDL2
WAIT↓ input time from RD↓
tRDWT1
tRDWT2
tWRWT
tWTL
0.5tCY
1.5tCY
WAIT↓ input time from WR↓
WAIT low-level width
0.5tCY
(0.5+2n)tCY+10
100
(2+2n)tCY
Write data setup time
tWDS
Write data hold time
tWDH
Load resistor ≥ 5 kΩ
20
WR low-level width
tWRL1
tASTRD
tASTWR
tRDAST
(2.5+2n) tCY –20
0.5tCY–30
1.5tCY–30
tCY–10
RD↓ delay time from ASTB↓
WR↓ delay time from ASTB↓
ASTB↑ delay time from
RD↑ in external fetch
tCY+40
tCY+50
Address hold time from
tRDADH
tRDWD
tCY
ns
RD↑ in external fetch
Write data output time from RD↑
Write data output time from WR↓
Address hold time from WR↑
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
0.5tCY+5
0.5tCY+15
5
0.5tCY+30
0.5tCY+90
30
ns
ns
ns
ns
ns
ns
ns
ns
tWRWD
15
90
tWRADH
tCY
tCY+60
tCY
tCY+100
2.5tCY+80
2.5tCY+80
RD↑ delay time from WAIT↑
WR↑ delay time from WAIT↑
tWTRD
tWTWR
0.5tCY
0.5tCY
Remarks 1. tCY = TCY/4
2. n indicates number of waits.
41
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(3) Serial Interface (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)
(a) Serial Interface Channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY1
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
800
1600
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3200
4800
SCK0 high/low-level
width
tKH1
tKL1
tSIK1
VDD = 4.5 to 5.5 V
tKCY1/2–50
tKCY1/2–100
100
SI0 setup time
(to SCK0↑)
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
150
300
400
SI0 hold time
tKSI1
400
(from SCK0↑)
Note
SO0 output delay time tKSO1
C = 100 pF
300
ns
from SCK0↓
Note C is the load capacitance of SCK0 and SO0 output line.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY2
800
1600
3200
4800
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
SCK0 high/low-level
width
tKH2
tKL2
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
800
1600
2400
100
SI0 setup time
(to SCK0↑)
tSIK2
tKSI2
VDD = 2.0 to 5.5 V
150
SI0 hold time
(from SCK0↑)
400
Note
SO0 output delay time tKSO2
C = 100 pF
VDD = 2.0 to 5.5 V
300
500
160
ns
ns
ns
from SCK0↓
SCK0 rise, fall time
tR2
tF2
When external device
expansion function is used
When external When 16-bit timer
device expansion output function is
function is not used
700
ns
ns
used
When 16-bit timer
output function is
not used
1000
Note C is the load capacitance of SO0 output line.
42
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iii) SBI mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY3
800
3200
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 V ≤ VDD < 4.5 V
4800
SCK0 high/low-level
width
tKH3
tKL3
tSIK3
VDD = 4.5 to 6.0 V
tKCY3/2–50
tKCY3/2–150
100
SB0, SB1 setup time
(to SCK0↑)
4.5 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.5 V
300
400
SB0, SB1 hold time
(from SCK0↑)
tKSI3
tKCY3/2
SB0, SB1output delay
time from SCK0↓
tKSO3
R = 1 kΩ,
VDD = 4.5 to 5.5 V
0
250
ns
ns
ns
ns
ns
Note
C = 100 pF
0
1000
SB0, SB1↓ from SCK0↑ tKSB
SCK0↓ from SB0, SB1↓ tSBK
tKCY3
tKCY3
tKCY3
SB0, SB1 high-level
width
tSBH
SB0, SB1 low-level
width
tSBL
tKCY3
ns
Note R and C are the load resistors and load capacitance of the SB0, SB1 and SCK0 output line.
43
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iv) SBI mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY4
800
3200
4800
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 V ≤ VDD < 4.5 V
SCK0 high/low-level
width
tKH4
tKL4
4.5 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.5 V
1600
2400
100
SB0, SB1 setup time
tSIK4
4.5 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 4.5 V
(to SCK0↑)
300
400
SB0, SB1 hold time
tKSI4
tKCY4/2
(from SCK0↑)
SB0, SB1 output delay tKSO4
time from SCK0↓
R = 1 kΩ,
VDD = 4.5 to 5.5 V
0
300
ns
ns
ns
ns
ns
Note
C = 100 pF
0
1000
SB0, SB1↓ from SCK0↑ tKSB
SCK0↓ from SB0, SB1↓ tSBK
tKCY4
tKCY4
tKCY4
SB0, SB1 high-level
width
tSBH
SB0, SB1 low-level
width
tSBL
tKCY4
ns
ns
ns
SCK0 rise, fall time
tR4
tF4
When external device
160
700
expansion function is used
When external When 16-bit timer
device expansion output function is
function is not used
used
When 16-bit timer
output function is
not used
1000
ns
Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
44
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(v) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
R = 1 kΩ, 2.7 V ≤ VDD ≤ 5.5 V
C = 100 pF
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY5
1600
3200
4800
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
2.0 V ≤ VDD < 2.7 V
SCK0 high-level width
SCK0 low-level width
tKH5
tKL5
tSIK5
VDD = 2.7 to 5.5 V tKCY5/2–160
tKCY5/2–190
VDD = 4.5 to 5.5 V
tKCY5/2–50
tKCY5/2–100
300
SB0, SB1 setup time
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
(to SCK0↑)
350
400
500
SB0, SB1 hold time
tKSI5
600
(from SCK0↑)
SB0, SB1 output delay tKSO5
0
300
ns
time from SCK0↓
Note R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
45
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(vi) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
2.7 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK0 cycle time
tKCY6
1600
3200
4800
650
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.0 V ≤ VDD < 2.7 V
SCK0 high-level width tKH6
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
1300
2100
800
SCK0 low-level width
tKL6
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
1600
2400
100
SB0, SB1 setup time
(to SCK0↑)
tSIK6
tKSI6
VDD = 2.0 to 5.5 V
150
SB0, SB1 hold time
(from SCK0↑)
tKCY6/2
SB0, SB1 output delay tKSO6
R = 1 kΩ,
4.5 V ≤ VDD ≤ 5.5 V
0
0
0
300
500
800
160
ns
ns
ns
ns
time from SCK0↓
C = 100 pF Note 2.0 V ≤ VDD < 4.5 V
SCK0 rise, fall time
tR6
tF6
When external device
expansion function is used
When external When 16-bit timer
device expansion output function is
function is not used
700
ns
ns
used
When 16-bit timer
output function is
not used
1000
Note R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
46
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(b) Serial Interface Channel 1
(i) 3-wire serial I/O mode (SCK1... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY7
800
1600
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
3200
4800
SCK1 high/low-level
width
tKH7
tKL7
tSIK7
VDD = 4.5 to 5.5 V
tKCY7/2–50
tKCY7/2–100
100
SI1 setup time
(to SCK1↑)
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
150
300
400
SI1 hold time
tKSI7
400
(from SCK1↑)
Note
SO1 output delay time tKSO7
C = 100 pF
300
ns
from SCK1↓
Note C is the load capacitance of SCK1 and SO1 output line.
(ii) 3-wire serial I/O mode (SCK1... External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY8
800
1600
3200
4800
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
SCK1 high/low-level
width
tKH8
tKL8
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
800
1600
2400
100
SI1 setup time
(to SCK1↑)
tSIK8
tKSI8
VDD = 2.0 to 5.5 V
150
SI1 hold time
(from SCK1↑)
400
Note
SO0 output delay time tKSO8
C = 100 pF
VDD = 2.0 to 5.5 V
300
500
160
ns
ns
ns
from SCK1↓
SCK1 rise, fall time
tR8
tF8
When external device
expansion function is used
When external When 16-bit timer
device expansion output function is
function is not used
700
ns
ns
used
When 16-bit timer
output function is
not used
1000
Note C is the load capacitance of SO1 output line.
47
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY9
800
1600
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
3200
4800
SCK1 high/low-level
width
tKH9
tKL9
tSIK9
VDD = 4.5 to 5.5 V
tKCY9/2–50
tKCY9/2–100
100
SI1 setup time
(to SCK1↑)
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
150
300
400
SI1 hold time
tKSI9
400
(from SCK1↑)
SO1 output delay time tKSO9
C = 100 pF Note
300
ns
from SCK1↓
STB↑ from SCK1↑
Strobe signal
tSBD
tSBW
tKCY9/2–100
tKCY9–30
tKCY9–60
tKCY9–90
100
tKCY9/2+100
tKCY9+30
tKCY9+60
tKCY9+90
ns
ns
ns
ns
ns
2.7 V ≤ VDD ≤ 5.5 V
2.0 V ≤ VDD < 2.7 V
high-level width
Busy signal setup time tBYS
(to busy signal
detection timing)
Busy signal hold time
(from busy signal
detection timing)
tBYH
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
100
150
200
300
ns
ns
ns
ns
ns
SCK1↓ from busy
tSPS
2tKCY9
inactive
Note C is the load capacitance of SCK1 and SO1 output line.
48
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1... External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
SCK1 cycle time
tKCY10
800
1600
3200
4800
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
SCK1 high/low-level
width
tKH10,
tKL10
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
800
1600
2400
100
SI1 setup time
(to SCK1↑)
tSIK10
tKSI10
VDD = 2.0 to 5.5 V
150
SI1 hold time
(from SCK1↑)
400
Note
SO1 output delay time tKSO10
C = 100 pF
VDD = 2.0 to 5.5 V
300
500
160
ns
ns
ns
from SCK1↓
SCK1 rise, fall time
tR10, tF10
When external device expansion
function is used
When external device expansion
function is not used
1000
ns
Note C is the load capacitance of the SO1 output line.
49
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
Clock Timing
1/fX
t
XL
t
XH
V
V
IH4 (MIN.)
IL4 (MAX.)
X1 Input
1/fXT
t
XTL
t
XTH
V
IH5 (MIN.)
IL5 (MAX.)
XT1 Input
V
TI Timing
t
TIL0
t
TIH0
TI0
1/fTI1
t
TIL1
t
TIH1
TI1,TI2
50
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Read/Write Operation
External fetch (No wait):
A8-A15
Higher 8-Bit Address
t
ADD1
Hi-Z
Lower 8-Bit
Address
AD0-AD7
Operation Code
t
ADS
t
ADH
t
RDD1
t
RDADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
External fetch (Wait insertion):
A8-A15
Higher 8-Bit Address
t
ADD1
Hi-Z
Lower 8-Bit
Address
AD0-AD7
Operation Code
t
ADS
t
ADH
t
RDD1
t
RDADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
WAIT
t
RDWT1
t
WTL
t
WTRD
51
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
External data access (No wait):
A8-A15
Higher 8-Bit Address
t
ADD2
Hi-Z
Lower 8-Bit
Address
Hi-Z
Hi-Z
AD0-AD7
Read Data
Write Data
t
ADS
t
RDD2
t
ADH
t
ASTH
t
RDH
ASTB
RD
t
ASTRD
t
RDWD
t
RDL2
t
WDS
tWDH
t
WRWD
t
WRADH
WR
t
ASTWR
t
WRL1
External data access (Wait insertion):
A8-A15
Higher 8-Bit Address
t
ADD2
Hi-Z
Hi-Z
Hi-Z
Lower 8-Bit
Address
Read Data
Write Data
AD0-AD7
t
ADS
t
ADH
t
ASTH
t
RDD2
t
RDH
ASTB
RD
t
ASTRD
t
RDL2
t
WDS
t
WDH
t
RDWD
t
WRWD
WR
t
ASTWR
t
WRL1
t
WRADH
WAIT
t
WTL
t
WTRD
t
RDWT2
t
WTL
t
WTWR
t
WRWT
52
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Serial Transfer Timing
3-wire serial I/O mode:
tKCYm
tKLm
tKHm
tRn
tFn
SCK0,SCK1
tSIKm
tKSIm
SI0,SI1
Input Data
tKSOm
SO0,SO1
Output Data
m = 1, 2, 7, 8
n = 2, 8
SBI mode (Bus release signal transfer):
t
KCY3, 4
t
KL3, 4
R4
t
KH3, 4
t
t
F4
SCK0
t
SIK3, 4
tKSB
t
SBL
t
SBH
t
SBK
t
KSI3, 4
SB0, SB1
t
KSO3, 4
SBI Mode (command signal transfer):
t
KCY3, 4
t
KL3, 4
R4
t
KH3, 4
t
t
F4
SCK0
t
SIK3, 4
t
KSB
t
SBK
t
KSI3, 4
SB0, SB1
t
KSO3, 4
53
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
2-wire serial I/O mode:
tKCY5,6
tKL5,6
tR6
tKH5,6
tF6
SCK0
tSIK5,6
tKSI5,6
tKSO5,6
SB0, SB1
3-wire serial I/O mode with automatic transmit/receive function:
SO1
SI1
D7
D2
D1
D0
D7
D2
D1
D0
t
SIK9,10
KSO9,10
t
KSI9,10
t
t
KH9,10
t
F10
SCK1
STB
t
R10
t
KL9,10
KCY9,10
t
SBW
t
SBD
t
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
9Note
10Note
SCK1
7
10 + nNote
1
8
t
BYS
t
BYH
t
SPS
BUSY
(Active High)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
54
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
A/D converter characteristics (TA = –40 to +85 °C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Overall error
Symbol
Test Conditions
MIN.
8
TYP.
8
MAX.
Unit
8
bit
%
Note
2.7 V ≤ AVREF ≤ AVDD
1.8 V ≤ AVREF < 2.7 V
2.0 V ≤ AVDD ≤ 5.5 V
1.8 V ≤ AVDD < 2.0 V
0.6
1.4
200
200
%
Conversion time
tCONV
19.1
38.2
24/fX
AVSS
1.8
µs
µs
µs
V
Sampling time
tSAMP
VIAN
Analog input voltage
Reference voltage
AVREF
AVDD
AVREF
V
AVREF–AVSS resistance RAIREF
4
14
kΩ
Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85 °C)
Parameter
Symbol
Test Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data retention supply
voltage
VDDDR
Data retention supply
current
IDDDR
VDDDR = 1.8 V
0.1
10
µA
Subsystem clock stop and feed-
back resister disconnected
Release signal set time tSREL
Oscillation stabilization tWAIT
wait time
0
µs
ms
ms
Release by RESET
Release by interrupt
218/fX
Note
Note In combination with bit 0 to bit 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/
fX and 215/fX to 218/fX is possible.
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
VDD
t
SREL
VDDDR
STOP Instruction Execution
RESET
t
WAIT
55
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Data Retention Timing (Standby Release Signal : STOP Mode Release by Interrupt Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retension Mode
V
DD
V
DDDR
tSREL
STOP Instruction Execition
Standby Release Signal
(Interrupt Request)
t
WAIT
Interrupt Input Timing
t
INTL
t
INTH
INTP0-INTP2
t
INTL
INTP3
RESET Input Timing
t
RSL
RESET
56
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
12. PACKAGE DRAWINGS
64 PIN PLASTIC SHRINK DIP (750 mil)
64
33
32
1
A
K
L
F
D
M
R
B
C
M
N
NOTE
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
58.68 MAX.
1.78 MAX.
1.778 (T.P.)
2.311 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
0.50±0.10
D
–0.005
F
G
H
I
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.51 MIN.
4.31 MAX.
5.08 MAX.
19.05 (T.P.)
17.0
J
K
L
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0~15°
0~15°
P64C-70-750A,C-1
Remark Dimensions and materials of ES products are the same as those of mass-production products.
57
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
64 PIN PLASTIC QFP ( 14)
A
B
48
49
33
32
detail of lead end
64
1
17
16
G
H
M
I
J
K
N
L
P64GC-80-AB8-2
NOTE
ITEM
A
MILLIMETERS
INCHES
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
±
±
17.6 0.4
0.693 0.016
+0.009
–0.008
±
B
14.0 0.2
0.551
+0.009
±
C
D
F
14.0 0.2
0.551
–0.008
±
±
0.693 0.016
17.6 0.4
1.0
1.0
0.039
G
H
I
0.039
+0.004
–0.005
±
0.35 0.10
0.014
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
±
±
K
1.8 0.2
0.071 0.008
+0.009
–0.008
±
0.031
L
0.8 0.2
+0.10
–0.05
+0.004
–0.003
0.15
M
N
P
0.006
0.10
2.55
0.004
0.100
±
Q
S
0.1 0.1
±
0.004 0.004
2.85 MAX.
0.112 MAX.
Remark Dimensions and materials of ES products are the same as those of mass-production products.
58
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
13. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact our salespersonnel.
Table 13-1. Surface Mounting Type Soldering Conditions
µPD78011HGC(A)-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm)
µPD78012HGC(A)-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm)
µPD78013HGC(A)-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm)
µPD78014HGC(A)-×××-AB8 : 64-Pin Plastic QFP (14 × 14 mm)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or above),
Number of times: Thrice max.
IR35-00-3
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above),
Number of times: Thrice max.
VP15-00-3
WS60-00-1
Wave soldering
Solder bath temperature: 260 °C max. Duration: 10 sec. max.
Number of times: Once
Preliminary heat temperature: 120 °C max. (Package surface temperature)
Partial heating
Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side)
—
Caution Use more than one soldering method should be avoided (except in the case of partial heating).
Table 13-2. Insertion Type Soldering Conditions
µPD78011HCW(A)-××× : 64-Pin Plastic Shrink DIP (750 mil)
µPD78012HCW(A)-××× : 64-Pin Plastic Shrink DIP (750 mil)
µPD78013HCW(A)-××× : 64-Pin Plastic Shrink DIP (750 mil)
µPD78014HCW(A)-××× : 64-Pin Plastic Shrink DIP (750 mil)
Soldering Method
Soldering Conditions
Solder bath temperature: 260°C max., Duration: 10 sec. max.
Wave soldering
(pin only)
Partial heating
Pin temperature: 300°C max., Duration: 3 sec. max. (per pin)
Caution Wave soldering is only for the lead part in order that jet solder can not contact with the chip directly.
59
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for the development of systems using the µPD78014H subseries.
Language processor software
Notes 1, 2, 3, 4
RA78K/0
CC78K0
DF78014
Assembler package common to 78K/0 series
C compiler package common to 78K/0 series
Device file common to µPD78014 subseries
C compiler library source file common to 78K/0 series
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4, 6
Notes 1, 2, 3, 4
CC78K0-L
Debugging tools
IE-78000-R
In-circuit emulator common to 78K/0 series
IE-78000R-A
In-circuit emulator common to 78K/0 series (for integrated debugger)
Break board common to 78K/0 series
IE-78000-R-BK
IE-78014-R-EM-A
EP-78240CW-R
EV-9200GC-64
Emulation board common to µPD78018F and 78018FY subseries (VDD = 3.0 to 6.0 V)
Emulation probe common to µPD78244 subseries
Socket mounted on printed wiring board of target system created for 64-pin plastic QFP
(GC-AB8 type)
Notes 5, 6, 7
SM78K0
System emulator common to 78K/0 series
Integrated debugger common to 78K/0 series
Screen debugger for IE-78000-R
Notes 4, 5, 6, 7
ID78K0
Notes 1, 2
SD78K/0
Notes 1, 2, 3, 4, 5, 6, 7
DF78014
Device file common to µPD78014 subseries
Real-Time OS
Notes 1, 2
RX78K/0
Real-time OS for 78K/0 series
OS for 78K/0 series
Notes 1, 2
MX78K0
60
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Fuzzy Inference Devleopment Support System
Note 1
Note 6
FE9000
FT9080
FI78K0
FD78K0
/FE9200
/FT9085
Fuzzy knowledge data creation tool
Note 1
Note 2
Translator
Notes 1, 2
Notes 1, 2
Fuzzy inference module
Fuzzy inference debugger
Notes 1. PC-9800 series (MS-DOSTM) based
2. IBM PC/ATTM and compatible machine (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 series 300TM (HP-UXTM) based
4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-UX/V) based
5. PC-9800 series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatible machine (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
Remarks 1. For development tools manufactured by a third party, refer to the 78K/0 Series Selection Guide (U11126E).
2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78014.
61
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document No.
Document Name
Japanese
Planned to publish
U12174J
English
µPD78014H Subseries User's Manual
Planned to publish
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A) Data Sheet
78K/0 Series User's Manual - Instruction
78K/0 Series Instruction List
This document
IEU-849
IEU-1372
U10903J
—
—
—
78K/0 Series Instruction Set
U10904J
µPD78014H Subseries Special Function Register List
Planned to publish
Development Tools Documents (User's Manual)
Document No.
Document Name
Japanese
EEU-809
EEU-815
EEU-817
U11802J
U11801J
U11789J
EEU-656
EEU-655
11517J
English
EEU-1399
EEU-1404
EEU-1402
U11802E
U11081E
U11789E
EEU-1280
EEU-1284
—
RA78K Series Assembler Package
Operation
Language
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
Operation
Assembly Language
Structural Assembly Language
Operation
CC78K Series C Compiler
CC78K/0 C Compiler
Language
Operation
Language
11518J
—
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
IE-78000-R
Programming Know-how
EEA-618
EEU-777
EEU-810
U10057J
EEU-867
EEU-962
EEU-986
U10181J
U10092J
EEA-1208
—
U11376E
U10057E
EEU-1427
U10418E
U10332E
U10181E
U10092E
IE-78000-R-A
IE-78000-R-BK
IE-78014-R-EM-A
EP-78240
SM78K0 System Simulator Windows Based
SM78K Series System Simulator
Reference
External Components User Open
Interface
ID78K0 Integrated Debugger EWS Based
ID78K0 Integrated Debugger PC Based
ID78K0 Integrated Debugger Windows Based
SD78K/0 Screen Debugger
Reference
Reference
Guide
U11151J
U11539J
U11649J
EEU-852
U10952J
EEU-5024
U11279J
—
U11539E
U11649E
—
Introduction
Reference
Introduction
Reference
PC-9800 Series (MS-DOS) Based
SD78K/0 Screen Deb
—
EEU-1414
U11279E
IBM PC/AT (PC DOS) Based
Caution The contents of the above related documents are subject to change without notice. The latest documents
should be used for design, etc.
62
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Embedded Software Documents (User's Manual)
Document No.
Japanese
Document Name
English
—
78K/0 Series Real-Time OS
78K/0 Series OS MX78K0
Fundamental
Installation
Technical
U11537J
U11536J
U11538J
EEU-5010
EEU-829
EEU-862
—
—
Fundamental
—
Fuzzy Knowledge Data Creation Tool
78K/0, 78K/II, 87AD Series
EEU-1438
EEU-1444
Fuzzy Inference Development Support System - Translator
78K/0 Series Fuzzy Inference Development Suport System -
Fuzzy Inference Module
EEU-858
EEU-921
EEU-1441
EEU-1458
78K/0 Series Fuzzy Inference Development Support System -
Fuzzy Inference Debugger
Other Documents
Document No.
Document Name
Japanese
C10943X
English
IC Package Manual
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Device
NEC Semiconductor Device Reliability/Quality Control System
Electrostatic Discharge (ESD) Test
C10535J
C11531J
C10983J
MEM-539
C11893J
U11416J
C10535E
C11531E
C10983E
—
Guide to Quality Assurance for Semiconductor Device
Guide for Products Related to Micro-Computer: Other Companies
MEI-1202
—
Caution The contents of the above related documents are subject to change without notice. The latest documents
should be used for design, etc.
63
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
64
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 800-729-9288
Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 0211-65 03 490
Tel: 02-528-0303
Fax: 02-528-4411
Fax: 01-30-67 58 99
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Fax: 01908-670-290
Fax: 250-3583
Tel: 01-504-2787
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics (Germany) GmbH
Scandinavia Office
Fax: 02-66 75 42 99
Fax: 02-719-5951
Taeby, Sweden
Tel: 08-63 80 820
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
Fax: 08-63 80 388
J96. 8
65
µPD78011H(A), 78012H(A), 78013H(A), 78014H(A)
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
IBM-DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
HP9000 Series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a tradmark of SPARC International, Inc.
SunOS is a tradmark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
Some related decuments are preliminary versions. This document, however, is not indicated as preliminary.
The export of this product from J apan is regulated by the J apanese governm ent. To export this product m ay be
prohibited without governm ental license, the need for which m ust be judged by the custom er. The export or re-
export of this product from a country other than J apan m ay also be prohibited without a license from that country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
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