UPD780114GB(A1)-XXX-8ES [NEC]
Microcontroller, 8-Bit, MROM, 10MHz, CMOS, PQFP44, 10 X 10 MM, PLASTIC, LQFP-44;
| 型号： | UPD780114GB(A1)-XXX-8ES |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 8-Bit, MROM, 10MHz, CMOS, PQFP44, 10 X 10 MM, PLASTIC, LQFP-44 时钟 微控制器 外围集成电路 |
| 文件： | 总431页 (文件大小：2614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary User’s Manual
78K0/KC1
8-Bit Single-Chip Microcontrollers
µPD780111
µPD780112
µPD780113
µPD780114
µPD78F0114
µPD780111(A)
µPD780112(A)
µPD780113(A)
µPD780114(A)
µPD78F0114(A)
µPD780111(A1)
µPD780112(A1)
µPD780113(A1)
µPD780114(A1)
Document No. U16227EJ1V0UD00 (1st edition)
Date Published June 2002 N CP(K)
2002
©
Printed in Japan
[MEMO]
2
Preliminary User’s Manual U16227EJ1V0UD
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
Ethernet is a trademark of Xerox Corp.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
3
Preliminary User’s Manual U16227EJ1V0UD
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed: µPD78F0114 and 78F0114(A)
The customer must judge the need for a license: µPD780111, 780112, 780113, 780114, 780111(A), 780112(A),
780113(A), 780114(A), 780111(A1), 780112(A1), 780113(A1),
and 780114(A1)
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5D 98. 12
4
Preliminary User’s Manual U16227EJ1V0UD
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
• Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-244 58 45
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 040-244 45 80
• Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 11-6462-6829
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 021-6841-1137
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Fax: 0211-65 03 327
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
• Sucursal en España
Madrid, Spain
Fax: 02-2719-5951
Tel: 091-504 27 87
Fax: 091-504 28 60
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 250-3583
Fax: 01-30-67 58 99
J02.4
5
Preliminary User’s Manual U16227EJ1V0UD
INTRODUCTION
Readers
This manual is intended for user engineers who wish to understand the functions of the
78K0/KC1 Series and design and develop application systems and programs for these
devices.
The target products are as follows.
78K0/KC1 Series: µPD780111, 780112, 780113, 780114, 78F0114, 780111(A),
780112(A), 780113(A), 780114(A), 78F0114(A), 780111(A1),
780112(A1), 780113(A1), and 780114(A1)
Purpose
This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization
The 78K0/KC1 Series manual is separated into two parts: this manual and the
instructions edition (common to the 78K/0 Series).
78K0/KC1
78K/0 Series
User’s Manual
Instructions
User’s Manual
(This Manual)
• Pin functions
• CPU functions
• Internal block functions
• Instruction set
• Interrupts
• Explanation of each instruction
• Other on-chip peripheral functions
• Electrical specifications (Target values)
6
Preliminary User’s Manual U16227EJ1V0UD
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
•
When using this manual as the manual for (A) products and (A1) products:
→ Only the quality grade differs between standard products and (A) and (A1)
products. Read the part number as follows.
• µPD780111 → µPD780111(A), 780111(A1)
• µPD780112 → µPD780112(A), 780112(A1)
• µPD780113 → µPD780113(A), 780113(A1)
• µPD780114 → µPD780114(A), 780114(A1)
• µPD78F0114 → µPD78F0114(A)
•
•
To gain a general understanding of functions:
→ Read this manual in the order of the CONTENTS.
How to interpret the register format:
→ For a bit number enclosed in square, the bit name is defined as a reserved word
in the assembler, and is already defined in the header file named sfrbit.h in the C
compiler.
•
•
To check the details of a register when you know the register name.
→ Refer to APPENDIX C REGISTER INDEX.
To know details of the 78K/0 Series instructions.
→ Refer to the separate document 78K/0 Series Instructions User’s Manual
(U12326E).
Caution Examples in this manual employ the “standard” quality grade for
general electronics. When using examples in this manual for the
“special” quality grade, review the quality grade of each part and/or
circuit actually used.
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note:
Footnote for item marked with Note in the text.
Caution:
Remark:
Information requiring particular attention
Supplementary information
...
Numerical representations: Binary
Decimal
×××× or ××××B
××××
...
...
Hexadecimal
××××H
7
Preliminary User’s Manual U16227EJ1V0UD
Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
This manual
U12326E
78K0/KC1 User’s Manual
78K/0 Series Instructions User’s Manual
Documents Related to Development Tools (Software) (User’s Manuals)
Document Name
Document No.
RA78K0 Assembler Package
CC78K0 C Compiler
Operation
U14445E
U14446E
U11789E
U14297E
U14298E
U14611E
U15006E
Language
Structured Assembly Language
Operation
Language
SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later
SM78K Series System Simulator Ver. 2.10 or Later
Operation (WindowsTM Based)
External Part User Open Interface
Specifications
ID78K Series Integrated Debugger Ver. 2.30 or Later
RX78K0 Real-Time OS
Operation (Windows Based)
Fundamentals
U15185E
U11537E
U11536E
U14610E
Installation
Project Manager Ver. 3.12 or Later (Windows Based)
Documents Related to Development Tools (Hardware) (User’s Manuals)
Document Name
IE-78K0-NS In-Circuit Emulator
Document No.
U13731E
IE-78K0-NS-A In-Circuit Emulator
U14889E
IE-780148-NS-EM1 Emulation Board
To be prepared
Documents Related to Flash Memory Programming
Document Name
PG-FP3 Flash Memory Programmer User’s Manual
PG-FP4 Flash Memory Programmer User’s Manual
Document No.
U13502E
U15260E
Other Documents
Document Name
SEMICONDUCTOR SELECTION GUIDE − Product & Packages −
Semiconductor Device Mounting Technology Manual
Document No.
X13769E
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C10983E
C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
8
Preliminary User’s Manual U16227EJ1V0UD
CONTENTS
CHAPTER 1 OUTLINE .............................................................................................................................25
1.1 Features .......................................................................................................................................25
1.2 Applications.................................................................................................................................26
1.3 Ordering Information..................................................................................................................27
1.4 Pin Configuration (Top View).....................................................................................................29
1.5 78K0/Kxx Series Lineup .............................................................................................................31
1.6 Block Diagram.............................................................................................................................33
1.7 Outline of Functions...................................................................................................................34
CHAPTER 2 PIN FUNCTIONS................................................................................................................36
2.1 Pin Function List.........................................................................................................................36
2.2 Description of Pin Functions.....................................................................................................38
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
P00 and P01 (port 0) ......................................................................................................................38
P10 to P17 (port 1) .........................................................................................................................39
P20 to P27 (port 2) .........................................................................................................................39
P30 to P33 (port 3) .........................................................................................................................40
P60 to P63 (port 6) .........................................................................................................................40
P70 to P73 (port 7) .........................................................................................................................40
P120 (port 12).................................................................................................................................41
P130 (port 13).................................................................................................................................41
AVREF..............................................................................................................................................41
2.2.10 AVSS ...............................................................................................................................................41
2.2.11 RESET ...........................................................................................................................................41
2.2.12 X1 and X2.......................................................................................................................................41
2.2.13 XT1 and XT2 ..................................................................................................................................41
2.2.14 VDD and EVDD .................................................................................................................................41
2.2.15 VSS and EVSS ..................................................................................................................................41
2.2.16 VPP (flash memory versions only) ...................................................................................................41
2.2.17 IC (mask ROM versions only).........................................................................................................42
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins..........................................43
CHAPTER 3 CPU ARCHITECTURE.......................................................................................................46
3.1 Memory Space.............................................................................................................................46
3.1.1
3.1.2
3.1.3
3.1.4
Internal program memory space.....................................................................................................52
Internal data memory space...........................................................................................................53
Special function register (SFR) area...............................................................................................53
Data memory addressing ...............................................................................................................54
3.2 Processor Registers...................................................................................................................59
3.2.1
3.2.2
3.2.3
Control registers .............................................................................................................................59
General-purpose registers..............................................................................................................62
Special Function Registers (SFRs).................................................................................................63
3.3 Instruction Address Addressing ...............................................................................................67
3.3.1
3.3.2
Relative addressing........................................................................................................................67
Immediate addressing ....................................................................................................................68
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Preliminary User’s Manual U16227EJ1V0UD
3.3.3
3.3.4
Table indirect addressing............................................................................................................... 69
Register addressing....................................................................................................................... 69
3.4 Operand Address Addressing .................................................................................................. 70
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
Implied addressing......................................................................................................................... 70
Register addressing....................................................................................................................... 71
Direct addressing........................................................................................................................... 72
Short direct addressing.................................................................................................................. 73
Special function register (SFR) addressing ................................................................................... 74
Register indirect addressing .......................................................................................................... 75
Based addressing.......................................................................................................................... 76
Based indexed addressing ............................................................................................................ 77
Stack addressing ........................................................................................................................... 77
CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 78
4.1 Port Functions............................................................................................................................ 78
4.2 Port Configuration...................................................................................................................... 80
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
Port 0............................................................................................................................................. 81
Port 1............................................................................................................................................. 83
Port 2............................................................................................................................................. 89
Port 3............................................................................................................................................. 90
Port 6............................................................................................................................................. 92
Port 7............................................................................................................................................. 93
Port 12........................................................................................................................................... 94
Port 13........................................................................................................................................... 95
4.3 Registers Controlling Port Function ........................................................................................ 96
4.4 Port Function Operations........................................................................................................ 100
4.4.1
4.4.2
4.4.3
Writing to I/O port......................................................................................................................... 100
Reading from I/O port .................................................................................................................. 100
Operations on I/O port ................................................................................................................. 100
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 101
5.1 Functions of Clock Generator................................................................................................. 101
5.2 Configuration of Clock Generator .......................................................................................... 102
5.3 Registers Controlling Clock Generator.................................................................................. 103
5.4 System Clock Oscillator.......................................................................................................... 109
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
X1 oscillator ................................................................................................................................. 109
Subsystem clock oscillator........................................................................................................... 109
When subsystem clock is not used.............................................................................................. 112
Ring-OSC oscillator ..................................................................................................................... 112
Prescaler ..................................................................................................................................... 112
5.5 Clock Generator Operation ..................................................................................................... 112
5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock........................... 119
5.7 Changing System Clock and CPU Clock Settings................................................................ 120
5.7.1
Time required for switching between system clock and CPU clock ............................................. 120
5.8 Clock Switching Flowchart and Register Setting ................................................................. 121
5.8.1
5.8.2
5.8.3
Switching from Ring-OSC clock to X1 input clock........................................................................ 121
Switching from X1 input clock to Ring-OSC clock........................................................................ 122
Switching from X1 input clock to subsystem clock....................................................................... 123
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Preliminary User’s Manual U16227EJ1V0UD
5.8.4
5.8.5
Switching from subsystem clock to X1 input clock........................................................................124
Register settings...........................................................................................................................125
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00............................................................................126
6.1 Functions of 16-Bit Timer/Event Counter 00..........................................................................126
6.2 Configuration of 16-Bit Timer/Event Counter 00 ...................................................................127
6.3 Registers Controlling 16-Bit Timer/Event Counter 00...........................................................130
6.4 Operation of 16-Bit Timer/Event Counter 00..........................................................................136
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Interval timer operation.................................................................................................................136
PPG output operations .................................................................................................................138
Pulse width measurement operations...........................................................................................140
External event counter operation..................................................................................................147
Square-wave output operation .....................................................................................................149
One-shot pulse output operation ..................................................................................................150
6.5 Cautions for 16-Bit Timer/Event Counter 00 ..........................................................................155
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 ...........................................................159
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 .............................................................159
7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51.......................................................161
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 ..............................................162
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51............................................................168
7.4.1
7.4.2
7.4.3
7.4.4
Operation as interval timer ...........................................................................................................168
Operation as external event counter.............................................................................................170
Square-wave output operation .....................................................................................................171
PWM output operation..................................................................................................................173
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51..............................................................175
CHAPTER 8 8-BIT TIMERS H0 AND H1 ...........................................................................................176
8.1 Functions of 8-Bit Timers H0 and H1......................................................................................176
8.2 Configuration of 8-Bit Timers H0 and H1 ...............................................................................176
8.3 Registers Controlling 8-Bit Timers H0 and H1.......................................................................178
8.4 Operation of 8-Bit Timers H0 and H1......................................................................................181
8.4.1
8.4.2
8.4.3
Operation as interval timer ...........................................................................................................181
Operation as PWM pulse generator .............................................................................................184
Carrier generator mode operation (8-bit timer H1 only)................................................................190
CHAPTER 9 WATCH TIMER ................................................................................................................197
9.1 Functions of Watch Timer........................................................................................................197
9.2 Configuration of Watch Timer .................................................................................................199
9.3 Register Controlling Watch Timer...........................................................................................199
9.4 Watch Timer Operations ..........................................................................................................201
9.4.1
9.4.2
Watch timer operation ..................................................................................................................201
Interval timer operation.................................................................................................................202
CHAPTER 10 WATCHDOG TIMER ......................................................................................................204
10.1 Functions of Watchdog Timer .................................................................................................204
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Preliminary User’s Manual U16227EJ1V0UD
10.2 Configuration of Watchdog Timer.......................................................................................... 206
10.3 Registers Controlling Watchdog Timer ................................................................................. 207
10.4 Operation of Watchdog Timer................................................................................................. 209
10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by a mask option .. 209
10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected
by mask option............................................................................................................................. 210
10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is
selected by mask option)............................................................................................................. 211
10.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped by software” is
selected by mask option)............................................................................................................. 213
CHAPTER 11 A/D CONVERTER ......................................................................................................... 214
11.1 Functions of A/D Converter .................................................................................................... 214
11.2 Configuration of A/D Converter.............................................................................................. 216
11.3 Registers Controlling A/D Converter ..................................................................................... 218
11.4 A/D Converter Operations....................................................................................................... 222
11.4.1 Basic operations of A/D converter ............................................................................................... 222
11.4.2 Input voltage and conversion results ........................................................................................... 224
11.4.3 A/D converter operation mode..................................................................................................... 225
11.5 How to Read A/D Converter Characteristics Table............................................................... 228
11.6 Cautions for A/D Converter..................................................................................................... 230
CHAPTER 12 SERIAL INTERFACE UART0 ...................................................................................... 235
12.1 Functions of Serial Interface UART0...................................................................................... 235
12.2 Configuration of Serial Interface UART0 ............................................................................... 236
12.3 Registers Controlling Serial Interface UART0....................................................................... 239
12.4 Operation of Serial Interface UART0...................................................................................... 243
12.4.1 Operation stop mode ................................................................................................................... 243
12.4.2 Asynchronous serial interface (UART) mode............................................................................... 244
12.4.3 Dedicated baud rate generator .................................................................................................... 252
CHAPTER 13 SERIAL INTERFACE UART6 ...................................................................................... 258
13.1 Functions of Serial Interface UART6...................................................................................... 258
13.2 Configuration of Serial Interface UART6 ............................................................................... 262
13.3 Registers Controlling Serial Interface UART6....................................................................... 265
13.4 Operation of Serial Interface UART6...................................................................................... 273
13.4.1 Operation stop mode ................................................................................................................... 273
13.4.2 Asynchronous serial interface (UART) mode............................................................................... 274
13.4.3 Dedicated baud rate generator .................................................................................................... 292
CHAPTER 14 SERIAL INTERFACE CSI10 ........................................................................................ 301
14.1 Functions of Serial Interface CSI10........................................................................................ 301
14.2 Configuration of Serial Interface CSI10 ................................................................................. 301
14.3 Registers Controlling Serial Interface CSI10......................................................................... 303
14.4 Operation of Serial Interface CSI10........................................................................................ 305
14.4.1 Operation stop mode ................................................................................................................... 305
14.4.2 3-wire serial I/O mode.................................................................................................................. 306
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Preliminary User’s Manual U16227EJ1V0UD
CHAPTER 15 INTERRUPT FUNCTIONS .............................................................................................314
15.1 Interrupt Function Types..........................................................................................................314
15.2 Interrupt Sources and Configuration......................................................................................314
15.3 Registers Controlling Interrupt Functions .............................................................................317
15.4 Interrupt Servicing Operations................................................................................................324
15.4.1 Maskable interrupt acknowledgement ..........................................................................................324
15.4.2 Software interrupt request acknowledgement ..............................................................................326
15.4.3 Multiple interrupt servicing............................................................................................................327
15.4.4 Interrupt request hold ...................................................................................................................330
CHAPTER 16 KEY INTERRUPT FUNCTION ......................................................................................331
16.1 Functions of Key Interrupt.......................................................................................................331
16.2 Configuration of Key Interrupt.................................................................................................331
16.3 Register Controlling Key Interrupt..........................................................................................332
CHAPTER 17 STANDBY FUNCTION...................................................................................................333
17.1 Standby Function and Configuration .....................................................................................333
17.1.1 Standby function...........................................................................................................................333
17.1.2 Registers controlling standby function..........................................................................................335
17.2 Standby Function Operation....................................................................................................337
17.2.1 HALT mode ..................................................................................................................................337
17.2.2 STOP mode..................................................................................................................................341
CHAPTER 18 RESET FUNCTION ........................................................................................................344
18.1 Register for Confirming Reset Source ...................................................................................349
CHAPTER 19 CLOCK MONITOR .........................................................................................................350
19.1 Functions of Clock Monitor .....................................................................................................350
19.2 Configuration of Clock Monitor...............................................................................................350
19.3 Registers Controlling Clock Monitor ......................................................................................351
19.4 Operation of Clock Monitor......................................................................................................352
CHAPTER 20 POWER-ON-CLEAR CIRCUIT ......................................................................................356
20.1 Functions of Power-on-Clear Circuit ......................................................................................356
20.2 Configuration of Power-on-Clear Circuit................................................................................357
20.3 Operation of Power-on-Clear Circuit ......................................................................................357
20.4 Cautions for Power-on-Clear Circuit.......................................................................................358
CHAPTER 21 LOW-VOLTAGE DETECTOR........................................................................................360
21.1 Functions of Low-Voltage Detector ........................................................................................360
21.2 Configuration of Low-Voltage Detector..................................................................................360
21.3 Registers Controlling Low-Voltage Detector .........................................................................361
21.4 Operation of Low-Voltage Detector.........................................................................................364
21.5 Cautions for Low-Voltage Detector.........................................................................................368
13
Preliminary User’s Manual U16227EJ1V0UD
CHAPTER 22 MASK OPTIONS ........................................................................................................... 372
CHAPTER 23 µPD78F0114................................................................................................................... 373
23.1 Internal Memory Size Switching Register.............................................................................. 374
23.2 Flash Memory Programming................................................................................................... 375
23.2.1 Selection of communication mode............................................................................................... 375
23.2.2 Flash memory programming function .......................................................................................... 376
23.2.3 Connecting Flashpro III/Flashpro IV ............................................................................................ 377
23.2.4 Connection on adapter for flash memory writing.......................................................................... 379
CHAPTER 24 INSTRUCTION SET....................................................................................................... 384
24.1 Conventions Used in Operation List...................................................................................... 384
24.1.1 Operand identifiers and specification methods............................................................................ 384
24.1.2 Description of operation column .................................................................................................. 385
24.1.3 Description of flag operation column............................................................................................ 385
24.2 Operation List........................................................................................................................... 386
24.3 Instructions Listed by Addressing Type................................................................................ 394
CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)............................................. 397
CHAPTER 26 PACKAGE DRAWING................................................................................................... 413
CHAPTER 27 CAUTIONS FOR WAIT................................................................................................. 414
27.1 Cautions for Wait...................................................................................................................... 414
27.2 Peripheral Hardware That Generates Wait ............................................................................ 415
27.3 Example of Wait Occurrence .................................................................................................. 416
APPENDIX A DEVELOPMENT TOOLS............................................................................................... 417
A.1 Software Package..................................................................................................................... 419
A.2 Language Processing Software.............................................................................................. 420
A.3 Flash Memory Writing Tools................................................................................................... 421
A.4 Debugging Tools...................................................................................................................... 422
A.4.1 Hardware..................................................................................................................................... 422
A.4.2 Software ...................................................................................................................................... 423
APPENDIX B EMBEDDED SOFTWARE ............................................................................................. 424
APPENDIX C REGISTER INDEX ......................................................................................................... 425
C.1 Register Index (In Alphabetical Order with Respect to Register Names) .......................... 425
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ......................... 428
14
Preliminary User’s Manual U16227EJ1V0UD
LIST OF FIGURES (1/7)
Figure No.
2-1
Title
Page
Pin I/O Circuit List ....................................................................................................................................44
3-1
Memory Map (µPD780111)......................................................................................................................47
Memory Map (µPD780112)......................................................................................................................48
Memory Map (µPD780113)......................................................................................................................49
Memory Map (µPD780114)......................................................................................................................50
Memory Map (µPD78F0114)....................................................................................................................51
Data Memory Addressing (µPD780111) ..................................................................................................54
Data Memory Addressing (µPD780112) ..................................................................................................55
Data Memory Addressing (µPD780113) ..................................................................................................56
Data Memory Addressing (µPD780114) ..................................................................................................57
Data Memory Addressing (µPD78F0114) ................................................................................................58
Format of Program Counter .....................................................................................................................59
Format of Program Status Word ..............................................................................................................59
Format of Stack Pointer ...........................................................................................................................61
Data to Be Saved to Stack Memory .........................................................................................................61
Data to Be Restored from Stack Memory.................................................................................................61
Configuration of General-Purpose Registers............................................................................................62
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
4-1
Port Types................................................................................................................................................78
Block Diagram of P00 ..............................................................................................................................81
Block Diagram of P01 ..............................................................................................................................82
Block Diagram of P10 ..............................................................................................................................83
Block Diagram of P11 and P14 ................................................................................................................84
Block Diagram of P12 ..............................................................................................................................85
Block Diagram of P13 ..............................................................................................................................86
Block Diagram of P15 ..............................................................................................................................87
Block Diagram of P16 and P17 ................................................................................................................88
Block Diagram of P20 to P27 ...................................................................................................................89
Block Diagram of P30 to P32 ...................................................................................................................90
Block Diagram of P33 ..............................................................................................................................91
Block Diagram of P60 to P63 ...................................................................................................................92
Block Diagram of P70 to P73 ...................................................................................................................93
Block Diagram of P120 ............................................................................................................................94
Block Diagram of P130 ............................................................................................................................95
Format of Port Mode Register..................................................................................................................96
Format of Pull-up Resistor Option Register..............................................................................................98
Format of Input Switch Control Register (ISC) .........................................................................................99
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
5-1
5-2
5-3
5-4
5-5
Block Diagram of Clock Generator.........................................................................................................102
Subsystem Clock Feedback Resistor.....................................................................................................103
Format of Processor Clock Control Register (PCC)...............................................................................104
Format of Ring-OSC Mode Register (RCM)...........................................................................................105
Format of Main Clock Mode Register (MCM).........................................................................................106
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Preliminary User’s Manual U16227EJ1V0UD
LIST OF FIGURES (2/7)
Figure No.
Title
Page
5-6
Format of Main OSC Control Register (MOC)........................................................................................107
Format of Oscillation Stabilization Time Counter Status Register (OSTC).............................................107
Format of Oscillation Stabilization Time Select Register (OSTS)...........................................................108
External Circuit of X1 Oscillator..............................................................................................................109
External Circuit of Subsystem Clock Oscillator.......................................................................................109
Examples of Incorrect Resonator Connection ........................................................................................110
Timing Diagram of CPU Default Start Using Ring-OSC .........................................................................113
Status Transition Diagram......................................................................................................................114
Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)..............................................................121
Switching from X1 Input Clock to Ring-OSC Clock (Flowchart)..............................................................122
Switching from X1 Input Clock to Subsystem Clock (Flowchart) ............................................................123
Switching from Subsystem Clock to X1 Input Clock (Flowchart) ............................................................124
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
6-1
Block Diagram of 16-Bit Timer/Event Counter 00...................................................................................127
Format of 16-Bit Timer Mode Control Register 00 (TMC00)...................................................................131
Format of Capture/Compare Control Register 00 (CRC00)....................................................................132
Format of 16-Bit Timer Output Control Register 00 (TOC00) .................................................................133
Format of Prescaler Mode Register 00 (PRM00) ...................................................................................134
Format of Port Mode Register 0 (PM0)...................................................................................................135
Control Register Settings for Interval Timer Operation...........................................................................136
Interval Timer Configuration Diagram.....................................................................................................137
Timing of Interval Timer Operation.........................................................................................................137
Control Register Settings for PPG Output Operation .............................................................................138
Configuration of PPG Output..................................................................................................................139
PPG Output Operation Timing................................................................................................................139
Control Register Settings for Pulse Width Measurement with Free-Running Counter
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
and One Capture Register......................................................................................................................140
Configuration Diagram for Pulse Width Measurement with Free-Running Counter................................141
Timing of Pulse Width Measurement Operation with Free-Running Counter
6-14
6-15
and One Capture Register (with Both Edges Specified).........................................................................141
Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter ..............142
CR010 Capture Operation with Rising Edge Specified ..........................................................................143
Timing of Pulse Width Measurement Operation with Free-Running Counter
6-16
6-17
6-18
(with Both Edges Specified) ...................................................................................................................143
Control Register Settings for Pulse Width Measurement with Free-Running Counter and
6-19
6-20
Two Capture Registers...........................................................................................................................144
Timing of Pulse Width Measurement Operation with Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)......................................................................145
Control Register Settings for Pulse Width Measurement by Means of Restart.......................................146
Timing of Pulse Width Measurement Operation by Means of Restart
6-21
6-22
(with Rising Edge Specified)...................................................................................................................146
Control Register Settings in External Event Counter Mode....................................................................147
Configuration Diagram of External Event Counter..................................................................................148
External Event Counter Operation Timing (with Rising Edge Specified) ................................................148
6-23
6-24
6-25
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LIST OF FIGURES (3/7)
Figure No.
Title
Page
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
Control Register Settings in Square-Wave Output Mode.......................................................................149
Square-Wave Output Operation Timing.................................................................................................149
Control Register Settings for One-Shot Pulse Output with Software Trigger .........................................151
Timing of One-Shot Pulse Output Operation with Software Trigger.......................................................152
Control Register Settings for One-Shot Pulse Output with External Trigger ..........................................153
Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) ..........154
Start Timing of 16-Bit Timer Counter 00 (TM00) ....................................................................................155
Timings After Change of Compare Register During Timer Count Operation..........................................155
Capture Register Data Retention Timing ...............................................................................................156
Operation Timing of OVF00 Flag ...........................................................................................................157
7-1
Block Diagram of 8-Bit Timer/Event Counter 50.....................................................................................159
Block Diagram of 8-Bit Timer/Event Counter 51.....................................................................................160
Format of Timer Clock Selection Register 50 (TCL50)...........................................................................162
Format of Timer Clock Selection Register 51 (TCL51)...........................................................................163
Format of 8-Bit Timer Mode Control Register 50 (TMC50) ....................................................................164
Format of 8-Bit Timer Mode Control Register 51 (TMC51) ....................................................................165
Format of Port Mode Register 1 (PM1) ..................................................................................................167
Format of Port Mode Register 3 (PM3) ..................................................................................................167
Interval Timer Operation Timing.............................................................................................................168
External Event Counter Operation Timing (with Rising Edge Specified)................................................170
Square-Wave Output Operation Timing.................................................................................................172
PWM Output Operation Timing ..............................................................................................................174
Timing of Operation with CR5n Changed...............................................................................................175
8-Bit Timer Counter 5n Start Timing.......................................................................................................175
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
8-1
Block Diagram of 8-Bit Timer H0............................................................................................................176
Block Diagram of 8-Bit Timer H1............................................................................................................177
Format of 8-Bit Timer H Mode Register 0 (TMHMD0)............................................................................178
Format of 8-Bit Timer H Mode Register 1 (TMHMD1)............................................................................179
Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)..............................................................180
Register Setting in Interval Timer Mode.................................................................................................181
Timing of Interval Timer Operation.........................................................................................................182
Register Setting in PWM Pulse Generator Mode ...................................................................................184
Operation Timing in PWM Pulse Generator Mode .................................................................................186
Example of Connection Between 8-Bit Timer H1 and 8-Bit Timer/Event Counter 51.............................190
Transfer Timing......................................................................................................................................191
Register Setting in Carrier Generator Mode...........................................................................................192
Carrier Generator Mode Operation Timing.............................................................................................194
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
9-1
9-2
9-3
Watch Timer Block Diagram...................................................................................................................197
Format of Watch Timer Operation Mode Register (WTM)......................................................................200
Operation Timing of Watch Timer/Interval Timer....................................................................................203
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LIST OF FIGURES (4/7)
Figure No.
Title
Page
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
Block Diagram of Watchdog Timer.........................................................................................................206
Format of Watchdog Timer Mode Register (WDTM)..............................................................................207
Format of Watchdog Timer Enable Register (WDTE) ............................................................................208
Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock) ..............................211
Operation in STOP Mode (CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock) ........211
Operation in STOP Mode (CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock) ........212
Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock) ...........................213
Operation in HALT Mode........................................................................................................................213
11-1
Block Diagram of A/D Converter ............................................................................................................214
Block Diagram of Power-Fail Detection Function ...................................................................................215
Format of A/D Conversion Register (ADCR) ..........................................................................................216
Format of A/D Converter Mode Register (ADM).....................................................................................218
Timing Chart When Boost Reference Voltage Generator Is Used..........................................................219
Format of Analog Input Channel Specification Register (ADS) ..............................................................220
Format of Power-Fail Comparison Mode Register (PFM).......................................................................221
Format of Power-Fail Comparison Threshold Register (PFT) ................................................................221
Basic Operation of A/D Converter ..........................................................................................................223
Relationship Between Analog Input Voltage and A/D Conversion Result ..............................................224
A/D Conversion Operation......................................................................................................................225
Power-Fail Detection (When PFEN = 1 and PFCM = 0).........................................................................226
Overall Error...........................................................................................................................................228
Quantization Error ..................................................................................................................................228
Zero-Scale Error.....................................................................................................................................229
Full-Scale Error ......................................................................................................................................229
Integral Linearity Error............................................................................................................................229
Differential Linearity Error.......................................................................................................................229
Circuit Configuration of Series Resistor String .......................................................................................230
Storing Conversion Result in ADCR and Timing of Data Read from ADCR...........................................231
Analog Input Pin Connection..................................................................................................................232
Timing of A/D Conversion End Interrupt Request Generation................................................................233
Timing of A/D Converter Sampling and A/D Conversion Start Delay .....................................................234
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16
11-17
11-18
11-19
11-20
11-21
11-22
11-23
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
Block Diagram of Serial Interface UART0 ..............................................................................................237
Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) .....................................239
Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0) ...........................241
Format of Baud Rate Generator Control Register 0 (BRGC0)................................................................242
Format of Normal UART Transmit/Receive Data ...................................................................................247
Example of Normal UART Transmit/Receive Data Format.....................................................................247
Normal Transmission Completion Interrupt Request Timing ..................................................................249
Reception Completion Interrupt Request Timing....................................................................................250
Noise Filter Circuit..................................................................................................................................251
Configuration of Baud Rate Generator...................................................................................................252
Permissible Baud Rate Range During Reception...................................................................................256
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Preliminary User’s Manual U16227EJ1V0UD
LIST OF FIGURES (5/7)
Figure No.
Title
Page
13-1
LIN Transmission Operation...................................................................................................................259
LIN Reception Operation........................................................................................................................260
Port Configuration for LIN Reception Operation.....................................................................................261
Block Diagram of Serial Interface UART6..............................................................................................263
Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) .....................................265
Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) ...........................267
Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) ...............................268
Format of Clock Selection Register 6 (CKSR6)......................................................................................269
Format of Baud Rate Generator Control Register 6 (BRGC6) ...............................................................270
Format of Asynchronous Serial Interface Control Register 6 (ASICL6)..................................................271
Format of Normal UART Transmit/Receive Data ...................................................................................280
Example of Normal UART Transmit/Receive Data Format ....................................................................281
Normal Transmission Completion Interrupt Request Timing..................................................................283
Processing Flow of Continuous Transmission........................................................................................285
Timing of Starting Continuous Transmission..........................................................................................286
Timing of Ending Continuous Transmission...........................................................................................287
Reception Completion Interrupt Request Timing....................................................................................288
Reception Error Interrupt........................................................................................................................289
Noise Filter Circuit..................................................................................................................................290
SBF Transmission..................................................................................................................................290
SBF Reception.......................................................................................................................................291
Configuration of Baud Rate Generator...................................................................................................293
Permissible Baud Rate Range During Reception...................................................................................298
Transfer Rate During Continuous Transmission ....................................................................................300
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
14-1
14-2
14-3
14-4
14-5
14-6
14-7
Block Diagram of Serial Interface CSI10................................................................................................302
Format of Serial Operation Mode Register 10 (CSIM10) .......................................................................303
Format of Serial Clock Selection Register 10 (CSIC10).........................................................................304
Timing in 3-Wire Serial I/O Mode ...........................................................................................................309
Timing of Clock/Data Phase...................................................................................................................311
Output Operation of First Bit...................................................................................................................312
Output Value of SO10 Pin (Last Bit).......................................................................................................313
15-1
15-2
15-3
15-4
15-5
Basic Configuration of Interrupt Function...............................................................................................316
Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)..............................................................319
Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L)............................................................320
Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L)....................................................321
Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN) ..................................................................322
Format of Program Status Word ............................................................................................................323
Interrupt Request Acknowledgement Processing Algorithm...................................................................325
Interrupt Request Acknowledgement Timing (Minimum Time)...............................................................326
Interrupt Request Acknowledgement Timing (Maximum Time)..............................................................326
Examples of Multiple Interrupt Servicing................................................................................................328
15-6
15-7
15-8
15-9
15-10
19
Preliminary User’s Manual U16227EJ1V0UD
LIST OF FIGURES (6/7)
Figure No.
15-11
Title
Page
Interrupt Request Hold ...........................................................................................................................330
16-1
16-2
Block Diagram of Key Interrupt...............................................................................................................331
Format of Key Return Mode Register (KRM)..........................................................................................332
17-1
17-2
17-3
17-4
17-5
17-6
17-7
Operation Timing When STOP Mode Is Released.................................................................................334
Format of Oscillation Stabilization Time Counter Status Register (OSTC).............................................335
Format of Oscillation Stabilization Time Select Register (OSTS)...........................................................336
HALT Mode Release by Interrupt Request Generation..........................................................................339
HALT Mode Release by RESET Input ...................................................................................................340
STOP Mode Release by Interrupt Request Generation .........................................................................342
STOP Mode Release by RESET Input...................................................................................................343
18-1
18-2
18-3
18-4
18-5
Block Diagram of Reset Function...........................................................................................................345
Timing of Reset by RESET Input............................................................................................................346
Timing of Reset Due to Watchdog Timer Overflow ................................................................................346
Timing of Reset in STOP Mode by RESET Input ...................................................................................346
Format of Reset Control Flag Register (RESF)......................................................................................349
19-1
19-2
19-3
Block Diagram of Clock Monitor .............................................................................................................350
Format of Clock Monitor Mode Register (CLM)......................................................................................351
Timing of Clock Monitor..........................................................................................................................353
20-1
20-2
20-3
Block Diagram of Power-on-Clear Circuit...............................................................................................357
Timing of Internal Reset Signal Generation in Power-on-Clear Circuit...................................................357
Example of Software Processing After Release of Reset.......................................................................358
21-1
21-2
21-3
21-4
21-5
21-6
21-7
Block Diagram of Low-Voltage Detector.................................................................................................360
Format of Low-Voltage Detection Register (LVIM).................................................................................362
Format of Low-Voltage Detection Level Selection Register (LVIS) ........................................................363
Timing of Low-Voltage Detector Internal Reset Signal Generation ........................................................365
Timing of Low-Voltage Detector Interrupt Signal Generation .................................................................367
Example of Software Processing After Release of Reset.......................................................................369
Example of Software Processing of LVI Interrupt...................................................................................371
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
Format of Internal Memory Size Switching Register (IMS).....................................................................374
Communication Mode Selection Format.................................................................................................376
Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode..........................................................377
Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode (Using Handshake) ..........................377
Connection of Flashpro III/Flashpro IV in UART (UART0) Mode............................................................378
Connection of Flashpro III/Flashpro IV in UART (UART0) Mode (Using Handshake)............................378
Connection of Flashpro III/Flashpro IV in UART (UART6) Mode............................................................378
Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode...................................379
Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode (Using Handshake) ...380
20
Preliminary User’s Manual U16227EJ1V0UD
LIST OF FIGURES (7/7)
Figure No.
Title
Page
23-10
23-11
23-12
Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode ....................................381
Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode (Using Handshake).....382
Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode ....................................383
A-1
Development Tool Configuration............................................................................................................418
21
Preliminary User’s Manual U16227EJ1V0UD
LIST OF TABLES (1/3)
Table No.
Title
Page
1-1
2-1
Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions...................................28
Pin I/O Circuit Types ................................................................................................................................43
3-1
3-2
3-3
3-4
3-5
Set Value of Internal Memory Size Switching Register (IMS)...................................................................46
Internal Memory Capacity.........................................................................................................................52
Vector Table.............................................................................................................................................52
Internal High-Speed RAM Capacity..........................................................................................................53
Special Function Register List..................................................................................................................64
4-1
4-2
4-3
4-4
Port Functions ..........................................................................................................................................79
Port Configuration ....................................................................................................................................80
Pull-up Resistor of Port 6..........................................................................................................................92
Settings of Port Mode Register and Output Latch When Using Alternate Function..................................97
5-1
5-2
5-3
5-4
5-5
5-6
5-7
Configuration of Clock Generator...........................................................................................................102
Relationship Between CPU Clock and Minimum Instruction Execution Time.........................................105
Relationship Between Operation Clocks in Each Operation Status........................................................118
Oscillation Control Flags and Clock Oscillation Status...........................................................................118
Time Required to Switch Between Ring-OSC Clock and X1 Input Clock...............................................119
Maximum Time Required for CPU Clock Switchover .............................................................................120
Clock and Register Setting.....................................................................................................................125
6-1
6-2
6-3
Configuration of 16-Bit Timer/Event Counter 00.....................................................................................127
TI000 Pin Valid Edge and CR000, CR010 Capture Trigger....................................................................128
TI010 Pin Valid Edge and CR000 Capture Trigger.................................................................................128
7-1
8-1
Configuration of 8-Bit Timer/Event Counters 50 and 51.........................................................................161
Configuration of 8-Bit Timers H0 and H1................................................................................................176
9-1
9-2
9-3
9-4
9-5
Watch Timer Interrupt Time....................................................................................................................198
Interval Timer Interval Time....................................................................................................................198
Watch Timer Configuration.....................................................................................................................199
Watch Timer Interrupt Time....................................................................................................................201
Interval Timer Interval Time....................................................................................................................202
10-1
10-2
10-3
Loop Detection Time of Watchdog Timer ...............................................................................................204
Mask Option Setting and Watchdog Timer Operation Mode ..................................................................205
Configuration of Watchdog Timer...........................................................................................................206
11-1
11-2
11-3
Configuration of A/D Converter ..............................................................................................................216
Settings of ADCS and ADCE..................................................................................................................219
A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value) .......................234
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Table No.
Title
Page
12-1
12-2
12-3
12-4
Configuration of Serial Interface UART0................................................................................................236
Cause of Reception Error.......................................................................................................................251
Set Data of Baud Rate Generator ..........................................................................................................255
Maximum/Minimum Permissible Baud Rate Error..................................................................................257
13-1
13-2
13-3
13-4
13-5
Configuration of Serial Interface UART6................................................................................................262
Write Processing and Writing to TXB6 During Execution of Continuous Transmission..........................284
Cause of Reception Error.......................................................................................................................289
Set Data of Baud Rate Generator ..........................................................................................................297
Maximum/Minimum Permissible Baud Rate Error..................................................................................299
14-1
Configuration of Serial Interface CSI10..................................................................................................301
15-1
15-2
15-3
15-4
15-5
Interrupt Source List...............................................................................................................................315
Flags Corresponding to Interrupt Request Sources ...............................................................................318
Ports Corresponding to EGPn and EGNn..............................................................................................322
Time from Generation of Maskable Interrupt Until Servicing..................................................................324
Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing ...........................327
16-1
16-2
Assignment of Key Interrupt Detection Pins...........................................................................................331
Configuration of Key Interrupt ................................................................................................................331
17-1
17-2
17-3
17-4
17-5
Relationship Between HALT Mode, STOP Mode, and Clock.................................................................333
Operating Statuses in HALT Mode.........................................................................................................337
Operation After HALT Mode Release.....................................................................................................340
Operating Statuses in STOP Mode........................................................................................................341
Operation After STOP Mode Release....................................................................................................343
18-1
18-2
Hardware Statuses After Reset..............................................................................................................347
RESF Status When Reset Request Is Generated..................................................................................349
19-1
19-2
Configuration of Clock Monitor...............................................................................................................350
Operation Status of Clock Monitor (When CLME = 1)............................................................................352
22-1
Flash Memory Versions Supporting Mask Options of Mask ROM Versions...........................................372
23-1
23-2
23-3
23-4
Differences Between µPD78F0114 and Mask ROM Versions ...............................................................373
Internal Memory Size Switching Register Settings.................................................................................374
Communication Mode List......................................................................................................................375
Main Functions of Flash Memory Programming.....................................................................................376
24-1
Operand Identifiers and Specification Methods......................................................................................384
23
Preliminary User’s Manual U16227EJ1V0UD
LIST OF TABLES (3/3)
Table No.
Title
Page
27-1
27-2
Registers That Generate Wait and Number of CPU Wait Clocks...........................................................415
Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter) .......416
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Preliminary User’s Manual U16227EJ1V0UD
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1.1 Features
{ ROM, RAM capacities
Item
Program Memory
(ROM)
Data Memory
(Internal High-Speed RAM)
Part Number
µPD780111
µPD780112
µPD780113
µPD780114
µPD78F0114
Mask ROM
8 KB
512 bytes
16 KB
24 KB
32 KB
32 KBNote
1024 bytes
Flash memory
1024 bytesNote
Note The internal flash memory and internal high-speed RAM capacities can be changed using the internal
memory size switching register (IMS).
{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)
{ Short startup is possible via the CPU default start using the on-chip Ring-OSC
{ On-chip clock monitor function using on-chip Ring-OSC
{ On-chip watchdog timer (operable with Ring-OSC clock)
{ On-chip UART supporting LIN (Local Interconnect Network) bus
{ On-chip key interrupt function
{ Minimum instruction execution time can be changed from high speed (0.2 µs: @ 10 MHz operation with X1
input clock) to ultra low-speed (122 µs: @ 32.768 kHz operation with subsystem clock)
{ I/O ports: 32 (N-ch open drain: 4)
{ Timer: 7 channels
{ Serial interface: 3 channels
(UART: 2 channels, CSI: 1 channel)
{ 10-bit resolution A/D converter: 8 channels
{ Supply voltage: VDD = 2.7 to 5.5 V
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1.2 Applications
{ Automotive equipment
•
•
System control for body electricals (power windows, keyless entry reception, etc.)
Sub-microcontrollers for control
{ Home audio, car audio
{ AV equipment
{ PC peripheral equipment (keyboards, etc.)
{ Household electrical appliances
•
•
Outdoor air conditioner units
Microwave ovens, electric rice cookers
{ Industrial equipment
•
•
•
Pumps
Vending machines
FA
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1.3 Ordering Information
Part Number
Package
Quality Grade
µPD780111GB-×××-8ES
µPD780112GB-×××-8ES
µPD780113GB-×××-8ES
µPD780114GB-×××-8ES
µPD780111GB(A)-×××-8ES
µPD780112GB(A)-×××-8ES
µPD780113GB(A)-×××-8ES
µPD780114GB(A)-×××-8ES
µPD780111GB(A1)-×××-8ES
µPD780112GB(A1)-×××-8ES
µPD780113GB(A1)-×××-8ES
µPD780114GB(A1)-×××-8ES
µPD78F0114M1GB-8ES
µPD78F0114M2GB-8ES
µPD78F0114M3GB-8ES
µPD78F0114M4GB-8ES
µPD78F0114M5GB-8ES
µPD78F0114M6GB-8ES
µPD78F0114M1GB(A)-8ES
µPD78F0114M2GB(A)-8ES
µPD78F0114M3GB(A)-8ES
µPD78F0114M4GB(A)-8ES
µPD78F0114M5GB(A)-8ES
µPD78F0114M6GB(A)-8ES
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
44-pin plastic LQFP (10 × 10)
Standard
Standard
Standard
Standard
Special
Special
Special
Special
Special
Special
Special
Special
Standard
Standard
Standard
Standard
Standard
Standard
Special
Special
Special
Special
Special
Special
Remark ××× indicates ROM code suffix.
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
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Mask ROM versions (µPD780111, 780112, 780113, and 780114) include mask options. When ordering, it is
possible to select “Power-on-clear (POC) circuit can be used/cannot be used”, “Ring-OSC clock can be
stopped/cannot be stopped by software” and “Pull-up resistor incorporated/not incorporated in 1-bit units (P60 to
P63)”.
Flash memory versions corresponding to the mask options of the mask ROM versions are as follows.
Table 1-1. Flash Memory Versions Corresponding to Mask Options of Mask ROM Versions
Mask Option
Flash Memory Versions
(Part Number)
POC Circuit
POC cannot be used
Ring-OSC
Cannot be stopped
µPD78F0114M1GB-8ES
µPD78F0114M1GB(A)-8ES
Can be stopped by software
Cannot be stopped
µPD78F0114M2GB-8ES
µPD78F0114M2GB(A)-8ES
POC used (VPOC = 2.85 V 0.15 V)
POC used (VPOC = 3.5 V 0.2 V)
µPD78F0114M3GB-8ES
µPD78F0114M3GB(A)-8ES
Can be stopped by software
Cannot be stopped
µPD78F0114M4GB-8ES
µPD78F0114M4GB(A)-8ES
µPD78F0114M5GB-8ES
µPD78F0114M5GB(A)-8ES
Can be stopped by software
µPD78F0114M6GB-8ES
µPD78F0114M6GB(A)-8ES
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1.4 Pin Configuration (Top View)
44-pin plastic LQFP (10 × 10)
•
µPD780111GB-×××-8ES, 780112GB-×××-8ES, 780113GB-×××-8ES, 780114GB-×××-8ES,
µPD780111GB(A)-×××-8ES, 780112GB(A)-×××-8ES, 780113GB(A)-×××-8ES,
µPD780114GB(A)-×××-8ES, 780111GB(A1)-×××-8ES, 780112GB(A1)-×××-8ES,
µPD780113GB(A1)-×××-8ES, 780114GB(A1)-×××-8ES, 78F0114M1GB-8ES,
µPD78F0114M2GB-8ES, 78F0114M3GB-8ES, 78F0114M4GB-8ES, 78F0114M5GB-8ES,
µPD78F0114M6GB-8ES, 78F0114M1GB(A)-8ES, 78F0114M2GB(A)-8ES, 78F0114M3GB(A)-8ES,
µPD78F0114M4GB(A)-8ES, 78F0114M5GB(A)-8ES, 78F0114M6GB(A)-8ES
44 43 42 41 40 39 38 37 36 35 34
1
33
32
31
30
29
28
27
26
25
24
23
AVREF
AVSS
P73/KR3
2
P00/TI000
3
IC (VPP
)
P01/TI010/TO00
P10/SCK10/TxD0
P11/SI10/RxD0
P12/SO10
4
VDD
5
VSS
6
X1
X2
7
P13/TxD6
8
RESET
XT1
P14/RxD6
9
P15/TOH0
10
11
XT2
P16/TOH1/INTP5
EVDD
P130
12 13 14 15 16 17 18 19 20 21 22
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. Connect the AVREF pin to VDD.
3. Connect the AVSS pin to VSS.
Remark Figures in parentheses apply only to the µPD78F0114.
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Pin Identification
ANI0 to ANI7:
AVREF:
AVSS:
Analog input
RESET:
Reset
Analog reference voltage
Analog ground
RxD0, RxD6:
Receive data
SCK10:
Serial clock input/output
Serial data input
Serial data output
EVDD:
Power supply for port
Ground for port
SI10:
EVSS:
SO10:
IC:
Internally connected
TI000, TI010,
TI50, TI51:
TO00, TO50, TO51,
TOH0, TOH1:
TxD0, TxD6:
VDD:
INTP0 to INTP5: External interrupt input
Timer input
KR0 to KR3:
P00, P01:
P10 to P17:
P20 to P27:
P30 to P33:
P60 to P63:
P70 to P73:
P120:
Key return
Port 0
Timer output
Port 1
Transmit data
Port 2
Power supply
Port 3
VPP:
Programming power supply
Ground
Port 6
VSS:
Port 7
X1, X2:
Crystal (X1 input clock)
Crystal (Subsystem clock)
Port 12
Port 13
XT1, XT2:
P130:
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CHAPTER 1 OUTLINE
1.5 78K0/Kxx Series Lineup
The lineup of products in the 78K0/Kxx Series (under development or in planning) is shown below.
78K0/KB1 Series: 30-pin (7.62 mm 0.65 mm pitch)
µ
PD78F0103
PD780103
Flash memory: 24 KB, RAM: 768 bytes
Mask ROM: 24 KB, RAM: 768 bytes
Mask ROM: 16 KB, RAM: 768 bytes
µ
PD780102
µ
Mask ROM: 8 KB, RAM: 512 bytes
PD780101
µ
78K0/KC1 Series: 44-pin (10 × 10 mm 0.8 mm pitch)
PD78F0114
Flash memory: 32 KB, RAM: 1 KB
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
µ
µ
PD780114
PD780113
µ
Mask ROM: 16 KB, RAM: 512 bytes
Mask ROM: 8 KB, RAM: 512 bytes
PD780112
µ
PD780111
µ
78K0/KD1 Series: 52-pin (10 × 10 mm 0.65 mm pitch)
PD78F0124
Flash memory: 32 KB, RAM: 1 KB
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
µ
PD780124
µ
µ
PD780123
PD780122
Mask ROM: 16 KB, RAM: 512 bytes
Mask ROM: 8 KB, RAM: 512 bytes
µ
µ
PD780121
78K0/KE1 Series: 64-pin (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch)
PD78F0134
Flash memory: 32 KB, RAM: 1 KB
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
µ
PD78F0138
PD780138
Flash memory: 60 KB, RAM: 2 KB
Mask ROM: 60 KB, RAM: 2 KB
µ
PD780134
µ
µ
PD780133
µ
PD780136
Mask ROM: 48 KB, RAM: 2 KB
µ
Mask ROM: 16 KB, RAM: 512 bytes
Mask ROM: 8 KB, RAM: 512 bytes
µ
PD780132
PD780131
µ
78K0/KF1 Series: 80-pin (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch)
PD78F0148
Flash memory: 60 KB, RAM: 2 KB
Mask ROM: 60 KB, RAM: 2 KB
Mask ROM: 48 KB, RAM: 2 KB
µ
µ
PD780148
PD780146
PD780144
µ
Mask ROM: 32 KB, RAM: 1 KB
Mask ROM: 24 KB, RAM: 1 KB
µ
PD780143
µ
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The function list in the 78K0/Kxx Series (under development or in planning) is shown below.
Part Number
78K0/KB1
78K0/KC1
78K0/KD1
52 pins
78K0/KE1
78K0/KF1
80 pins
Item
Package
30 pins
44 pins
24 K
64 pins
Internal
memory
(bytes)
Mask ROM
8 K
16 K
24 K
−
8 K
−
8 K 24 K
−
8 K 24 K
16 K 32 K
−
48 K
−
24 K 48 K
32 K 60 K
−
16 K 32 K
16 K 32 K
60 K
Flash memory
RAM
−
24 K
−
32 K
−
32 K
−
32 K
−
60 K
−
60 K
512
768
512
1 K
512
1 K
DD = 2.7 to 5.5 V
<Connect REGC pin to VDD
0.24 µs (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.2 µs (when 10 MHz, VDD = 4.0 to 5.5 V)
512
1 K
2 K
1 K
2 K
Power supply voltage
V
Minimum instruction
execution time
0.2 µs (when 10 MHz, VDD = 4.0 to 5.5 V)
>
0.4 µs (when 5 MHz, VDD = 2.7 to 5.5 V)
0.24 µs (when 8.38 MHz, VDD = 3.3 to 5.5 V)
0.4 µs (when 5 MHz, VDD = 2.7 to 5.5 V)
Clock
Port
X1 input
2 to 10 MHz
32.768 kHz
Sub
−
Ring-OSC
CMOS I/O
CMOS input
CMOS output
240 kHz (TYP.)
17
4
19
26
38
54
8
4
1
N-ch open-drain
I/O
−
Timer
16 bits (TM0)
8 bits (TM5)
8 bits (TMH)
For watch
WDT
1 ch
2 ch
1 ch
2 ch
1 ch
2 ch
1 ch
2 ch
1 ch
−
Serial
3-wire CSI
1 ch
2 ch
1 ch
2 ch
1 ch
interface
Automatic
−
transmit/receive
3-wire CSI
UART
−
1 ch
UART
1 ch
supporting LIN-
bus
10-bit A/D converter
4 ch
6
8 ch
Interrupt
External
Internal
7
8
9
9
11
12
15
16
19
8 ch
17
20
Key return input
Reset RESET pin
−
4 ch
Provided
2.85 V 0.15 V/3.5 V 0.20 V (selectable by mask option)
POC
LVI
3.1 V 0.15 V/3.3 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V 0.2 V (selectable by software)
Clock monitor
WDT
Provided
Provided
Multiplier/divider
ROM correction
Standby function
−
16 bits × 16 bits, 32 bits ÷ 16 bits
−
Provided
−
HALT/STOP mode
Standard products, special (A) products: −40 to +85°C
Special (A1) products: −40 to +110°C (mask ROM version only)
Operating ambient
temperature
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1.6 Block Diagram
TO00/TI010/P01
TI000/P00
16-bit timer/
event counter 00
2
8
8
4
Port 0
Port 1
Port 2
Port 3
P00, P01
P10 to P17
P20 to P27
P30 to P33
TOH0/P15
TOH1/P16
8-bit timer H0
8-bit timer H1
4
4
Port 6
Port 7
P60 to P63
P70 to P73
P120
8-bit timer/
event counter 50
TI50/TO50/P17
TI51/TO51/P33
8-bit timer/
event counter 51
78K/0
CPU
core
ROM
(Flash
memory)
Port 12
Port 13
Watch timer
P130
Watchdog timer
Clock monitor
Power on clear/
low voltage
indicator
Serial
interface UART0
RxD0/P11
TxD0/P10
Internal
high-speed
RAM
KR0/P70 to
KR3/P73
RxD6/P14
TxD6/P13
Serial
interface UART6
Key return
4
SI10/P11
SO10/P12
SCK10/P10
Reset control
Serial
interface CSI10
Ring-OSC
ANI0/P20 to
8
ANI7/P27
A/D converter
AVREF
AVSS
RESET
X1
V
DD
,
V
SS
,
IC
X2
XT1
XT2
EVDD EVSS (VPP
)
System control
INTP0/P120
INTP1/P30 to
4
Interrupt control
INTP4/P33
INTP5/P16
Remark Items in parentheses are available only in the µPD78F0114.
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1.7 Outline of Functions
Item
µPD780111
8 KB
µPD780112
16 KB
µPD780113
24 KB
µPD780114
32 KB
µPD78F0114
32 KBNote
Internal memory
ROM
(flash memory)
High-speed RAM 512 bytes
64 KB
1 KB
1 KBNote
Memory space
X1 input clock (oscillation frequency)
Ceramic/crystal/external clock oscillation
(10 MHz: VDD = 4.0 to 5.5 V, 8.38 MHz: VDD = 3.3 to 5.5 V, 5 MHz: VDD = 2.7 to 5.5 V)
Ring-OSC clock
On-chip Ring oscillation (240 kHz (TYP.))
(oscillation frequency)
Subsystem clock
Crystal/external clock oscillation (32.768 kHz)
(oscillation frequency)
General-purpose registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time
0.2 µs/0.4 µs/0.8 µs/1.6 µs/3.2 µs (X1 input clock: @ fXP = 10 MHz operation)
8.3 µs/16.6 µs/33.2 µs/66.4 µs/132.8 µs (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.)
operation)
122 µs (subsystem clock: when operating at fXT = 32.768 kHz)
Instruction set
I/O ports
• 16-bit operation • Multiply/divide (8 bits × 8 bits × 4 banks)
• Bit manipulate (set, reset, test, and Boolean operation) • BCD adjust, etc.
Total:
32
CMOS I/O
19
8
CMOS input
CMOS output
N-ch open-drain I/O
1
4
Timers
• 16-bit timer/event counter: 1 channel
• 8-bit timer/event counter: 2 channels
• 8-bit timer:
2 channels
1 channel
1 channel
• Watch timer
• Watchdog timer:
Timer outputs
A/D converter
Serial interface
5 (PWM output: 3)
10-bit resolution × 8 channels
• UART mode supporting LIN-bus:
• 3-wire serial I/O mode:
• UART mode:
1 channel
1 channel
1 channel
Vectored interrupt Internal
15
7
sources
External
Key interrupt
Reset
Key interrupt (INTKR) occurs by detecting falling edge of key input pins (KR0 to KR3).
• Reset using RESET pin
• Internal reset by watchdog timer
• Internal reset by clock monitor
• Internal reset by power-on-clear
• Internal reset by low-voltage detector
Supply voltage
VDD = 2.7 to 5.5 V
Operating ambient temperature
Standard products, (A) products: TA = −40 to +85°C
(A1) products: TA = −40 to +110°C (µPD780111, 780112, 780113, and 780114 only)
Package
• 44-pin plastic LQFP (10 × 10)
Note The internal flash memory capacity and internal high-speed RAM capacity can be changed using the internal
memory size switching register (IMS).
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An outline of the timer is shown below.
16-Bit Timer/
8-Bit Timer/
8-Bit Timers H0
and H1
Watch Timer
Watchdog Timer
Event Counter 00 Event Counters
50 and 51
Operation Interval timer
mode
1 channel
1 channel
1 output
1 output
−
2 channels
2 channels
2 outputs
−
2 channels
1 channelNote
1 channel
External event counter
−
−
−
−
−
−
−
1
−
−
−
−
−
−
−
Function
Timer output
2 outputs
PPG output
−
PWM output
2 outputs
−
2 outputs
Pulse width measurement
Square-wave output
Interrupt source
2 inputs
1 output
2
−
−
2
2 outputs
2
Note In the watch timer, the watch timer function and interval timer function can be used simultaneously.
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CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
(1) Port pins
Pin Name
I/O
Function
After Reset Alternate Function
P00
P01
I/O
Port 0.
Input
TI000
2-bit I/O port.
TI010/TO00
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
P11
P12
P13
P14
P15
P16
P17
I/O
Port 1.
Input
SCK10/TxD0
SI10/RxD0
SO10
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
TxD6
RxD6
TOH0
TOH1/INTP5
TI50/TO50
ANI0 to ANI7
P20 to P27
Input
I/O
Port 2.
Input
Input
8-bit input-only port.
P30 to P32
P33
Port 3.
INTP1 to INTP3
4-bit I/O port.
INTP4/TI51/TO51
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60 to P63
P70 to P73
I/O
I/O
Port 6.
Input
Input
−
4-bit I/O port (N-ch open drain).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a mask
option only for mask ROM versions.
Port 7.
KR0 to KR3
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
P130
I/O
Port 12.
Input
INTP0
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Output
Port 13.
Output
−
1-bit output-only port.
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CHAPTER 2 PIN FUNCTIONS
(2) Non-port pins
Pin Name
I/O
Input
Function
After Reset Alternate Function
INTP0
INTP1 to INTP3
INTP4
INTP5
SI10
External interrupt request input for which the valid edge (rising Input
edge, falling edge, or both rising and falling edges) can be
specified
P120
P30 to P32
P33/TI51/TO51
P16/TOH1
P11/RxD0
P12
Input
Serial data input to serial interface
Input
Input
Input
Input
SO10
Output
I/O
Serial data output from serial interface
Clock input/output for serial interface
Serial data input to asynchronous serial interface
SCK10
RxD0
P10/TxD0
P11/SI10
P14
Input
RxD6
TxD0
Output
Input
Serial data output from asynchronous serial interface
Input
Input
P10/SCK10
P13
TxD6
TI000
External count clock input to 16-bit timer/event counter 00
Capture trigger input to capture registers (CR000, CR010) of
16-bit timer/event counter 00
P00
TI010
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
P01/TO00
TO00
TI50
Output
Input
16-bit timer/event counter 00 output
External count clock input to 8-bit timer/event counter 50
External count clock input to 8-bit timer/event counter 51
8-bit timer/event counter 50 output
8-bit timer/event counter 51 output
8-bit timer H0 output
Input
Input
P01/TI010
P17/TO50
P33/TO51/INTP4
P17/TI50
P33/TI51/INTP4
P15
TI51
TO50
TO51
TOH0
TOH1
ANI0 to ANI7
AVREF
AVSS
Output
Input
8-bit timer H1 output
P16/INTP5
P20 to P27
−
Input
Input
−
A/D converter analog input
Input
Input
A/D converter reference voltage input
−
−
A/D converter ground potential. Make the same potential as
EVSS or VSS.
−
KR0 to KR3
RESET
X1
Input
Key interrupt input
P70 to P73
Input
System reset input
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Input
Connecting crystal resonator for X1 input clock oscillation
X2
−
XT1
Input
Connecting crystal resonator for subsystem clock oscillation
XT2
−
−
−
−
−
−
−
VDD
Positive power supply (except for ports)
Positive power supply for ports
EVDD
VSS
Ground potential (except for ports)
Ground potential for ports
EVSS
IC
Internally connected. Connect directly to EVSS or VSS.
VPP
Flash memory programming mode setting. High-voltage
application for program write/verify. Connect directly to EVSS
or VSS in normal operation mode.
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2.2 Description of Pin Functions
2.2.1 P00 and P01 (port 0)
P00 and P01 function as a 2-bit I/O port. These pins also function as timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P00 and P01 function as a 2-bit I/O port. P00 to P06 can be set to input or output in 1-bit units using port mode
register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).
(2) Control mode
P00 and P01 function as timer I/O.
(a) TI000
This is the pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a
capture trigger signal to the capture registers (CR000 or CR001) of 16-bit timer/event counter 00.
(b) TI010
This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event
counter 00.
(c) TO00
This is timer output pin.
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2.2.2 P10 to P17 (port 1)
P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial
interface data I/O, clock I/O, and timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode
register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).
(2) Control mode
P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
(a) SI10, SO10
These are serial interface serial data I/O pins.
(b) SCK10
This is the serial interface serial clock I/O pin.
(c) RxD0, RxD6, TxD0, and TxD6
These are the serial data I/O pins of the asynchronous serial interface.
(d) TI50
This is the pin for inputting an external count clock to 8-bit timer/event counter 50.
(e) TO50, TOH0, and TOH1
These are timer output pins.
(f) INTP5
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising
and falling edges) can be specified.
2.2.3 P20 to P27 (port 2)
P20 to P27 function as an 8-bit input-only port. These pins also function as pins for A/D converter analog input.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit input-only port.
(2) Control mode
P20 to P27 function as A/D converter analog input pins (ANI0 to ANI7).
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2.2.4 P30 to P33 (port 3)
P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and
timer I/O.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode
register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
(2) Control mode
P30 to P33 function as external interrupt request input pins and timer I/O pins.
(a) INTP1 to INTP4
These are the external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI51
This is an external count clock input pin to 8-bit timer/event counter 51.
(c) TO51
This is a timer output pin.
2.2.5 P60 to P63 (port 6)
P60 to P63 function as a 4-bit I/O port. P60 to P63 can be set to input port or output port in 1-bit units using port
mode register 6 (PM6).
P60 to P63 are N-ch open-drain pins. Use of an on-chip pull-up resistor can be specified by a mask option only for
mask ROM versions.
2.2.6 P70 to P73 (port 7)
P70 to P73 function as a 4-bit I/O port. These pins also function as key interrupt input pins.
The following operation modes can be specified in 1-bit units.
(1) Port mode
P70 to P73 function as a 4-bit I/O port. P70 to P73 can be set to input or output in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
(2) Control mode
P70 to P73 function as key interrupt input pins.
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2.2.7 P120 (port 12)
P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input.
The following operation modes can be specified.
(1) Port mode
P120 functions as a 1-bit I/O port. P120 can be set to input or output using port mode register 12 (PM12). Use of
an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
(2) Control mode
P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling
edge, or both rising and falling edges) can be specified.
2.2.8 P130 (port 13)
P130 functions as a 1-bit output-only port.
2.2.9 AVREF
This is the A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin to VDD.
2.2.10 AVSS
This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with
the same potential as the EVSS pin or VSS pin.
2.2.11 RESET
This is the active-low system reset input pin.
2.2.12 X1 and X2
These are the pins for connecting a crystal resonator for X1 input clock oscillation.
When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.
2.2.13 XT1 and XT2
These are the pins for connecting a crystal resonator for subsystem clock oscillation.
When supplying an external clock, input a signal to the XT1 pin and input the inverse signal to the XT2 pin.
2.2.14 VDD and EVDD
VDD is the positive power supply pin for other than ports.
EVDD is the positive power supply pin for ports.
2.2.15 VSS and EVSS
VSS is the ground potential pin for other than ports.
EVSS is the ground potential pin for ports.
2.2.16 VPP (flash memory versions only)
This is a pin for flash memory programming mode setting and high-voltage application for program write/verify.
Connect directly to EVSS or VSS in the normal operation mode.
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2.2.17 IC (mask ROM versions only)
The IC (Internally Connected) pin is provided to set the test mode to check the 78K0/KC1 Series at shipment.
Connect it directly to EVSS or VSS pin with the shortest possible wire in the normal operation mode.
When a potential difference is produced between the IC pin and the EVSS or VSS pin because the wiring between
these two pins is too long or external noise is input to the IC pin, the user’s program may not operate normally.
• Connect the IC pin directly to EVSS or VSS.
EVSS or VSS IC
As short as possible
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the types of pin I/O circuits and the recommended connections of unused pins.
Refer to Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-1. Pin I/O Circuit Types
Pin Name
I/O Circuit Type
8-A
I/O
Recommended Connection of Unused Pins
P00/TI000
I/O
Input: Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P01/TI010/TO00
P12/SO10
5-A
P13/TxD6
P14/RxD6
8-A
5-A
8-A
P15/TOH0
P16/TOH1/INTP5
P17/TI50/TO50
P20/ANI0 to P27/ANI7
9-C
8-A
Input
I/O
Connect to EVDD or EVSS.
P30/INTP1 to P32/INTP3
Input: Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P33/TI51/TO51/INTP4
P60, P61 (Mask ROM version)
13-S
13-R
13-W
13-V
8-A
Input: Connect to EVSS.
Output: Leave open and keep this pin to low.
P60, P61 (Flash memory version)
P62, P63 (Mask ROM version)
P62, P63 (Flash memory version)
P70/KR0 to P73/KR3
Input: Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P120/INTP0
P130
RESET
XT1
3-C
2
Output
Input
Leave open.
−
16
Connect directly to EVDD or VDD.
Leave open.
XT2
−
−
−
−
AVREF
AVSS
−
−
−
Connect directly to EVDD or VDD.
Connect directly to EVSS or VSS.
Connect directly to EVSS or VSS.
IC
VPP
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Figure 2-1. Pin I/O Circuit List (1/2)
Type 2
Type 8-A
EVDD
P-ch
Pullup
enable
IN
VDD
Data
P-ch
IN/OUT
Schmitt-triggered input with hysteresis characteristics
Output
disable
N-ch
Type 3-C
Type 9-C
EVDD
P-ch
Comparator
+
P-ch
N-ch
IN
–
AVSS
Data
OUT
VREF
(threshold voltage)
N-ch
Input
enable
Type 5-A
Type 13-R
EVDD
Pullup
enable
P-ch
IN/OUT
V
DD
Data
Output disable
N-ch
Data
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
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Figure 2-1. Pin I/O Circuit List (2/2)
Type 13-S
Type 13-W
EVDD
IN/OUT
Mask
option
Data
Output disable
N-ch
IN/OUT
Data
Output disable
N-ch
Input
enable
Middle-voltage input buffer
Type 13-V
Type 16
EVDD
Feedback
cut-off
Mask
option
IN/OUT
P-ch
Data
Output disable
N-ch
XT1
XT2
Input
enable
Middle-voltage input buffer
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3.1 Memory Space
Products in the 78K0/KC1 Series can each access a 64 KB memory space. Figures 3-1 to 3-5 show the memory
maps.
Caution Regardless of the internal memory capacity, the initial value of the internal memory size
switching register (IMS) of all products in the 78K0/KC1 Series is fixed (CFH). Therefore, set the
value corresponding to each product as indicated below.
Table 3-1. Set Value of Internal Memory Size Switching Register (IMS)
Internal Memory Size Switching Register (IMS)
µPD780111
µPD780112
µPD780113
µPD780114
µPD78F0114
42H
44H
C6H
C8H
Value corresponding to mask ROM version
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Figure 3-1. Memory Map (µPD780111)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
FEE0H
FEDFH
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
1FFFH
Program area
CALLF entry area
Program area
Data memory
space
1000H
0FFFH
Reserved
0800H
07FFH
0080H
007FH
2000H
1FFFH
CALLT table area
Vector table area
0040H
003FH
Program
memory
space
Internal ROM
8192 × 8 bits
0000H
0000H
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Figure 3-2. Memory Map (µPD780112)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
FEE0H
FEDFH
32 × 8 bits
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
3FFFH
Program area
CALLF entry area
Program area
Data memory
space
1000H
0FFFH
Reserved
0800H
07FFH
0080H
007FH
4000H
3FFFH
CALLT table area
Vector table area
0040H
003FH
Program
memory
space
Internal ROM
16384 × 8 bits
0000H
0000H
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Figure 3-3. Memory Map (µPD780113)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
FEE0H
FEDFH
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
5FFFH
Program area
CALLF entry area
Program area
Data memory
space
1000H
0FFFH
Reserved
0800H
07FFH
0080H
007FH
6000H
5FFFH
CALLT table area
Vector table area
Program
memory
space
0040H
003FH
Internal ROM
24576 × 8 bits
0000H
0000H
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Figure 3-4. Memory Map (µPD780114)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
FEE0H
FEDFH
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
7FFFH
Program area
CALLF entry area
Program area
Data memory
space
1000H
0FFFH
Reserved
0800H
07FFH
0080H
007FH
8000H
7FFFH
CALLT table area
Vector table area
0040H
003FH
Program
memory
space
Internal ROM
32768 × 8 bits
0000H
0000H
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Figure 3-5. Memory Map (µPD78F0114)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
FEE0H
FEDFH
32 × 8 bits
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
7FFFH
Program area
CALLF entry area
Program area
Data memory
space
1000H
0FFFH
Reserved
0800H
07FFH
0080H
007FH
8000H
7FFFH
CALLT table area
Vector table area
0040H
003FH
Program
memory
space
Flash memory
32768 × 8 bits
0000H
0000H
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3.1.1 Internal program memory space
The internal program memory space stores the program and table data. Normally, it is addressed with the program
counter (PC).
78K0/KC1 Series products incorporate internal ROM (or flash memory), as shown below.
Table 3-2. Internal Memory Capacity
Part Number
Internal ROM
Structure
Capacity
µPD780111
Mask ROM
8192 × 8 bits (0000H to 1FFFH)
16384 × 8 bits (0000H to 3FFFH)
24576 × 8 bits (0000H to 5FFFH)
32768 × 8 bits (0000H to 7FFFH)
32768 × 8 bits (0000H to 7FFFH)
µPD780112
µPD780113
µPD780114
µPD78F0114
Flash memory
The internal program memory space is divided into the following areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch
upon RESET input or generation of each interrupt request are stored in the vector table area.
Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd
addresses.
Table 3-3. Vector Table
Vector Table Address
0000H
Interrupt Source
Vector Table Address
0018H
Interrupt Source
INTCSI10/INTST0
INTTMH1
INTTMH0
INTTM50
RESET input, POC, LVI,
clock monitor, WDT
001AH
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
INTLVI
INTP0
001CH
001EH
INTP1
0020H
INTTM000
INTTM010
INTAD
INTP2
0022H
INTP3
0024H
INTP4
0026H
INTSR0
INTP5
0028H
INTWTI
INTSRE6
INTSR6
INTST6
002AH
INTTM51
002CH
INTKR
002EH
INTWT
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
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3.1.2 Internal data memory space
78K0/KC1 Series products incorporate the following internal high-speed RAMs.
Table 3-4. Internal High-Speed RAM Capacity
Part Number
µPD780111
Internal Expansion RAM
512 × 8 bits (FD00H to FEFFH)
µPD780112
µPD780113
µPD780114
µPD78F0114
1024 × 8 bits (FB00H to FEFFH)
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per one bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
3.1.3 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Table 3-5 Special Function Register List in 3.2.3 Special Function Registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
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3.1.4 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of
the register or memory relevant to the execution of instructions.
The address of an instruction to be executed next is addressed by the program counter (PC) (for details, see 3.3
Instruction Address Addressing).
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
78K0/KC1 Series, based on operability and other considerations. For areas containing data memory in particular,
special addressing methods designed for the functions of special function registers (SFR) and general-purpose
registers are available for use. Data memory addressing is illustrated in Figures 3-6 to 3-10. For the details of each
addressing mode, see 3.4 Operand Address Addressing.
Figure 3-6. Data Memory Addressing (µPD780111)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
General-purpose registers
Register addressing
32 × 8 bits
Short direct
addressing
FEE0H
FEDFH
Internal high-speed RAM
512 × 8 bits
FE20H
FE1FH
FD00H
FCFFH
Direct addressing
Register indirect
addressing
Based addressing
Based indexed
addressing
Reserved
2000H
1FFFH
Internal ROM
8192 × 8 bits
0000H
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Figure 3-7. Data Memory Addressing (µPD780112)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
General-purpose registers
Register addressing
32 × 8 bits
Short direct
addressing
FEE0H
FEDFH
Internal high-speed RAM
512 × 8 bits
FE20H
FE1FH
FD00H
FCFFH
Direct addressing
Register indirect
addressing
Based addressing
Based indexed
addressing
Reserved
4000H
3FFFH
Internal ROM
16384 × 8 bits
0000H
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Figure 3-8. Data Memory Addressing (µPD780113)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
General-purpose registers
Register addressing
32 × 8 bits
Short direct
addressing
FEE0H
FEDFH
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
Based indexed
addressing
6000H
5FFFH
Internal ROM
24576 × 8 bits
0000H
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Figure 3-9. Data Memory Addressing (µPD780114)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
General-purpose registers
Register addressing
32 × 8 bits
Short direct
addressing
FEE0H
FEDFH
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
Based indexed
addressing
8000H
7FFFH
Internal ROM
32768 × 8 bits
0000H
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Figure 3-10. Data Memory Addressing (µPD78F0114)
FFFFH
Special function
registers (SFRs)
256 × 8 bits
SFR addressing
FF20H
FF1FH
FF00H
FEFFH
General-purpose registers
Register addressing
32 × 8 bits
Short direct
addressing
FEE0H
FEDFH
Internal high-speed RAM
1024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Direct addressing
Register indirect
addressing
Based addressing
Reserved
Based indexed
addressing
8000H
7FFFH
Flash memory
32768 × 8 bits
0000H
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3.2 Processor Registers
The 78K0/KC1 Series products incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-11. Format of Program Counter
15
0
PC
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETB, RETI and POP PSW
instructions.
RESET input sets the PSW to 02H.
Figure 3-12. Format of Program Status Word
7
0
PSW
IE
Z
RBS1
AC
RBS0
0
ISP
CY
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(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and only non-maskable interrupt requests
become acknowledgeable. Other interrupt requests are all disabled.
When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgement is
controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a
priority specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgement and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction
execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other
cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-
level vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L) (refer
to 15.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) can not be acknowledged. Actual
request acknowledgement is controlled by the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value
upon rotate instruction execution and functions as a bit accumulator during bit operation instruction
execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
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Figure 3-13. Format of Stack Pointer
15
0
SP
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restored) from
the stack memory.
Each stack operation saves/restores data as shown in Figures 3-14 and 3-15.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-14. Data to Be Saved to Stack Memory
Interrupt and
BRK instructions
PUSH rp instruction
CALL, CALLF, and
CALLT instructions
_
_
_
_
SP SP
SP
3
3
2
1
_
_
_
_
_
_
SP SP
SP
2
2
1
SP SP
SP
2
2
1
PC7 to PC0
PC15 to PC8
PSW
Register pair lower
Register pair upper
SP
PC7 to PC0
SP
SP
SP
PC15 to PC8
SP
SP
SP
Figure 3-15. Data to Be Restored from Stack Memory
RETI and RETB
instructions
POP rp instruction
RET instruction
SP
SP + 1
Register pair lower
Register pair upper
SP
SP + 1
SP
PC7 to PC0
PC7 to PC0
PC15 to PC8
PSW
SP + 1
SP + 2
PC15 to PC8
SP SP + 2
SP SP + 2
SP SP + 3
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The
general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register
(AX, BC, DE, and HL).
These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of
the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-16. Configuration of General-Purpose Registers
(a) Absolute Name
16-bit processing
RP3
8-bit processing
R7
FEFFH
FEF8H
BANK0
BANK1
BANK2
BANK3
R6
R5
R4
R3
R2
R1
R0
RP2
RP1
RP0
FEF0H
FEE8H
FEE0H
15
0
7
0
(b) Function Name
16-bit processing
8-bit processing
H
FEFFH
FEF8H
BANK0
BANK1
BANK2
BANK3
HL
DE
BC
L
D
E
B
C
A
X
FEF0H
FEE8H
AX
FEE0H
15
0
7
0
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CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special Function Registers (SFRs)
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Each manipulation bit unit can be specified as follows.
•
•
•
1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows.
•
Symbol
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
by the header file “sfrbit.h” in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols
can be written as an instruction operand.
•
R/W
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R:
Read only
W: Write only
•
•
Manipulatable bit units
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
After reset
Indicates each register status upon RESET input.
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Table 3-5. Special Function Register List (1/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulatable Bit Unit
After
Reset
1 Bit
8 Bits
16 Bits
FF00H
FF01H
FF02H
FF03H
FF06H
FF07H
FF08H
FF09H
FF0AH
FF0BH
FF0CH
FF0DH
FF0FH
FF10H
FF11H
FF12H
FF13H
FF14H
FF15H
FF16H
FF17H
FF18H
FF19H
FF1AH
FF1BH
FF1FH
FF20H
FF21H
FF23H
FF26H
FF27H
FF28H
FF29H
FF2AH
FF2BH
FF2CH
FF30H
FF31H
FF33H
FF37H
Port 0
P0
P1
P2
P3
P6
P7
R/W
R/W
R
√
√
√
√
√
√
−
√
√
√
√
√
√
−
−
−
−
−
−
−
√
00H
00H
Port 1
Port 2
00H
Port 3
R/W
R/W
R/W
R
00H
Port 6
00H
Port 7
00H
A/D conversion result register
ADCR
Undefined
Receive buffer register 6
Transmit buffer register 6
Port 12
RXB6
TXB6
P12
R
R/W
R/W
R/W
R
−
−
√
√
−
−
√
√
√
√
√
−
−
−
−
−
−
√
FFH
FFH
00H
Port 13
P13
00H
Serial I/O shift register 10
16-bit timer counter 00
SIO10
TM00
00H
R
0000H
16-bit timer capture/compare register 000
16-bit timer capture/compare register 010
CR000
CR010
R/W
R/W
−
−
−
−
√
√
0000H
0000H
8-bit timer counter 50
TM50
CR50
CMP00
CMP10
CMP01
CMP11
TM51
PM0
R
−
−
−
−
−
−
−
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
FFH
00H
00H
00H
00H
8-bit timer compare register 50
8-bit timer H compare register 00
8-bit timer H compare register 10
8-bit timer H compare register 01
8-bit timer H compare register 11
8-bit timer counter 51
R/W
R/W
R/W
R/W
R/W
R
Port mode register 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port mode register 1
PM1
Port mode register 3
PM3
Port mode register 6
PM6
Port mode register 7
PM7
A/D converter mode register
Analog input channel specification register
Power-fail comparison mode register
Power-fail comparison threshold register
Port mode register 12
ADM
ADS
PFM
PFT
PM12
PU0
Pull-up resistor option register 0
Pull-up resistor option register 1
Pull-up resistor option register 3
Pull-up resistor option register 7
PU1
PU3
PU7
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Table 3-5. Special Function Register List (2/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulatable Bit Unit
After
Reset
1 Bit
8 Bits
16 Bits
FF3CH
FF41H
FF43H
FF48H
FF49H
FF4FH
FF50H
Pull-up resistor option register 12
8-bit timer compare register 51
PU12
R/W
R/W
R/W
R/W
R/W
R/W
R/W
√
−
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
00H
00H
00H
00H
00H
00H
01H
CR51
TMC51
EGP
8-bit timer mode control register 51
External interrupt rising edge enable register
External interrupt falling edge enable register
Input switch control register
EGN
ISC
Asynchronous serial interface operation mode
register 6
ASIM6
FF53H
FF55H
Asynchronous serial interface reception error
status register 6
ASIS6
ASIF6
R
R
−
−
√
√
−
−
00H
00H
Asynchronous serial interface transmission
status register 6
FF56H
FF57H
FF58H
FF69H
FF6AH
FF6BH
FF6CH
FF6DH
FF6EH
FF6FH
FF70H
Clock selection register 6
CKSR6
BRGC6
ASICL6
TMHMD0
TCL50
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
−
−
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
00H
FFH
16H
00H
00H
00H
00H
00H
00H
00H
01H
Baud rate generator control register 6
Asynchronous serial interface control register 6
8-bit timer H mode register 0
Timer clock selection register 50
8-bit timer mode control register 50
8-bit timer H mode register 1
TMC50
TMHMD1
TMCYC1
KRM
8-bit timer H carrier control register 1
Key return mode register
Watch timer operation mode register
WTM
Asynchronous serial interface operation mode
register 0
ASIM0
FF71H
FF72H
FF73H
Baud rate generator control register 0
Receive buffer register 0
BRGC0
RXB0
R/W
R
−
−
−
√
√
√
−
−
−
1FH
FFH
00H
Asynchronous serial interface reception error
status register 0
ASIS0
R
FF74H
FF80H
FF81H
FF84H
FF8CH
FF98H
FF99H
FFA0H
FFA1H
FFA2H
FFA3H
FFA4H
FFA9H
Transmit shift register 0
TXS0
W
−
√
√
−
−
−
−
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
−
−
−
−
−
−
FFH
00H
Serial operation mode register 10
Serial clock selection register 10
Transmit buffer register 10
Timer clock selection register 51
Watchdog timer mode register
Watchdog timer enable register
Ring-OSC mode register
CSIM10
CSIC10
SOTB10
TCL51
WDTM
WDTE
RCM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
00H
Undefined
00H
67H
9AH
00H
Main clock mode register
MCM
00H
Main OSC control register
MOC
00H
Oscillation stabilization time counter status register OSTC
00H
Oscillation stabilization time select register
Clock monitor mode register
OSTS
CLM
R/W
R/W
05H
00H
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Table 3-5. Special Function Register List (3/3)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulatable Bit Unit
After
Reset
1 Bit
8 Bits
16 Bits
FFACH
FFBAH
FFBBH
FFBCH
FFBDH
FFBEH
FFBFH
FFE0H
FFE1H
FFE2H
FFE4H
FFE5H
FFE6H
FFE8H
FFE9H
FFEAH
FFF0H
FFFBH
Reset control flag register
RESF
R
R/W
−
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
−
−
−
√
00HNote 1
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
FFH
FFH
FFH
FFH
CFH
00H
16-bit timer mode control register 00
Prescaler mode register 00
TMC00
PRM00
CRC00
TOC00
LVIM
R/W
Capture/compare control register 00
16-bit timer output control register 00
Low-voltage detection register
R/W
R/W
R/W
Low-voltage detection level selection register
Interrupt request flag register 0L
Interrupt request flag register 0H
Interrupt request flag register 1L
Interrupt mask flag register 0L
LVIS
R/W
IF0
IF0L R/W
IF0H R/W
R/W
IF1L
−
√
MK0 MK0L R/W
MK0H R/W
Interrupt mask flag register 0H
Interrupt mask flag register 1L
MK1L
R/W
−
√
Priority specification flag register 0L
Priority specification flag register 0H
Priority specification flag register 1L
Internal memory size switching registerNote 2
Processor clock control register
PR0 PR0L R/W
PR0H R/W
PR1L
IMS
R/W
R/W
R/W
−
−
−
PCC
Notes 1. This value varies depending on the reset source.
2. The default value of IMS is fixed (CFH) in all products in the 78K0/KC1 Series regardless of the internal
memory capacity. Therefore, set the following value to each product.
Internal Memory Size Switching Register (IMS)
µPD780111
µPD780112
µPD780113
µPD780114
µPD78F0114
42H
44H
C6H
C8H
Value corresponding to mask ROM version
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each
byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is
executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by
the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.
In other words, relative addressing consists of relative branching from the start address of the following
instruction to the −128 to +127 range.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
PC indicates the start address
of the instruction after the BR instruction.
...
PC
+
8
7
6
S
α
jdisp8
15
0
PC
When S = 0, all bits of
When S = 1, all bits of
α
α
are 0.
are 1.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11
instruction is branched to the 0800H to 0FFFH area.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
In the case of CALLF !addr11 instruction
7
6
4
3
0
fa10–8
CALLF
fa7–0
15
11 10
1
8 7
0
PC
0
0
0
0
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3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
This function is carried out when the CALLT [addr5] instruction is executed.
This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to
the entire memory space.
[Illustration]
7
6
1
5
1
0
1
Operation code
1
ta4–0
15
8
0
7
0
6
1
5
1
0
0
Effective address
0
0
0
0
0
0
0
7
Memory (Table)
Low Addr.
0
High Addr.
Effective address+1
15
8
7
0
PC
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)
and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically
(implicitly) addressed.
Of the 78K0/KC1 Series instruction words, the following instructions employ implied addressing.
Instruction
MULU
Register to Be Specified by Implied Addressing
A register for multiplicand and AX register for product storage
AX register for dividend and quotient storage
DIVUW
ADJBA/ADJBS
ROR4/ROL4
A register for storage of numeric values that become decimal correction targets
A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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3.4.2 Register addressing
[Function]
The general-purpose register to be specified is accessed as an operand with the register bank select flags
(RBS0 to RBS1) and the register specify codes (Rn and RPn) of an operation code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier
Description
X, A, C, B, E, D, L, H
AX, BC, DE, HL
r
rp
‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; when selecting C register as r
Operation code
0
1
1
0
0
0
1
0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code
1
0
0
0
0
1
0
0
Register specify code
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3.4.3 Direct addressing
[Function]
The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an
operand address.
[Operand format]
Identifier
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
1
0
1
1
0
1
0
0
0
OP code
00H
FEH
[Illustration]
7
0
OP code
addr16 (lower)
addr16 (upper)
Memory
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3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers
(SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter
are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to the [Illustration] shown below.
[Operand format]
Identifier
saddr
Description
Label or FE20H to FF1FH immediate data
saddrp
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Operation code
0
0
0
0
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
OP code
30H (saddr-offset)
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
1
8 7
0
Effective address
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
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3.4.5 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier
sfr
Description
Special function register name
sfrp
16-bit manipulatable special function register name (even address
only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
1
0
1
0
1
1
1
0
0
0
1
0
1
0
0
0
OP code
20H (sfr-offset)
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective address
1
1
1
1
1
1
1
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3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1
0
0
0
0
1
0
1
[Illustration]
16
8
7
7
0
0
DE
D
E
The memory address
specified with the
register pair DE
Memory
The contents of the memory
addressed are transferred.
7
0
A
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3.4.7 Based addressing
[Function]
8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in
the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address
the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
1
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
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3.4.8 Based indexed addressing
[Function]
The B or C register contents specified in an instruction word are added to the contents of the base register, that
is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the
sum is used to address the memory.
Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from
the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
−
[HL + B], [HL + C]
[Description example]
In the case of MOV A, [HL + B]
Operation code
1
0
1
0
1
0
1
1
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and return
instructions are executed or the register is saved/reset upon generation of an interrupt request.
With stack addressing, only the internal high-speed RAM area can be accessed.
[Description example]
In the case of PUSH DE
Operation code
1
0
1
1
0
1
0
1
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
78K0/KC1 Series products are provided with the ports shown in Figure 4-1, which enable variety of control
operations. The functions of each port are shown in Table 4-1.
In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the
alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Types
P30
P00
P01
Port 0
Port 1
Port 3
Port 6
Port 7
P33
P60
P10
P63
P70
P17
P20
P73
Port 12
Port 13
P120
P130
Port 2
P27
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Table 4-1. Port Functions
Pin Name
I/O
Function
After Reset Alternate Function
P00
P01
I/O
I/O
Port 0.
Input
TI000
2-bit I/O port.
TI010/TO00
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P10
P11
P12
P13
P14
P15
P16
P17
Port 1.
Input
SCK10/TxD0
SI10/RxD0
SO10
8-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
TxD6
RxD6
TOH0
TOH1/INTP5
TI50/TO50
ANI0 to ANI7
P20 to P27
Input
I/O
Port 2.
Input
Input
8-bit input-only port.
P30 to P32
P33
Port 3.
INTP1 to INTP3
4-bit I/O port.
INTP4/TI51/TO51
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P60 to P63
P70 to P73
I/O
I/O
Port 6.
Input
Input
−
4-bit I/O port (N-ch open drain).
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a mask
option only for mask ROM versions.
Port 7.
KR0 to KR3
4-bit I/O port.
Input/output can be specified in 1-bit units.
Use of an on-chip pull-up resistor can be specified by a
software setting.
P120
P130
I/O
Port 12.
Input
INTP0
1-bit I/O port.
Use of an on-chip pull-up resistor can be specified by a
software setting.
Output
Port 13.
Output
−
1-bit output-only port.
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4.2 Port Configuration
Ports consist of the following hardware.
Table 4-2. Port Configuration
Configuration
Item
Control registers
Port mode register (PM0, PM1, PM3, PM6, PM7, PM12)
Pull-up resistor option register (PU0, PU1, PU3, PU7, PU12)
Input switch control register (ISC)
Port
Total: 32 (CMOS I/O: 19, CMOS input: 8, CMOS output: 1, N-ch open drain I/O: 4)
Pull-up resistor
• Mask ROM version
Total: 23 (software control: 19, mask option specification: 4)
• Flash memory version: Total: 19
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4.2.1 Port 0
Port 0 is a 2-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units
using port mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O.
RESET input sets port 0 to input mode.
Figures 4-2 and 4-3 show block diagrams of port 0.
Figure 4-2. Block Diagram of P00
EVDD
WRPU
PU00
P-ch
Alternate function
RD
WRPORT
Output latch
P00/TI000
(P00)
WRPM
PM00
PU0: Pull-up resistor option register 0
PM:
RD:
Port mode register
Port 0 read signal
WR: Port 0 write signal
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Figure 4-3. Block Diagram of P01
EVDD
WRPU
PU01
P-ch
Alternate
function
RD
WRPORT
Output latch
(P01)
P01/TI010/TO00
WRPM
PM01
Alternate
function
PU0: Pull-up resistor option register 0
PM:
RD:
Port mode register
Port 0 read signal
WR: Port 0 write signal
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4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units
using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 1 (PU1).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
RESET input sets port 1 to input mode.
Figures 4-4 to 4-9 show block diagrams of port 1.
Caution When P10/SCK10/TxD0, P11/SI10/RxD0, and P12/SO10 are used as general-purpose ports, do not
write to serial clock selection register 10 (CSIC10).
Figure 4-4. Block Diagram of P10
EVDD
WRPU
PU10
P-ch
Alternate
function
RD
WRPORT
Output latch
P10/SCK10/TxD0
(P10)
WRPM
PM10
Alternate
function
PU1: Pull-up resistor option register 1
PM:
RD:
Port mode register
Port 1 read signal
WR: Port 1 write signal
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Figure 4-5. Block Diagram of P11 and P14
EVDD
WRPU
PU11, PU14
P-ch
Alternate
function
RD
WRPORT
Output latch
(P11, P14)
P11/SI10/RxD0,
P14/RxD6
WRPM
PM11, PM14
PU1: Pull-up resistor option register 1
PM:
RD:
Port mode register
Port 1 read signal
WR: Port 1 write signal
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Figure 4-6. Block Diagram of P12
EVDD
WRPU
PU12
P-ch
RD
WRPORT
Output latch
(P12)
P12/SO10
WRPM
PM12
Alternate
function
PU1: Pull-up resistor option register 1
PM:
RD:
Port mode register
Port 1 read signal
WR: Port 1 write signal
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Figure 4-7. Block Diagram of P13
EVDD
WRPU
PU13
P-ch
RD
WRPORT
Output latch
(P13)
P13/TxD6
WRPM
PM13
Alternate
function
PU1: Pull-up resistor option register 1
PM:
RD:
Port mode register
Port 1 read signal
WR: Port 1 write signal
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Figure 4-8. Block Diagram of P15
EVDD
WRPU
PU15
P-ch
RD
WRPORT
Output latch
(P15)
P15/TOH0
WRPM
PM15
Alternate
function
PU1: Pull-up resistor option register 1
PM:
RD:
Port mode register
Port 1 read signal
WR: Port 1 write signal
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Figure 4-9. Block Diagram of P16 and P17
EVDD
WRPU
PU16, PU17
P-ch
Alternate
function
RD
WRPORT
Output latch
(P16, P17)
P16/TOH1/INTP5,
P17/TI50/TO50
WRPM
PM16, PM17
Alternate
function
PU1: Pull-up resistor option register 1
PM:
RD:
Port mode register
Port 1 read signal
WR: Port 1 write signal
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CHAPTER 4 PORT FUNCTIONS
4.2.3 Port 2
Port 2 is an 8-bit input-only port.
This port can also be used for A/D converter analog input.
Figure 4-10 shows a block diagram of port 2.
Figure 4-10. Block Diagram of P20 to P27
RD
+
P20/ANI0 to P27/ANI7
A/D converter
–
VREF
RD:
Port 2 read signal
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4.2.4 Port 3
Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units
using port mode register 3 (PM3). When used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input.
RESET input sets port 3 to input mode.
Figures 4-11 and 4-12 show block diagrams of port 3.
Figure 4-11. Block Diagram of P30 to P32
EVDD
WRPU
PU30 to PU32
P-ch
Alternate
function
RD
WRPORT
Output latch
(P30 to P32)
P30/INTP1 to
P32/INTP3
WRPM
PM30 to PM32
PU3: Pull-up resistor option register 3
PM:
RD:
Port mode register
Port 3 read signal
WR: Port 3 write signal
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Figure 4-12. Block Diagram of P33
EVDD
WRPU
PU33
P-ch
Alternate
function
RD
WRPORT
Output latch
(P33)
P33/INTP4/TI51/TO51
WRPM
PM33
Alternate
function
PU3: Pull-up resistor option register 3
PM:
RD:
Port mode register
Port 3 read signal
WR: Port 3 write signal
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4.2.5 Port 6
Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units
using port mode register 6 (PM6).
This port has the following functions for pull-up resistors. These functions differ depending on whether the product
is a mask ROM version or a flash memory version.
Table 4-3. Pull-up Resistor of Port 6
Pins P60 to P63
Mask ROM version
An on-chip pull-up resistor can be
specified in 1-bit units by mask option
Flash memory version
On-chip pull-up resistors are not provided
RESET input sets port 6 to input mode.
Figure 4-13 shows block diagram of port 6.
Figure 4-13. Block Diagram of P60 to P63
EVDD
Mask option resistor
RD
Mask ROM versions only
No pull-up resistor for
flash memory versions
Selector
WRPORT
Output latch
(P60 to P63)
P60 to P63
WRPM
PM60 to PM63
PM:
RD:
WR: Port 6 write signal
Port mode register
Port 6 read signal
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4.2.6 Port 7
Port 7 is a 4-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units
using port mode register 7 (PM7). When the P70 to P73 pins are used as an input port, use of an on-chip pull-up
resistor can be specified by pull-up resistor option register 7 (PU7).
This port can also be used for key return input.
RESET input sets port 7 to input mode.
Figure 4-14 shows a block diagram of port 7.
Figure 4-14. Block Diagram of P70 to P73
EVDD
WRPU
PU70 to PU73
P-ch
Alternate function
RD
WRPORT
Output latch
(P70 to P73)
P70/KR0 to
P73/KR3
WRPM
PM70 to PM73
PU7: Pull-up resistor option register 7
PM:
RD:
Port mode register
Port 7 read signal
WR: Port 7 write signal
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4.2.7 Port 12
Port 12 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units
using port mode register 12 (PM12). When used as an input port, use of an on-chip pull-up resistor can be specified
by pull-up resistor option register 12 (PU12).
This port can also be used for external interrupt input.
RESET input sets port 12 to input mode.
Figure 4-15 shows a block diagram of port 12.
Figure 4-15. Block Diagram of P120
EVDD
WRPU
PU120
P-ch
Alternate
function
RD
WRPORT
Output latch
(P120)
P120/INTP0
WRPM
PM120
PU12: Pull-up resistor option register 12
PM:
RD:
Port mode register
Port 12 read signal
WR: Port 12 write signal
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4.2.8 Port 13
Port 13 is a 1-bit output-only port.
Figure 4-16 shows a block diagram of port 13.
Figure 4-16. Block Diagram of P130
RD
WRPORT
Output latch
(P130)
P130
RD:
Port 13 read signal
WD: Port 13 write signal
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4.3 Registers Controlling Port Function
Port functions are controlled by the following three types of registers.
•
•
•
Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12)
Pull-up resistor option registers (PU0, PU1, PU3, PU7, PU12)
Input switch control register (ISC)
(1) Port mode registers (PM0, PM1, PM3, PM6, PM7, and PM12)
These registers specify input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table
4-4.
Figure 4-17. Format of Port Mode Register
Symbol
PM0
7
1
6
1
5
1
4
1
3
1
2
1
1
0
Address After reset
R/W
R/W
PM01
PM00
FF20H
FF21H
FF23H
FF26H
FF27H
FF2CH
FFH
FFH
FFH
FFH
FFH
FFH
7
6
5
4
3
2
1
0
PM1
PM3
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
R/W
R/W
R/W
R/W
R/W
7
1
6
1
5
1
4
1
3
2
1
0
PM33
PM32
PM31
PM30
7
1
6
1
5
1
4
1
3
2
1
0
PM6
PM63
PM62
PM61
PM60
7
1
6
1
5
1
4
1
3
2
1
0
PM7
PM73
PM72
PM71
PM70
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
PM12
PM120
PMmn
Pmn pin I/O mode selection
(m = 0, 1, 3, 6, 7, 12; n = 0 to 7)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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Table 4-4. Settings of Port Mode Register and Output Latch When Using Alternate Function
Pin Name
Alternate Function
Function Name
PM××
P××
I/O
Input
P00
TI000
TI010
TO00
SCK10
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1
0
1
1
1
0
1
1
×
×
0
×
1
1
×
×
0
1
×
0
0
×
×
0
×
×
×
0
×
×
P01
Input
Output
Input
P10
Output
Output
Input
TxD0
P11
SI10
RxD0
Input
P12
P13
P14
P15
P16
SO10
Output
Output
Input
TxD6
RxD6
TOH0
TOH1
INTP5
TI50
Output
Output
Input
P17
Input
TO50
Output
Input
P30 to P32
P33
INTP1 to INTP3
INTP4
TI51
Input
Input
TO51
Output
Input
P70 to P73
P120
KR0 to KR3
INTP0
Input
Remark ×:
Don’t care
PM××: Port mode register
P××: Port output latch
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(2) Pull-up resistor option registers (PU0, PU1, PU3, PU7, and PU12)
These registers specify whether the on-chip pull-up resistors of P00, P01, P10 to P17, P30 to P33, P70 to P73, or
P120 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode
of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3, PU7, and PU12.
On-chip pull-up resistors cannot be used for bits set to output mode and bits used as alternate-function output
pins, regardless of the settings of PU0, PU1, PU3, PU7, and PU12.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 4-18. Format of Pull-up Resistor Option Register
Symbol
PU0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address After reset
R/W
R/W
PU01
PU00
FF30H
FF31H
FF33H
FF37H
FF3CH
00H
00H
00H
00H
00H
7
6
5
4
3
2
1
0
PU1
PU3
PU17
PU16
PU15
PU14
PU13
PU12
PU11
PU10
R/W
R/W
R/W
R/W
7
0
6
0
5
0
4
0
3
2
1
0
PU33
PU32
PU31
PU30
7
0
6
0
5
0
4
0
3
2
1
0
PU7
PU73
PU72
PU71
PU70
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
PU12
PU120
PUmn
Pmn pin on-chip pull-up resistor selection
(m = 0, 1, 3, 7, 12; n = 0 to 7)
0
1
On-chip pull-up resistor not connected
On-chip pull-up resistor connected
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(3) Input switch control register (ISC)
This register is used to receive a status signal transmitted from the master during LIN (Local Interconnect
Network) reception. The input signal is switched by setting ISC.
For the port configuration during LIN reception, refer to Figure 13-3 Port Configuration for LIN Reception
Operation in CHAPTER 13 SERIAL INTERFACE UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 4-19. Format of Input Switch Control Register (ISC)
Address: FF4FH After reset: 00H R/W
Symbol
ISC
7
0
6
0
5
0
4
0
3
0
2
0
1
0
ISC1
ISC0
ISC1
Input signal selection
0
1
TI000 input
RxD6 input
ISC0
Input signal selection
0
1
INTP0 input
RxD6 input
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the
pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does
not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
The output latch contents are undefined, but since the output buffer is off, the pin status does not change.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the
port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins,
the output latch contents for pins specified as input are undefined, even for bits other than the
manipulated bit.
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CHAPTER 5 CLOCK GENERATOR
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three system clock oscillators are available.
•
•
X1 oscillator
The X1 oscillator oscillates a clock of 2.0 to 10.0 MHz. Oscillation can be stopped by executing the STOP
instruction or setting the main OSC control register (MOC) and processor clock control register (PCC).
Ring-OSC oscillator
The Ring-OSC oscillator oscillates a clock of 240 kHz (TYP.). Oscillation can be stopped by setting the Ring-
OSC mode register (RCM) when “Can be stopped by software” is set by a mask option and the X1 input clock is
used as the CPU clock.
•
Subsystem clock oscillator
The subsystem clock oscillator oscillates a clock of 32.768 kHz. Oscillation cannot be stopped. When
subsystem clock oscillator is not used, setting not to use the on-chip feedback resistor is possible using the
processor clock control register (PCC), and the power consumption can be reduced in the STOP mode.
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5.2 Configuration of Clock Generator
The clock generator consists of the following hardware.
Table 5-1. Configuration of Clock Generator
Configuration
Item
Control registers
Processor clock control register (PCC)
Ring-OSC mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Oscillator
X1 oscillator
Ring-OSC oscillator
Subsystem clock oscillator
Figure 5-1. Block Diagram of Clock Generator
Internal bus
Oscillation
Main clock
Main OSC
control
register
(MOC)
Processor clock
control register
(PCC)
stabilization time
mode register
select register
(MCM)
MCS MCM0
(OSTS)
OSTS2 OSTS1 OSTS0
3
CLS CSS PCC2 PCC1 PCC0
MCC CLS
MSTOP
4
X1 oscillation
STOP
C
P
U
CPU clock
(fCPU
Controller
stabilization time counter
)
Oscillation
stabilization
time counter
status
MOST MOST MOST MOST MOST
11
13
14
15
16
register
(OSTC)
X1
X2
fX
X1 oscillator
fXP
Prescaler
Operation
clock switch
f
2
X
f
X
f
X
fX
22 23 24
Ring-OSC
oscillator
fR
Watch clock
Prescaler
Subsystem
clock oscillator
XT1
XT2
1/2
Clock to peripheral
hardware
fXT
Mask option
1: Cannot be stopped
0. Can be stopped
Prescaler
FRC
8-bit timer H1,
watchdog timer
RSTOP
Ring-OSC mode
register (RCM)
Internal bus
102
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5.3 Registers Controlling Clock Generator
The following six registers are used to control the clock generator.
•
•
•
•
•
•
Processor clock control register (PCC)
Ring-OSC mode register (RCM)
Main clock mode register (MCM)
Main OSC control register (MOC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
(1) Processor clock control register (PCC)
The PCC register is used to select the CPU clock, the division ratio, main system clock oscillator operation/stop
and whether to use the on-chip feedback resistor of the subsystem clock oscillator.
The PCC is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PCC to 00H.
Figure 5-2. Subsystem Clock Feedback Resistor
FRC
P-ch
Feedback resistor
XT1
XT2
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Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 00H R/WNote 1
Symbol
PCC
7
6
5
4
3
0
2
1
0
MCC
FRC
CLS
CSS
PCC2
PCC1
PCC0
MCC
Control of X1 oscillator operationNote 2
0
1
Oscillation possible
Oscillation stopped
FRC
Subsystem clock feedback resistor selectionNote 3
0
1
On-chip feedback resistor used
On-chip feedback resistor not used
CLS
0
CPU clock status
X1 input clock or Ring-OSC clock
Subsystem clock
1
CSSNote 4
PCC2
PCC1
PCC0
CPU Clock (fCPU) Selection
MCM0 = 0 MCM0 = 1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
0
1
0
1
0
fX
fR
fXP
fX/2
fX/22
fX/23
fX/24
fXT/2
fR/2
fXP/2
fR/22
fR/23
fR/24
fXP/22
fXP/23
fXP/24
1
Other than above
Setting prohibited
Notes 1. Bit 5 is read-only.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator
operation. When the CPU is operating on the Ring-OSC clock, use bit 7 (MSTOP) of the main OSC
control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP
instruction should not be used.
3. The feedback resistor is required to adjust the bias point of the oscillation waveform to close to the
middle of the power supply voltage. Setting FRC to 1 can further reduce the current consumption in
the STOP mode, but only when the subsystem clock is not used.
4. Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Caution Be sure to set bit 3 to 0.
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
2. fX:
Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC
clock oscillation frequency)
3. fR:
Ring-OSC clock oscillation frequency
4. fXP:
5. fXT:
X1 input clock oscillation frequency
Subsystem clock oscillation frequency
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The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/KC1 Series. Therefore, the
relationship between the CPU clock (fCPU) and minimum instruction execution time is as shown in the Table 5-2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
Minimum Instruction Execution Time: 2/fCPU
Ring-OSC ClockNote
X1 Input ClockNote
Subsystem Clock
(at 10 MHz Operation)
(at 240 kHz (TYP.) Operation)
(at 32.768 kHz Operation)
fX
0.2 µs
8.3 µs (TYP.)
−
−
−
−
−
fX/2
0.4 µs
0.8 µs
1.6 µs
3.2 µs
16.6 µs (TYP.)
33.2 µs (TYP.)
66.4 µs (TYP.)
132.8 µs (TYP.)
−
fX/22
fX/23
fX/24
fXT/2
−
122.1 µs
Note The main clock mode register (MCM) is used to set the CPU clock (X1 input clock/Ring-OSC clock) (see
Figure 5-5).
(2) Ring-OSC mode register (RCM)
This register sets the operation mode of Ring-OSC.
This register is valid when “Can be stopped by software” is set for Ring-OSC by a mask option, and the X1 input
clock or subsystem clock is selected as the CPU clock. If “Cannot be stopped” is selected for Ring-OSC by a
mask option, settings for this register are invalid.
RCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-4. Format of Ring-OSC Mode Register (RCM)
Address: FFA0H After reset: 00H R/W
Symbol
RCM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
RSTOP
RSTOP
Ring-OSC oscillating/stopped
0
1
Ring-OSC oscillating
Ring-OSC stopped
Caution Make sure that the bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.
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(3) Main clock mode register (MCM)
This register sets the CPU clock (X1 input clock/Ring-OSC clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-5. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/WNote
Symbol
MCM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
MCS
MCM0
MCS
CPU clock status
0
1
Operates with Ring-OSC clock
Operates with X1 input clock
MCM0
Selection of clock supplied to CPU
0
1
Ring-OSC clock
X1 input clock
Note Bit 1 is read-only.
Cautions 1. When Ring-OSC clock is selected as the clock to be supplied to the CPU, the
divided clock of the Ring-OSC oscillator output (fX) is supplied to the peripheral
hardware (fX = 240 kHz (TYP.)).
Operation of the peripheral hardware with Ring-OSC clock cannot be
guaranteed. Therefore, when Ring-OSC clock is selected as the clock supplied
to the CPU, do not use peripheral hardware. In addition, stop the peripheral
hardware before switching the clock supplied to the CPU from the X1 input clock
to the Ring-OSC clock. Note, however, that the following peripheral hardware
can be used when the CPU operates on the Ring-OSC clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when fR/27 is selected as count clock
• Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM00 is selected (TI000 valid edge))
2. Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1
input clock operation (bit 4 (CSS) of the processor clock control register (PCC)
is changed from 1 to 0).
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(4) Main OSC control register (MOC)
This register selects the operation mode of the X1 input clock.
This register is used to stop the X1 oscillator operation when the CPU is operating with the Ring-OSC clock.
Therefore, this register is valid only when the CPU is operating with the Ring-OSC clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-6. Format of Main OSC Control Register (MOC)
Address: FFA2H After reset: 00H R/W
Symbol
MOC
7
6
0
5
0
4
0
3
0
2
0
1
0
0
0
MSTOP
MSTOP
Control of X1 oscillator operation
0
1
X1 oscillator operating
X1 oscillator stopped
Cautions 1. Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting MSTOP.
2. To stop X1 oscillation during operation with the subsystem clock, set bit 7 (MCC)
of the processor clock control register (PCC) to 1 (setting by MSTOP is not
possible).
(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
RESET input, the STOP instruction, MSTOP = 1, and MCC = 1 clear OSTC to 00H.
Figure 5-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H
R
Symbol
OSTC
7
0
6
0
5
0
4
3
2
1
0
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
Oscillation stabilization time status
211/fXP min. (204.8 µs min.)
213/fXP min. (819.2 µs min.)
214/fXP min. (1.64 ms min.)
215/fXP min. (3.27 ms min.)
216/fXP min. (6.55 ms min.)
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
Caution After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
Remarks 1. Values in parentheses are for operation with fXP = 10 MHz.
2. fXP: X1 input clock oscillation frequency
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(6) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released.
The wait time set by OSTS is valid only after STOP mode is released with the X1 input clock selected as CPU
clock. After STOP mode is released with Ring-OSC selected as CPU clock, the oscillation stabilization time must
be confirmed by OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 5-8. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H R/W
Symbol
OSTS
7
0
6
0
5
0
4
0
3
0
2
1
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
0
0
0
1
1
0
1
0
1
0
1
211/fXP (204.8 µs)
213/fXP (819.2 µs)
214/fXP (1.64 ms)
215/fXP (3.27 ms)
216/fXP (6.55 ms)
Setting prohibited
1
1
0
0
Other than above
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC is being used
as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
2. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
VSS
Remarks 1. Values in parentheses are for operation with fXP = 10 MHz.
2. fXP: X1 input clock oscillation frequency
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5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (Standard: 10 MHz) connected to the X1
and X2 pins.
External clocks can be input to the X1 oscillator. In this case, input the clock signal to the X1 pin and input the
inverse signal to the X2 pin.
Figure 5-9 shows the external circuit of the X1 oscillator.
Figure 5-9. External Circuit of X1 Oscillator
(a) Crystal, ceramic oscillation
(b) External clock
IC
X1
External
clock
X1
X2
VSS
X2
Crystal resonator or
ceramic resonator
5.4.2 Subsystem clock oscillator
The subsystem clock oscillator oscillates with a crystal resonator (Standard: 32.768 kHz) connected to the XT1
and XT2 pins.
External clocks can be input to the subsystem clock oscillator. In this case, input the clock signal to the XT1 pin
and the inverse signal to the XT2 pin.
Figure 5-10 shows an external circuit of the subsystem clock oscillator.
Figure 5-10. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
External
clock
IC
XT1
XT1
XT2
32.768
kHz
XT2
VSS
Cautions are listed on the next page.
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Cautions 1. When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area
enclosed by the broken lines in the Figure 5-11 to avoid an adverse effect from wiring
capacitance.
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V . Do
not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
•
Note that the subsystem clock oscillator is designed as a low-amplitude circuit for reducing
power consumption.
Figure 5-11 shows examples of incorrect resonator connection.
Figure 5-11. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring
(b) Crossed signal line
PORT
IC
X2
X1
IC
X2
X1
VSS
VSS
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
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Figure 5-11. Examples of Incorrect Resonator Connection (2/2)
(c) Wiring near high alternating current
(d) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
DD0
Pmn
X1
IC
X2
X1
IC
X2
A
B
C
High current
V
SS
V
SS
(e) Signals are fetched
IC
X2
X1
VSS
Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert
resistors in series on the XT2 side.
Cautions 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1,
resulting in malfunctioning.
To prevent that from occurring, it is recommended to wire X2 and XT1 so that they are not in
parallel, and to connect the IC pin between X2 and XT1 directly to V
.
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5.4.3 When subsystem clock is not used
If it is not necessary to use the subsystem clock for low power consumption operations and watch operations,
connect the XT1 and XT2 pins as follows.
XT1: Connect to EVDD or VDD
XT2: Leave open
In this state, however, some current may leak via the on-chip feedback resistor of the subsystem clock oscillator
when the X1 input clock and Ring-OSC clock stop. To minimize leakage current, the above on-chip feedback resistor
can be set not to be used via bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the
XT1 and XT2 pins as described above.
5.4.4 Ring-OSC oscillator
Ring-OSC oscillator is incorporated in the µPD780111, 780112, 780113, 780114, and 78F0114.
“Can be stopped by software” or “Cannot be stopped” can be selected by a mask option. The Ring-OSC clock
always oscillates after RESET release (240 kHz (TYP.)).
5.4.5 Prescaler
The prescaler generates various clocks by dividing the X1 oscillator output (fX) when the X1 input clock is selected
as the clock to be supplied to the CPU.
Caution When the Ring-OSC clock is selected as the clock supplied to the CPU, the prescaler generates
various clocks by dividing the Ring-OSC oscillator output (fX) (fX = 240 kHz (TYP.)).
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode.
•
•
•
•
•
X1 input clock fXP
Ring-OSC clock fR
Subsystem clock fXT
CPU clock fCPU
Clock to peripheral hardware
The CPU starts operation when the on-chip Ring-OSC oscillator starts outputting after reset release in the
78K0/KC1 Series, thus enabling the following.
(1) Enhancement of security function
When the X1 input clock is set as the CPU clock by the default setting, the device cannot operate if the X1 input
clock is damaged or badly connected and therefore does not operate after reset is released. However, the start
clock of the CPU is the on-chip Ring-OSC clock, so the device can be started by the Ring-OSC clock after reset
release by the clock monitor (detection of X1 input clock stop). Consequently, the system can be safely shut
down by performing a minimum operation, such as acknowledging a reset source by software or performing
safety processing when there is a malfunction.
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(2) Improvement of performance
Because the CPU can be started without waiting for the X1 input clock oscillation stabilization time, the total
performance can be improved.
A timing diagram of the CPU default start using Ring-OSC is shown in Figure 5-12.
Figure 5-12. Timing Diagram of CPU Default Start Using Ring-OSC
X1 input clock
(fXP
)
Ring-OSC clock
(f
R)
Subsystem clock
(fXT
)
RESET
Switched by software
X1 input clock
Ring-OSC clock
CPU clock
Operation
stopped: 17/f
R
Note
X1 oscillation stabilization time: 211/fXP to 216/fXP
Note Check using the oscillation stabilization time counter status register (OSTC).
(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the Ring-
OSC clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks of the Ring-OSC
clock have elapsed after RESET release (or clock supply to the CPU stops for 17 clocks). During the
RESET period, oscillation of the X1 input clock and Ring-OSC clock is stopped.
(b) After RESET release, the CPU clock can be switched from the Ring-OSC clock to the X1 input clock using bit
0 (MCM0) of the main clock mode register (MCM) after the X1 input clock oscillation stabilization time has
elapsed. At this time, check the oscillation stabilization time using the oscillation stabilization time counter
status register (OSTC) before switching the CPU clock. The CPU clock status can be checked using bit 1
(MCS) of MCM.
(c) Ring-OSC can be set to stopped/oscillating using the Ring-OSC mode register (RCM) when “Can be stopped
by software” is selected for the Ring-OSC by a mask option, if the X1 input or subsystem clock is used as the
CPU clock. Make sure that MCS is 1 at this time.
(d) When Ring-OSC is used as the CPU clock, the X1 input clock can be set to stopped/oscillating using the
main OSC control register (MOC). Make sure that MCS is 0 at this time.
When the subsystem clock is used as the CPU clock, whether the X1 input clock stops or oscillates can be
set by the processor clock control register (PCC). In addition, HALT mode can be used during operation with
the subsystem clock, but STOP mode cannot be used (subsystem clock oscillation cannot be stopped by the
STOP instruction).
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(e) Select the X1 input clock oscillation stabilization time (211/fXP, 213/fXP, 214/fXP, 215/fXP, 216/fXP) using the oscillation
stabilization time select register (OSTS) when releasing STOP mode while X1 input clock is being used as
the CPU clock. In addition, when releasing STOP mode while RESET is released and Ring-OSC is being
used as the CPU clock, check the X1 input clock oscillation stabilization time using the oscillation
stabilization time counter status register (OSTC).
A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation
clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 5-3 and 5-4, respectively.
Figure 5-13. Status Transition Diagram (1/4)
(1) When “Ring-OSC can be stopped by software” is selected by mask option
(when subsystem clock is not used)
HALTNote 4
HALT instruction
Interrupt
HALT
instruction
Interrupt
Interrupt
HALT
instruction
HALT
Interrupt
instruction
Status 4
CPU clock: fXP
XP: Oscillating
: Oscillation stopped
MSTOP = 1Note 3
Status 3
CPU clock: fXP
XP: Oscillating
Status 1
CPU clock: f
XP: Oscillation stopped
RSTOP = 0
MCM0 = 0
Status 2
R
CPU clock: f
XP: Oscillating
: Oscillating
R
f
f
f
f
f
f
fR
RSTOP = 1Note 1
MCM0 = 1Note 2
MSTOP = 0
STOP
R
: Oscillating
f : Oscillating
R
R
Interrupt
instruction
STOP
Interrupt
STOP
instruction
instruction
Interrupt
Interrupt
STOP
instruction
STOPNote 4
Reset release
ResetNote 5
Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3. When shifting from status 2 to status 1, make sure that MCS is 0.
4. When “Ring-OSC can be stopped by software” is selected by a mask option, the watchdog timer
stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer.
However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0.
5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 5-13. Status Transition Diagram (2/4)
(2) When “Ring-OSC can be stopped by software” is selected by mask option
(when subsystem clock is used)
Status 6
CPU clock: fXT
f
: Oscillation
XP stopped
f
: Oscillating/
Roscillation
stopped
Interrupt
MCC = 0
MCC = 1
HALT
instruction
Status 5
CPU clock: fXT
XP: Oscillating
: Oscillating/
oscillation
stopped
Interrupt
f
HALTNote 4
fR
HALT
instruction
HALT
instruction
Interrupt
HALT
instruction
CSS = 0Note 6
HALT
instruction
Interrupt
CSS = 1Note 5
Interrupt
Status 4
CPU clock: fXP
XP: Oscillating
: Oscillation
stopped
Status 1
Status 2
CPU clock: f
XP: Oscillating
: Oscillating
Status 3
CPU clock: fXP
XP: Oscillating
RSTOP = 0
MCM0 = 0
MSTOP = 1Note 3
CPU clock: f
R
R
f
XP: Oscillation
f
f
f
f
f
stopped
MCM0 = 1Note 2
MSTOP = 0
RSTOP = 1Note 1
fR
R
R
: Oscillating
fR
: Oscillating
STOP
instruction
STOP
instruction
Interrupt
Interrupt
STOP
instruction
Interrupt
Reset release
STOPNote 4
ResetNote 7
Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
2. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
3. When shifting from status 2 to status 1, make sure that MCS is 0.
4. When “Ring-OSC can be stopped by software” is selected by a mask option, the watchdog timer
stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer.
However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0.
5. Shifting to status 5 (subsystem clock operation) can be performed only from status 3 or 4 (X1 input
clock operation).
6. Shifting to status 1 or status 2 from status 5 is not possible.
7. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 5-13. Status Transition Diagram (3/4)
(3) When “Ring-OSC cannot be stopped” is selected by mask option
(when subsystem clock is not used)
HALT
HALT
instruction
Interrupt
HALT instruction
Interrupt
Interrupt
HALT
instruction
Status 3
CPU clock: fXP
XP: Oscillating
: Oscillating
Status 1
CPU clock: f
fXP: Oscillation stopped
Status 2
CPU clock: f
XP: Oscillating
: Oscillating
MCM0 = 0
MSTOP = 1Note 2
R
R
f
f
f
f
MCM0 = 1Note 1
MSTOP = 0
R
f : Oscillating
R
R
STOP
instruction
Interrupt
Interrupt
STOP
STOP
instruction
Interrupt
instruction
STOPNote 3
Reset release
ResetNote 4
Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2. When shifting from status 2 to status 1, make sure that MCS is 0.
3. The watchdog timer operates using Ring-OSC even in STOP mode if “Ring-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Figure 5-13. Status Transition Diagram (4/4)
(4) When “Ring-OSC cannot be stopped” is selected by mask option
(when subsystem clock is used)
Status 5
CPU clock: fXT
fXP: Oscillation stopped
fR: Oscillating/
oscillation stopped
Interrupt
MCC = 0
MCC = 1
HALT instruction
Interrupt
Status 4
CPU clock: fXT
fXP: Oscillating
fR: Oscillating/
oscillation stopped
HALT
HALT instruction
HALT instruction
HALT
instruction
Interrupt
Interrupt
CSS = 0Note 5
HALT
instruction
Interrupt
CSS = 1Note 4
Status 1
CPU clock: fR
fXP: Oscillation stopped
fR: Oscillating
Status 3
MCM0 = 0
MSTOP = 1Note 2
Status 2
CPU clock: fXP
fXP: Oscillating
fR: Oscillating
CPU clock: fR
fXP: Oscillating
fR: Oscillating
MCM0 = 1Note 1
MSTOP = 0
STOP
instruction
Interrupt
STOP
instruction
STOP
instruction
Interrupt
Interrupt
STOPNote 3
Reset release
ResetNote 6
Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2. When shifting from status 2 to status 1, make sure that MCS is 0.
3. The watchdog timer operates using Ring-OSC even in STOP mode if “Ring-OSC cannot be stopped”
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
4. Shifting to status 4 (subsystem clock operation) can be performed only from status 3 (X1 input clock
operation).
5. Shifting to status 1 or status 2 from status 4 is not possible.
6. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
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Table 5-3. Relationship Between Operation Clocks in Each Operation Status
Status
X1
Ring-OSC Oscillator
Subsystem
Clock
CPU Clock
After
Prescaler Clock Supplied
to Peripherals
Oscillator
Oscillator
Release
Note 1
Note 2
MCM0 = 0
MCM0 = 1
Operation
Mode
Reset
STOP
HALT
RSTOP = 0 RSTOP = 1
Stopped
Stopped
Stopped
Ring-OSC
Note 3
Stopped
Stopped
Ring-OSC
Oscillating
Oscillating
Stopped
Oscillating
Oscillating
Note 4
X1
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for Ring-OSC by a mask
option.
Notes 1. When “Cannot be stopped” is selected for Ring-OSC by a mask option.
2. When “Can be stopped by software” is selected for Ring-OSC by a mask option.
3. Operates using the CPU clock at STOP instruction execution.
4. Operates using the CPU clock at HALT instruction execution.
Remark RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
MCM0: Bit 0 of the main clock mode register (MCM)
Table 5-4. Oscillation Control Flags and Clock Oscillation Status
X1 Oscillator
Ring-OSC Oscillator
Oscillating
MSTOP = 1Note RSTOP = 0
RSTOP = 1
Stopped
Setting prohibited
Oscillating
MSTOP = 0Note RSTOP = 0
Oscillating
Stopped
RSTOP = 1
MCC = 1Note
MCC = 0Note
RSTOP = 0
RSTOP = 1
RSTOP = 0
RSTOP = 1
Stopped
Oscillating
Stopped
Oscillating
Oscillating
Stopped
Note Setting X1 oscillator oscillating/stopped differs depending on the CPU clock used.
• When the Ring-OSC clock is used as the CPU clock: Set using the MSTOP bit
• When the subsystem clock is used as the CPU clock: Set using the MCC bit
Caution The RSTOP setting is valid only when “Can be stopped by software” is set for Ring-OSC
by a mask option.
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
MCC:
Bit 7 of the processor clock control register (PCC)
RSTOP: Bit 0 of the Ring-OSC mode register (RCM)
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5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Ring-OSC clock and X1 input
clock.
In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions
are executed using the pre-switch clock after switching MCM0 (see Table 5-5).
Bit 1 (MCS) of MCM is used to judge that operation is performed using either the Ring-OSC clock or X1 input clock.
To stop the clock, wait for the number of clocks shown in Table 5-5 before stopping.
Table 5-5. Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
PCC
Time Required for Switching
PCC2
PCC1
PCC0
X1→Ring-OSC
Ring-OSC→X1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
fXP/fR + 1 clock
fXP/2fR + 1 clock
fXP/4fR + 1 clock
fXP/8fR + 1 clock
2 clocks
fXP/16fR + 1 clock
Caution To calculate the maximum time, set fR = 120 kHz.
Remarks 1. PCC: Processor clock control register
2. fXP: X1 input clock oscillation frequency
3. fR: Ring-OSC clock oscillation frequency
4. The maximum time is the number of clocks of the CPU clock before switching.
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5.7 Changing System Clock and CPU Clock Settings
5.7.1 Time required for switching between system clock and CPU clock
The system clock and CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the
processor clock control register (PCC).
The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on
the pre-switchover clock for several instructions (see Table 5-6).
Whether the system is operating on the X1 input clock (or Ring-OSC clock) or the subsystem clock can be
ascertained using bit 5 (CLS) of the PCC register.
Table 5-6. Maximum Time Required for CPU Clock Switchover
Set Value Before
Switchover
Set Value After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
1
×
×
×
0
0
0
0
0
1
×
0
0
1
1
0
×
0
1
0
1
0
×
16 clocks
16 clocks
16 clocks
8 clocks
4 clocks
16 clocks
8 clocks
4 clocks
2 clocks
fXP/fXT clocks
(306 clocks)
8 clocks
4 clocks
2 clocks
1 clock
1 clock
8 clocks
fXP/2fXT clocks
(153 clocks)
4 clocks
2 clocks
1 clock
1 clock
fXP/4fXT clocks
(77 clocks)
2 clocks
1 clock
1 clock
fXP/8fXT clocks
(39 clocks)
1 clock
1 clock
fXP/16fXT clocks
(20 clocks)
1
1 clock
Remarks 1. The maximum time is the number of clocks of the pre-switchover CPU clock.
2. Figures in parentheses apply to operation with fXP = 10 MHz and fXT = 32.768 kHz.
Caution Selection of the CPU clock cycle division factor (PCC0 to PCC2) and switchover from the X1
input clock to the subsystem clock (changing CSS from 0 to 1) should not be set
simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock cycle division factor
(PCC0 to PCC2) and switchover from the subsystem clock to the X1 input clock (changing CSS
from 1 to 0).
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5.8 Clock Switching Flowchart and Register Setting
5.8.1 Switching from Ring-OSC clock to X1 input clock
Figure 5-14. Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
After reset
PCC = 00H
RCM = 00H
MCM = 00H
MOC = 00H
OSTC = 00H
OSTS = 05HNote
; fCPU = f
R
; Ring-OSC oscillation
Register value
after reset
; Ring-OSC clock operation
; X1 oscillation
; Oscillation stabilization time status register
; Oscillation stabilization time fXP/216
Each processing
OSTC checkNote
; X1 oscillation stabilization time status check
X1 oscillation stabilization
time has not elapsed
Ring-OSC clock
operation
X1 oscillation stabilization time has elapsed
PCC setting
Ring-OSC
clock operation
(dividing set PCC)
MCM.0 ← 1
MCM.1 (MCS) is changed from 0 to 1
X1 input clock operation
X1 input clock
Note Check the oscillation stabilization wait time of the X1 oscillator after reset release using the OSTC register
and then switch to the X1 input clock operation after the oscillation stabilization wait time has elapsed. The
OSTS register setting is valid only after STOP mode is released during X1 input clock operation.
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5.8.2 Switching from X1 input clock to Ring-OSC clock
Figure 5-15. Switching from X1 Input Clock to Ring-OSC Clock (Flowchart)
Register setting
in X1 input
clock operation
PCC.7 (MCC) = 0
PCC.4 (CSS) = 0
MCM = 03H
; X1 oscillation
; X1 input clock or Ring-OSC clock
; X1 input clock operation
Yes: RSTOP = 1
RCM.0Note
(RSTOP) = 1?
X1 input
clock operation
; Ring-OSC oscillating?
No: RSTOP = 0
RSTOP = 0
MCM0 ← 0
; Ring-OSC oscillating
MCM.1 (MCS) is changed from 1 to 0
Ring-OSC
clock operation
Ring-OSC clock operation
Note Required only when “clock can be stopped by software” is selected for Ring-OSC by a mask option.
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5.8.3 Switching from X1 input clock to subsystem clock
Figure 5-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart)
Register setting
in X1 input
clock operation
PCC.7 (MCC) = 0
PCC.4 (CSS) = 0
MCM = 03H
; X1 oscillation
; X1 input clock or Ring-OSC clock
; X1 input clock operation
X1 input
clock operation
CSS ← 1
; Subsystem clock operation
MCS = 1 not changed.
CLS is changed from 0 to 1.
Subsystem
clock
Subsystem clock operation
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5.8.4 Switching from subsystem clock to X1 input clock
Figure 5-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart)
PCC.4 (CSS) = 1
MCM = 03H
; Subsystem clock operation
No: X1 oscillating
MCC = 1?
; X1 oscillating?
Yes: X1 oscillation stopped
MCC ← 0
; X1 oscillation enabled
Subsystem
clock operation
OSTC check
; Wait for X1 oscillation stabilization time
X1 oscillation
stabilization time
not elapsed
X1 oscillation stabilization time elapsed
CSS ← 0
; X1 input clock operation
CLS is changed from 1 to 0.
MCS = 1 not changed.
X1 input
clock operation
X1 input clock operation
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5.8.5 Register settings
Table 5-7. Clock and Register Setting
fCPU
Mode
Setting Flag
MCM
Status Flag
PCC MCM
PCC Register
MOC
RCM
Register Register Register Register Register
MCC
CSS
MCM0 MSTOP RSTOPNote 1 CLS
MCS
X1 input clockNote 2
Ring-OSC clock
Ring-OSC oscillating
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
Ring-OSC stopped
X1 oscillating
X1 stopped
0
0
0
0Note 3
0
1
Subsystem clockNote 4 X1 oscillating, Ring-OSC oscillating
0
1Note 5
1Note 5
1Note 5
1Note 5
0Note 6
0Note 6
0Note 6
0Note 6
X1 stopped, Ring-OSC oscillating
1
X1 oscillating, Ring-OSC stopped
0
X1 stopped, Ring-OSC stopped
1
Notes 1. Valid only when “clock can be stopped by software” is selected for Ring-OSC by a mask option.
2. Do not set MCC = 1 or MSTOP = 1 during X1 input clock operation (even if MCC = 1 or MSTOP = 1 is set,
the X1 oscillation does not stop).
3. Do not set MCC = 1 during Ring-OSC operation (even if MCC = 1 is set, the X1 oscillation does not stop).
To stop X1 oscillation during Ring-OSC operation, use MSTOP.
4. Shifting to subsystem clock operation mode must be performed from the X1 input clock operation mode.
From subsystem clock operation mode, only X1 input clock operation mode can be shifted to.
5. Do not set MCM0 = 0 (shifting to Ring-OSC) during subsystem clock operation.
6. Do not set MSTOP = 1 during subsystem clock operation (even if MSTOP = 1 is set, X1 oscillation does
not stop). To stop X1 oscillation during subsystem clock operation, use MCC.
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.1 Functions of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions.
•
•
•
•
•
•
Interval timer
PPG output
Pulse width measurement
External event counter
Square-wave output
One-shot pulse output
(1) Interval timer
16-bit timer/event counter 00 generates an interrupt request at the preset time interval.
(2) PPG output
16-bit timer/event counter 00 can output a rectangular wave whose frequency and output pulse width can be set
freely.
(3) Pulse width measurement
16-bit timer/event counter 00 can measure the pulse width of an externally input signal.
(4) External event counter
16-bit timer/event counter 00 can measure the number of pulses of an externally input signal.
(5) Square-wave output
16-bit timer/event counter 00 can output a square wave with any selected frequency.
(6) One-shot pulse output
16-bit timer event counter 00 can output a one-shot pulse whose output pulse width can be set freely.
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6.2 Configuration of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 consists of the following hardware.
Table 6-1. Configuration of 16-Bit Timer/Event Counter 00
Configuration
Item
Timer counter
16 bits × 1 (TM00)
Register
16-bit timer capture/compare register: 16 bits × 2 (CR000, CR010)
Timer output
Control registers
1 (TO00)
16-bit timer mode control register 00 (TMC00)
16-bit timer capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 0 (PM0)Note
Note See Figure 4-2 Block Diagram of P00 and Figure 4-3 Block Diagram of P01.
Figure 6-1 shows the block diagram.
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
CRC002CRC001 CRC000
INTTM000
16-bit timer capture/compare
register 000 (CR000)
Noise
elimi-
nator
TI010/TO00/P01
Match
fX
f
f
X
X
/22
/28
16-bit timer counter 00
(TM00)
Clear
Output
controller
TO00/TI010/
P01
Match
Noise
elimi-
nator
2
fX
Noise
elimi-
nator
16-bit timer capture/compare
register 010 (CR010)
TI000/P00
INTTM010
CRC002
PRM001
TMC003 TMC002 TMC001OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
PRM000
16-bit timer output
control register 00
(TOC00)
16-bit timer mode
control register 00
(TMC00)
Prescaler mode
register 00 (PRM00)
Internal bus
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(1) 16-bit timer counter 00 (TM00)
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchronization with the rising edge of the input clock. The count value is reset to
0000H in the following cases.
<1> At RESET input
<2> If TMC003 and TMC002 are cleared
<3> If the valid edge of TI000 is input in the mode in which clear & start occurs when inputting the valid edge of
TI000
<4> If TM00 and CR000 match in the mode in which clear & start occurs on a match of TM00 and CR000
<5> OSPT00 is set in one-shot pulse output mode
(2) 16-bit timer capture/compare register 000 (CR000)
CR000 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register
00 (CRC00).
•
When CR000 is used as a compare register
The value set in CR000 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the
interval time when TM00 is set to interval timer operation.
•
When CR000 is used as a capture register
It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or
TI010 valid edge is set using prescaler mode register 00 (PRM00).
If the capture trigger is specified to be the valid edge of the TI000 pin, the situation is as shown in Table 6-2.
On the other hand, when the capture trigger is specified to be the valid edge of the TI010 pin, the situation is
as shown in Table 6-3.
Table 6-2. TI000 Pin Valid Edge and CR000, CR010 Capture Trigger
ES001 ES000
TI000 Pin Valid Edge
Falling edge
CR000 Capture Trigger
Rising edge
CR010 Capture Trigger
Falling edge
0
0
1
1
0
1
0
1
Rising edge
Falling edge
Rising edge
Setting prohibited
Both rising and falling edges
Setting prohibited
No capture operation
Setting prohibited
Both rising and falling edges
Table 6-3. TI010 Pin Valid Edge and CR000 Capture Trigger
TI010 Pin Valid Edge CR000 Capture Trigger
ES101 ES100
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Falling edge
Rising edge
Setting prohibited
Setting prohibited
Both rising and falling edges
Both rising and falling edges
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CR000 can be set by a 16-bit memory manipulation instruction.
RESET input clears CR000 to 0000H.
Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match
of TM00 and CR000. However, in the free-running mode and in the clear mode using the
valid edge of TI000, if CR000 is set to 0000H, an interrupt request (INTTM000) is generated
following overflow (FFFFH).
2. If the changed value of CR000 is smaller than the value of 16-bit timer counter 00 (TM00),
TM00 continues counting and starts counting again from 0 after overflow. Therefore, if the
value of CR000 after the change is smaller than before the change, the timer should be
restarted after CR000 is changed.
3. When P01 is used as the valid edge of TI010, it cannot be used as the timer output (TO00).
Moreover, when P01 is used as TO00, it cannot be used as the valid edge of TI010.
4. When CR000 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
5. Do not rewrite the compare register during TM00 operation.
(3) 16-bit timer capture/compare register 010 (CR010)
CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00
(CRC00).
•
When CR010 is used as a compare register
The value set in the CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and
an interrupt request (INTTM010) is generated if they match.
•
When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by
prescaler mode register 00 (PRM00).
CR010 can be set by a 16-bit memory manipulation instruction.
RESET input clears CR010 to 0000H.
Cautions 1. Set CR010 to other than 0000H. This means a 1-pulse count operation cannot be performed
when CR010 is used as the event counter.
However, in the free-running mode and in the clear mode using the valid edge of TI000, if
CR010 is set to 0000H, an interrupt request (INTTM010) is generated following overflow
(FFFFH).
2. When CR010 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
3. Do not rewrite the compare register during TM00 operation.
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6.3 Registers Controlling 16-Bit Timer/Event Counter 00
The following five registers are used to control 16-bit timer/event counter 00.
•
•
•
•
•
16-bit timer mode control register 00 (TMC00)
Capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 0 (PM0)
(1) 16-bit timer mode control register 00 (TMC00)
This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output
timing, and detects an overflow.
TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC00 to 00H.
Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to
values other than 0, 0 (operation stop mode), respectively. Set TMC002 and TMC003 to 0, 0 to
stop the operation.
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Figure 6-2. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address FFBAH After reset: 00H R/W
Symbol
TMC00
7
0
6
0
5
0
4
0
3
2
1
0
TMC003TMC002TMC001 OVF00
TMC003 TMC002 TMC001
Operating mode and clear
mode selection
TO00 output timing selection
No change
Interrupt request generation
Not generated
0
0
0
0
0
1
0
1
0
Operation stop
(TM00 cleared to 0)
Free-running mode
Match between TM00 and
CR000 or match between
TM00 and CR010
Generated on match between
TM00 and CR000, or match
between TM00 and CR010
0
1
1
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 valid edge
1
1
1
0
0
1
0
1
0
Clear & start occurs on TI000
valid edge
−
Clear & start occurs on match
between TM00 and CR000
Match between TM00 and
CR000 or match between
TM00 and CR010
1
1
1
Match between TM00 and
CR000, match between TM00
and CR010 or TI000 valid edge
OVF00
16-bit timer counter 00 (TM00) overflow detection
0
1
Overflow not detected
Overflow detected
Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.
2. Set the valid edge of the TI000/P00 pin using prescaler mode register 00 (PRM00).
3. If any the following modes: the mode in which clear & start occurs on match between TM00
and CR000, the mode in which clear & start occurs at the TI00 valid edge, or free-running
mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes from
FFFFH to 0000H, the OVF00 flag is set to 1.
Remarks 1. TO00: 16-bit timer/event counter 00 output pin
2. TI000: 16-bit timer/event counter 00 input pin
3. TM00: 16-bit timer counter 00
4. CR000: 16-bit timer capture/compare register 000
5. CR010: 16-bit timer capture/compare register 010
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(2) Capture/compare control register 00 (CRC00)
This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010).
CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CRC00 to 00H.
Figure 6-3. Format of Capture/Compare Control Register 00 (CRC00)
Address: FFBCH After reset: 00H R/W
Symbol
CRC00
7
0
6
0
5
0
4
0
3
0
2
1
0
CRC002
CRC001
CRC000
CRC002
CR010 operating mode selection
0
1
Operates as compare register
Operates as capture register
CRC001
CR000 capture trigger selection
0
1
Captures on valid edge of TI010
Captures on valid edge of TI000 by reverse phase
CRC000
CR000 operating mode selection
0
1
Operates as compare register
Operates as capture register
Cautions 1. Timer operation must be stopped before setting CRC00.
2. When the mode in which clear & start occurs on a match between TM00 and CR000 is
selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified
as a capture register.
3. To ensure that the capture operation is performed properly, the capture trigger requires a
pulse two times longer than the count clock selected by prescaler mode register 00 (PRM00).
(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter 00 output controller. It sets/resets the R-S
type flip-flop (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output,
enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software.
TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC00 to 00H.
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Figure 6-4. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FFBDH After reset: 00H R/W
Symbol
TOC00
7
0
6
5
4
3
2
1
0
OSPT00
OSPE00
TOC004
LVS00
LVR00
TOC001
TOE00
OSPT00
One-shot pulse output trigger control via software
0
1
No one-shot pulse trigger
One-shot pulse trigger
OSPE00
One-shot pulse output operation control
0
1
Successive pulse output mode
One-shot pulse output modeNote
TOC004
Timer output F/F control using match of CR010 and TM00
0
1
Disables inversion operation
Enables inversion operation
LVS00
LVR00
16-bit timer/event counter 00 timer output F/F status setting
0
0
1
1
0
1
0
1
No change
Timer output F/F reset (0)
Timer output F/F set (1)
Setting prohibited
TOC001
Timer output F/F control using match of CR000 and TM00
0
1
Disables inversion operation
Enables inversion operation
TOE00
16-bit timer/event counter 00 output control
0
1
Disables output (output fixed to level 0)
Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between
the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not
occur.
Cautions 1. Timer operation must be stopped before setting TOC00.
2. If LVS00 and LVR00 are read after data is set, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the operating clock is required to write to OSPT00
successively.
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(4) Prescaler mode register 00 (PRM00)
This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges.
PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears PRM00 to 00H.
Figure 6-5. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH After reset: 00H R/W
Symbol
PRM00
7
6
5
4
3
0
2
0
1
0
ES101
ES100
ES001
ES000
PRM001
PRM000
ES101
ES100
TI010 valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES001
ES000
TI000 valid edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
PRM001
PRM000
Count clock selection
0
0
1
1
0
1
0
1
fX (10 MHz)
fX/22 (2.5 MHz)
fX/28 (39.06 kHz)
TI000 valid edgeNote
Note The external clock requires a pulse two times longer than internal count clock (fX).
Cautions 1. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode
using the valid edge of TI000 and the capture trigger.
2. Always set data to PRM00 after stopping the timer operation.
3. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is
immediately detected after the rising edge or both the rising and falling edges are set as the
valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00
(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. However, when re-
enabling operation after the operation has been stopped once, the rising edge is not
detected.
4. When P01 is used as the TI010 valid edge, it cannot be used as the timer output (TO00), and
when used as TO00, it cannot be used as the TI010 valid edge.
Remarks 1. fX: X1 input clock oscillation frequency
2. TI000, TI010: 16-bit timer/event counter 00 input pin
3. Figures in parentheses are for operation with fX = 10 MHz.
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(5) Port mode register 0 (PM0)
This register sets port 0 input/output in 1-bit units.
When using the P01/TO00/TI010 pin for timer output, set the output latch of PM01 and P01 to 0.
PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM0 to FFH.
Figure 6-6. Format of Port Mode Register 0 (PM0)
Address: FF20H After reset: FFH R/W
Symbol
PM0
7
1
6
1
5
1
4
1
3
1
2
1
1
0
PM01 PM00
PM0n
P0n pin I/O mode selection (n = 0, 1)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-7 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value
preset in 16-bit timer capture/compare register 000 (CR000) as the interval.
When the count value of 16-bit timer counter 00 (TM00) matches the value set in CR000, counting continues with
the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.
The count clock of the 16-bit timer/event counter 00 can be selected with bits 0 and 1 (PRM000, PRM001) of
prescaler mode register 00 (PRM00).
See 6.5 Cautions for 16-Bit Timer/Event Counter 00 (2) 16-bit timer capture/compare register setting for
details of the operation when the compare register value is changed during timer count operation.
Figure 6-7. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF0
0
TMC00
0
0
0
0
1
1
0/1
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
0/1
0/1
0
CR000 used as compare register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. For details,
see Figures 6-2 and 6-3.
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Figure 6-8. Interval Timer Configuration Diagram
16-bit timer capture/compare
register 000 (CR000)
INTTM000
fX
fX/22
fX/28
16-bit timer counter 00
(TM00)
OVF00
Noise
eliminator
TI000/P00
Clear
circuit
fX
Figure 6-9. Timing of Interval Timer Operation
t
Count clock
TM00 count value
0000H
0000H
0001H
N
0001H
N
0000H 0001H
N
N
Count start
Clear
Clear
N
N
N
CR000
INTTM000
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
TO00
Interval time
Remark Interval time = (N + 1) × t
N = 0001H to FFFFH
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6.4.2 PPG output operations
Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown
in Figure 6-10 allows operation as PPG (Programmable Pulse Generator) output.
In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer
capture/compare register 000 (CR000), respectively.
Figure 6-10. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF0
0
TMC00
0
0
0
0
1
1
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
0
×
0
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
TOC00
0
0
0
1
0/1
0/1
1
1
Enables TO00 output
Inverts output on match between TM00 and CR000
Specifies initial value of TO00 output F/F
Inverts output on match between TM00 and CR010
Disables one-shot pulse output
Cautions 1. Values in the following range should be set in CR000 and CR010:
0000H < CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark ×: Don’t care
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Figure 6-11. Configuration of PPG Output
16-bit timer capture/compare
register 000 (CR000)
fX
f
X
X
/22
/28
Clear
circuit
16-bit timer counter 00
(TM00)
f
Noise
eliminator
TI000/P00
TO00/TI010/P01
fX
16-bit timer capture/compare
register 010 (CR010)
Figure 6-12. PPG Output Operation Timing
t
Count clock
TM00 count value
0000H 0001H
M – 1
M
0000H 0001H
N – 1
N
Count start
Clear
CR000 capture value
CR010 capture value
TO00
N
M
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
Remark 0000H < M < N ≤ FFFFH
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6.4.3 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer
counter 00 (TM00).
There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
(1) Pulse width measurement with free-running counter and one capture register
When 16-bit timer counter 00 (TM00) is operated in free-running mode (see register settings in Figure 6-13), and
the edge specified by prescaler mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken
into 16-bit timer capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is
set.
Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of
PRM00.
For valid edge detection, sampling is performed using the count clock selected by PRM00, and a capture
operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width.
Figure 6-13. Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00
TMC00
0
0
0
0
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
1
0/1
0
CR000 used as compare register
CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
For details, see Figures 6-2 and 6-3.
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Figure 6-14. Configuration Diagram for Pulse Width Measurement with Free-Running Counter
fX
/22
/28
16-bit timer counter 00
(TM00)
f
X
X
OVF00
f
16-bit timer capture/compare
register 010 (CR010)
TI000
INTTM010
Internal bus
Figure 6-15. Timing of Pulse Width Measurement Operation with Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
Count clock
0000H 0001H
D0 D0 + 1
D1 D1 + 1
FFFFH 0000H
D2
D3
TM00 count value
TI000 pin input
CR010 capture value
INTTM010
D0
D1
D2
D3
OVF00
(D1 – D0) × t
(10000H – D1 + D2) × t
(D3 – D2) × t
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(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 00 (TM00) is operated in free-running mode (see Figure 6-16), it is possible to
simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin.
When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to
the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt
request signal (INTTM010) is set.
Also, when the edge specified by bits 6 and 7 (ES100 and ES101) of PRM00 is input to the TI010 pin, the value
of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal
(INTTM000) is set.
Any of three edgesrising, falling, or both edgescan be selected as the valid edge of the TI000 pin and the
TI010 pin, specified using bits 4 and 5 (ES000 and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00,
respectively.
For valid edge detection of the TI000 and TI010 pins, sampling is performed at the interval selected by prescaler
mode register 00 (PRM00), and a capture operation is only performed when a valid level is detected twice, thus
eliminating noise with a short pulse width.
Figure 6-16. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF0
0
TMC00
0
0
0
0
0
1
0/1
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
1
0
1
CR000 used as capture register
Captures valid edge of TI010 pin to CR000
CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
For details, see Figure 6-2.
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•
Capture operation (free-running mode)
The capture register operation when capture trigger is input is shown below.
Figure 6-17. CR010 Capture Operation with Rising Edge Specified
Count clock
TM00
N – 3
N – 2
N – 1
N
N + 1
TI000
Rising edge detection
N
CR010
INTTM010
Figure 6-18. Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)
t
Count clock
0000H 0001H
D0 D0 + 1
D1 D1 + 1
FFFFH 0000H
D2 D2 + 1 D2 + 2
D3
TM00 count value
TI000 pin input
D0
D1
D2
CR010 capture value
INTTM010
TI010 pin input
CR000 capture value
INTTM000
D1
D2 + 1
OVF00
(D1 – D0) × t
(10000H – D1 + D2) × t
(D3 – D2) × t
(10000H – D1 + (D2 + 1)) × t
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(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 00 (TM00) is operated in free-running mode (see Figure 6-19), it is possible to
measure the pulse width of the signal input to the TI000 pin.
When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to
the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt
request signal (INTTM010) is set.
Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into
16-bit timer capture/compare register 000 (CR000).
Either of two edgesrising or fallingcan be selected as the valid edge of the TI000 pin specified using bits 4
and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00).
For TI000 pin valid edge detection, sampling is performed at the interval selected by prescaler mode register 00
(PRM00), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise
with a short pulse width.
Figure 6-19. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF0
0
TMC00
0
0
0
0
0
1
0/1
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000.
CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-20. Timing of Pulse Width Measurement Operation with Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
t
Count clock
TM00 count value
TI000 pin input
0000H 0001H
D0 D0 + 1
D1 D1 + 1
FFFFH 0000H
D2 D2 + 1
D3
CR010 capture value
CR000 capture value
INTTM010
D0
D2
D1
D3
OVF00
(D1 – D0) × t
(10000H – D1 + D2) × t
(D3 – D2) × t
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(4) Pulse width measurement by means of restart
When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken
into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000
pin is measured by clearing TM00 and restarting the count operation (see Figure 6-21).
Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode
register 00 (PRM00).
In valid edge detection, sampling is performed using the count clock cycle selected by prescaler mode register 00
(PRM00) and a capture operation is only performed when a valid level is detected twice, thus eliminating noise
with a short pulse width.
Figure 6-21. Control Register Settings for Pulse Width Measurement by Means of Restart
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00
TMC00
0
0
0
0
1
0
0/1
0
Clears and starts at valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
1
1
1
CR000 used as capture register
Captures to CR000 at inverse edge to valid edge of TI000.
CR010 used as capture register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
For details, see Figure 6-2.
Figure 6-22. Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified)
t
Count clock
0000H 0001H
D0 0000H 0001H D1
D2 0000H 0001H
TM00 count value
TI000 pin input
CR010 capture value
D0
D2
D1
CR000 capture value
INTTM010
D1 × t
D2 × t
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6.4.4 External event counter operation
The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer
counter 00 (TM00).
TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.
When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is
cleared to 0 and the interrupt request signal (INTTM000) is generated.
Input a value other than 0000H to CR000 (a count operation with 1-bit pulse cannot be carried out).
Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of
prescaler mode register 00 (PRM00).
Because operation is carried out only after the valid edge is detected twice by sampling using the internal clock (fX),
noise with short pulse widths can be eliminated.
Figure 6-23. Control Register Settings in External Event Counter Mode
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00
TMC00
0
0
0
0
1
1
0/1
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
0/1
0/1
0
CR000 used as compare register
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
For details, see Figures 6-2 and 6-3.
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Figure 6-24. Configuration Diagram of External Event Counter
16-bit timer capture/compare
register 000 (CR000)
Match
INTTM000
f
X
Clear
f
f
X
X
/22
/28
16-bit timer/counter 00 (TM00)
OVF00
f
X
Noise eliminator
Noise eliminator
16-bit timer capture/compare
register 010 (CR010)
Valid edge of TI000
Internal bus
Figure 6-25. External Event Counter Operation Timing (with Rising Edge Specified)
TI000 pin input
TM00 count value
CR000
0000H 0001H 0002H 0003H 0004H 0005H
N − 1
N
0000H 0001H 0002H 0003H
N
INTTM000
Caution When reading the external event counter count value, TM00 should be read.
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6.4.5 Square-wave output operation
A square wave with any selected frequency can be output at intervals of the count value preset to 16-bit timer
capture/compare register 000 (CR000).
The TO00 pin output status is reversed at intervals of the count value preset to CR000 by setting bit 0 (TOE00) and
bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave with any selected
frequency to be output.
Figure 6-26. Control Register Settings in Square-Wave Output Mode
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00
TMC00
0
0
0
0
1
1
0
0
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
0/1
0/1
0
CR000 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
TOC00
0
0
0
0
0/1
0/1
1
1
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F.
Does not invert output on match between TM00 and CR010.
Disables one-shot pulse output.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. For
details, see Figures 6-3 and 6-4.
Figure 6-27. Square-Wave Output Operation Timing
Count clock
TM00 count value
CR000
0000H 0001H 0002H
N − 1
N
0000H 0001H 0002H
N − 1
N
0000H
N
INTTM000
TO00 pin output
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6.4.6 One-shot pulse output operation
16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external
trigger (TI000 pin input).
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-27, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.
By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes
active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the
output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000
(CR000)Note
.
Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00
register, the TMC003 and TMC002 bits of the TMC00 register must be set to 00.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 register.
Cautions 1. Do not set the OSPT00 bit while the one-shot pulse is being output. To output the one-shot
pulse again, wait until the current one-shot pulse output is completed.
2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software
trigger, do not change the level of the TI000 pin or its alternate-function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
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Figure 6-28. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00
TMC00
0
0
0
0
0
1
0
0
Free-running mode
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
0
0/1
0
CR000 as compare register
CR010 as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 LVS00
0/1
LVR00 TOC001 TOE00
TOC00
0
0
1
1
0/1
1
1
Enables TO00 output
Inverts output upon match
between TM00 and CR000
Specifies initial value of
TO00 output F/F
Inverts output upon match
between TM00 and CR010
Sets one-shot pulse output mode
Set to 1 for output
Caution Do not set 0000H to the CR000 and CR010 registers.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
For details, see Figures 6-3 and 6-4.
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Figure 6-29. Timing of One-Shot Pulse Output Operation with Software Trigger
Set TMC00 to 0CH
(TM00 count starts)
Count clock
TM00 count
CR010 set value
CR000 set value
0000H 0001H
N
N + 1 0000H
N – 1
N
N
M – 1
M
M + 1 M + 2
N
N
N
M
M
M
M
OSPT00
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC003 and TMC002 bits.
Remark N < M
(2) One-shot pulse output with external trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in
Figure 6-30, and by using the valid edge of the TI000 pin as an external trigger.
The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES001) of prescaler mode register 00
(PRM00). The rising, falling, or both the rising and falling edges can be specified.
When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the
output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010).
After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register
000 (CR000)Note
.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 register.
Caution Even if the external trigger is generated again while the one-shot pulse is output, it is ignored.
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Figure 6-30. Control Register Settings for One-Shot Pulse Output with External Trigger
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00
TMC00
0
0
0
0
1
0
0
0
Clears and starts at
valid edge of TI000 pin
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
CRC00
0
0
0
0
0
0
0/1
0
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 LVS00
0/1
LVR00 TOC001 TOE00
0/1
TOC00
0
0
1
1
1
1
Enables TO00 output
Inverts output upon match
between TM00 and CR000
Specifies initial value of
TO00 output F/F
Inverts output upon match
between TM00 and CR010
Sets one-shot pulse output mode
Caution Do not set the CR000 and CR010 registers to 0000H.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
For details, see Figures 6-3 and 6-4.
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Figure 6-31. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
Set TMC00 to 08H
(TM00 count starts)
Count clock
TM00 count value
CR010 set value
CR000 set value
0000H 0001H
0000H
N
N
N + 1 N + 2
M − 2 M − 1
M
M + 1 M + 2
N
N
N
M
M
M
M
TI000 pin input
INTTM010
INTTM000
TO00 pin output
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC002 and TMC003 bits.
Remark N < M
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.5 Cautions for 16-Bit Timer/Event Counter 00
(1) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Figure 6-32. Start Timing of 16-Bit Timer Counter 00 (TM00)
Count clock
0000H
0001H
0002H
0003H
0004H
TM00 count value
Timer start
(2) 16-bit timer capture/compare register setting (in the mode in which clear & start occurs on match
between TM00 and CR000)
Set 16-bit timer capture/compare registers 000, 010 (CR000, CR010) to other than 0000H. This means a 1-pulse
count operation cannot be performed when 16-bit timer/event counter 00 is used as an event counter.
(3) Operation after compare register change during timer count operation
If the value after 16-bit timer capture/compare register 000 (CR000) is changed is smaller than that of 16-bit timer
counter 00 (TM00), TM00 continues counting, overflows and then restarts counting from 0. Thus, if the value (M)
after CR000 changes is smaller than that (N) before the change, it is necessary to restart the timer after changing
CR000.
Figure 6-33. Timings After Change of Compare Register During Timer Count Operation
Count clock
N
M
CR000
X − 1
X
FFFFH
0000H
0001H
0002H
TM00 count value
Remark N > X > M
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(4) Capture register data retention timing
If the valid edge of the TI000 pin is input during 16-bit timer capture/compare register 010 (CR010) read, CR010
performs a capture operation. However, the value read at this time is not guaranteed.
The interrupt request flag (TMIF010) is set upon detection of the valid edge.
Figure 6-34. Capture Register Data Retention Timing
Count clock
TM00 count value
Edge input
N
N + 1
N + 2
M
M + 1
M + 2
Interrupt request flag
Capture read signal
CR010 interrupt value
X
N + 2
M + 1
Capture
Capture, but
read value is
not guaranteed
(5) Valid edge setting
Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control
register 00 (TMC00) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4
and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00).
(6) Re-triggering one-shot pulse
(a) One-shot pulse output by software
When a one-shot pulse is output, do not set the OSPT00 bit to 1. Do not output the one-shot pulse again
until INTTM000, which occurs upon a match with the CR000 register, or INTTM010, which occurs upon a
match with the CR010 register, occurs.
(b) One-shot pulse output with external trigger
If the external trigger occurs again while a one-shot pulse is output, it is ignored.
(c) One-shot pulse output function
When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change
the level of the TI000 pin or its alternate function port pin.
Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the
TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing.
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(7) Operation of OVF00 flag
<1> The OVF00 flag is set to 1 in the following case.
When of the following modes: the mode in which clear & start occurs on a match between TM00 and
CR000, the mode in which clear & start occurs on a TI00 valid edge, or the free-running mode, is selected
↓
CR000 is set to FFFFH
↓
TM00 is counted up from FFFFH to 0000H.
Figure 6-35. Operation Timing of OVF00 Flag
Count clock
CR000
TM00
FFFFH
FFFEH
FFFFH
0000H
0001H
OVF00
INTTM000
<2> Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the
occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.
(8) Conflicting operations
<1> Conflict between the read period of the 16-bit timer capture/compare register (CR000/CR010) and capture
trigger input (CR000/CR010 used as capture register)
Capture trigger input has priority. The data read from CR000/CR010 is undefined.
<2> Conflict between the write period of the 16-bit timer capture/compare register (CR000/CR010) and the
match timing of 16-bit timer counter 00 (TM00) (CR000/CR010 used as a compare register)
Match determination is not performed normally. Do not write any data to CR000/CR010 near the match
timing.
(9) Timer operation
<1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare
register 010 (CR010).
<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins
are not acknowledged.
<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between
the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not
occur.
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(10) Capture operation
<1> If TI000 valid edge is specified as the count clock, a capture operation by the capture register specified as
the trigger for TI000 is not possible.
<2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than
the count clock selected by prescaler mode register 00 (PRM00).
<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input
(INTTM000/INTTM010), however, is generated at the rise of the next count clock.
(11) Compare operation
<1> When the 16-bit timer capture/compare register (CR000/CR010) is overwritten during timer operation, a
match interrupt may be generated or a clear operation may not be performed normally if that value is close
to or larger than the timer value.
<2> A capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger
has been input.
(12) Edge detection
<1> If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising
and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16-bit timer counter
00 (TM00) operation, a rising edge is detected immediately after the operation is enabled. Be careful
therefore when pulling up the TI000 or TI010 pin. However, the rising edge is not detected at restart after
the operation has been stopped once.
<2> The sampling clock used to remove noise differs when the TI000 valid edge is used as the count clock and
when it is used as a capture trigger. In the former case, the count clock is fX, and in the latter case the
count clock is selected by prescaler mode register 00 (PRM00). The capture operation is started only after
a valid edge is detected twice by sampling, thus eliminating noise with a short pulse width.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.1 Functions of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 have the following functions.
•
•
•
•
Interval timer
External event counter
Square-wave output
PWM output
Figures 7-1 and 7-2 show the block diagrams of 8-bit timer/event counters 50 and 51.
Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
8-bit timer compare
register 50 (CR50)
Selector
INTTM50
TI50/TO50/P17
Match
fX
f /2
X
S
INV
/22
Q
f
f
f
X
X
X
8-bit timer
/26
/28
OVF
TO50/TI50/P17
counter 50 (TM50)
R
f
X
/213
Clear
S
R
Invert
level
3
Selector
TCE50 TMC506 LVS50 LVR50 TMC501 TOE50
TCL502 TCL501 TCL500
8-bit timer mode control
register 50 (TMC50)
Timer clock selection
register 50 (TCL50)
Internal bus
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Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
8-bit timer compare
register 51 (CR51)
Selector
INTTM51
TI51/TO51/P33/INTP4
Match
fX
f /2
X
S
INV
/24
Q
f
f
f
X
X
X
8-bit timer
/26
/28
OVF
TO51/TI51/P33/INTP4
counter 51 (TM51)
R
f
X
/212
Clear
S
R
Invert
level
3
Selector
TCE51 TMC516 LVS51 LVR51 TMC511 TOE51
TCL512 TCL511 TCL510
8-bit timer mode control
register 51 (TMC51)
Timer clock selection
register 51 (TCL51)
Internal bus
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7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51
8-bit timer/event counters 50 and 51 consist of the following hardware.
Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51
Item
Timer register
Configuration
8-bit timer counter 5n (TM5n)
Register
8-bit timer compare register 5n (CR5n)
1 (TO5n)
Timer output
Control registers
Timer clock selection register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 1 (PM1)Note or port mode register 3 (PM3)Note
Note See Figure 4-9 Block Diagram of P16 and P17 and Figure 4-12 Block Diagram of P33.
(1) 8-bit timer counter 5n (TM5n)
TM5n is an 8-bit register that counts the count pulses and is read-only.
The counter is incremented in synchronization with the rising edge of the count clock.
When the count value is read during operation, count clock input is temporary stopped, and then the count value
is read. In the following situations, the count value is cleared to 00H.
<1> RESET input
<2> When TCE5n is cleared
<3> When TM5n and CR5n match in the mode in which clear & start occurs upon a match of the TM5n and
CR5n.
(2) 8-bit timer compare register 5n (CR5n)
CR5n can be read and written by an 8-bit memory manipulation instruction.
Except in PWM mode, the value set in CR5n is constantly compared with the 8-bit timer counter 5n (TM5n) count
value, and an interrupt request (INTTM5n) is generated if they match.
In PWM mode, when the TO5n pin becomes active due to a TM5n overflow and the values of TM5n and CR5n
match, the TO5n pin becomes inactive.
The value of CR5n can be set within 00H to FFH.
Cautions 1. In the mode in which clear & start occurs on a match of TM5n and CR5n (TMC5n6 = 0), do
not write other values to CR5n during operation.
2. In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock
selected by TCL5n) or more.
Remark n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
The following three registers are used to control 8-bit timer/event counters 50 and 51.
•
•
•
Timer clock selection register 5n (TCL5n)
8-bit timer mode control register 5n (TMC5n)
Port mode register 1 (PM1) or port mode register 3 (PM3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of TI5n input.
TCL5n can be set by an 8-bit memory manipulation instruction.
RESET input clears TCL5n to 00H.
Remark n = 0, 1
Figure 7-3. Format of Timer Clock Selection Register 50 (TCL50)
Address: FF6AH After reset: 00H R/W
Symbol
TCL50
7
0
6
0
5
0
4
0
3
0
2
1
0
TCL502
TCL501
TCL500
TCL502
TCL501
TCL500
Count clock selection
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TI50 falling edge
TI50 rising edge
fX (10 MHz)
fX/2 (5 MHz)
fX/22 (2.5 MHz)
fX/26 (156.25 kHz)
fX/28 (39.06 kHz)
fX/213 (1.22 kHz)
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to set bits 3 to 7 to 0.
Remarks 1. fX: X1 input clock oscillation frequency
2. Figures in parentheses apply to operation at fX = 10 MHz.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Figure 7-4. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH After reset: 00H R/W
Symbol
TCL51
7
0
6
0
5
0
4
0
3
0
2
1
0
TCL512
TCL511
TCL510
TCL512
TCL511
TCL510
Count clock selection
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TI51 falling edge
TI51 rising edge
fX (10 MHz)
fX/2 (5 MHz)
fX/24 (625 kHz)
fX/26 (156.25 kHz)
fX/28 (39.06 kHz)
fX/212 (2.44 kHz)
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to set bits 3 to 7 to 0.
Remarks 1. fX: X1 input clock oscillation frequency
2. Figures in parentheses apply to operation at fX = 10 MHz.
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(2) 8-bit timer mode control register 5n (TMC5n)
TMC5n is a register that performs the following five types of settings.
<1> 8-bit timer counter 5n (TM5n) count operation control
<2> 8-bit timer counter 5n (TM5n) operating mode selection
<3> Timer output F/F (flip flop) status setting
<4> Active level selection in timer F/F control or PWM (free-running) mode.
<5> Timer output control
TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark n = 0, 1
Figure 7-5. Format of 8-Bit Timer Mode Control Register 50 (TMC50)
Address: FF6BH
Symbol
After reset: 00H R/WNote
7
6
5
0
4
0
3
2
1
0
TMC50
TCE50
TMC506
LVS50
LVR50
TMC501
TOE50
TCE50
TM50 count operation control
0
1
After clearing to 0, count operation disabled (counter stopped)
Count operation start
TMC506
TM50 operating mode selection
0
1
Mode in which clear & start occurs on a match between TM50 and CR50
PWM (free-running) mode
LVS50
LVR50
Timer output F/F status setting
0
0
1
1
0
1
0
1
No change
Timer output F/F reset (0)
Timer output F/F set (1)
Setting prohibited
TMC501
In other modes (TMC506 = 0)
Timer F/F control
In PWM mode (TMC506 = 1)
Active level selection
0
1
Inversion operation disabled
Inversion operation enabled
Active-high
Active-low
TOE50
Timer output control
0
1
Output disabled (TO50 pin outputs the low level)
Output enabled
Note Bits 2 and 3 are write-only.
(Refer to Caution and Remark on the page after the next.)
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Figure 7-6. Format of 8-Bit Timer Mode Control Register 51 (TMC51)
Address: FF43H
Symbol
After reset: 00H R/WNote
7
6
5
0
4
0
3
2
1
0
TMC51
TCE51
TMC516
LVS51
LVR51
TMC511
TOE51
TCE51
TM51 count operation control
0
1
After clearing to 0, count operation disabled (counter stopped)
Count operation start
TMC516
TM51 operating mode selection
0
1
Mode in which clear & start occurs on a match between TM51 and CR51
PWM (free-running) mode
LVS51
LVR51
Timer output F/F status setting
0
0
1
1
0
1
0
1
No change
Timer output F/F reset (0)
Timer output F/F set (1)
Setting prohibited
TMC511
In other modes (TMC516 = 0)
Timer F/F control
In PWM mode (TMC516 = 1)
Active level selection
0
1
Inversion operation disabled
Inversion operation enabled
Active-high
Active-low
TOE51
Timer output control
0
1
Output disabled (TO51 pin outputs the low level)
Output enabled
Note Bits 2 and 3 are write-only.
(Refer to Caution and Remark on the next page.)
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Cautions 1. To clear TCE5n to 0, set the interrupt mask flag (TMMK5n) to 1 beforehand. Otherwise, an
interrupt may occur when TCE5n is cleared.
TCE5n is cleared to 0 as follows.
TMMK5n = 1; Mask set
TCE5n = 0;
TMIF5n = 0;
Timer clear
Interrupt request flag clear
TMMK5n = 0; Mask clear
•
•
•
TCE5n = 1;
Timer start
•
•
•
2. The settings of LVS5n and LVR5n are valid in other than PWM mode.
3. Do not rewrite TMC5n1 and TOE5n simultaneously.
4. When switching to the PWM mode, do not rewrite TM5n6 and LVS5n or LVR5n
simultaneously.
5. To rewrite TMC5n6, stop operation beforehand.
Remarks 1. In PWM mode, PWM output is made inactive by setting TCE5n to 0.
2. If LVS5n and LVR5n are read after data is set, 0 is read.
3. The values of the TMC5n6, LVS5n, LVR5n, TMC5n1, and TOE5n bits are reflected at the TO5n pin
regardless of the value of TCE5n.
4. n = 0, 1
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(3) Port mode register 1 (PM1) and 3 (PM3)
These registers set port 1 and 3 input/output in 1-bit units.
When using the P17/TO50/TI50 and P33/TO51/TI51 pins for timer output, set PM17 and PM33 and the output
latches of P17 and P33 to 0.
PM1 and PM3 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 7-7. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol
PM1
7
6
5
4
3
2
1
0
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM10
PM1n
P1n pin I/O mode selection (n = 0 to 7)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
Figure 7-8. Format of Port Mode Register 3 (PM3)
Address: FF23H After reset: FFH R/W
Symbol
PM3
7
0
6
0
5
0
4
0
3
2
1
0
PM33
PM32
PM31
PM30
PM3n
P3n pin I/O mode selection (n = 0 to 3)
0
1
Output mode (output buffer on)
Input mode (output buffer off)
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.4 Operations of 8-Bit Timer/Event Counters 50 and 51
7.4.1 Operation as interval timer
8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals
of the count value preset to 8-bit timer compare register 5n (CR5n).
When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the
TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
The count clock of TM5n can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n
(TCL5n).
[Setting]
<1> Set the registers.
•
•
•
TCL5n: Select the count clock.
CR5n: Compare value
TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n
and CR5n.
(TMC5n = 0000×××0B × = Don’t care)
<2> After TCE5n = 1 is set, the count operation starts.
<3> If the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> INTTM5n is generated repeatedly at the same interval.
Set TCE5n to 0 to stop the count operation.
Caution Do not write other values to CR5n during operation.
Figure 7-9. Interval Timer Operation Timing (1/2)
(a) Basic operation
t
Count clock
TM5n count value
CR5n
00H 01H
Count start
N
N
00H 01H
N
00H 01H
N
N
Clear
Clear
N
N
TCE5n
INTTM5n
Interrupt acknowledged
Interval time
Interrupt acknowledged
Interval time
TO5n
Interval time
Remark Interval time = (N + 1) × t
N = 00H to FFH
n = 0, 1
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Figure 7-9. Interval Timer Operation Timing (2/2)
(b) When CR5n = 00H
t
Count clock
TM5n 00H
CR5n
00H 00H
00H 00H
TCE5n
INTTM5n
TO5n
Interval time
(c) When CR5n = FFH
t
Count clock
TM5n
01
FE
FF
FF
00
FE
FF
FF
00
CR5n
FF
TCE5n
INTTM5n
Interrupt acknowledged
Interval time
Interrupt
acknowledged
TO5n
Remark n = 0, 1
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7.4.2 Operation as external event counter
The external event counter counts the number of external clock pulses to be input to TI5n by 8-bit timer counter 5n
(TM5n).
TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input.
Either the rising or falling edge can be selected.
When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0
and an interrupt request signal (INTTM5n) is generated.
Whenever the TM5n value matches the value of CR5n, INTTM5n is generated.
[Setting]
<1> Set each register.
•
TCL5n: Select TI5n input edge.
TI5n falling edge → TCL5n = 00H
TI5n rising edge → TCL5n = 01H
CR5n: Compare value
•
•
TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
CR5n, disable the timer F/F inversion operation, disable timer output.
(TMC5n = 0000××00B × = Don’t care)
<2> When TCE5n = 1 is set, the number of pulses input from TI5n is counted.
<3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match.
Figure 7-10. External Event Counter Operation Timing (with Rising Edge Specified)
TI5n
Count start
TM5n count value
CR5n
00
01
02
03
04
05
N – 1
N
00
01
02
03
N
INTTM5n
Remark N = 00H to FFH
n = 0, 1
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
7.4.3 Square-wave output operation
A square wave with any selected frequency is output at intervals of the value preset to 8-bit timer compare register
5n (CR5n).
The TO5n pin output status is inverted at intervals of the count value preset to CR5n by setting bit 0 (TOE5n) of 8-
bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output
(duty = 50%).
[Setting]
<1> Set each register.
•
•
•
•
Set the port latches (P17 and P33)Note and port mode registers (PM17 and PM33)Note to 0.
TCL5n: Select the count clock.
CR5n: Compare value
TMC5n: Stop the count operation, select the mode in which clear & start occurs on a match of TM5n and
CR5n.
LVS5n LVR5n
Timer Output F/F Status Setting
High-level output
Low-level output
1
0
0
1
Timer output F/F inversion enabled
Timer output enabled
(TMC5n = 00001011B or 00000111B)
<2> After TCE5n = 1 is set, the count operation starts.
<3> The timer output F/F is inverted by a match of TM5n and CR5n. After INTTM5n is generated, TM5n is
cleared to 00H.
<4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output from
TO5n.
The frequency is as follows.
Frequency = fCNT/2 (N + 1)
(N: 00H to FFH, fCNT: Count clock)
Note 8-bit timer/event counter 50: P17, PM17
8-bit timer/event counter 51: P33, PM33
Caution Do not write other values to CR5n during operation.
Remark n = 0, 1
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Figure 7-11. Square-Wave Output Operation Timing
Count clock
TMn count value
00H
01H
02H
N – 1
N
00H
01H
02H
N – 1
N
00H
Count start
N
CR5n
TO5nNote
Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control
register 5n (TMC5n).
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7.4.4 PWM output operation
8-bit timer/event counter 5n operates as a PWM output when bit 6 (TMC5n6) of 8-bit timer mode control register 5n
(TMC5n) is set to 1.
The duty ratio pulse determined by the value set to 8-bit timer compare register 5n (CR5n) is output from TO5n.
Set the active level width of the PWM pulse to CR5n; the active level can be selected with bit 1 (TMC5n1) of
TMC5n.
The count clock can be selected with bits 0 to 2 (TCL5n0 to TCL5n2) of timer clock selection register 5n (TCL5n).
PWM output can be enabled/disabled with bit 0 (TOE5n) of TMC5n.
Caution In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock (clock selected by
TCL5n) or more.
(1) PWM output basic operation
[Setting]
<1> Set each register.
•
•
•
•
Set the port latches (P17, P33)Note and port mode registers (PM17, PM33)Note to 0.
TCL5n: Select the count clock.
CR5n: Compare value
TMC5n: Stop the count operation, select PWM mode.
The timer output F/F is not changed.
TMC5n1
Active Level Selection
0
1
Active-high
Active-low
Timer output enabled
(TMC5n = 01000001B or 01000011B)
<2> The count operation starts when TCE5n = 1.
Set TCE5n to 0 to stop the count operation.
Note 8-bit timer/event counter 50: P17, PM17
8-bit timer/event counter 51: P33, PM33
[PWM output operation]
<1> PWM output (output from TO5n) outputs an inactive level after the count operation starts until an overflow
occurs.
<2> When an overflow occurs, the active level set in <1> above is output.
The active level is output until CR5n matches the count value of 8-bit timer counter 5n (TM5n).
<3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again.
<4> Operations <2> and <3> are repeated until the count operation stops.
<5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive.
Remark n = 0, 1
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Figure 7-12. PWM Output Operation Timing
(a) Basic operation (active level = H)
Count clock
TM5n
00H 01H
N
FFH 00H 01H 02H
N
N + 1
FFH 00H 01H 02H
M
00H
CR5n
TCE5n
INTTM5n
TO5n
Active level
Inactive level
Active level
(b) CR5n = 00H
Count clock
TM5n 00H 01H
FFH 00H 01H 02H
N
N + 1 N + 2
FFH 00H 01H 02H
M 00H
00H
CR5n
TCE5n
INTTM5n
TO5n
L
Inactive level
Inactive level
(c) CR5n = FFH
TM5n
CR5n
M 00H
00H 01H
FFH 00H 01H 02H
N
N + 1 N + 2
FFH 00H 01H 02H
FFH
TCE5n
INTTM5n
TO5n
Active level
Inactive level
Inactive level
Active level
Inactive level
Remark n = 0, 1
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(2) Operation with CR5n changed
Figure 7-13. Timing of Operation with CR5n Changed
(a) CR5n value is changed from N to M before clock rising edge of FFH
→ Value is reloaded to CR5n at overflow immediately after change.
Count clock
TM5n
CR5n
N
N + 1 N + 2
FFH 00H 01H 02H
M
M + 1 M + 2
FFH 00H 01H 02H
M M + 1 M + 2
N
M
TCE5n
H
INTTM5n
TO5n
<2>
<1> CR5n change (N → M)
(b) CR5n value is changed from N to M after clock rising edge of FFH
→ Value is reloaded to CR5n at second overflow.
Count clock
TM5n
N
N + 1 N + 2
FFH 00H 01H 02H
N
N + 1 N + 2
FFH 00H 01H 02H
M M + 1 M + 2
CR5n
N
N
M
TCE5n
H
INTTM5n
TO5n
<2>
<1> CR5n change (N → M)
Caution When reloading from CR5n between <1> and <2> in Figure 7-13, the value read differs from the
actual value (read value: M, actual value of CR5n: N).
7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51
(1) Timer start error
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Figure 7-14. 8-Bit Timer Counter 5n Start Timing
Count clock
TM5n count value
00H
Timer start
01H
02H
03H
04H
Remark n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.1 Functions of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 have the following functions.
•
•
•
8-bit-accuracy interval timer
8-bit-accuracy PWM pulse generator mode
8-bit-accuracy carrier generator mode (8-bit timer H1 only)
8.2 Configuration of 8-Bit Timers H0 and H1
8-bit timers H0 and H1 consist of the following hardware.
Table 8-1. Configuration of 8-Bit Timers H0 and H1
Configuration
Item
Timer register
Registers
8-bit timer counter Hn (TMHn)
8-bit timer H compare register 0n (CMP0n)
8-bit timer H compare register 1n (CMP1n)
Timer output
Two outputs (TOHn)
Control registers
8-bit timer H mode register n (TMHMDn)
8-bit timer H carrier control register 1 (TMCYC1)Note
Note 8-bit timer H1 only
Remark n = 0, 1
Figures 8-1 and 8-2 show the block diagrams.
Figure 8-1. Block Diagram of 8-Bit Timer H0
Internal bus
8-bit timer H mode control
register 0 (TMHMD0)
8-bit timer H
8-bit timer H
TMHE0 CKS02 CKS01 CKS00 TMMD01TMMD00 TOLEV0 TOEN0
compare register compare register
10 (CMP10)
00 (CMP00)
3
2
TOH0/P15
Decoder
Selector
F/F
R
Match
Interrupt
generator
Output
controller
Level
inversion
f
X
f
X
/2
/22
/26
8-bit timer
counter H0
(TMH0)
f
f
X
X
f
X
/210
Clear
TO50/TI50/P17
PWM mode signal
1
0
Timer H enable signal
INTTMH0
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Figure 8-2. Block Diagram of 8-Bit Timer H1
Internal bus
8-bit timer H mode control
register 1 (TMHMD1)
8-bit timer H carrier
control register 1
(TMCYC1)
8-bit timer H
compare register
11 (CMP11)
8-bit timer H
compare register
01 (CMP01)
TMHE1 CKS12 CKS11 CKS10 TMMD11TMMD10 TOLEV1 TOEN1
RMC1 NRZB1 NRZ1
Reload/
interrupt
control
INTTM51
3
2
TOH1/
INTP5/
P16
Decoder
Selector
F/F
Match Interrupt
generator
Output
controller
Level
inversion
R
f
X
f
f
f
X
X
X
/22
/24
/26
8-bit timer
counter H1
(TMH1)
f
X
/212
f
/27
R
Clear
Carrier generator mode signal
PWM mode signal
1
0
Timer H enable signal
INTTMH1
(1) 8-bit timer H compare register 0n (CMP0n)
This register can be read/written by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
After reset: 00H R/W Address: FF18H, FF1AH
7
5
3
2
1
0
6
4
CMP0n
Caution This register cannot be rewritten during timer count operation.
(2) 8-bit timer H compare register 1n (CMP1n)
This register can be read/written by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
After reset: 00H R/W Address: FF19H, FF1BH
7
5
3
2
1
0
6
4
CMP1n
The CMP1n register can be rewritten during timer count operation.
In the carrier generator mode, an interrupt request signal (INTTMHn) is generated if the values of the timer counter
and CMP1n register match after setting the CMP1n register. The timer counter value is cleared at the same time. If
the CMP1n register value is rewritten during timer operation, reloading is performed at the timing at which the counter
value and CMP1n register value match. If the transfer timing and writing from CPU to CMP1n register conflict,
transfer is not performed.
Remark n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.3 Registers Controlling 8-Bit Timers H0 and H1
8-bit timers H0 and H1 are controlled by 8-bit timer H mode registers 0 and 1 (TMHMD0, TMHMD1) and 8-bit timer
H carrier control register 1 (TMCYC1)Note
.
Note 8-bit timer H1 only
(1) 8-bit timer H mode registers 0 and 1 (TMHMD0, TMHMD1)
These registers control the mode of timer H.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 8-3. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
Address: FF69H After reset: 00H R/W
7
5
3
2
1
0
6
4
TMHMD0
TMHE0 CKS02
CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0
TMHE0
Timer operation enable
0
1
Stops timer count operation
Enables timer count operation (count operation started by inputting clock)
CKS02
CKS01
CKS00
Count clock (fCNT) selection
(10 MHz)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
f
f
f
f
f
X
X
X
X
X
/2
(5 MHz)
/22
/26
(2.5 MHz)
(156.25 kHz)
/210 (9.77 kHz)
TO50
Other than above
Setting prohibited
TMMD01 TMMD00
Timer operation mode
0
1
0
0
Interval timer mode
PWM pulse generator mode
Other than above Setting prohibited
TOLEV0
Timer output level control (in default mode)
0
1
Low level
High level
TOEN0
Timer output control
0
1
Disables output
Enables output
Caution When TMHE0 = 1, setting the other bits of the TMHMD0 register is prohibited.
Remarks 1. fX: X1 input clock oscillation frequency
2. Figures in parentheses apply to operation at fX = 10 MHz
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Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
Address: FF6CH After reset: 00H R/W
7
5
3
2
1
0
6
4
TMHMD1
TMHE1 CKS12
CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
TMHE1
Timer operation enable
0
1
Stops timer count operation
Enables timer count operation (count operation started by inputting clock)
CKS12
CKS11
CKS10
Count clock (fCNT) selection
(10 MHz)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
f
f
f
f
f
f
X
X
X
X
X
/22
/24
/26
(2.5 MHz)
(625 kHz)
(156.25 kHz)
/212 (2.44 kHz)
/27
(1.88 kHz (TYP.))
R
Other than above
Setting prohibited
TMMD11 TMMD10
Timer operation mode
0
0
1
0
1
0
Interval timer mode
Carrier generator mode
PWM pulse generator mode
Other than above Setting prohibited
TOLEV1
Timer output level control (in default mode)
0
1
Low level
High level
TOEN1
Timer output control
0
1
Disables output
Enables output
Caution When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.
Remarks 1. fX: X1 input clock oscillation frequency
2. fR: Ring-OSC clock oscillation frequency
3. Figures in parentheses apply to operation at fX = 10 MHz, fR = 240 kHz (TYP.).
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(2) 8-bit timer H carrier control register 1 (TMCYC1)
This register controls the remote control output and carrier pulse output status of 8-bit timer H1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 8-5. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)
Address: FF6DH After reset: 00H R/WNote
TMCYC1
0
0
0
0
0
RMC1
NRZB1
NRZ1
RMC1
NRZB1
Remote control output
0
0
1
1
0
1
0
1
Low-level output
High-level output
Low-level output
Carrier pulse output
NRZ1
Carrier pulse output status flag
0
1
Carrier output disabled status (low-level status)
Carrier output enabled status
(RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status)
Note Bit 0 is read-only.
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.4 Operation of 8-Bit Timers H0 and H1
8.4.1 Operation as interval timer
When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is
generated and 8-bit timer counter Hn is cleared to 00H.
Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the
CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.
(1) Usage
Generates the INTTMHn signal repeatedly at the same interval.
<1> Set each register.
Figure 8-6. Register Setting in Interval Timer Mode
(i) Setting timer H mode register n (TMHMDn)
TMHEn
0
CKSn2 CKSn1
0/1 0/1
CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn
0/1 0/1 0/1
TMHMDn
0
0
Timer output setting
Timer output level inversion setting
Interval timer mode setting
Count clock (fCNT) selection
Count operation stopped
(ii) CMP0n register setting
Compare value (N)
•
<2> Count operation starts when TMHEn = 1.
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated
and 8-bit timer counter Hn is cleared to 00H.
Interval timer = (N +1)/fCNT
<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, set
TMHEn to 0.
Remark n = 0, 1
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(2) Timing chart
The timing in interval timer mode is shown below.
Figure 8-7. Timing of Interval Timer Operation (1/2)
(a) Basic operation
Count clock
Count start
00H
01H
N
N
00H
Clear
01H
N
00H 01H 00H
Clear
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
Interval time
<1>
<2>
Level inversion,
<3>
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
match interrupt occurrence,
8-bit timer counter Hn clear
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn
is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.
<3> The INTTMHn signal and TOHn output become inactive by setting the TMHEn bit to 0 during timer Hn
operation. If these are inactive from the first, the level is retained.
Remark n = 0, 1
N = 00H to FFH
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Figure 8-7. Timing of Interval Timer Operation (2/2)
(b) Operation when CMP0n = FFH
Count clock
Count start
00H
00H
01H
FEH
FFH
00H
FEH
FFH
8-bit timer counter Hn
Clear
Clear
FFH
CMP0n
TMHEn
INTTMHn
TOHn
Interval time
(c) Operation when CMP0n = 00H
Count clock
Count start
00H
00H
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
Interval time
Remark n = 0, 1
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8.4.2 Operation as PWM pulse generator
In PWM mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register
during timer operation is prohibited.
8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register
during timer operation is possible.
The operation in PWM mode is as follows.
TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the
CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn
and the CMP1n register match.
(1) Usage
In PWM mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.
<1> Set each register.
Figure 8-8. Register Setting in PWM Pulse Generator Mode
(i) Setting timer H mode register n (TMHMDn)
TMHEn
0
CKSn2 CKSn1
0/1 0/1
CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn
0/1 0/1
TMHMDn
1
0
1
Timer output enabled
Timer output level inversion setting
PWM mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) Setting CMP0n register
Compare value (N): Cycle setting
•
(iii) Setting CMP1n register
•
Compare value (M): Duty setting
Remarks 1. n = 0, 1
2. 00H ≤ CMP1n (M) < CMP0n (N) < FFH
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared,
an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time,
the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the
CMP1n register.
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<4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the
compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the
CMP0n register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not
generated.
<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty ratio can be obtained.
<6> To stop the count operation, set TMHEn = 0.
If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock
frequency is fCNT, the PWM pulse output cycle and duty ratio are as follows.
PWM pulse output cycle = (N+1)/fCNT
Duty ratio = Inactive width : Active width = (M + 1) : (N – M)
Caution In PWM mode, three operation clocks (signal selected using the CKSn2 to CKSn0 bits of the
TMHMDn register) are required to transfer the CMP1n register value after rewriting the register.
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(2) Timing chart
The operation timing in PWM mode is shown below.
Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H ≤ CMP1n (M) < CMPn0 (N) < FFH
Remark n = 0, 1
Figure 8-9. Operation Timing in PWM Pulse Generator Mode (1/4)
(a) Basic operation
Count clock
00H 01H
A5H 00H 01H 02H
A5H 00H 01H 02H
A5H 00H
8-bit timer counter Hn
A5H
01H
CMP0n
CMP1n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
<4>
<2>
<3>
<1>
TOHn
(TOLEVn = 1)
<1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one
count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0).
<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted,
the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.
<3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is
returned. At this time, the 8-bit timer counter value is not cleared and the INTTMHn signal is not output.
<4> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.
Remark n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
Figure 8-9. Operation Timing in PWM Pulse Generator Mode (2/4)
(b) Operation when CMP0n = FFH, CMP1n = 00H
Count clock
8-bit timer counter Hn
00H 01H
FFH 00H 01H 02H
FFH 00H 01H 02H
FFH 00H
FFH
00H
CMP0n
CMP1n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
(c) Operation when CMP0n = FFH, CMP1n = FEH
Count clock
00H 01H
FEH FFH 00H 01H
FEH FFH 00H 01H
FEH FFH 00H
8-bit timer counter Hn
FFH
FEH
CMP0n
CMP1n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
Remark n = 0, 1
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Figure 8-9. Operation Timing in PWM Pulse Generator Mode (3/4)
(d) Operation when CMP0n = 01H, CMP1n = 00H
Count clock
00H 01H 00H 01H 00H
00H 01H 00H 01H
8-bit timer counter Hn
CMP0n
01H
00H
CMP1n
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
Remark n = 0, 1
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Figure 8-9. Operation Timing in PWM Pulse Generator Mode (4/4)
(e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H)
Count clock
8-bit timer counter Hn
00H 01H 02H
A5H 00H 01H 02H 03H
A5H 00H 01H 02H 03H
A5H 00H
A5H
03H
CMP0n
CMP1n
01H
01H (03H)
<2>
<2>'
TMHEn
INTTMHn
TOHn
(TOLEVn = 0)
<3>
<4>
<6>
<1>
<5>
<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count
clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0).
<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn
is cleared, the TOHn output becomes active, and the INTTMHn signal is output.
<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the
values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to
the CMP1n register and the CMP1n register value is changed (<2>’).
However, three count clocks or more are required from when the CMP1n register value is changed to when
the value is transferred to the register. If a match signal is generated within three count clocks, the changed
value cannot be transferred to the register.
<5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output
becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
<6> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.
Remark n = 0, 1
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CHAPTER 8 8-BIT TIMERS H0 AND H1
8.4.3 Carrier generator mode operation (8-bit timer H1 only)
The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer/event counter 51.
In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer/event counter 51,
and the carrier pulse is output from the TOH1 output.
In carrier generator mode, the connection between 8-bit timer H1 and 8-bit timer/event counter 51 is as shown
below.
Figure 8-10. Example of Connection Between 8-Bit Timer H1 and 8-Bit Timer/Event Counter 51
INTTM51
8-bit timer/event counter 51
TO51
TMMD01,
TMMD11
INTTM51
Selector
INTC
INTTM5H1
INTTMH1
8-bit timer H1
TOH1
Prescaler
CPU
(1) Carrier generation
In carrier generator mode, 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse
waveform and 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform.
Rewriting the CMP11 register during 8-bit timer H1 operation is possible but rewriting the CMP01 register is
prohibited.
(2) Carrier output control
Carrier output is controlled by the interrupt request signal (INTTM51) of 8-bit timer/event counter 51 and the
NRZ1 and RMC1 bits of the 8-bit timer H carrier control register (TMCYC1). The relationship between the
outputs is shown below.
RMC1 Bit
NRZ1 Bit
Output
Low-level output
0
0
1
1
0
1
0
1
High-level output
Low-level output
Carrier pulse output
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To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register
have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written.
The INTTM51 signal is synchronized with the 8-bit timer H1 clock and output as the INTTM5H1 signal. The
INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the
NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below.
Figure 8-11. Transfer Timing
TMHE1
8-bit timer H1
count clock
INTTM51
INTTM5H1
<1>
0
1
0
NRZ1
NRZB1
RMC1
<2>
1
0
1
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(3) Usage
Outputs an arbitrary carrier clock from the TOH1 pin.
<1> Set each register.
Figure 8-12. Register Setting in Carrier Generator Mode
(i) Setting 8-bit timer H mode register 1 (TMHMD1)
TMHE1
0
CKS12 CKS11
0/1 0/1
CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
0/1 0/1 0/1
TMHMD1
0
1
Timer output enabled
Timer output level inversion setting
Carrier generator mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) CMP01 register setting
• Compare value
(iii) CMP11 register setting
• Compare value
(iv) TMCYC1 register setting
• RMC1 = 1 ... Remote control output enable bit
• NRZB1 = 0/1 ... carrier output enable bit
(v) TCL51 and TMC51 register setting
• Refer to 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51.
<2> When TMHE1 = 1, 8-bit timer H1 starts counting.
<3> When TCE51 of 8-bit timer mode control register 51 (TMC51) is set to 1, 8-bit timer/event counter 51 starts
counting.
<4> After the count operation is enabled, the first compare register to be compared is the CMP01 register.
When the count value of 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal
is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared
with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register.
<5> When the count value of 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal
is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared
with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register.
<6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated.
<7> The INTTM51 signal is synchronized with 8-bit timer H1 and output as the INTTM5H1 signal. The
INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is
transferred to the NRZ1 bit.
<8> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin.
<9> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, set
TMHE1 to 0.
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If the setting value of the CMP01 register is 1, the setting value of the CMP11 register is M, and the count clock
frequency is fCNT, the carrier clock output cycle and duty ratio are as follows.
Carrier clock output cycle = (1 + M + 2)/fCNT
Duty ratio = High-level width : Low-level width = ( M + 1) : (1 + 1)
(4) Timing chart
The carrier output control timing is shown below.
Cautions 1. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
2. In the carrier generator mode, three operating clocks (signal selected by CKS12 to CKS10
bits of TMHMD1 register) or more are required from when the CMP11 register value is
changed to when the value is transferred to the register.
3. Be sure to set the RMC1 bit before the count operation is started.
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Figure 8-13. Carrier Generator Mode Operation Timing (1/3)
(a) Operation when CMP01 = 1, CMP11 = 1
8-bit timer H1
count clock
8-bit timer counter
H1 count value
00H
N
00H
N
00H
N
00H
N
00H
N
00H
N
N
CMP01
CMP11
N
TMHE1
INTTMH1
Carrier clock
<3>
<4>
<1> <2>
00H 01H
8-bit timer 51
count clock
TM51 count value
L
00H 01H
L
00H 01H
L
L
00H 01H
L
00H 01H
CR51
TCE51
<5>
INTTM51
NRZB1
0
1
0
1
0
<6>
0
1
0
1
0
NRZ1
Carrier clock
TOH1
<7>
<1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer H1 operation is stopped.
<2> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the
inactive level.
<3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer
counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to
00H.
<4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is
generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to
00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty ratio fixed to 50% is
generated.
<5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 and output as the INTTM5H1
signal.
<6> The INTTM5H1 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is
transferred to the NRZ1 bit.
<7> When NRZ1 = 0 is set, the TOH1 output becomes low level.
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Figure 8-13. Carrier Generator Mode Operation Timing (2/3)
(b) Operation when CMP01 = 1, CMP11 = M (operation when carrier clock phase is asynchronous to NRZ1 phase)
8-bit timer H1
count clock
8-bit timer counter
00H
N
00H 01H
M
00H
N
00H 01H
M
00H
N
00H
H1 count value
N
CMP01
M
CMP11
TMHE1
INTTMH1
Carrier clock
<3>
<4>
<1> <2>
00H 01H
8-bit timer 51
count clock
TM51 count value
L
00H 01H
L
00H 01H
L
L
00H 01H
L
00H 01H
CR51
TCE51
<5>
INTTM51
NRZB1
NRZ1
0
1
0
1
0
<6>
0
1
0
1
0
Carrier clock
TOH1
<7>
<1> When TMHE1 = 0 and TCE51 = 0, 8-bit timer H1 operation is stopped.
<2> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the
inactive level.
<3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer
counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to
00H.
<4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is
generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to
00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty ratio fixed to other than
50% is generated.
<5> When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 and output as the INTTM5H1
signal.
<6> When the carrier clock phase becomes asynchronous to the NRZ1 bit phase, a carrier signal is output at the
first rising edge of the carrier clock if NRZ1 is set to 1.
<7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier
clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).
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Figure 8-13. Carrier Generator Mode Operation Timing (3/3)
(c) Operation when CMP11 is changed
8-bit timer H1
count clock
8-bit timer counter
H1 count value
00H 01H
N
00H 01H
00H
N
N
00H 01H
L
00H
M
CMP01
CMP11
TMHE1
<3>
<3>’
M
L
M (L)
INTTMH1
<4>
<5>
<2>
Carrier clock
<1>
<1> When TMHE1 = 1 is set, 8-bit timer H1 starts a count operation. At that time, the carrier clock is held at the
inactive level.
<2> When the count value of 8-bit timer counter H1 matches the CMP01 register value, 8-bit timer counter H1 is
cleared and the INTTMH1 signal is output.
<3> The CMP11 register can be rewritten during 8-bit timer H1 operation, however, the changed value (L) is
latched. The CMP11 register is changed when the count value of 8-bit timer counter H1 and the CMP11
register value before the change (M) match (<3>’).
<4> When the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match,
the INTTMH1 signal is output, the carrier signal is inverted, and 8-bit timer counter H1 is cleared to 00H.
<5> The timing at which the count value of 8-bit timer counter H1 and the CMP11 register value match again is
indicated by the value after the change (L).
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CHAPTER 9 WATCH TIMER
9.1 Functions of Watch Timer
The watch timer has the following functions.
•
•
Watch timer
Interval timer
The watch timer and the interval timer can be used simultaneously.
Figure 9-1 shows the watch timer block diagram.
Figure 9-1. Watch Timer Block Diagram
Clear
5-bit counter
Clear
INTWT
INTWTI
f
/27
X
11-bit prescaler
/25 f /26 f /27 f /28
f
W
f
W
/24 f
W
W
W
W
f
W
/210
f
W
/211 f /29
W
f
XT
WTM7 WTM6 WTM5 WTM4
Internal bus
WTM3
WTM2 WTM1 WTM0
Watch timer operation
mode register (WTM)
Remark fX: X1 input clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
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(1) Watch timer
When the X1 input clock or subsystem clock is used, interrupt requests (INTWT) are generated at preset
intervals.
Table 9-1. Watch Timer Interrupt Time
Interrupt Time
When Operated at fXT = 32.768 kHz
When Operated at fX = 10 MHz
205 µs
24/fW
25/fW
213/fW
214/fW
488 µs
977 µs
0.25 s
0.5 s
410 µs
0.105 s
0.210 s
Remark fX: X1 input clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
(2) Interval timer
Interrupt requests (INTWTI) are generated at preset time intervals.
Table 9-2. Interval Timer Interval Time
Interval Time
When Operated at fXT = 32.768 kHz
When Operated at fX = 10 MHz
205 µs
410 µs
24/fW
25/fW
26/fW
27/fW
28/fW
29/fW
210/fW
211/fW
488 µs
977 µs
1.95 ms
3.91 ms
7.81 ms
15.6 ms
31.2 ms
62.4 ms
820 µs
1.64 ms
3.28 ms
6.55 ms
13.1 ms
26.2 ms
Remark fX: X1 input clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
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9.2 Configuration of Watch Timer
The watch timer consists of the following hardware.
Table 9-3. Watch Timer Configuration
Configuration
Item
Counter
5 bits × 1
Prescaler
11 bits × 1
Control register
Watch timer operation mode register (WTM)
9.3 Register Controlling Watch Timer
The watch timer is controlled by the watch timer operation mode register (WTM).
•
Watch timer operation mode register (WTM)
This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit
counter operation control.
WTM is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WTM to 00H.
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Figure 9-2. Format of Watch Timer Operation Mode Register (WTM)
Address: FF6FH After reset: 00H R/W
Symbol
WTM
7
6
5
4
3
2
<1>
<0>
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
WTM7
Watch timer count clock selection
0
1
fX/27 (78.125 kHz)
fXT (32.768 kHz)
WTM6
WTM5
WTM4
Prescaler interval time selection
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24/fW
25/fW
26/fW
27/fW
28/fW
29/fW
210/fW
211/fW
WTM3
WTM2
Interrupt time selection
0
0
1
1
0
1
0
1
214/fW
213/fW
25/fW
24/fW
WTM1
5-bit counter operation control
0
1
Clear after operation stop
Start
WTM0
Watch timer operation enable
0
1
Operation stop (clear both prescaler and timer)
Operation enable
Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM)
during watch timer operation.
Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT)
2. fX: X1 input clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
4. Figures in parentheses apply to operation with fX = 10 MHz, fXT = 32.768 kHz.
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9.4 Watch Timer Operations
9.4.1 Watch timer operation
The watch timer generates an interrupt request (INTWT) at a specific time interval by using the X1 input clock or
subsystem clock.
When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count
operation starts. When these bits are set to 0, the 5-bit counter is cleared and the count operation stops.
When the interval timer is simultaneously operated, zero-second start can be achieved only for the watch timer by
setting WTM1 to 0. In this case, however, the 11-bit prescaler is not cleared. Therefore, an error up to 211 × 1/fW
seconds occurs in the first overflow (INTWT) after zero-second start.
The interrupt request is generated at the following time intervals.
Table 9-4. Watch Timer Interrupt Time
WTM3
WTM2
Interrupt Time Selection When Operated at fXT = 32.768 kHz
(WTM7 = 1)
When Operated at fX = 10 MHz
(WTM7 = 0)
0
0
1
1
0
1
0
1
214/fW
213/fW
25/fW
24/fW
0.5 s
0.210 s
0.25 s
977 µs
488 µs
0.105 s
410 µs
205 µs
Remark fX: X1 input clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
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9.4.2 Interval timer operation
The watch timer operates as interval timer which generates interrupt requests (INTWTI) repeatedly at an interval of
the preset count value.
The interval time can be selected with bits 4 to 6 (WTM4 to WTM6) of the watch timer operation mode register
(WTM).
When bit 0 (WTM0) of the WTM is set to 1, the count operation starts. When this bit is set to 0, the count operation
stops.
Table 9-5. Interval Timer Interval Time
WTM6
WTM5
WTM4
Interval Time
When Operated at
When Operated at
fXT = 32.768 kHz (WTM7 = 1)
fX = 10 MHz (WTM7 = 0)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
24/fW
25/fW
26/fW
27/fW
28/fW
29/fW
210/fW
211/fW
488 µs
205 µs
977 µs
410 µs
1.95 ms
3.91 ms
7.81 ms
15.6 ms
31.2 ms
62.4 ms
820 µs
1.64 ms
3.28 ms
6.55 ms
13.1 ms
26.2 ms
Remark fX: X1 input clock oscillation frequency
fXT: Subsystem clock oscillation frequency
fW: Watch timer clock frequency
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Figure 9-3. Operation Timing of Watch Timer/Interval Timer
5-bit counter
0H
Overflow
Overflow
Start
Count clock
/211
f
W
Watch timer
interrupt INTWT
Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s)
Interval timer
interrupt INTWTI
Interval time
(T)
T
n × T
n × T
Caution When operation of the watch timer and 5-bit counter is enabled by the watch timer mode control
register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1), the interval until the first
interrupt request (INTWT) is generated after the register is set does not exactly match the
specification made with bit 3 (WTM3) of WTM. This is because there is a delay of one 11-bit
prescaler output cycle until the 5-bit counter starts counting. Subsequently, however, the INTWT
signal is generated at the specified intervals.
Remark fW: Watch timer clock frequency
n: The number of times of interval timer operations
Figures in parentheses are for operation with fW = 32.768 kHz (WTM7 = 1, WTM3, WTM2 = 0, 0)
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CHAPTER 10 WATCHDOG TIMER
10.1 Functions of Watchdog Timer
The watchdog timer detects an inadvertent program loop. If a program loop is detected, an internal reset signal
(WDTRES) is generated.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, refer to CHAPTER 18 RESET FUNCTION.
Table 10-1. Loop Detection Time of Watchdog Timer
Loop Detection Time
During Ring-OSC Clock Operation
fR/211 (8.53 ms)
During X1 Input Clock Operation
fXP/213 (819.2 µs)
fR/212 (17.07 ms)
fXP/214 (1.64 ms)
fXP/215 (3.28 ms)
fXP/216 (6.55 ms)
fXP/217 (13.11 ms)
fXP/218 (26.21 ms)
fXP/219 (52.43 ms)
fXP/220 (104.86 ms)
fR/213 (34.13 ms)
fR/214 (68.27 ms)
fR/215 (136.53 ms)
fR/216 (273.07 ms)
fR/217 (546.13 ms)
fR/218 (1.09 s)
Remarks 1. fR: Ring-OSC clock oscillation frequency
2. fXP: X1 input clock oscillation frequency
3. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz
The operation mode of the watchdog timer (WDT) is switched according to the mask option setting of the on-chip
Ring-OSC as shown in Table 10-2.
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Table 10-2. Mask Option Setting and Watchdog Timer Operation Mode
Mask Option
Ring-OSC Cannot Be Stopped
Ring-OSC Can Be Stopped by Software
Watchdog timer clock
source
Fixed to fRNote 1
.
• Selectable by software (fXP, fR or
stopped)
• When reset is released: fR
Operation after reset
Operation mode selection
Features
Operation starts with the maximum
interval (fR/218).
Operation starts with maximum
interval (fR/218).
The interval can be changed only
once.
The clock selection/interval can be
changed only once.
• The watchdog timer cannot be
stopped.
The watchdog timer can be stopped in
standby modeNote 2
.
• Current in STOP mode ≅ 10 µA
Notes 1. As long as power is being supplied, Ring-OSC oscillation cannot be stopped (except in the reset
period).
2. Clock supply to the watchdog timer is stopped in accordance with the watchdog timer clock
source as follows:
<1> When the clock source is fXP
Clock supply to the watchdog timer is stopped while fXP is stopped, during HALT/STOP
instruction execution, and during the oscillation stabilization time.
<2> When the clock source is fR
Clock supply to the watchdog timer is stopped if fR is stopped by software before STOP
instruction execution when the CPU clock is fXP and during HALT/STOP instruction
execution.
Remarks 1. fR: Ring-OSC clock oscillation frequency
2. fXP: X1 input clock oscillation frequency
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10.2 Configuration of Watchdog Timer
The watchdog timer consists of following hardware.
Table 10-3. Configuration of Watchdog Timer
Item
Configuration
Control registers
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 10-1. Block Diagram of Watchdog Timer
f
f
XP/213 to
XP/220
f
/22
R
Clock
input
controller
Output
controller
WDTRES
(internal reset signal)
16-bit
counter
Selector
or
f
XP/24
f
f
R
R
/211 to
/218
2
3
3
Clear
Mask option
(to set "Ring-OSC
cannot be stopped" or
"Ring-OSC can be
stopped by software")
0
1
1
WDCS4 WDCS3 WDCS2 WDCS1 WDCS0
Watchdog timer enable
register (WDTE)
Watchdog timer mode
register (WDTM)
Internal bus
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10.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
•
•
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Figure 10-2. Format of Watchdog Timer Mode Register (WDTM)
Address: FF98H After reset: 67H R/W
7
0
6
1
5
1
4
3
2
1
0
Symbol
WDTM
WDCS4
WDCS3
WDCS2
WDCS1
WDCS0
WDCS4Note 1 WDCS3Note 1
Operation clock selection
0
0
1
0
1
×
Ring-OSC clock (fR)
X1 input clock (fXP)
Watchdog timer operation stopped
WDCS2Note 2 WDCS1Note 2 WDCS0Note 2
Overflow time setting
During Ring-OSC clock
operationNote 3
During X1 input clock operation
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fR/211 (8.53 ms)
fR/212 (17.07 ms)
fR/213 (34.13 ms)
fR/214 (68.27 ms)
fR/215 (136.53 ms)
fR/216 (273.07 ms)
fR/217 (546.13 ms)
fR/218 (1.09 s)
fXP/213 (819.2 µs)
fXP/214 (1.64 ms)
fXP/215 (3.28 ms)
fXP/216 (6.55 ms)
fXP/217 (13.11 ms)
fXP/218 (26.21 ms)
fXP/219 (52.43 ms)
fXP/220 (104.86 ms)
Notes 1. If “Ring-OSC cannot be stopped” is specified by a mask option, this cannot be set. The Ring-
OSC clock will be selected no matter what value is written.
2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
3. Ring-OSC clock oscillation frequency: 120 kHz (MIN.), 240 kHz (TYP.), or 480 kHz (MAX.)
Caution If data is written to WDTM, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
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Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “Ring-OSC cannot be stopped”
is selected by a mask option, other values are ignored).
2. After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing attempted a second time, an internal reset signal
is generated.
3. WDTM cannot be set by a 1-bit memory manipulation instruction.
Remarks 1. fR: Ring-OSC clock oscillation frequency
2. fXP: X1 input clock oscillation frequency
3. ×: Don’t care
4. Figures in parentheses apply to operation at fR = 240 kHz (TYP.), fXP = 10 MHz
(2) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 9AH.
Figure 10-3. Format of Watchdog Timer Enable Register (WDTE)
Address: FF99H After reset: 9AH R/W
7
6
5
4
3
2
1
0
Symbol
WDTE
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated (an error occurs in the assembler).
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
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10.4 Operation of Watchdog Timer
10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by a mask option
The operation clock of watchdog timer is fixed to the Ring-OSC.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
•
•
•
Operation clock: Ring-OSC clock
Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.))
Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
.
•
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4
(WDCS3, WDCS4) of WDTM, it is ignored.
2. As soon as WDTM is written, the counter of the watchdog timer is cleared.
Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP
instruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected as
the count source, so clear the watchdog timer using the interrupt request of TMH1 before the
watchdog timer overflows. If this processing is not performed, an internal reset signal is
generated when the watchdog timer overflows after STOP instruction execution.
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10.4.2 Watchdog timer operation when “Ring-OSC can be stopped by software” is selected by mask option
The operation clock of the watchdog timer can be selected as either the Ring-OSC clock or the X1 input clock.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1).
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
•
•
•
Operation clock: Ring-OSC clock oscillation frequency (fR)
Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.))
Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2, 3
.
•
Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).
Ring-OSC clock (fR)
X1 input clock (fXP)
Watchdog timer operation stopped
Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
•
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared.
2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. If other values are set, the watchdog timer cannot be
operated (an error occurs in the assembler).
3. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal
reset signal is not generated even if the following processing is performed.
•
•
•
WDTM is written a second time.
A 1-bit memory manipulation instruction is executed to WDTE.
A value other than ACH is written to WDTE.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0.
For the watchdog timer operation during STOP mode and HALT mode in each status, refer to 10.4.3 Watchdog
timer operation in STOP mode and 10.4.4 Watchdog timer operation in HALT mode.
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10.4.3 Watchdog timer operation in STOP mode (when “Ring-OSC can be stopped by software” is selected
by mask option)
The watchdog timer stops counting during STOP instruction execution regardless of whether the X1 input clock or
Ring-OSC clock is being used.
(1) When the CPU clock and the watchdog timer operation clock are the X1 input clock (fXP) when the STOP
instruction is executed
When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,
counting stops for the oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
and then counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0.
Figure 10-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: X1 Input Clock)
Normal
operation
Oscillation stabilization time
CPU operation
STOP
Normal operation
f
XP
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
fR
Watchdog timer
Operating
Operation stopped
Operating
(2) When the CPU clock is the X1 input clock (fXP) and the watchdog timer operation clock is the Ring-OSC
clock (fR) when the STOP instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0.
Figure 10-5. Operation in STOP Mode
(CPU Clock: X1 Input Clock, WDT Operation Clock: Ring-OSC Clock)
Normal
operation
Oscillation stabilization time
Normal operation
CPU operation
STOP
fXP
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
fR
Watchdog timer
Operating Operation stopped
Operating
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(3) When the CPU clock is the Ring-OSC clock (fR) and the watchdog timer operation clock is the X1 input
clock (fXP) when the STOP instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started
using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0
<1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses.
<2> The CPU clock is switched to the X1 input clock (fXP).
Figure 10-6. Operation in STOP Mode
(CPU Clock: Ring-OSC Clock, WDT Operation Clock: X1 Input Clock)
<1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time
select register (OSTS) has elapsed
Normal operation
(Ring-OSC clock)
STOP
Clock supply stopped
Normal operation (Ring-OSC clock)
CPU operation
fXP
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
fR
17 clocks
Watchdog timer
Operating
Operation stopped
Operating
<2> Timing when counting is started after the CPU clock is switched to the X1 input clock (fXP)
Normal operation (Ring-OSC clock)
CPU clock
Note
fR → fXP
Normal operation
(Ring-OSC clock)
Clock supply
stopped
STOP
Normal operation (X1 input clock)
CPU operation
f
XP
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
fR
17 clocks
Watchdog timer
Operating
Operation stopped
Operating
Note Confirm the oscillation stabilization time of fXP using the oscillation stabilization time counter status register
(OSTC).
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(4) When CPU clock and watchdog timer operation clock are the Ring-OSC clocks (fR) during STOP
instruction execution
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is started again using the operation clock before the operation was stopped. At this time, the
counter is not cleared to 0.
Figure 10-7. Operation in STOP Mode (CPU Clock and WDT Operation Clock: Ring-OSC Clock)
Normal operation
(Ring-OSC clock)
STOP
Clock supply stopped
Normal operation (Ring-OSC clock)
CPU operation
fXP
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
fR
17 clocks
Operating
Watchdog timer
Operating
Operation stopped
10.4.4 Watchdog timer operation in HALT mode (when “Ring-OSC can be stopped by software” is selected by
mask option)
The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the
X1 input clock (fXP), Ring-OSC clock (fR), or subsystem clock (fXT), or whether the operation clock of the watchdog
timer is the X1 input clock (fXP) or Ring-OSC clock (fR). After HALT mode is released, counting is started again using
the operation clock before the operation was stopped. At this time, the counter is not cleared to 0.
Figure 10-8. Operation in HALT Mode
Normal operation
HALT
Normal operation
CPU operation
f
XP
f
R
f
XT
Watchdog timer
Operating Operation stopped
Operating
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CHAPTER 11 A/D CONVERTER
11.1 Functions of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to
ANI7) with a resolution of 10 bits.
The A/D converter has the following two functions.
(1) 10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to
ANI7. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
(2) Power-fail detection function
This function is used to detect a voltage drop in a battery. The A/D conversion result (ADCR register value) and
power-fail comparison threshold register (PFT) value are compared. INTAD is generated only when a
comparative condition has been matched.
Figure 11-1. Block Diagram of A/D Converter
Series resistor string
ANI0/P20
ANI1/P21
Sample & hold circuit
Voltage comparator
ANI2/P22
AVREF
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
(Can be used as
analog power supply)
Successive
approximation
register (SAR)
AVSS
Controller
INTAD
A/D conversion result
register (ADCR)
3
ADS2 ADS1 ADS0
ADCS FR2
Internal bus
FR1
ADCE
FR0
Analog input channel
specification register
(ADS)
A/D converter mode
register (ADM)
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Figure 11-2. Block Diagram of Power-Fail Detection Function
PFCM PFEN
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ANI4/P24
ANI5/P25
ANI6/P26
ANI7/P27
INTAD
A/D converter
Comparator
Power-fail comparison
threshold register (PFT)
ADS2 ADS1 ADS0
PFEN PFCM
Analog input channel
specification register
(ADS)
Power-fail comparison
mode register (PFM)
Internal bus
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11.2 Configuration of A/D Converter
The A/D converter consists of the following hardware.
Table 11-1. Configuration of A/D Converter
Item
Analog input
Registers
Configuration
8 channels (ANI0 to ANI7)
Successive approximation register (SAR)
A/D conversion result register (ADCR)
Control registers
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
Power-fail comparison mode register (PFM)
Power-fail comparison threshold register (PFT)
(1) Successive approximation register (SAR)
This register compares the analog input voltage value with the voltage tap (compare voltage) value applied from
the series resistor string, and holds the result starting from the most significant bit (MSB).
When the result up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are
transferred to the A/D conversion result register.
(2) A/D conversion result register (ADCR)
The ADCR is 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in
ADCR in order starting from the most significant bit (MSB).
ADCR can be read by a 16-bit memory manipulation instruction.
RESET input makes ADCR undefined.
Figure 11-3. Format of A/D Conversion Register (ADCR)
Address: FF08H, FF09H After reset: Undefined
FF09H
R
FF08H
Symbol
ADCR
0
0
0
0
0
0
Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read the
conversion result following conversion completion before writing to ADM and ADS. Using
timing other than the above may cause an incorrect conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
(3) Sample & hold circuit
The sample & hold circuit samples each analog input signal sequentially applied from the input circuit, and sends
it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion.
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(4) Voltage comparator
The voltage comparator compares the analog input with the series resistor string output voltage.
(5) Series resistor string
The series resistor string is connected between AVREF and AVSS, and generates a voltage to be compared with
the analog input.
(6) ANI0 to ANI7 pins
These eight-channel analog input pins input analog signals to undergo A/D conversion to the A/D converter.
ANI0 to ANI7 are alternate-function pins that can also be used for digital input.
Cautions 1. Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher or
a voltage of AVSS or lower (even if within the range of absolute maximum ratings) is input to
an analog input channel, the converted value of that channel becomes undefined. In
addition, the converted values of the other channels may also be affected.
2. The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27). When
A/D conversion is performed with any of ANI0 to ANI7 selected, do not execute the input
instruction to port 2 while conversion is in progress; otherwise the conversion resolution
may be degraded. If a digital pulse is applied to the pins adjacent to the pins currently used
for A/D conversion, the expected value of the A/D conversion may not be obtained due to
coupling noise. Therefore, do not apply a pulse to the pins adjacent to the pin undergoing
A/D conversion.
(7) AVREF pin
The AVREF pin inputs the A/D converter reference voltage.
It converts signals input to ANI0 to ANI7 into digital signals based on a voltage between AVREF and AVSS.
In a standby mode, the current flowing into series resistor strings can be reduced by changing the input voltage of
the AVREF pin to AVSS level.
It can also be used as the analog power supply. When the A/D converter is used, be sure to use the AVREF pin
for the power supply.
Caution A series resistor string of several tens of kΩ is connected between the AVREF and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will result in
series connection to the series resistor string between the AVREF and AVSS pins, resulting in a
large reference voltage error.
(8) AVSS pin
The AVSS pin is the GND potential pin for the A/D converter. Always use the AVSS pin at the same potential as
the EVSS or VSS pin, even when the A/D converter is not used.
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11.3 Registers Controlling A/D Converter
The following four registers are used to control the A/D converter.
•
•
•
•
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
Power-fail comparison mode register (PFM)
Power-fail comparison threshold register (PFT)
(1) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 11-4. Format of A/D Converter Mode Register (ADM)
Address: FF28H After reset: 00H R/W
Symbol
7
6
0
5
4
3
2
0
1
0
0
ADM ADCS
FR2
FR1
FR0
ADCE
ADCS
A/D conversion operation control
0
1
Stops conversion operation
Enables conversion operation
Conversion time selectionNote 1
= 10 MHz
FR2
FR1
FR0
f
fX = 8.38 MHz
X
f
X
= 2 MHz
144
sNote 1
120 sNote 1
288/f
240/f
192/f
144/f
120/f
X
X
X
X
X
µ
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
34.3
28.6
22.9
17.2
14.3
µ
µ
µ
µ
µ
s
s
s
s
s
28.8
24.0
19.2
14.4
12.0
µ
µ
µ
µ
µ
s
µ
s
96
72
60
48
s
s
s
s
µ
µ
µ
µ
s
s
sNote 1
11.5 sNote 1
9.6
µ
sNote 1
96/f
X
µ
Other than above
Setting prohibited
ADCE
Boost reference voltage generator operation controlNote 2
Stops operation of reference voltage generator
0
1
Enables operation of reference voltage generator
Notes 1. Set so that the A/D conversion time is 14 µs or longer but less than 100 µs.
2. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that
generates the reference voltage for boosting is controlled by ADCE, and it takes 14 µs from operation
start to operation stabilization. Therefore, when ADCS is set to 1 after 14 µs or more has elapsed
from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion
result.
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Table 11-2. Settings of ADCS and ADCE
ADCS
ADCE
A/D Conversion Operation
0
0
1
1
0
1
0
1
Stop status (DC power consumption path does not exist)
Conversion waiting mode (only reference voltage generator consumes power)
Conversion mode (reference voltage generator operation stoppedNote
Conversion mode (reference voltage generator operates)
)
Note Data of first conversion cannot be used.
Figure 11-5. Timing Chart When Boost Reference Voltage Generator Is Used
Boost reference voltage generator: operating
ADCE
Boost reference voltage
Conversion
operation
Conversion
waiting
Conversion
operation
Conversion stopped
ADCS
Note
Note 14 µs or more is required for reference voltage stabilization.
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the
identical data.
2. For the sampling time of the A/D converter and the A/D conversion start delay time, refer to
(11) in 11.6 Cautions for A/D Converter.
3. If data is written to ADM, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
Remark fX: X1 input clock oscillation frequency
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(2) Analog input channel specification register (ADS)
This register specifies the input port of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation.
RESET input clears this register to 00H.
Figure 11-6. Format of Analog Input Channel Specification Register (ADS)
Address: FF29H After reset: 00H R/W
Symbol
ADS
7
0
6
0
5
0
4
0
3
0
2
1
0
ADS2
ADS1
ADS0
ADS2
ADS1
ADS0
Analog input channel specification
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Cautions 1. Be sure to set bits 3 to 7 of ADS to 0.
2. If data is written to ADS, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
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(3) Power-fail comparison mode register (PFM)
The power-fail comparison mode register (PFM) is a register that controls the comparison operation.
PFM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 11-7. Format of Power-Fail Comparison Mode Register (PFM)
Address: FF2AH After reset: 00H R/W
Symbol
7
6
5
0
4
0
3
0
2
0
1
0
0
0
PFM PFEN
PFCM
PFEN
Power-fail comparison enable
0
1
Stops power-fail comparison (used as a normal A/D converter)
Enables power-fail comparison (used for power-fail detection)
PFCM
Power-fail comparison mode selection
Interrupt request signal (INTAD) generation
No INTAD generation
0
1
ADCR3 ≥ PFT3
ADCR3 < PFT3
ADCR3 ≥ PFT3
ADCR3 < PFT3
No INTAD generation
INTAD generation
Caution If data is written to PFM, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
(4) Power-fail comparison threshold register (PFT)
The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the
values with the A/D conversion result.
8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result.
PFT can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 11-8. Format of Power-Fail Comparison Threshold Register (PFT)
Address: FF2BH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
PFT PFT7
PFT6
PFT5
PFT4
PFT3
PFT2
PFT1
PFT0
Caution If data is written to PFT, a wait cycle is generated. For details, refer to CHAPTER 27 CAUTIONS
FOR WAIT.
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11.4 A/D Converter Operations
11.4.1 Basic operations of A/D converter
<1> Select one channel for A/D conversion with analog input channel specification register (ADS).
<2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<3> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
input analog voltage is held until the A/D conversion operation is ended.
<4> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
(1/2) AVREF by the tap selector.
<5> The voltage difference between the series resistor string voltage tap and analog input is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB of SAR remains set to 1. If the
analog input is smaller than (1/2) AVREF0, the MSB is reset to 0.
<6> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
•
•
Bit 9 = 1: (3/4) VDD
Bit 9 = 0: (1/4) VDD
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
•
•
Analog input voltage ≥ Voltage tap: Bit 8 = 1
Analog input voltage < Voltage tap: Bit 8 = 0
<7> Comparison is continued in this way up to bit 0 of SAR.
<8> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
value is transferred to the A/D conversion result register (ADCR) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
Caution The first A/D conversion value immediately after A/D conversion operations start may not fall
within the rating.
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Figure 11-9. Basic Operation of A/D Converter
Conversion time
Sampling time
Sampling
A/D converter
operation
A/D conversion
Conversion
result
Undefined
SAR
Conversion
result
ADCR
INTAD
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)
is reset (0) by software.
If a write operation is performed to one of the ADM, analog input channel specification register (ADS), power-fail
comparison mode register (PFM), or power-fail comparison threshold register (PFT) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the
beginning.
RESET input makes the A/D conversion result register (ADCR) undefined.
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11.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D
conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression.
VIN
ADCR = INT (
× 1024 + 0.5)
AVREF
or
AVREF
AVREF
1024
(ADCR − 0.5) ×
− VIN < (ADCR + 0.5) ×
1024
where, INT( ): Function which returns integer part of value in parentheses
VIN: Analog input voltage
AVREF: AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
Figure 11-10 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 11-10. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021
A/D conversion result
(ADCR)
3
2
1
0
1
1
3
2
5
3
2043 1022 2045 1023 2047
2048 1024 2048 1024 2048
1
2048 1024 2048 1024 2048 1024
Input voltage/AVREF
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11.4.3 A/D converter operation mode
The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to
ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed.
In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison
mode register (PFM).
•
•
Normal 10-bit A/D converter (PFEN = 0)
Power-fail detection function (PFEN = 1)
(1) A/D conversion operation (when PFEN = 0)
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail
comparison mode register (PFM) to 0, the A/D conversion operation of the voltage, which is applied to the analog
input pin specified by the analog input channel specification register (ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and
when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The
A/D conversion operations are repeated until new data is written to ADS.
If ADS is rewritten during A/D conversion, the A/D conversion under execution is suspended, and the A/D
conversion of the newly selected analog input channel is started.
If 0 is written to ADCS of ADM during A/D conversion, the conversion operation is immediately stopped.
Figure 11-11. A/D Conversion Operation
Rewriting ADM
ADCS = 1
Rewriting ADS
ANIn
ADCS = 0
A/D conversion
ANIn
ANIn
ANIm
ANIm
Conversion is stopped
Conversion result is not retained
Stopped
ANIn
ANIn
ANIm
ADCR
INTAD
(PFEN = 0)
Remarks 1. n = 0 to 7
2. m = 0 to 7
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(2) Power-fail detection function (when PFEN = 1)
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail
comparison mode register (PFM) to 1, the A/D conversion operation of the voltage applied to the analog input pin
specified by the analog input channel specification register (ADS) is started.
When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion
result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an
interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM.
<1> When PFEN = 0
INTAD is generated at the end of each A/D conversion.
<2> When PFEN = 1 and PFCM = 0
The ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when
ADCR ≥ PFT.
<3> When PFEN = 1 and PFCM = 1
The ADCR and PFT values are compared when A/D conversion ends and INTAD is only generated when
ADCR < PFT.
Figure 11-12. Power-Fail Detection (When PFEN = 1 and PFCM = 0)
A/D conversion
ANIn
ANIn
80H
ANIn
7FH
ANIn
80H
ADCR
PFT
80H
INTAD
(PFEN = 1)
Note
First conversion
Condition match
Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is
replaced by the next conversion result.
Remark n = 0 to 7
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The setting methods are described below.
When used as A/D conversion operation
•
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<2> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
<3> Set bit 7 (ADCS) of ADM to 1.
<4> An interrupt request signal (INTAD) is generated.
<5> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<Change the channel>
<6> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS.
<7> An interrupt request signal (INTAD) is generated.
<8> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<Complete A/D conversion>
<9> Clear ADCS to 0.
<10> Clear ADCE to 0.
Cautions 1. Make sure the period of <1> to <3> is 14 µs or more.
2. It is no problem if the order of <1> and <2> is reversed.
3. <1> can be omitted. However, do not use the first conversion result after <3> in this
case.
4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0.
•
When used as power-fail function
<1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM).
<2> Set power-fail comparison condition using bit 6 (PFCM) of PFM.
<3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<4> Select the channel and conversion time using bits 2 to 0 (ADS2 to ADS0) of the analog input channel
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
<5> Set a threshold value to the power-fail comparison threshold register (PFT).
<6> Set bit 7 (ADCS) of ADM to 1.
<7> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<8> ADCR and PFT are compared and an interrupt request signal (INTAD) is generated if the conditions
match.
<Change the channel>
<9> Change the channel using bits 2 to 0 (ADS2 to ADS0) of ADS.
<10> Transfer the A/D conversion data to the A/D conversion result register (ADCR).
<11> ADCR and the power-fail comparison threshold register (PFT) are compared and an interrupt request
signal (INTAD) is generated if the conditions match.
<Complete A/D conversion>
<12> Clear ADCS to 0.
<13> Clear ADCE to 0.
Cautions 1. Make sure the period of <3> to <6> is 14 µs or more.
2. It is no problem if order of <3>, <4>, and <5> is changed.
3. <3> can be omitted. However, do not use the first conversion result after <6> in this
case.
4. The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.
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11.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the
full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of
these express the overall error.
Note that the quantization error is not included in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an
analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot
be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral
linearity error, and differential linearity error in the characteristics table.
Figure 11-13. Overall Error
Figure 11-14. Quantization Error
……
1
1
……
1
1
Ideal line
Overall
error
Quantization error
1/2LSB
1/2LSB
……
0
0
……
0
0
0
AVREF
0
AVREF
Analog input
Analog input
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(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output
changes from 0……000 to 0……010.
(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It
expresses the maximum value of the difference between the actual measurement value and the ideal straight line
when the zero-scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value
and the ideal value.
Figure 11-15. Zero-Scale Error
Figure 11-16. Full-Scale Error
111
Full-scale error
Ideal line
011
111
110
010
001
101
000
Ideal line
Zero-scale error
000
0
AVREF–3 AVREF–2 AVREF–1 AVREF
0
1
2
3
AVREF
Analog input (LSB)
Analog input (LSB)
Figure 11-17. Integral Linearity Error
Figure 11-18. Differential Linearity Error
……
1
1
……
1
1
Ideal 1LSB width
Ideal line
Differential
linearity error
Integral linearity
error
……
0
……
0
0
0
AVREF
AVREF
0
0
Analog input
Analog input
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(8) Conversion time
This expresses the time since sampling has been started until digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time
Conversion time
11.6 Cautions for A/D Converter
(1) Power consumption in standby mode
The A/D converter stops operating in the standby mode. At this time, the power consumption can be reduced by
stopping the conversion operation (by setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 0).
Figure 11-19 shows the circuit configuration of series resistor string.
Figure 11-19. Circuit Configuration of Series Resistor String
AVREF
ADCS
P-ch
Series resistor string
AVSS
(2) Input range of ANI0 to ANI7
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AVREF or higher and AVSS or lower
(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that
channel becomes undefined. In addition, the converted values of the other channels may also be affected.
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(3) Conflicting operations
<1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end
of conversion
ADCR read has priority. After the read operation, the new conversion result is written to ADCR.
Old data can be read from ADCR at the timing of (1) and new data can be read from ADCR at the timing of
(2) as shown in Figure 11-20. A master-slave configuration is employed for transferring the A/D conversion
result to ADCR.
Figure 11-20. Storing Conversion Result in ADCR and Timing of Data Read from ADCR
(1) Timing to read old data
Internal clock
Conversion
end
INTAD
Master write signal
Conversion
result N
A/D conversion (master)
Conversion result N + 1
Slave write signal
ADCR (slave)
Read data
Conversion result N
Conversion result N
(2) Timing to read new data
Internal clock
Conversion
end
INTAD
Master write signal
Conversion
result N
Conversion result N + 1
A/D conversion (master)
Slave write signal
ADCR (slave)
Read data
Conversion result N + 1
Conversion result N + 1
<2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel
specification register (ADS) write
ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal
(INTAD) generated.
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(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI7.
Because the effect increases in proportion to the output impedance of the analog input source, it is recommended
that a capacitor be connected externally, as shown in Figure 11-21, to reduce noise.
Figure 11-21. Analog Input Pin Connection
If there is a possibility that noise equal to or higher than AVREF or
equal to or lower than AVSS may enter, clamp with a diode with a
small V value (0.3 V or lower).
F
Reference
voltage
input
AVREF
ANI0 to ANI7
C = 100 to 1,000 pF
AVSS
V
SS
(5) ANI0/P20 to ANI7/P27
The analog input pins (ANI0 to ANI7) are also used as input port pins (P20 to P27).
When A/D conversion is performed with any of ANI0 to ANI7 selected, do not execute the input instruction to port
2 while conversion is in progress; otherwise the conversion resolution may be degraded.
If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected value
of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to the pins
adjacent to the pin undergoing A/D conversion.
(6) Input impedance of ANI0 to ANI7 pins
In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one tenth
of the conversion time.
Since only the leakage current flows other than during sampling and the current for charging the capacitor also
flows during sampling, the input impedance fluctuates and has no meaning.
To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input
source 10 kΩ or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI7 pins (see Figure 11-21).
(7) AVREF pin input impedance
A series resistor string of several tens of 10 kΩ is connected between the AVREF and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to
the series resistor string between the AVREF and AVSS pins, resulting in a large reference voltage error.
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(8) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 11-22. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
ADS rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
A/D conversion
ANIn
ANIn
ANIm
ANIn
ANIm
ADCR
INTAD
ANIn
ANIm
ANIm
Remarks 1. n = 0 to 7
2. m = 0 to 7
(9) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating. Take
measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion
result.
(10) A/D conversion result register (ADCR) read operation
When a write operation is performed to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following
conversion completion before writing to ADM and ADS. Using timing other than the above may cause an
incorrect conversion result to be read.
Do not read ADCR when the CPU is operating on the subsystem clock and oscillation of the X1 input clock is
stopped.
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(11) A/D converter sampling time and A/D conversion start delay time
The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM).
The delay time exists until actual sampling is started after A/D converter operation is enabled.
When using a set in which the A/D conversion time must be strictly observed, care is required for the contents
shown in Figure 11-23 and Table 11-3.
Figure 11-23. Timing of A/D Converter Sampling and A/D Conversion Start Delay
ADCS ← 1 or ADS rewrite
ADCS
Sampling timing
INTAD
Wait
A/D
Sampling
time
period conversion
start delay
time
Conversion time
Table 11-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)
FR2
FR1
FR0
Conversion Time
Sampling Time
A/D Conversion Start Delay TimeNote
MIN.
MAX.
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
288/fX
240/fX
192/fX
144/fX
120/fX
96/fX
40/fX
32/fX
28/fX
24/fX
16/fX
14/fX
12/fX
36/fX
32/fX
28/fX
18/fX
16/fX
14/fX
32/fX
24/fX
20/fX
16/fX
12/fX
Other than above
Setting prohibited
−
−
−
Note The A/D conversion start delay time is the time after wait period. For the wait function, refer to CHAPTER 27
CAUTIONS FOR WAIT.
Remark fX: X1 clock oscillation frequency
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CHAPTER 12 SERIAL INTERFACE UART0
12.1 Functions of Serial Interface UART0
Serial interface UART0 has the following two modes.
(1) Operation stop mode
This mode is used when serial transfer is not executed and can enable a reduction in the power consumption.
For details, refer to 12.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
The functions of this mode are outlined below.
•
Two-pin configuration TXD0: Transmit data output pin
RXB0: Receive data input pin
•
•
•
•
•
Length of transfer data can be selected from 7 or 8 bits.
Dedicated on-chip 5-bit baud rate generator allowing any baud rate to be set
Transmission and reception can be performed independently.
Four operating clock inputs selectable
Fixed to LSB-first transfer
Cautions 1. The default value of the TXD0 pin is high level. Exercise care when using the TXD0 pin as a
port pin.
2. If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART0 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD0 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
3. Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to start
communication.
4. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the
transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0
is set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2
clocks after RXE0 = 0 is set.
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12.2 Configuration of Serial Interface UART0
Serial interface UART0 consists of the following hardware.
Table 12-1. Configuration of Serial Interface UART0
Configuration
Item
Registers
Receive buffer register 0 (RXB0)
Receive shift register 0 (RXS0)
Transmit shift register 0 (TXS0)
Control registers
Asynchronous serial interface operation mode register 0 (ASIM0)
Asynchronous serial interface reception error status register 0 (ASIS0)
Baud rate generator control register 0 (BRGC0)
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Figure 12-1. Block Diagram of Serial Interface UART0
Filter
RxD0/SI10/P11
Receive shift register 0
(RXS0)
Asynchronous serial
interface operation mode
register 0 (ASIM0)
Asynchronous serial
interface reception error
status register 0 (ASIS0)
Reception control
INTSR0
Receive buffer register 0
(RXB0)
Baud rate
generator
f
X
/2
f
f
X
X
/23
/25
Reception unit
Internal bus
TO50/TI50/P17
(TM50 output)
Baud rate generator
control register 0
(BRGC0)
Baud rate
generator
Transmit shift register 0
(TXS0)
INTST0
Transmission control
TxD0/SCK10/P10
Registers
Transmission unit
CHAPTER 12 SERIAL INTERFACE UART0
(1) Receive buffer register 0 (RXB0)
This 8-bit register stores parallel data converted by receive shift register 0 (RXS0).
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 0 (RXS0).
If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is
always 0.
If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0.
RESET input or POWER0 = 0 sets this register to FFH.
RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
(2) Receive shift register 0 (RXS0)
This register converts the serial data input to the RXD0 pin into parallel data.
RXS0 cannot be directly manipulated by a program.
(3) Transmit shift register 0 (TXS0)
This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is
transmitted from the TXD0 pins.
RESET input, POWR0 = 0, or TXE0 = 0 sets this register to FFH.
TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read.
Caution Do not write the next transmit data to TXS0 before the transmission completion interrupt signal
(INTST0) is generated.
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12.3 Registers Controlling Serial Interface UART0
Serial interface UART0 is controlled by the following three registers.
•
•
•
Asynchronous serial interface operation mode register 0 (ASIM0)
Asynchronous serial interface reception error status register 0 (ASIS0)
Baud rate generator control register 0 (BRGC0)
(1) Asynchronous serial interface operation mode register 0 (ASIM0)
This 8-bit register controls the serial transfer operations of serial interface UART0.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 01H.
Figure 12-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (1/2)
Address: FF70H After reset: 01H R/W
Symbol
ASIM0
7
6
5
4
3
2
1
0
1
POWER0
TXE0
RXE0
PS01
PS00
CL0
SL0
POWER0
0Note
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit.
1
Enables operation of the internal operation clock.
TXE0
Enables/disables transmission
Disables transmission (synchronously resets the transmission circuit).
Enables transmission.
0
1
RXE0
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
Enables reception.
0
1
Note The input from the RXD0 pin is fixed to high level when POWER0 = 0.
Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. Clear TXE0 to 0 first, and then clear
POWER0 to 0.
2. At startup, set POWER0 to 1 and then set RXE0 to 1. Clear RXE0 to 0 first, and then clear
POWER0 to 0.
3. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the
transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is
set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks
after RXE0 = 0 is set.
4. Be sure to set bit 0 to 1.
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Figure 12-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2)
PS01
PS00
Transmission operation
Does not output parity bit.
Reception operation
Reception without parity
0
0
1
1
0
1
0
1
Outputs 0 parity.
Reception as 0 parityNote
Judges as odd parity.
Judges as even parity.
Outputs odd parity.
Outputs even parity.
CL0
0
Specifies character length of transmit/receive data
Character length of data = 7 bits
Character length of data = 8 bits
1
SL0
0
Specifies number of stop bits of transmit data
Number of stop bits = 1
Number of stop bits = 2
1
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
2. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
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(2) Asynchronous serial interface reception error status register 0 (ASIS0)
This register indicates an error status on completion of reception by serial interface UART0. It includes three
error flag bits (PE0, FE0, OVE0).
This register can be set by an 8-bit memory manipulation instruction and is read-only.
RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when this
register is read.
Figure 12-3. Format of Asynchronous Serial Interface Reception Error Status Register 0 (ASIS0)
Address: FF73H After reset: 00H R
Symbol
ASIS0
7
0
6
0
5
0
4
0
3
0
2
1
0
PE0
FE0
OVE0
PE0
0
Status flag indicating parity error
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1
If the parity of transmit data does not match the parity bit on completion of reception.
FE0
0
Status flag indicating framing error
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If the stop bit is not detected on completion of reception.
1
OVE0
Status flag indicating overrun error
0
1
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
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(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and controls the baud rate.
BRGC0 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
Figure 12-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol
BRGC0
7
6
5
0
4
3
2
1
0
TPS01
TPS00
MDL04
MDL03
MDL02
MDL01
MDL00
TPS01
TPS00
Base clock (fXCLK) selection
0
0
1
1
0
1
0
1
TM50 output (TO50)
fX/2 (5 MHz)
fX/23 (1.25 MHz)
fX/25 (312.5 kHz)
MDL04
MDL03
MDL02
MDL01
MDL00
k
Selection of 5-bit counter
output clock
0
0
0
0
0
1
1
1
×
0
0
0
×
0
0
1
×
0
1
0
×
8
Setting prohibited
fXCLK/8
9
fXCLK/9
10
fXCLK/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
0
1
0
0
1
26
27
28
30
31
fXCLK/26
fXCLK/27
fXCLK/28
fXCLK/30
fXCLK/31
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
2. The baud rate is the output clock of the 5-bit counter divided by 2.
Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS01 and TPS00 bits
2. fX:
3. k:
4. ×:
X1 input clock oscillation frequency
Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31)
Don’t care
5. Figures in parentheses apply to operation at fX = 10 MHz
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12.4 Operation of Serial Interface UART0
This section explains the two modes of serial interface UART0.
12.4.1 Operation stop mode
In this mode, serial transfer cannot be executed, thus reducing the power consumption. In addition, the pins can
be used as ordinary port pins in this mode.
(1) Register setting
The operation stop mode is set by asynchronous serial interface operation mode register 0 (ASIM0).
ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 01H.
Address: FF70H After reset: 01H R/W
Symbol
ASIM0
7
6
5
4
3
2
1
0
1
POWER0
TXE0
RXE0
PS01
PS00
CL0
SL0
POWER0
0Note
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit.
1
Enables operation of the internal operation clock.
TXE0
Enables/disables transmission
Disables transmission (synchronously resets the transmission circuit).
Enables transmission.
0
1
RXE0
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
Enables reception.
0
1
Note The input from the RXD0 pin is fixed to high level when POWER0 = 0.
Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. Clear TXE0 to 0 first, and then clear
POWER0 to 0.
2. At startup, set POWER0 to 1 and then set RXE0 to 1. Clear RXE0 to 0 first, and then clear
POWER0 to 0.
3. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the
transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is
set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks
after RXE0 = 0 is set.
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12.4.2 Asynchronous serial interface (UART) mode
In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed.
A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of
baud rates.
(1) Register setting
The UART mode is set by asynchronous serial interface operation mode register 0 (ASIM0) and asynchronous
serial interface reception error status register 0 (ASIS0).
(a) Asynchronous serial interface operation mode register 0 (ASIM0)
This 8-bit register controls the serial transfer operations of serial interface UART0.
ASIM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 01H.
Address: FF70H After reset: 01H R/W
Symbol
ASIM0
7
6
5
4
3
2
1
0
1
POWER0
TXE0
RXE0
PS01
PS00
CL0
SL0
POWER0
0Note
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit.
1
Enables operation of the internal operation clock.
TXE0
Enables/disables transmission
Disables transmission (synchronously resets the transmission circuit).
Enables transmission.
0
1
RXE0
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
Enables reception
0
1
Note The input from the RXD0 pin is fixed to high level when POWER0 = 0.
Cautions 1. At startup, set POWER0 to 1 and then set TXE0 to 1. Clear TXE0 to 0 first, and then clear
POWER0 to 0.
2. At startup, set POWER0 to 1 and then set RXE0 to 1. Clear RXE0 to 0 first, and then clear
POWER0 to 0.
3. TXE0 and RXE0 are synchronized with the base clock (fXCLK) set by BRGC0. Therefore, the
transmission unit may not be initialized if TXE0 = 1 is not set again 2 clocks after TXE0 = 0 is
set. Similarly, the reception unit may not be initialized if RXE0 = 1 is not set again 2 clocks
after RXE0 = 0 is set.
4. Be sure to set bit 0 to 1.
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PS01
PS00
Transmission operation
Reception operation
Reception without parity
Reception as 0 parityNote
0
0
1
1
0
1
0
1
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
Judges as odd parity.
Judges as even parity.
CL0
0
Specifies character length of transmit/receive data
Character length of data = 7 bits
Character length of data = 8 bits
1
SL0
0
Specifies number of stop bits of transmit data
Number of stop bits = 1
Number of stop bits = 2
1
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE0) of asynchronous serial
interface reception error status register 0 (ASIS0) is not set and the error interrupt does not occur.
Cautions 1. Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
2. Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always performed with
“number of stop bits = 1”, and therefore, is not affected by the set value of the SL0 bit.
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(b) Asynchronous serial interface reception error status register 0 (ASIS0)
This register indicates an error status on completion of reception by serial interface UART0. It includes three
error flag bits (PE0, FE0, OVE0).
This register can be set by an 8-bit memory manipulation instruction and is read-only.
RESET input clears this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0. 00H is read when
this register is read.
Address: FF73H After reset: 00H R
Symbol
ASIS0
7
0
6
0
5
0
4
0
3
0
2
1
0
PE0
FE0
OVE0
PE0
0
Status flag indicating parity error
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
1
If the parity of transmit data does not match the parity bit on completion of reception.
FE0
0
Status flag indicating framing error
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If the stop bit is not detected on completion of reception.
1
OVE0
Status flag indicating overrun error
0
1
If POWER0 = 0 and RXE0 = 0, or if ASIS0 register is read.
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE0 bit differs depending on the set values of the PS01 and PS00 bits of
asynchronous serial interface operation mode register 0 (ASIM0).
2. Only the first bit of the receive data is checked as the stop bit, regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 0
(RXB0) but discarded.
4. If data is read from ASIS0, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
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(2) Communication operation
(a) Normal transmit/receive data format
Figure 12-5 shows the format of the transmit/receive data.
Figure 12-5. Format of Normal UART Transmit/Receive Data
1 data frame
Start
bit
Parity
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop bit
Character bits
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits (LSB first)
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface mode register 0 (ASIM0).
Figure 12-6. Example of Normal UART Transmit/Receive Data Format
1. Data length: 8 bits, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 7 bits, Parity: Odd parity, Stop bit: 2 bits, Transfer data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
Stop
3. Data length: 8 bits, Parity: None, Stop bit: 1 bit, Transfer data: 87H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
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(b) Parity types and operation
The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
(i) Even parity
• Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that there is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
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(c) Transmission
The TXD0 pin outputs a high level when bit 7 (POWER0) of asynchronous serial interface mode register 0
(ASIM0) is set to 1. If bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be
started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are
automatically appended to the data.
When transmission is started, the start bit is output from the TXD0 pin, followed by the rest of the data in
order starting from the LSB. When transmission is completed, the parity and stop bits set by ASIM0 are
appended and a transmission completion interrupt request (INTST0) is generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 12-7 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
transmission completion interrupt signal (INTST0) is generated.
Figure 12-7. Normal Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
Parity
STOP
T
XD0 (output)
START
D0
D1
D2
D6
D7
INTST0
2. Stop bit length: 2
T
XD0 (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTST0
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(d) Reception
Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial
interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1.
The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is
detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the
RXD0 pin input is sampled again ( in Figure 12-8). If the RXD0 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in receive shift
register 0 (RXS0) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR0) is generated and the data of RXS0 is written to receive buffer register 0 (RXB0). If an
overrun error (OVE0) occurs, however, the receive data is not written to RXB0.
Even if a parity error (PE0) or a framing error (FE0) occurs while reception is in progress, reception continues
to the reception position of the stop bit, and an error interrupt (INTSR0) is generated after completion of
reception.
Figure 12-8. Reception Completion Interrupt Request Timing
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
RX
D0 (input)
INTSR0
RXB0
Cautions 1. Be sure to read receive buffer register 0 (RXB0) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 0 (ASIS0)
before reading RXB0.
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(e) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt request (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt servicing (INTSR0) (refer to Table 12-2).
The contents of ASIS0 are reset to 0 when ASIS0 is read.
Table 12-2. Cause of Reception Error
Reception Error
Parity error
Cause
Value of ASIS0
The parity specified for transmission does not match the parity of the 04H
receive data.
Framing error
Overrun error
Stop bit is not detected.
02H
01H
Reception of the next data is completed before data is read from
receive buffer register 0 (RXB0).
(f) Noise filter of receive data
The RXD0 signal is sampled using the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 12-9, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Figure 12-9. Noise Filter Circuit
Base clock
Internal signal A
R
XD0/SI10/P11
Internal signal B
In
Q
In
Q
LD_EN
Match detector
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12.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and an 5-bit programmable counter, and
generates a serial clock for transmission/reception of UART0.
Separate 5-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
•
•
•
Base clock (Clock)
The clock selected by bits 7 and 6 (TPS01 and TPS00) of baud rate generator control register 0 (BRGC0) is
supplied to each module when bit 7 (POWER0) of asynchronous serial interface operation mode register 0
(ASIM0) is 1. This clock is called the base clock “Clock” and its frequency is called fXCLK. “Clock” is fixed to
low level when POWER0 = 0.
Transmission counter
This counter stops, cleared to 0, when bit 7 (POWER0) or bit 6 (TXE0) of asynchronous serial interface
operation mode register 0 (ASIM0) is 0.
It starts counting when POWER0 = 1 and TXE0 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit shift register 0 (TXS0).
Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER0) or bit 5 (RXE0) of asynchronous serial
interface operation mode register 0 (ASIM0) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
Figure 12-10. Configuration of Baud Rate Generator
POWER0
f
X/2
POWER0, TXE0 (or RXE0)
5-bit counter
f
X
/23
Clock
(fXCLK
Selector
)
fX
/25
TO50/TI50/P17
(TM50 output)
Match detector
Baud rate
1/2
BRGC0: TPS01, TPS00
BRGC0: MDL04 to MDL00
Remark POWER0: Bit 7 of asynchronous serial interface operation mode register 0 (ASIM0)
TXE0:
Bit 6 of ASIM0
RXE0:
BRGC0:
Bit 5 of ASIM0
Baud rate generator control register 0
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(2) Generation of serial clock
A serial clock can be generated by using baud rate generator control register 0 (BRGC0).
Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0.
Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value of the 5-bit counter.
(a) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and controls the baud rate.
BRGC0 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to 1FH.
Address: FF71H After reset: 1FH R/W
Symbol
BRGC0
7
6
5
0
4
3
2
1
0
TPS01
TPS00
MDL04
MDL03
MDL02
MDL01
MDL00
TPS01
TPS00
Base clock (fXCLK) selection
0
0
1
1
0
1
0
1
TM50 output (TO50)
fX/2 (5 MHz)
fX/23 (1.25 MHz)
fX/25 (312.5 kHz)
MDL04
MDL03
MDL02
MDL01
MDL00
k
Selection of 5-bit counter
output clock
0
0
0
0
0
1
1
1
×
0
0
0
×
0
0
1
×
0
1
0
×
8
Setting prohibited
fXCLK/8
9
fXCLK/9
10
fXCLK/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
0
1
0
0
1
26
27
28
30
31
fXCLK/26
fXCLK/27
fXCLK/28
fXCLK/30
fXCLK/31
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
2. The baud rate value is the output clock of the 5-bit counter divided by 2.
Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS01 and TPS00 bits
2. fX:
3. k:
4. ×:
X1 input clock oscillation frequency
Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31)
Don’t care
5. Figures in parentheses apply to operation with fX = 10 MHz
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(b) Baud rate
The baud rate can be calculated by the following expression.
fXCLK
• Baud rate =
[bps]
2 × k
fXCLK: Frequency of base clock (Clock) selected by the TPS01 and TPS00 bits of the BRGC0 register
k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
(c) Error of baud rate
The baud rate error can be calculated by the following expression.
Actual baud rate (baud rate with error)
• Error (%) =
− 1 × 100 [%]
Desired baud rate (correct baud rate)
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at
the reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock (Clock) = 2.5 MHz = 2,500,000 Hz
Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16)
Target baud rate = 76,800 bps
Baud rate = 2.5 M/(2 × 16)
= 2,500,000/(2 × 16) = 78,125 [bps]
Error = (78,125/76,800 − 1) × 100
= 1.725 [%]
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(3) Example of setting baud rate
Table 12-3. Set Data of Baud Rate Generator
Baud Rate
[bps]
fX = 10.0 MHz
fX = 8.38 MHz
fX = 4.19 MHz
TPS01,
TPS00
k
Calculated ERR[%] TPS01,
k
Calculated ERR[%] TPS01,
k
Calculated ERR[%]
value
TPS00
Value
TPS00
Value
2425
4676
9699
10475
18705
−
2400
4800
−
−
3
3
3
2
2
2
1
1
1
−
−
−
−
3
3
3
2
2
2
1
1
1
1
−
−
−
3
3
2
2
2
−
2
1
1
−
−
27
14
27
25
14
−
1.03
−2.58
1.03
0.72
−2.58
−
−
−
−
27
14
13
27
17
14
27
18
14
9
4850
1.03
9600
16
15
8
9766
1.73
0.16
1.73
0
9353
−2.58
−3.15
1.03
10400
19200
31250
38400
76800
115200
153600
230400
10417
19531
31250
39063
78125
113636
156250
227273
10072
19398
30809
38796
77593
116389
149643
232778
20
16
8
−1.41
−2.58
1.03
1.73
1.73
−1.36
1.73
−1.36
27
14
9
38796
74821
116389
−
1.03
−2.58
1.03
−
22
16
11
1.03
−2.58
1.03
−
−
−
−
Remark TPS01, TPS00:
Bits 7 and 6 of baud rate generator control register 0 (BRGC0) (setting of base clock
(fXCLK))
k:
Value set by the MDL04 to MDL00 bits of BRGC0 (k = 8, 9, 10, ..., 31)
X1 input clock oscillation frequency
fX:
ERR:
Baud rate error
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(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 12-11. Permissible Baud Rate Range During Reception
Latch timing
Transfer rate
Start bit
Start bit
Start bit
Bit 0
FL
Bit 1
Bit 7
Parity bit
Stop bit
of UART0
1 data frame (11 × FL)
Minimum permissible
transfer rate
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible
transfer rate
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 12-11, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 0 (BRGC0) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 14-bit data is received, the theoretical values can be calculated as follows.
1
FL = (Brate)−
Brate: Baud rate of UART0
k:
Set value of BRGC0
1-bit data length
FL:
Margin of latch timing: 2 clocks
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21k + 2
k − 2
Minimum permissible transfer rate: FLmin = 11 × FL −
× FL =
FL
2k
2k
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
22k
1
BRmax = (FLmin/11)−
=
Brate
21k + 2
Similarly, the maximum permissible transfer rate can be calculated as follows.
10
11
k + 2
21k − 2
2 × k
× FLmax = 11 × FL −
× FL =
FL
2 × k
21k × 2
FLmax =
FL × 11
20k
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
20k
1
BRmin = (FLmax/11)−
=
Brate
21k − 2
The permissible baud rate error between UART0 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 12-4. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k)
Maximum Permissible Baud Rate Error
Minimum Permissible Baud Rate Error
8
+3.53%
+4.14%
+4.34%
+4.44%
−3.61%
−4.19%
−4.38%
−4.47%
16
24
31
Remarks 1. The accuracy of reception depends on the number of bits in one frame, input clock frequency,
and division ratio (k). The higher the input clock frequency and the higher the division ratio (k),
the higher the accuracy.
2. k: Set value of BRGC0
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CHAPTER 13 SERIAL INTERFACE UART6
13.1 Functions of Serial Interface UART6
Serial interface UART6 has the following two modes.
(1) Operation stop mode
This mode is used when serial transfer is not executed and can enable a reduction in the power consumption.
For details, refer to 13.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
This mode supports the LIN (Local Interconnect Network) bus. The functions of this mode are outlined below.
•
Two-pin configuration TXD6: Transmit data output pin
RXB6: Receive data input pin
•
•
•
•
•
•
•
•
Data length of transfer data can be selected from 7 or 8 bits.
Dedicated internal 8-bit baud rate generator allowing any baud rate to be set
Transmission and reception can be performed independently.
Twelve operating clock inputs selectable
MSB- or LSB-first transfer selectable
Inverted transmission operation
Tuning break field transmission from 13 to 20 bits
More than 11 bits can be identified for tuning break field reception (SBF reception flag provided).
Cautions 1. The default value of the TXD6 pin is the high level. Exercise care when using the TXD6 pin
as a port pin.
2. The TXD6 output inversion function inverts only the transmission side and not the reception
side. To use this function, the reception side must be ready for reception of inverted data (it
must be able to recognize a low-level start bit).
3. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD6 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
4. If data is continuously transmitted, the transfer rate from the stop bit to the next start bit is
extended two clocks. However, this does not affect the result of transfer because the
reception side initializes the timing when it has detected a start bit. Do not use the
continuous transmission function if the interface is incorporated in LIN.
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Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication
protocol intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one
master.
The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the
LIN master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave
is 15% or less.
Figures 13-1 and 13-2 outline the transmission and reception operations of LIN.
Figure 13-1. LIN Transmission Operation
Tuning
break field
Checksum
field
Wakeup
signal frame
Tuning field
Match field Data field Data field
Sleep
bus
13-bitNote 2 SBF
55H
transmission
Data
Data
Data
Data
8 bitsNote 3 Note 1 transmission
transmission transmission transmission transmission
TX6
Note 4
INTST6
Notes 1. The interval between each field is controlled by software.
2. The tuning break field is output by hardware. The output width is equal to the bit length set by bits 4 to
2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6). If the output width
needs to be adjusted more accurately, use baud rate generator control register 6 (BRGC6).
3. The wakeup signal frame is substituted by 80H transfer in the 8-bit mode.
4. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.
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Figure 13-2. LIN Reception Operation
Checksum
field
Wakeup
signal frame
Tuning
break field
Data filed
Tuning field
Match field Data filed
Sleep
bus
Data
reception
Data
Data
SF
reception
receptionNote 5
13 bitsNote 2
ID reception
reception
SBF
reception
RX6
Disable
Enable
Note 3
Reception interrupt
(INTSR6)
Note 1
Edge detection
(INTP0)
Note 4
Enable
Capture timer
Disable
Notes 1. The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception
mode.
2. Reception continues until the STOP bit is detected. When 11 bits or more of SBF have been detected,
it is assumed that SBF reception has been completed correctly, and an interrupt signal is output. If
less than 11 bits of SBF have been detected, it is assumed that an SBF reception error has occurred.
The interrupt signal is not output and the SBF reception mode is restored.
3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception
completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is
suppressed, and error detection processing of UART communication and data transfer of the shift
register and RXB6 is not performed. The shift register holds the reset value FFH.
4. Calculate the baud rate error from the value obtained from the capture timer, disable UART6 after SF
reception, and then re-set baud rate generator control register 6 (BRGC6).
5. Distinguish the checksum field by software. Also perform processing by software to initialize UART6
after reception of the checksum field and to set the SBF reception mode again.
To perform a LIN receive operation, use a configuration like the one shown in Figure 13-3.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
(INTP0). The length of the tuning break field transmitted from the LIN master can be measured using the external
event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated using the time and
number of bits of the tuning break field.
The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit
timer/event counter 00 by port input switching control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000
externally.
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Figure 13-3. Port Configuration for LIN Reception Operation
MPX
A
P14/R D6
X
Q
RXD6 input
B
Port mode
(PM14)
Port latch
(P14)
MPX
P120/INTP0
MPX
A
Q
A
B
Q
INTP0 input
B
Port mode
(PM120)
Port input
switch control
(ISC0)
Port latch
(P120)
<ISC0>
0: A output
1: B output
MPX
P00/TI000
MPX
A
Q
A
Q
B
B
TI000 input
Port mode
(PM00)
Port input
switch control
(ISC1)
Port latch
(P00)
<ISC1>
0: A output
1: B output
Remark ISC0, ISC1: Bits 0 and 1 of the input switching control register (ISC) (see Figure 4-19.)
The resources used in the LIN communication operation are shown below.
<Resources used>
•
External interrupt (INTP0); wakeup signal detection
Use: Detects the wakeup signal edges and detects start of communication.
16-bit timer/event counter 00 (TI000); baud rate error detection
Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the
tuning break field (SBF) length and divides it by the number of bits.
Serial interface UART6
•
•
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13.2 Configuration of Serial Interface UART6
Serial interface UART6 consists of the following hardware.
Table 13-1. Configuration of Serial Interface UART6
Configuration
Item
Registers
Receive buffer register 6 (RXB6)
Receive shift register 6 (RXS6)
Transmit buffer register 6 (TXB6)
Transmit shift register 6 (TXS6)
Control registers
Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
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Figure 13-4. Block Diagram of Serial Interface UART6
Filter
RXD6/P14
INTSR6
Reception control
INTSRE6
Receive shift register 6
(RXS6)
Asynchronous serial
interface reception error
status register 6 (ASIS6)
Asynchronous serial
interface operation mode
register 6 (ASIM6)
Asynchronous serial interface
control register 6 (ASICL6)
Baud rate
generator
Receive buffer register 6
(RXB6)
fX-fX
/210
Reception unit
Internal bus
TO50/TI50/P17
(TM50 output)
Baud rate generator
control register 6
(BRGC6)
Asynchronous serial
interface transmission
status register 6 (ASIF6)
Asynchronous serial interface
control register 6 (ASICL6)
Clock selection
register 6 (CKSR6)
Baud rate
generator
Transmit buffer register 6
(TXB6)
Transmit shift register 6
(TXS6)
Transmission control
INTST6
TXD6/P13
Registers
Transmission unit
CHAPTER 13 SERIAL INTERFACE UART6
(1) Receive buffer register 6 (RXB6)
This 8-bit register stores parallel data converted by the receive shift register.
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows.
•
•
In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0.
If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.
RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
RESET input sets this register to FFH.
(2) Receive shift register 6 (RXS6)
This register converts the serial data input to the RXD6 pin into parallel data.
RXS6 cannot be directly manipulated by a program.
(3) Transmit buffer register 6 (TXB6)
This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.
This register can be read or written by an 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission
status register 6 (ASIF6) is 1.
2. Do not refresh (write the same value to) TXB6 by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation
mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).
However, if the same value is continuously transmitted in the transmission mode (POWER6
= 1 and TXE6 = 1), the same value can be written.
(4) Transmit shift register 6 (TXS6)
This register transmits the data transferred from TXB6 from the TXD6 pin as serial data. Data is transferred from
TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one
frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the TXD6
pin at the falling edge of the internal clock.
TXS6 cannot be directly manipulated by a program.
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13.3 Registers Controlling Serial Interface UART6
Serial interface UART6 is controlled by the following six registers.
•
•
•
•
•
•
Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
This 8-bit register controls the serial transfer operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 13-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF50H After reset: 01H R/W
Symbol
ASIM6
7
6
5
4
3
2
1
0
POWER6
TXE6
RXE6
PS61
PS60
CL6
SL6
ISRM6
POWER6
0Note 1
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit.
1Note 2
Enables operation of the internal operation clock
TXE6
Enables/disables transmission
Disables transmission (synchronously resets the transmission circuit).
Enables transmission
0
1
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when
POWER6 = 0.
2. Operation of the internal operation clock is enabled at the second input clock after 1 is written to the
POWER6 bit.
Caution At startup, set POWER6 to 1 and then set TXE6 to 1. Clear TXE6 to 0 first, and then clear
POWER6 to 0.
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Figure 13-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
RXE6
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
Enables reception
0
1
PS61
PS60
Transmission operation
Does not output parity bit.
Reception operation
Reception without parity
0
0
1
1
0
1
0
1
Outputs 0 parity.
Reception as 0 parityNote
Judges as odd parity.
Judges as even parity.
Outputs odd parity.
Outputs even parity.
CL6
0
Specifies character length of transmit/receive data
Character length of data = 7 bits
Character length of data = 8 bits
1
SL6
0
Specifies number of stop bits of transmit data
Number of stop bits = 1
Number of stop bits = 2
1
ISRM6
Enables/disables occurrence of reception completion interrupt in case of error
“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
0
1
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. At startup, set POWER6 to 1 and then set RXE6 to 1. Clear RXE6 to 0 first, and then clear
POWER6 to 0.
2. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
3. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.
4. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
5. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
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(2) Asynchronous serial interface reception error status register 6 (ASIS6)
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register can be set by an 8-bit memory manipulation instruction and is read-only.
RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this
register is read.
Figure 13-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
Address: FF53H After reset: 00H R
Symbol
ASIS6
7
0
6
0
5
0
4
0
3
0
2
1
0
PE6
FE6
OVE6
PE6
0
Status flag indicating parity error
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If the parity of transmit data does not match the parity bit on completion of reception
FE6
0
Status flag indicating framing error
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If the stop bit is not detected on completion of reception
1
OVE6
Status flag indicating overrun error
0
1
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
asynchronous serial interface operation mode register 6 (ASIM6).
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
(RXB6) but discarded.
4. If data is read from ASIS6, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
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(3) Asynchronous serial interface transmission status register 6 (ASIF6)
This register indicates the status of transmission by serial interface UART6. It includes two status flag bits
(TXBF6 and TXSF6).
Transmission can be continued without disruption even during an interrupt period, by writing the next data to the
TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
This register can be set by an 8-bit memory manipulation instruction, and is read-only.
RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.
Figure 13-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
Address: FF55H After reset: 00H R
Symbol
ASIF6
7
0
6
0
5
0
4
0
3
0
2
0
1
0
TXBF6
TXSF6
TXBF6
Transmit buffer data flag
0
1
If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)
If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6
0
Transmit shift register data flag
If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6
(TXB6) after completion of transfer
1
If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To continuously transmit data, write the data of the first byte to TXB6, check that the value of
the TXBF6 flag is 0, and then write the data of the second byte to TXB6. The operation is not
guaranteed if data is written to TXB6 while the TXBF6 flag is 1.
2. While continuous transmission is being executed, check the value of the TXSF6 flag after the
transmission completion interrupt to determine the subsequent write processing to TXB6.
• If TXSF6 is 1: Continuous transmission is in progress. Data of 1 byte can be written.
• If TXSF6 is 0: Continuous transmission is complete. Data of 2 bytes can be written. When
doing so, observe Caution 1 above.
3. While continuous transmission is in progress, check that TXSF6 is 0 after the transmission
completion interrupt, and then execute clearing (POWER6 = 0 or TXE6 = 0). If clearing is
executed while the TXSF6 flag is 1, the transmit data cannot be guaranteed.
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(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 13-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Symbol
CKSR6
7
0
6
0
5
0
4
0
3
2
1
0
TPS63
TPS62
TPS61
TPS60
TPS63
TPS62
TPS61
TPS60
Base clock (fXCLK)
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
fX (10 MHz)
fX/2 (5 MHz)
fX/22 (2.5 MHz)
fX/23 (1.25 MHz)
fX/24 (625 kHz)
fX/25 (312.5 kHz)
fX/26 (156.25 kHz)
fX/27 (78.13 kHz)
fX/28 (39.06 kHz)
fX/29 (19.53 kHz)
fX/210 (9.77 kHz)
TM50 output (TO50)
Setting prohibited
Other
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. Figures in parentheses are for operation with fX = 10 MHz
2. fX: X1 input clock oscillation frequency
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(5) Baud rate generator control register 6 (BRGC6)
This register selects the base clock of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 13-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
Address: FF57H After reset: FFH R/W
Symbol
BRGC6
7
6
5
4
3
2
1
0
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
k
Output clock selection of
8-bit counter
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
×
0
0
0
×
0
0
1
×
0
1
0
×
8
Setting prohibited
fXCLK/8
9
fXCLK/9
10
fXCLK/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252 fXCLK/252
253 fXCLK/253
254 fXCLK/254
255 fXCLK/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
MDL67 to MDL60 bits.
2. The baud rate is the output clock of the 8-bit counter divided by 2.
Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS63 to TPS60 bits of CKSR6 register
2. k:
3. ×:
Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)
Don’t care
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(6) Asynchronous serial interface control register 6 (ASICL6)
This register controls the serial transfer operations of serial interface UART6.
ASICL6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction.
RESET input sets this register to 16H.
Remark ASICL6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 =
1). However, transfer is started by refresh because bit 6 (SBRT6) and bit 5 (SBTT6) of ASICL6 are
cleared to 0 when communication is complete (when an interrupt signal is generated).
Figure 13-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)
Address: FF58H After reset: 16H R/WNote
Symbol
ASICL6
7
6
5
4
3
2
1
0
SBRF6
SBRT6
SBTT6
SBL62
SBL61
SBL60
DIR6
TXDLV6
SBRF6
SBF reception status flag
0
1
If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
SBF reception in progress
SBRT6
SBF reception trigger
0
1
−
SBF reception trigger
SBTT6
SBF transmission trigger
0
1
−
SBF transmission trigger
Note Bit 7 is read-only.
Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold
the status of the SBRF6 flag.
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
reception has been correctly completed.
4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =
1.
5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of
SBF transmission.
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Figure 13-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)
SBL62
SBL61
SBL60
SBF transmission output width control
SBF is output with 13-bits length.
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
SBF is output with 14-bits length.
SBF is output with 15-bits length.
SBF is output with 16-bits length.
SBF is output with 17-bits length.
SBF is output with 18-bits length.
SBF is output with 19-bits length.
SBF is output with 20-bits length.
DIR6
MSB/LSB-first transfer
0
1
MSB-first transfer
LSB-first transfer
TXDLV6
Enables/disables inverting TXD6 output
0
1
Normal output of TXD6
Inverted output of TXD6
Caution Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
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13.4 Operation of Serial Interface UART6
This section explains the two modes of serial interface UART6.
13.4.1 Operation stop mode
In this mode, serial transfer cannot be executed; therefore, the power consumption can be reduced. In addition,
the pins can be used as ordinary port pins in this mode.
(1) Register setting
The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).
ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Address: FF50H After reset: 01H R/W
Symbol
ASIM6
7
6
5
4
3
2
1
0
POWER6
TXE6
RXE6
PS61
PS60
CL
SL6
ISRM6
POWER6
0Note 1
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit.
1Note 2
Enables operation of the internal operation clock.
TXE6
Enables/disables transmission
Disables transmission operation (synchronously resets the transmission circuit).
Enables transmission
0
1
RXE6
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
Enables reception
0
1
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when
POWER6 = 0.
2. Operation of the internal operation clock is enabled at the second input clock after 1 is written to the
POWER6 bit.
Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. Clear TXE6 to 0 first, and then clear
POWER6 to 0.
2. At startup, set POWER6 to 1 and then set RXE6 to 1. Clear RXE6 to 0 first, and then clear
POWER6 to 0.
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13.4.2 Asynchronous serial interface (UART) mode
In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be
performed.
A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of
baud rates.
(1) Register setting
The UART mode is set by asynchronous serial interface operation mode register 6 (ASIM6), asynchronous serial
interface reception error status register 6 (ASIS6), asynchronous serial interface transmission status register 6
(ASIF6), and asynchronous serial interface control register 6 (ASICL6).
(a) Asynchronous serial interface operation mode register 6 (ASIM6)
This 8-bit register controls the serial transfer operations of serial interface UART6.
ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of
ASIM6 = 1).
Address: FF50H After reset: 01H R/W
Symbol
ASIM6
7
6
5
4
3
2
1
0
POWER6
TXE6
RXE6
PS61
PS60
CL6
SL6
ISRM6
POWER6
0Note 1
Enables/disables operation of internal operation clock
Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit.
1Note 2
Enables operation of the internal operation clock.
TXE6
Enables/disables transmission
Disables transmission (synchronously resets the transmission circuit).
Enables transmission
0
1
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when
POWER6 = 0.
2. Operation of the internal operation clock is enabled at the second input clock after 1 is written to the
POWER6 bit.
Caution At startup, set POWER6 to 1 and then set TXE6 to 1. Clear TXE6 to 0 first, and then clear
POWER6 to 0.
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RXE6
Enables/disables reception
Disables reception (synchronously resets the reception circuit).
Enables reception
0
1
PS61
PS60
Transmission operation
Does not output parity bit.
Reception operation
Reception without parity
0
0
1
1
0
1
0
1
Outputs 0 parity.
Reception as 0 parityNote
Judges as odd parity.
Judges as even parity.
Outputs odd parity.
Outputs even parity.
CL6
0
Specifies character length of transmit/receive data
Character length of data = 7 bits
Character length of data = 8 bits
1
SL6
0
Specifies number of stop bits of transmit data
Number of stop bits = 1
Number of stop bits = 2
1
ISRM6
Enables/disables occurrence of reception completion interrupt in case of error
“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
0
1
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. At startup, set POWER6 to 1 and then set RXE6 to 1. Clear RXE6 to 0 first, and then clear
POWER6 to 0.
2. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
3. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.
4. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
5. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
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(b) Asynchronous serial interface reception error status register 6 (ASIS6)
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register can be set by an 8-bit memory manipulation instruction and is read-only.
RESET input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when
this register is read.
Address: FF53H After reset: 00H R
Symbol
ASIS6
7
0
6
0
5
0
4
0
3
0
2
1
0
PE6
FE6
OVE6
PE6
0
Status flag indicating parity error
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If the parity of transmit data does not match the parity bit on completion of reception
FE6
0
Status flag indicating framing error
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If the stop bit is not detected on completion of reception
1
OVE6
Status flag indicating overrun error
0
1
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
asynchronous serial interface operation mode register 6 (ASIM6).
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
(RXB6) but discarded.
4. If data is read from ASIS6, a wait cycle is generated. For details, refer to CHAPTER 27
CAUTIONS FOR WAIT.
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(c) Asynchronous serial interface transmission status register 6 (ASIF6)
This register indicates the status of transmission by serial interface UART6. It includes two status flag bits
(TXBF6 and TXSF6).
Transmission can be continued without disruption even during an interrupt period, by writing the next data to
the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
This register can be set by an 8-bit memory manipulation instruction, and is read-only.
RESET input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.
Address: FF55H After reset: 00H R
Symbol
ASIF6
7
0
6
0
5
0
4
0
3
0
2
0
1
0
TXBF6
TXSF6
TXBF6
Transmit buffer data flag
0
1
If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)
If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6
0
Transmit shift register data flag
If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6
(TXB6) after completion of transfer
1
If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To continuously transmit data, write the data of the first byte to TXB6, check that the value of
the TXBF6 flag is 0, and then write the data of the second byte to TXB6. The operation is not
guaranteed if data is written to TXB6 while the TXBF6 flag is 1.
2. While continuous transmission is being executed, check the value of the TXSF6 flag after the
transmission completion interrupt to determine the subsequent write processing to TXB6.
• If TXSF6 is 1: Continuous transmission is in progress. Data of 1 byte can be written.
• If TXSF6 is 0: Continuous transmission is complete. Data of 2 bytes can be written. When
doing so, observe Caution 1 above.
3. While continuous transmission is in progress, check that TXSF6 is 0 after the transmission
completion interrupt, and then execute clearing (POWER6 = 0 or TXE6 = 0). If clearing is
executed while the TXSF6 flag is 1, the transmit data cannot be guaranteed.
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(d) Asynchronous serial interface control register 6 (ASICL6)
This register controls the serial transfer operations of serial interface UART6.
ASICL6 can be set by a 1-bit transfer instruction or an 8-bit memory manipulation instruction.
RESET input sets this register to 16H.
Remark ASICL6 can be refreshed (the same value is written) by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1). However, transfer is started by refresh because bit 6 (SBRT6) and bit 5
(SBTT6) of ASICL6 are cleared to 0 when communication is complete (when an interrupt signal is
generated).
Address: FF58H After reset: 16H R/WNote
Symbol
ASICL6
7
6
5
4
3
2
1
0
SBRF6
SBRT6
SBTT6
SBL62
SBL61
SBL60
DIR6
TXDLV6
SBRF6
SBF reception status flag
0
1
If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
SBF reception in progress
SBRT6
SBF reception trigger
0
1
−
SBF reception trigger
SBTT6
SBF transmission trigger
0
1
−
SBF transmission trigger
Note Bit 7 is read-only.
Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode and hold
the status of the SBRF6 flag.
2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
reception has been correctly completed.
4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6
= 1.
5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of
SBF transmission.
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SBL62
SBL61
SBL60
SBF transmission output width control
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
SBF is output with 13-bit length.
SBF is output with 14-bit length.
SBF is output with 15-bit length.
SBF is output with 16-bit length.
SBF is output with 17-bit length.
SBF is output with 18-bit length.
SBF is output with 19-bit length.
SBF is output with 20-bit length.
DIR6
MSB/LSB-first transfer
0
1
MSB-first transfer
LSB-first transfer
TXDLV6
Enables/disables inverting TXD6 output
0
1
Normal output of TXD6
Inverted output of TXD6
Caution Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
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(2) Communication operation
(a) Normal transmit/receive data format
Figure 13-11 shows the format of the transmit/receive data.
Figure 13-11. Format of Normal UART Transmit/Receive Data
1. LSB-first transmission/reception
1 data frame
Start
bit
Parity
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop bit
Character bits
2. MSB-first transmission/reception
1 data frame
Start
bit
Parity
bit
D7
D6
D5
D4
D3
D2
D1
D0
Stop bit
Character bits
One data frame consists of the following bits.
• Start bit ... 1 bit
• Character bits ... 7 or 8 bits
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface mode register 6 (ASIM6).
Whether data is transferred with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial
interface control register 6 (ASICL6).
Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.
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Figure 13-12. Example of Normal UART Transmit/Receive Data Format
1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Transfer data: 55H, TXD6 pin inverted
output
1 data frame
Start
D7
D6
D5
D4
D3
D2
D1
D0
Parity
Stop
4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Transfer data: 36H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
Parity
Stop
Stop
5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Transfer data: 87H
1 data frame
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
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(b) Parity types and operation
The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN.
(i) Even parity
• Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that there is no parity bit when data is received. Because there is no
parity bit, a parity error does not occur.
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(c) Normal transmission
The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode
register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled.
Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity
bit, and stop bit are automatically appended to the data.
When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,
the data is sequentially output from TXS6 to the TXD6 pin, starting from the LSB. When transmission is
completed, a transmission completion interrupt request (INTST6) is generated.
Transmission is stopped until the data to be transmitted next is written to TXB6.
Figure 13-13 shows the timing of the transmission completion interrupt request (INTST6). This interrupt
occurs as soon as the last stop bit has been output.
Figure 13-13. Normal Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
T
XD6 (output)
START
D0
D1
D2
D6
D7
Parity
STOP
INTST6
2. Stop bit length: 2
Parity
STOP
T
XD6 (output)
START
D0
D1
D2
D6
D7
INTST6
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(d) Continuous transmission
When transmit shift register 6 (TXS6) has started the shift operation, the next transmit data can be written to
transmit buffer register 6 (TXB6). As a result, data can be transmitted without intermission even while an
interrupt that has occurred after transmission of one data frame is being serviced, thus realizing an efficient
communication rate. To transmit data continuously, however, transmission processing must be executed
while referencing bits 1 (TXBF6) and 0 (TXSF6) of asynchronous serial interface transmission status register
6 (ASIF6).
Caution When the device is incorporated in LIN, the continuous transmission function cannot be
used. Make sure that asynchronous serial interface transmission status register 6 (ASIF6)
is 00H before writing transmit data to transmit buffer register 6 (TXB6).
Table 13-2. Write Processing and Writing to TXB6 During Execution of Continuous Transmission
TXBF6
TXSF6
Write Processing During Execution of
Continuous Transmission
Writing to TXB6 During Execution of
Continuous Transmission
0
0
Enables writing 2 bytes or
Enables writing
transmission completion processing
0
1
1
0
Enables writing 1 byte
Enables writing
Disables writing
Enables writing 2 bytes or
transmission completion processing
1
1
Enables writing 1 byte
Disables writing
Cautions 1. To continuously transmit data, write the data of the first byte to TXB6, check that the
value of the TXBF6 flag is 0, and then write the data of the second byte to TXB6. The
operation is not guaranteed if data is written to TXB6 while the TXBF6 flag is 1.
2. While continuous transmission is being executed, check the value of the TXSF6 flag
after the transmission completion interrupt to determine the subsequent write
processing to TXB6.
• If TXSF6 is 1: Continuous transmission is in progress. Data of 1 byte can be written.
• If TXSF6 is 0: Continuous transmission is completed. Data of 2 bytes can be written.
To do so, observe Caution 1 above.
3. While continuous transmission is in progress, check that TXSF6 is 0 after the
transmission completion interrupt, and then execute clearing (POWER6 = 0 or TXE6 =
0). If clearing is executed while the TXSF6 flag is 1, the transmit data cannot be
guaranteed.
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Figure 13-14 shows the processing flow of continuous transmission.
Figure 13-14. Processing Flow of Continuous Transmission
Set registers.
Write transmit data to
TXB6 register.
Read ASIF6
No
register.
TXBF6 = 0?
Yes
Interrupt occurs.
Transfer executed
necessary number
of times?
Yes
No
Read ASIF6
register.
TXSF6 = 1?
Read ASIF6
register.
TXSF6 = 0?
No
No
Yes
Yes
Write transmit data to
TXB6 register.
Completion of
transmission processing
Wait for interrupt.
Remark TXB6: Transmit buffer register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)
TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)
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Figure 13-15 shows the timing of starting continuous transmission, and Figure 13-16 shows the timing of
ending continuous transmission.
Figure 13-15. Timing of Starting Continuous Transmission
Start
Start
Start
T
XD6
Data (1)
Parity Stop
Data (2)
Parity
Stop
INTST6
TXB6
FF
FF
Data (1)
Data (2)
Data (3)
TXS6
Data (1)
Data (2)
Data (3)
TXBF6
TXSF6
Note
Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether
writing is enabled using only the TXBF6 bit.
Remark TXD6:
TXD6 pin (output)
INTST6: Interrupt request signal
TXB6:
TXS6:
Transmit buffer register 6
Transmit shift register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
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Figure 13-16. Timing of Ending Continuous Transmission
Start
Start
TXD6
Data (n)
Parity
Stop
Data (n–1)
Parity
Stop
Stop
INTST6
TXB6
TXS6
Data (n–1)
Data (n)
FF
Data (n–1)
Data (n)
TXBF6
TXSF6
POWER6 or TXE6
Remark TXD6:
INTST6:
TXD6 pin (output)
Interrupt request signal
Transmit buffer register 6
Transmit shift register 6
TXB6:
TXS6:
ASIF6:
TXBF6:
TXSF6:
Asynchronous serial interface transmission status register 6
Bit 1 of ASIF6
Bit 0 of ASIF6
POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)
TXE6:
Bit 6 of asynchronous serial interface operation mode register (ASIM6)
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(e) Normal reception
Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial
interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the
RXD6 pin input is sampled again ( in Figure 13-17). If the RXD6 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun
error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) or a framing error (FE6) occurs while reception is in progress, reception continues
to the reception position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion
of reception.
Figure 13-17. Reception Completion Interrupt Request Timing
Start
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Stop
RX
D6 (input)
INTSR6
RXB6
Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
before reading RXB6.
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(f) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data
reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception
error interrupt servicing (INTSR6/INTSRE6) (refer to Table 13-3).
The contents of ASIS6 are reset to 0 when ASIS6 is read.
Table 13-3. Cause of Reception Error
Reception Error
Parity error
Cause
Value of ASIS6
The parity specified for transmission does not match the parity of the 04H
receive data.
Framing error
Overrun error
Stop bit is not detected.
02H
01H
Reception of the next data is completed before data is read from
receive buffer register 6 (RXB6).
The error interrupt can be separated into INTSR6 and INTSRE6 by clearing bit 0 (ISRM6) of asynchronous
serial interface operation mode register 6 (ASIM6) to 0.
Figure 13-18. Reception Error Interrupt
1. If ISRM6 is cleared to 0 (INTSR6 and INTSRE6 are separated)
(a) No error during reception
(b) Error during reception
INTSR6
INTSR6
INTSRE6
INTSRE6
2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)
(a) No error during reception
(b) Error during reception
INTSR6
INTSR6
INTSRE6
INTSRE6
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(g) Noise filter of receive data
The RXD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 13-19, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Figure 13-19. Noise Filter Circuit
Base clock
Internal signal A
R
XD6/P14
Internal signal B
In
Q
In
Q
LD_EN
Match detector
(h) SBF transmission
When the device is incorporated in LIN, the SBF (Synchronous Break Field) transmission control function is
used for transmission. For the transmission operation of LIN, refer to Figure 13-1 LIN Transmission
Operation.
The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode
register 6 (ASIM6) is set to 1. Transmission is enabled when bit 6 (TXE6) of ASIM6 is set to 1 next time, and
SBF transmission operation is started when bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) is set to 1.
After transmission has been started, the low levels of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of
ASICL6) are output. When SBF transmission has been completed, a transmission completion interrupt
request (INTST6) is generated, and SBTT6 is automatically cleared. After SBF transmission has been
completed, the normal transmission mode is restored.
Transmission is stopped until the data to be transmitted next is written to transmit buffer register 6 (TXB6) or
SBTT6 is set to 1.
Figure 13-20. SBF Transmission
1
2
3
4
5
6
7
8
9
10
11
12
13 Stop
TXD6
INTST6
SBTT6
Remark TXD6:
TXD6 pin (output)
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)
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(i) SBF reception
When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is
used for reception. For the reception operation of LIN, refer to Figure 13-2 LIN Reception Operation.
Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6
(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6)
of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,
the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable
status.
When the start bit has been detected, reception is started, and serial data is sequentially stored in the
receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is
11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At
this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of
errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status
register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed.
In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not
performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not
occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In
this case, the SBRF6 and SBRT6 bits are not cleared.
Figure 13-21. SBF Reception
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
1
2
3
4
5
6
7
8
9
10
11
RXD6
SBRT6
/SBRF6
INTSR6
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
1
2
3
4
5
6
7
8
9
10
RXD6
SBRT6
/SBRF6
INTSR6
“0”
Remark RXD6:
RXD6 pin (input)
SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)
SBRF6: Bit 7 of ASICL6
INTSR6: Reception completion interrupt request
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13.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and
generates a serial clock for transmission/reception of UART6.
Separate 8-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
•
•
Base clock (Clock)
The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to
each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is
1. This clock is called the base clock (Clock) and its frequency is called fXCLK. Clock is fixed to the low level
when POWER6 = 0.
Transmission counter
This counter stops, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface
operation mode register 6 (ASIM6) is 0.
It starts counting when POWER6 = 1 and TXE6 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).
If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been
completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues
counting until POWER6 or TXE6 is cleared to 0.
•
Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
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Figure 13-22. Configuration of Baud Rate Generator
POWER6
f
X
f
X
/2
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/22
POWER6, TXE6 (or RXE6)
Clock
/23
/24
/25
/26
/27
/28
/29
Selector
8-bit counter
(fXCLK
)
fX
/210
Match detector
Baud rate
1/2
TO50/TI50/P17
(TM50 output)
CKSR6: TPS63 to TPS60
BRGC6: MDL67 to MDL60
Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)
TXE6:
Bit 6 of ASIM6
RXE6:
Bit 5 of ASIM6
CKSR6:
BRGC6:
Clock selection register 6
Baud rate generator control register 6
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(2) Generation of serial clock
A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control
register 6 (BRGC6).
Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6.
Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
(a) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1).
Address: FF56H After reset: 00H R/W
Symbol
CKSR6
7
0
6
0
5
0
4
0
3
2
1
0
TPS63
TPS62
TPS61
TPS60
TPS63
TPS62
TPS61
TPS60
Base clock (fXCLK)
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
fX (10 MHz)
fX/2 (5 MHz)
fX/22 (2.5 MHz)
fX/23 (1.25 MHz)
fX/24 (625 kHz)
fX/25 (312.5 kHz)
fX/26 (156.25 kHz)
fX/27 (78.13 kHz)
fX/28 (39.06 kHz)
fX/29 (19.53 kHz)
fX/210 (9.77 kHz)
TM50 output
Other
Setting prohibited
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. Figures in parentheses are for operation with fX = 10 MHz
2. fX: X1 input clock oscillation frequency
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(b) Baud rate generator control register 6 (BRGC6)
This register selects the base clock of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1).
Address: FF57H After reset: FFH R/W
Symbol
BRGC6
7
6
5
4
3
2
1
0
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
k
Output clock selection of
8-bit counter
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
×
0
0
0
×
0
0
1
×
0
1
0
×
8
Setting prohibited
fXCLK/8
9
fXCLK/9
10
fXCLK/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
252 fXCLK/252
253 fXCLK/253
254 fXCLK/254
255 fXCLK/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
MDL67 to MDL60 bits.
2. The baud rate is the output clock of the 8-bit counter divided by 2.
Remarks 1. fXCLK: Frequency of base clock (Clock) selected by the TPS63 to TPS60 bits of CKSR6 register
2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)
3. ×: Don’t care
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(c) Baud rate
The baud rate can be calculated by the following expression.
fXCLK
• Baud rate =
[bps]
2 × k
fXCLK: Frequency of base clock (Clock) selected by TPS63 to TPS60 bits of CKSR6 register
k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)
(d) Error of baud rate
The baud rate error can be calculated by the following expression.
Actual baud rate (baud rate with error)
• Error (%) =
− 1 × 100 [%]
Desired baud rate (correct baud rate)
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at
the reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock (Clock) = 20 MHz = 20,000,000 Hz
Set value of MDL67 to MDL60 bits of BRGC6 register = 01000001B (k = 65)
Target baud rate = 153,600 bps
Baud rate = 20 M/(2 × 65)
= 20,000,000/(2 × 65) = 153,846 [bps]
Error = (153,846/153,600 − 1) × 100
= 0.160 [%]
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(3) Example of setting baud rate
Table 13-4. Set Data of Baud Rate Generator
Baud Rate
[bps]
fX = 10.0 MHz
fX = 8.38 MHz
fX = 4.19 MHz
TPS63 to
TPS60
k
Calculated ERR[%] TPS63 to
k
Calculated ERR[%] TPS63 to
k
Calculated ERR[%]
value
TPS60
value
TPS60
value
600
1200
6H
5H
4H
3H
2H
2H
1H
1H
0H
0H
0H
0H
0H
130
130
130
130
130
120
130
80
601
1202
0.16
0.16
0.16
0.16
0.16
0.16
0.16
0.00
0.16
0.16
0.94
−1.36
−1.36
6H
109
109
109
109
109
101
109
134
109
55
601
0.11
0.11
0.11
0.11
0.11
0.28
0.11
0.06
0.11
−0.80
1.03
1.03
1.03
5H
109
109
109
109
109
101
109
67
601
0.11
0.11
0.11
0.11
0.11
−0.28
0.11
0.06
−0.80
1.03
1.03
−2.58
1.03
5H
1201
4H
1201
2400
2404
4H
2403
3H
2403
4800
4808
3H
4805
2H
4805
9600
9615
2H
9610
1H
9610
10400
19200
31250
38400
76800
115200
153600
230400
10417
19231
31250
38462
76923
116279
151515
227272
2H
10371
19200
31268
38440
76182
116388
155185
232777
1H
10475
19220
31268
38090
77593
116389
149643
232778
1H
0H
0H
0H
130
65
0H
0H
55
0H
0H
27
43
0H
36
0H
18
33
0H
27
0H
14
22
0H
18
0H
9
Caution The maximum permissible frequency (fXCLK) of the base clock is 25 MHz.
Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK))
k:
Value set by MDL67 to MDL60 bits of baud rate generator control register 6
(BRGC6) (k = 8, 9, 10, ..., 255)
fX:
X1 input clock oscillation frequency
ERR:
Baud rate error
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(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 13-23. Permissible Baud Rate Range During Reception
Latch timing
Transfer rate
Start bit
Start bit
Start bit
Bit 0
FL
Bit 1
Bit 7
Parity bit
Stop bit
of UART6
1 data frame (11 × FL)
Minimum permissible
transfer rate
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum permissible
transfer rate
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmax
As shown in Figure 13-23, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
1
FL = (Brate)−
Brate: Baud rate of UART6
k:
Set value of BRGC6
1-bit data length
FL:
Margin of latch timing: 2 clocks
21k + 2
2k
k − 2
2k
Minimum permissible transfer rate: FLmin = 11 × FL −
× FL =
FL
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Therefore, the maximum receivable baud rate at the transmission destination is as follows.
22k
1
BRmax = (Flmin/11)−
=
Brate
21k + 2
Similarly, the maximum permissible transfer rate can be calculated as follows.
10
11
k + 2
21k − 2
2 × k
× FLmax = 11 × FL −
× FL =
FL
2 × k
21k × 2
FLmax =
FL × 11
20k
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
20k
1
BRmin = (FLmax/11)−
=
Brate
21k − 2
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 13-5. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k)
Maximum Permissible Baud Rate Error
Minimum Permissible Baud Rate Error
8
+3.53%
+4.26%
+4.56%
+4.66%
+4.72%
−3.61%
−4.31%
−4.58%
−4.67%
−4.73%
20
50
100
255
Remarks 1. The accuracy of reception depends on the number of bits in one frame, input clock frequency,
and division ratio (k). The higher the input clock frequency and the higher the division ratio (k),
the higher the accuracy.
2. k: Set value of BRGC6
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(5) Transfer rate during continuous transmission
When data is continuously transmitted, the transfer rate from a stop bit to the next start bit is extended by two
clocks from the normal value. However, the result of transfer is not affected because the timing is initialized on
the reception side when the start bit is detected.
Figure 13-24. Transfer Rate During Continuous Transmission
Start bit of
1 data frame
second byte
Bit 0
FL
Bit 1
FL
Bit 7
FL
Bit 0
FL
Start bit
FL
Start bit
FL
Parity bit
FL
Stop bit
FLstp
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK, the following
expression is satisfied.
FLstp = FL + 2/fXCLK
Therefore, the transfer rate during continuous transmission is:
Transfer rate = 11 × FL + 2/fXCLK
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CHAPTER 14 SERIAL INTERFACE CSI10
14.1 Functions of Serial Interface CSI10
Serial interface CSI10 has the following two modes.
•
•
Operation stop mode
3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not performed and can enable a reduction in the power consumption.
(2) 3-wire serial I/O mode (MSB/LSB-first selectable)
This mode is used to transfer 8-bit data using three lines: a serial clock line (SCK10) and two serial data lines
(SI10 and SO10).
The processing time of data transfer can be shortened in the 3-wire serial I/O mode because transmission and
reception can be simultaneously executed.
In addition, whether 8-bit data is transferred with the MSB or LSB first can be specified, so this interface can be
connected to any device.
The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers with a clocked serial
interface.
14.2 Configuration of Serial Interface CSI10
Serial interface CSI10 consists of the following hardware.
Table 14-1. Configuration of Serial Interface CSI10
Item
Configuration
Registers
Transmit buffer register 10 (SOTB10)
Serial I/O shift register 10 (SIO10)
Control registers
Serial operation mode register 10 (CSIM10)
Serial clock selection register 10 (CSIC10)
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Figure 14-1. Block Diagram of Serial Interface CSI10
Internal bus
8
8
Serial I/O shift
register 10 (SIO10)
Transmit buffer
register 10 (SOTB10)
Output
selector
SI10/P11/R D0
X
SO10/P12
Transmit data
controller
Output latch
Transmit controller
f
X
/2 to f
X
/27
D0
Clock start/stop controller &
clock phase controller
Selector
INTCSI10
SCK10/P10/T
X
(1) Transmit buffer register 10 (SOTB10)
This register sets the transmit data.
Transmission/reception is started by writing data to SOTB10 when bit 6 (TRMD10) of serial operation mode
register 10 (CSIM10) is 1.
The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and
output to the serial output pin (SO10).
SOTB10 can be written or read by an 8-bit memory manipulation instruction.
RESET input makes this register undefined.
Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication).
(2) Serial I/O shift register 10 (SIO10)
This is an 8-bit register that converts data from parallel data into serial data and vice versa.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO10 if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10)
is 0.
During reception, the data is read from the serial input pin (SI10) to SIO10.
RESET input clears this register to 00H.
Caution Do not access SIO10 when CSOT10 = 1 (during serial communication).
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14.3 Registers Controlling Serial Interface CSI10
Serial interface CSI10 is controlled by the following two registers.
•
•
Serial operation mode register 10 (CSIM10)
Serial clock selection register 10 (CSIC10)
(1) Serial operation mode register 10 (CSIM10)
CSIM10 is used to select the operation mode and enable or disable operation.
CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 14-2. Format of Serial Operation Mode Register 10 (CSIM10)
Address: FF80H After reset: 00H R/WNote 1
Symbol
CSIM10
7
6
5
0
4
3
0
2
0
1
0
0
CSIE10
TRMD10
DIR10
CSOT10
CSIE10
0
Operation control in 3-wire serial I/O mode
Stops operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins can be used as general-
purpose port pins).
1
Enables operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins are at active level).
TRMD10Note 2
Transmit/receive mode control
Receive mode (transmission disabled).
Transmit/receive mode
0Note 3
1
DIR10Note 4
First bit specification
0
1
MSB
LSB
CSOT10Note 5
Operation mode flag
Communication is stopped.
0
1
Communication is in progress.
Notes 1. Bit 0 is read-only.
2. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).
3. The SO10 pin is fixed to the low level when TRMD10 is 0. Reception is started when data is read from
SIO10.
4. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).
5. CSOT10 is cleared if CSIE10 is set to 0 (operation stopped).
Caution Be sure to set bit 5 to 0.
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(2) Serial clock selection register 10 (CSIC10)
CSIC10 is used to select the phase of the data clock and set the count clock.
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 14-3. Format of Serial Clock Selection Register 10 (CSIC10)
Address: FF81H After reset: 00H R/W
Symbol
CSIC10
7
0
6
0
5
0
4
3
2
1
0
CKP10
DAP10
CKS102
CKS101
CKS100
CKP10
0
DAP10
0
Data clock phase selection
Type
1
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
0
1
1
1
0
1
2
3
4
SCK10
SO10
SI10 input timing
SCK10
SO10
SI10 input timing
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
CKS102
CKS101
CKS100
CSI10 count clock selection
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/2 (5 MHz)
fX/22 (2.5 MHz)
fX/23 (1.25 MHz)
fX/24 (625 kHz)
fX/25 (312.5 kHz)
fX/26 (156.25 kHz)
fX/27 (78.13 kHz)
External clock input to SCK10
Cautions 1. Do not write CSIC10 during a communication operation or when using P10/SCK10/TXD0,
P11/SI10/RXD0, and P12/SO10 as general-purpose port pins.
2. The phase type of the data clock is type 1 after reset.
Remarks 1. Figures in parentheses are for operation with fX = 10 MHz
2. fX: X1 input clock oscillation frequency
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14.4 Operation of Serial Interface CSI10
Serial interface CSI10 can be used in the following two modes.
•
•
Operation stop mode
3-wire serial I/O mode
14.4.1 Operation stop mode
Serial transfer is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the
P10/SCK10/TXD0, P11/SI10/RXD0, and P12/SO10 pins can be used as ordinary I/O port pins in this mode.
(1) Register setting
The operation stop mode is set by serial operation mode register 10 (CSIM10).
(a) Serial operation mode register 10 (CSIM10)
CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM10 to 00H.
Address: FF80H After reset: 00H R/W
Symbol
CSIM10
7
6
5
0
4
3
0
2
0
1
0
0
CSIE10
TRMD10
DIR10
CSOT10
CSIE10
0
Operation control in 3-wire serial I/O mode
Stops operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins can be used as general-
purpose port pins).
1
Enables operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins are at active level).
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14.4.2 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connecting peripheral ICs and display controllers that have a clocked serial
interface.
In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and
serial input (SI10) lines.
(1) Register setting
The 3-wire serial I/O mode is set by serial operation mode register 10 (CSIM10) and serial clock selection register
10 (CSIC10).
(a) Serial operation mode register 10 (CSIM10)
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Address: FF80H After reset: 00H R/WNote 1
Symbol
CSIM10
7
6
5
0
4
3
0
2
0
1
0
0
CSIE10
TRMD10
DIR10
CSOT10
CSIE10
0
Operation control in 3-wire serial I/O mode
Stops operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins can be used as general-
purpose port pins).
1
Enables operation (SI10/P11/RXD0, SO10/P12, and SCK10/P10/TXD0 pins are at active level).
TRMD10Note 2
Transmit/receive mode control
Receive mode (transmission disabled).
Transmit/receive mode
0Note 3
1
DIR10Note 4
First bit specification
0
1
MSB
LSB
CSOT10Note 5
Operation mode flag
Communication is stopped.
0
1
Communication is in progress.
Notes 1. Bit 0 is read-only.
2. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).
3. The SO10 pin is fixed to the low level when TRMD10 is 0. Reception is started when data is read from
SIO10.
4. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).
5. CSOT10 is cleared if CSIE10 is set to 0 (operation stopped).
Caution Be sure to set bit 5 to 0.
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(b) Serial clock selection register 10 (CSIC10)
CSIC10 can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Address: FF81H After reset: 00H R/W
Symbol
CSIC10
7
0
6
0
5
0
4
3
2
1
0
CKP10
DAP10
CKS102
CKS101
CKS100
CKP10
0
DAP10
0
Data clock phase selection
Type
1
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
0
1
1
1
0
1
2
3
4
SCK10
SO10
SI10 input timing
SCK10
SO10
SI10 input timing
SCK10
SO10
D7 D6 D5 D4 D3 D2 D1 D0
SI10 input timing
CKS102
CKS101
CKS100
CSI10 count clock selection
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fX/2 (5 MHz)
fX/22 (2.5 MHz)
fX/23 (1.25 MHz)
fX/24 (625 kHz)
fX/25 (312.5 kHz)
fX/26 (156.25 kHz)
fX/27 (78.13 kHz)
External clock input to SCK10
Cautions 1. Do not write CSIC10 during a communication operation or when using P10/SCK10/TXD0,
P11/SI10/RXD0, and P12/SO10 as general-purpose port pins.
2. The phase type of the data clock is type 1 after reset.
Remarks 1. Figures in parentheses are for operation with fX = 10 MHz
2. fX: X1 input clock oscillation frequency
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(2) Setting of ports
<1> Transmit/receive mode
(a) To use externally input clock as system clock (SCK10)
Bit 1 (PM11) of port mode register 1: Set to 1
Bit 2 (PM12) of port mode register 1: Cleared to 0
Bit 0 (PM10) of port mode register 1: Set to 1
Bit 2 (P12) of port 1: Cleared to 0
(b) To use internal clock as system clock (SCK10)
Bit 1 (PM11) of port mode register 1: Set to 1
Bit 2 (PM12) of port mode register 1: Cleared to 0
Bit 0 (PM10) of port mode register 1: Cleared to 0
Bit 2 (P12) of port 1: Cleared to 0
Bit 0 (P10) of port 1: Set to 1
<2> Receive mode (with transmission disabled)
(a) To use externally input clock as system clock (SCK10)
Bit 1 (PM11) of port mode register 1: Set to 1
Bit 0 (PM10) of port mode register 1: Set to 1
(b) To use internal clock as system clock (SCK10)
Bit 1 (PM11) of port mode register 1: Set to 1
Bit 0 (PM10) of port mode register 1: Cleared to 0
Bit 0 (P10) of port 1: Set to 1
Remark The transmit/receive mode or receive mode is selected by using bit 6 (TRMD10) of serial operation
mode register 10 (CSIM10).
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(3) Communication operation
In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or
received in synchronization with the serial clock.
Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1.
Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition,
data can be received when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0.
Reception is started when data is read from serial I/O shift register 10 (SIO10).
After communication has been started, bit 0 (CSOT10) of CSIM10 is set to 1. When communication of 8-bit data
has been completed, a communication completion interrupt request flag (CSIIF10) is set, and CSOT10 is cleared
to 0. Then the next communication is enabled.
Caution Do not access the control register and data register when CSOT10 = 1 (during serial
communication).
Figure 14-4. Timing in 3-Wire Serial I/O Mode (1/2)
(1) Transmission/reception timing (Type 1; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0)
SCK10
Read/write trigger
SOTB10
SIO10
55H (communication data)
ABH
56H
ADH
5AH
B5H
6AH
D5H AAH
CSOT10
INTCSI10
CSIIF10
SI10 (receive AAH)
SO10
55H is written to SOTB10.
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Figure 14-4. Timing in 3-Wire Serial I/O Mode (2/2)
(2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1)
SCK10
Read/write trigger
SOTB10
SIO10
55H (communication data)
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOT10
INTCSI10
CSIIF10
SI10 (receives AAH)
SO10
55H is written to SOTB10.
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Figure 14-5. Timing of Clock/Data Phase
(a) Type 1; CKP10 = 0, DAP10 = 0
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
(b) Type 2; CKP10 = 0, DAP10 = 1
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
(c) Type 3; CKP10 = 1, DAP10 = 0
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
(d) Type 4; CKP10 = 1, DAP10 = 1
SCK10
SI10 capture
SO10
Writing to SOTB10 or
reading from SIO10
CSIIF10
D7
D6
D5
D4
D3
D2
D1
D0
CSOT10
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(4) Timing of output to SO10 pin (first bit)
When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin.
The output operation of the first bit at this time is described below.
Figure 14-6. Output Operation of First Bit
(1) When CKP10 = 0, DAP10 = 0 (or CKP10 = 1, DAP10 = 0)
SCK10
Writing to SOTB10 or
reading from SIO10
SOTB10
SIO10
Output latch
First bit
2nd bit
SO10
The first bit is directly latched by the SOTB10 register to the output latch at the falling (or rising) edge of SCK10,
and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is transferred to the
SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same time, the first bit of
the receive data is stored in the SIO10 register via the SI10 pin.
The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising)
edge of SCK10, and the data is output from the SO10 pin.
(2) When CKP10 = 0, DAP10 = 1 (or CKP10 = 1, DAP10 = 1)
SCK10
Writing to SOTB10 or
reading from SIO10
SOTB10
SIO10
Output latch
First bit
2nd bit
3rd bit
SO10
The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10
register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the
value of the SOTB10 register is transferred to the SIO10 register at the next rising (or falling) edge of SCK10, and
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin.
The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising)
edge of SCK10, and the data is output from the SO10 pin.
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(5) Output value of SO10 pin (last bit)
After communication has been completed, the SO10 pin holds the output value of the last bit.
Figure 14-7. Output Value of SO10 Pin (Last Bit)
(1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0)
SCK10
Writing to SOTB10 or
reading from SIO10
( ← Next request is issued.)
SOTB10
SIO10
Output latch
Last bit
SO10
(2) Type 2; when CKP10 = 0 and DAP10 = 1 (or CKP10 = 1, DAP10 = 1)
SCK10
Writing to SOTB10 or
reading from SIO10
( ← Next request is issued.)
SOTB10
SIO10
Output latch
SO10
Last bit
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CHAPTER 15 INTERRUPT FUNCTIONS
15.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group
and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L).
Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If
two or more interrupts with the same priority are generated simultaneously, each interrupt is serviced according to
its predetermined priority (see Table 15-1).
A standby release signal is generated.
Seven external interrupt requests and 15 internal interrupt requests are provided as maskable interrupts.
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts
are disabled. The software interrupt does not undergo interrupt priority control.
15.2 Interrupt Sources and Configuration
A total of 23 interrupt sources exist for maskable and software interrupts (see Table 15-1).
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Table 15-1. Interrupt Source List
Interrupt
Type
Default
Interrupt Source
Trigger
Internal/
External
Vector
Table
Basic
PriorityNote 1
Configuration
TypeNote 2
Name
INTLVI
Address
Maskable
0
1
Low-voltage detection
Internal
External
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
(A)
(B)
INTP0
Pin input edge detection
2
INTP1
3
INTP2
4
INTP3
5
INTP4
6
INTP5
7
INTSRE6
INTSR6
INTST6
UART6 reception error generation
End of UART6 reception
Internal
(A)
8
9
End of UART6 transmission
10
INTCSI10/
INTST0
End of CSI10 transfer/end of UART0
transmission
11
12
13
14
INTTMH1
INTTMH0
INTTM50
INTTM000
Match between TMH1 and CRH1
(when compare register is specified)
001AH
001CH
001EH
0020H
Match between TMH0 and CRH0
(when compare register is specified)
Match between TM50 and CR50
(when compare register is specified)
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
15
INTTM010
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection
0022H
(when capture register is specified)
16
17
INTAD
End of A/D conversion
0024H
0026H
INTSR0
End of UART0 reception or reception error
generation
18
19
INTWTI
Watch timer reference time interval signal
0028H
002AH
INTTM51
Match between TM51 and CR51
(when compare register is specified)
20
21
−
INTKR
INTWT
BRK
Key interrupt detection
Watch timer overflow
BRK instruction execution
Reset input
External
002CH
002EH
003EH
0000H
(C)
(A)
(D)
−
Internal
Software
Reset
−
−
−
RESET
POC
Power-on reset
LVI
Low-voltage detection
Clock monitor X1 oscillation stop detection
WDT WDT overflow
Notes 1. The default priority is the priority applicable when two or more maskable interrupt are generated
simultaneously. 0 is the highest priority, and 21 is the lowest.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1.
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Figure 15-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal maskable interrupt
Internal bus
IE
MK
PR
ISP
Vector table
address generator
Priority controller
Interrupt
request
IF
Standby release signal
(B) External maskable interrupt (INTP0 to INTP5)
Internal bus
External interrupt edge
enable register
(EGP, EGN)
MK
IE
PR
ISP
Vector table
address generator
Priority controller
Interrupt
request
Edge
detector
IF
Standby release signal
IF:
IE:
Interrupt request flag
Interrupt enable flag
ISP: In-service priority flag
MK:
PR:
Interrupt mask flag
Priority specification flag
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Figure 15-1. Basic Configuration of Interrupt Function (2/2)
(C) External maskable interrupt (INTKR)
Internal bus
MK
IE
PR
ISP
Interrupt
request
Vector table
address generator
Key
interrupt
detector
Priority controller
IF
1 when KRMn = 1 (n = 0 to 7)
Standby release signal
(D) Software interrupt
Internal bus
Interrupt
request
Vector table
address generator
IF:
IE:
Interrupt request flag
Interrupt enable flag
ISP: In-service priority flag
MK:
PR:
Interrupt mask flag
Priority specification flag
KRM: Key return mode register
15.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functions.
•
•
•
•
•
•
Interrupt request flag register (IF0L, IF0H, IF1L)
Interrupt mask flag register (MK0L, MK0H, MK1L)
Priority specification flag register (PR0L, PR0H, PR1L)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
Program status word (PSW)
Table 15-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding
to interrupt request sources.
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Table 15-2. Flags Corresponding to Interrupt Request Sources
Interrupt
Request
Interrupt Request Flag
Register
IF0L
Interrupt Mask Flag
Register
MK0L
Priority Specification Flag
Register
INTLVI
LVIIF
LVIMK
PMK0
LVIPR
PR0L
INTP0
PIF0
PPR0
INTP1
PIF1
PMK1
PPR1
INTP2
PIF2
PMK2
PPR2
INTP3
PIF3
PMK3
PPR3
INTP4
PIF4
PMK4
PPR4
INTP5
PIF5
PMK5
PPR5
INTSRE6
INTSR6
INTST6
INTCSI10
INTST0
INTTMH1
INTTMH0
INTTM50
INTTM000
INTTM010
INTAD
SREIF6
SRIF6
STIF6
DUALIF0Note
SREMK6
SRMK6
STMK6
DUALMK0
SREPR6
SRPR6
STPR6
DUALPR0
IF0H
MK0H
PR0H
TMIFH1
TMIFH0
TMIF50
TMIF000
TMIF010
ADIF
TMMKH1
TMMKH0
TMMK50
TMMK000
TMMK010
ADMK
TMPRH1
TMPRH0
TMPR50
TMPR000
TMPR010
ADPR
IF1L
MK1L
PR1L
INTSR0
INTWTI
INTTM51
INTKR
SRIF0
SRMK0
WTIMK
SRPR0
WTIPR
WTIIF
TMIF51
KRIF
TMMK51
KRMK
TMPR51
KRPR
INTWT
WTIF
WTMK
WTPR
Note If either of the two types of interrupt sources is generated, these flags are set (1).
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon RESET input.
IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are
combined to form 16-bit register IF0, they are read with a 16-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 15-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L)
Address: FFE0H After reset: 00H R/W
Symbol
IF0L
7
6
5
4
3
2
1
0
SREIF6
PIF5
PIF4
PIF3
PIF2
PIF1
PIF0
LVIIF
Address: FFE1H After reset: 00H R/W
Symbol
IF0H
7
6
5
4
3
2
1
0
TMIF010
TMIF000
TMIF50
TMIFH0
TMIFH1
DUALIF0
STIF6
SRIF6
Address: FFE2H After reset: 00H R/W
Symbol
IF1L
7
6
5
4
3
2
1
0
0Note
0Note
WTIF
KRIF
TMIF51
WTIIF
SRIF0
ADIF
XXIFX
Interrupt request flag
0
1
No interrupt request signal is generated
Interrupt request is generated, interrupt request status
Note Be sure to set bits 6 and 7 of IF1L to 0.
Cautions 1. When operating a timer, serial interface, or A/D converter after standby release, operate it
once after clearing the interrupt request flag. An interrupt request flag may be set by noise.
2. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and
then the interrupt routine is entered.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are
combined to form 16-bit register MK0, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 15-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L)
Address: FFE4H After reset: FFH R/W
Symbol
MK0L
7
6
5
4
3
2
1
0
SREMK6
PMK5
PMK4
PMK3
PMK2
PMK1
PMK0
LVIMK
Address: FFE5H After reset: FFH R/W
Symbol
MK0H
7
6
5
4
3
2
1
0
TMMK010 TMMK000
TMMK50
TMMKH0
TMMKH1
DUALMK0
STMK6
SRMK6
Address: FFE6H After reset: FFH R/W
Symbol
MK1L
7
6
5
4
3
2
1
0
1Note
1Note
WTMK
KRMK
TMMK51
WTIMK
SRMK0
ADMK
XXMKX
Interrupt servicing control
0
1
Interrupt servicing enabled
Interrupt servicing disabled
Note Be sure to set bits 6 and 7 of MK1L to 1.
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(3) Priority specification flag registers (PR0L, PR0H, PR1L)
The priority specification flag registers are used to set the corresponding maskable interrupt priority order.
PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
combined to form 16-bit register PR0, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 15-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L)
Address: FFE8H After reset: FFH R/W
Symbol
PR0L
7
6
5
4
3
2
1
0
SREPR6
PPR5
PPR4
PPR3
PPR2
PPR1
PPR0
LVIPR
Address: FFE9H After reset: FFH R/W
Symbol
PR0H
7
6
5
4
3
2
1
0
TMPR010 TMPR000
TMPR50
TMPRH0
TMPRH1
DUALPRO
STPR6
SRPR6
Address: FFEAH After reset: FFH R/W
Symbol
PR1L
7
6
5
4
3
2
1
0
1Note
1Note
WTPR
KRPR
TMPR51
WTIPR
SRPR0
ADPR
XXPRX
Priority level selection
0
1
High priority level
Low priority level
Note Be sure to set bits 6 and 7 of PR1L to 1.
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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
These registers specify the valid edge for INTP0 to INTP5.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 15-5. Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN)
Address: FF48H After reset: 00H R/W
Symbol
EGP
7
0
6
0
5
4
3
2
1
0
EGP5
EGP4
EGP3
EGP2
EGP1
EGP0
Address: FF49H After reset: 00H R/W
Symbol
EGN
7
0
6
0
5
4
3
2
1
0
EGN5
EGN4
EGN3
EGN2
EGN1
EGN0
EGPn
EGNn
INTPn pin valid edge selection (n = 0 to 5)
0
0
1
1
0
1
0
1
Interrupt disabled
Falling edge
Rising edge
Both rising and falling edges
Table 15-3 shows the ports corresponding to EGPn and EGNn.
Table 15-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register
Edge Detection Port
External Request Signal
INTP0
EGP0
EGP1
EGP2
EGP3
EGP4
EGP5
EGN0
EGN1
EGN2
EGN3
EGN4
EGN5
P120
P30
P31
P32
P33
P16
INTP1
INTP2
INTP3
INTP4
INTP5
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CHAPTER 15 INTERRUPT FUNCTIONS
(5) Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed,
the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt
request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are
transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction.
They are restored from the stack with the RETI, RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 15-6. Format of Program Status Word
After reset
02H
7
6
Z
5
4
3
2
0
1
0
PSW IE
RBS1 AC RBS0
ISP
CY
Used when normal instruction is executed
ISP
Priority of interrupt currently being serviced
0
High-priority interrupt servicing (low-priority
interrupt disabled)
Interrupt request not acknowledged, or low-
priority interrupt servicing (all maskable
interrupts enabled)
1
IE
0
Interrupt request acknowledgement enable/disable
Disabled
Enabled
1
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CHAPTER 15 INTERRUPT FUNCTIONS
15.4 Interrupt Servicing Operations
15.4.1 Maskable interrupt acknowledgement
A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not
acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times from
generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 15-4 below.
For the interrupt request acknowledgement timing, see Figures 15-8 and 15-9.
Table 15-4. Time from Generation of Maskable Interrupt Until Servicing
Minimum Time
7 clocks
8 clocks
Maximum TimeNote
32 clocks
33 clocks
When ××PR = 0
When ××PR = 1
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same
priority level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 15-7 shows the interrupt request acknowledgement algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then
PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged
interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into
the PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
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Figure 15-7. Interrupt Request Acknowledgement Processing Algorithm
Start
No
××IF = 1?
Yes (interrupt request generation)
No
××MK = 0?
Yes
Interrupt request held pending
Yes (High priority)
××PR = 0?
No (Low priority)
Any high-priority
Yes
Any high-priority
interrupt request among those
simultaneously generated
with ××PR = 0?
Yes
interrupt request among
those simultaneously generated
with ××PR = 0?
Interrupt request held pending
No
Interrupt request held pending
Yes
No
No
IE = 1?
Yes
Any high-priority
interrupt request among
those simultaneously
generated?
Interrupt request held pending
Interrupt request held pending
No
No
IE = 1?
Yes
Vectored interrupt servicing
Interrupt request held pending
No
ISP = 1?
Yes
Interrupt request held pending
Vectored interrupt servicing
××IF: Interrupt request flag
××MK: Interrupt mask flag
××PR: Priority specification flag
IE:
Flag that controls acknowledgement of maskable interrupt request (1 = Enable, 0 = Disable)
ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = high-priority interrupt
servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)
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Figure 15-8. Interrupt Request Acknowledgement Timing (Minimum Time)
6 clocks
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
CPU processing
Instruction
Instruction
××IF
(××PR = 1)
8 clocks
××IF
(××PR = 0)
7 clocks
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
Figure 15-9. Interrupt Request Acknowledgement Timing (Maximum Time)
25 clocks
6 clocks
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
CPU processing
Instruction
Divide instruction
××IF
(××PR = 1)
33 clocks
××IF
(××PR = 0)
32 clocks
Remark 1 clock: 1/fCPU (fCPU: CPU clock)
15.4.2 Software interrupt request acknowledgement
A software interrupt acknowledge is acknowledged by BRK instruction execution. Software interrupts cannot be
disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH,
003FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RETB instruction.
Caution Do not use the RETI instruction for restoring from the software interrupt.
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15.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected
(IE = 1). Also, when an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE
= 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable interrupt acknowledgement.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is used for multiple interrupt servicing.
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged
for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled
state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the
pending interrupt request is acknowledged following execution of at least one main processing instruction execution.
Table 15-5 shows interrupt requests enabled for multiple interrupt servicing and Figure 15-10 shows multiple
interrupt servicing examples.
Table 15-5. Interrupt Request Enabled for Multiple Interrupt Servicing During Interrupt Servicing
Multiple Interrupt Request
Maskable Interrupt Request
PR = 0 PR = 1
Interrupt Being Serviced
IE = 1
IE = 0
IE = 1
IE = 0
Maskable interrupt
ISP = 0
ISP = 1
×
×
×
×
×
×
×
Software interrupt
Remarks 1. : Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP and IE are flags contained in the PSW.
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower
priority is being serviced.
IE = 0: Interrupt request acknowledgement is disabled.
IE = 1: Interrupt request acknowledgement is enabled.
4. PR is a flag contained in PR0L, PR0H, and PR1L.
PR = 0: Higher priority level
PR = 1: Lower priority level
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Figure 15-10. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing
INTxx servicing
INTyy servicing
INTzz servicing
IE = 0
IE = 0
IE = 0
EI
EI
EI
INTxx
(PR = 1)
INTyy
(PR = 0)
INTzz
(PR = 0)
RETI
IE = 1
RETI
RETI
IE = 1
IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple
interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be
issued to enable interrupt request acknowledgement.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing
INTxx servicing
INTyy servicing
EI
IE = 0
INTyy
EI
INTxx
(PR = 0)
(PR = 1)
RETI
IE = 1
1 instruction execution
IE = 0
RETI
IE = 1
Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower
than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending,
and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
PR = 1: Lower priority level
IE = 0: Interrupt request acknowledgement disabled
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Figure 15-10. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled
Main processing
INTxx servicing INTyy servicing
IE = 0
EI
INTyy
(PR = 0)
INTxx
RETI
(PR = 0)
IE = 1
IE = 0
1 instruction execution
RETI
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt
request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request
is held pending, and is acknowledged following execution of one main processing instruction.
PR = 0: Higher priority level
IE = 0: Interrupt request acknowledgement disabled
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CHAPTER 15 INTERRUPT FUNCTIONS
15.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued for them while another instruction is being
executed, request acknowledgement is held pending until the end of execution of the next instruction. These
instructions (interrupt request hold instructions) are listed below.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MOV PSW, #byte
MOV A, PSW
MOV PSW, A
MOV1 PSW. bit, CY
MOV1 CY, PSW. bit
AND1 CY, PSW. bit
OR1 CY, PSW. bit
XOR1 CY, PSW. bit
SET1 PSW. bit
CLR1 PSW. bit
RETB
RETI
PUSH PSW
POP PSW
BT PSW. bit, $addr16
BF PSW. bit, $addr16
BTCLR PSW. bit, $addr16
EI
DI
Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registers.
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,
the software interrupt activated by executing the BRK instruction causes the IE flag to be
cleared. Therefore, even if a maskable interrupt request is generated during execution of the
BRK instruction, the interrupt request is not acknowledged.
Figure 15-11 shows the timing at which interrupt requests are held pending.
Figure 15-11. Interrupt Request Hold
PSW and PC saved, jump Interrupt servicing
CPU processing
Instruction N
Instruction M
to interrupt servicing
program
××IF
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (instruction request).
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CHAPTER 16 KEY INTERRUPT FUNCTION
16.1 Functions of Key Interrupt
A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a rising
edge to the key interrupt input pins (KR0 to KR3).
Table 16-1. Assignment of Key Interrupt Detection Pins
Flag
Description
KRM0
KRM1
KRM2
KRM3
Controls KR0 signal in 1-bit units.
Controls KR1 signal in 1-bit units.
Controls KR2 signal in 1-bit units.
Controls KR3 signal in 1-bit units.
16.2 Configuration of Key Interrupt
The key interrupt consists of the following hardware.
Table 16-2. Configuration of Key Interrupt
Item
Configuration
Control register
Key return mode register (KRM)
Figure 16-1. Block Diagram of Key Interrupt
KR3
KR2
KR1
KR0
INTKR
0
0
0
0
KRM3 KRM2 KRM1 KRM0
Key return mode register (KRM)
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16.3 Register Controlling Key Interrupt
(1) Key return mode register (KRM)
This register controls the KRM0 to KRM3 bits using the KR0 to KR3 signals, respectively.
This register is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 16-2. Format of Key Return Mode Register (KRM)
Address: FF6EH After reset: 00H R/W
Symbol
KRM
7
0
6
0
5
0
4
0
3
2
0
KRM3
KRM2
KRM1
KRM0
KRMn
Key interrupt mode control
0
1
Does not detect key interrupt signal
Detects key interrupt signal
Cautions 1. If any of the KRM0 to KRM3 bits used is set to 1, set bits 0 to 3 (PU70 to PU73) of the
corresponding pull-up resistor register 7 (PU7) to 1.
2. If KRM is changed, the interrupt request flag may be set. Therefore, disable interrupts and
then change the KRM register. Clear the interrupt request flag and enable interrupts.
3. The bits not used in the key interrupt mode can be used as normal ports.
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CHAPTER 17 STANDBY FUNCTION
17.1 Standby Function and Configuration
17.1.1 Standby function
Table 17-1. Relationship Between HALT Mode, STOP Mode, and Clock
X1 Input Clock
Oscillation continues
Oscillation stopped
Ring-OSC Clock
Oscillation continues
Oscillation continues
Subsystem Clock
Oscillation continues
Oscillation continues
CPU Clock
Operation stopped
Operation stopped
HALT mode
STOP mode
The standby function is designed to reduce the power consumption of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped, but the
system clock oscillator continues oscillating. In this mode, power consumption is not decreased as much as in
the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request
generation and carrying out intermittent operations.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the X1 input clock oscillator stops,
stopping the whole system, thereby considerably reducing the CPU power consumption.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is
released, select the HALT mode if it is necessary to start processing immediately upon interrupt request
generation.
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. STOP mode can be used only when operating on the X1 input clock or Ring-OSC clock.
HALT mode can be used when operating on the X1 input clock, Ring-OSC clock, or
subsystem clock. However, when the STOP instruction is executed during Ring-OSC clock
operation, the X1 oscillator stops, but Ring-OSC oscillator does not stop.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing STOP instruction.
3. The following sequence is recommended for power consumption reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) of the A/D converter
mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or
STOP instruction.
4. Ring-OSC clock oscillation cannot be stopped in the STOP mode. However, when the Ring-
OSC clock is used as the CPU clock, the CPU operation is stopped for 17/fR (s) after STOP
mode is released.
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Figure 17-1. Operation Timing When STOP Mode Is Released
STOP mode release
STOP mode
X1 input clock
Ring-OSC clock
X1 input clock is
selected as CPU clock
when STOP instruction
is executed
HALT status
(oscillation stabilization time set by OSTS)
X1 input clock
X1 input clock
Ring-OSC clock is
selected as CPU clock
when STOP instruction
is executed
Ring-OSC clock
Operation stopped
Clock switched
by software
(17/f )
R
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17.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
•
•
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
(1) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
RESET input, STOP instruction, MSTOP = 1, and MCC = 1 clear OSTC to 00H.
Figure 17-2. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H
R
Symbol
OSTC
7
0
6
0
5
0
4
3
2
1
0
MOST11
MOST13
MOST14
MOST15
MOST16
MOST11
MOST13
MOST14
MOST15
MOST16
Oscillation stabilization time status
211/fX min. (204.8 µs min.)
213/fX min. (819.2 µs min.)
214/fX min. (1.64 ms min.)
215/fX min. (3.27 ms min.)
216/fX min. (6.55 ms min.)
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
Caution After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
Remarks 1. Values in parentheses are for operation with fX = 10 MHz.
2. fX: X1 input clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait
time set by OSTS is valid only after STOP mode is released when the X1 input clock is selected as the CPU
clock. After STOP mode is released when the Ring-OSC clock is selected, check the oscillation stabilization time
using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
RESET input sets OSTS to 05H.
Figure 17-3. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFA4H After reset: 05H R/W
Symbol
OSTS
7
0
6
0
5
0
4
0
3
0
2
1
0
OSTS2
OSTS1
OSTS0
OSTS2
OSTS1
OSTS0
Oscillation stabilization time selection
0
0
0
1
1
0
1
0
1
0
1
211/fX (204.8 µs)
213/fX (819.2 µs)
214/fX (1.64 ms)
215/fX (3.27 ms)
216/fX (6.55 ms)
Setting prohibited
1
1
0
0
Other than above
Cautions 1. If the STOP mode is entered and then released while the Ring-OSC is being
used as the CPU clock, set the oscillation stabilization time as follows.
•
Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts only during the oscillation
stabilization time set by OSTS. Therefore, note that only the statuses during the
oscillation stabilization time set by OSTS are set to OSTC after STOP mode has
been released.
2. The wait time when STOP mode is released does not include the time after
STOP mode release until clock oscillation starts (“a” below) regardless of
whether STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
a
VSS
Remarks 1. Values in parentheses are for operation with fX = 10 MHz.
2. fX: X1 input clock oscillation frequency
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17.2 Standby Function Operation
17.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the X1 input clock, Ring-OSC clock, or subsystem clock.
The operating statuses in the HALT mode are shown below.
Table 17-2. Operating Statuses in HALT Mode (1/2)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is
Operating on X1 Input Clock
When HALT Instruction Is Executed While CPU Is
Operating on Ring-OSC Clock
When Ring-OSC
When Ring-OSC
Oscillation StoppedNote 1
When X1 Input Clock
Oscillation Continues
When X1 Input Clock
Oscillation Stopped
Oscillation Continues
When
When
When
When
When
When
When
When
Subsystem Subsystem Subsystem Subsystem Subsystem Subsystem Subsystem Subsystem
Clock Used
Clock Not
Used
Clock Used
Clock Not
Used
Clock Used
Clock Not
Used
Clock Used
Clock Not
Used
Item
System clock
The X1 oscillator, Ring-OSC oscillator, and subsystem clock oscillator are able to oscillate. Clock supply to the
CPU is stopped.
CPU
Operation stopped
Port (latch)
Status before HALT mode was set is retained
16-bit timer/event counter 00
8-bit timer/event counter 50
8-bit timer/event counter 51
8-bit timer H0
Operable
Operable
Operable
Operable
Operation stopped
Operable only when TI50 is selected as the count clock
Operable only when TI51 is selected as the count clock
Operable only when TO50 is selected as the count
clock during 8-bit timer/event counter 50 operation
8-bit timer H1
Watch timer
Operable
Operable
Operable
Operable only when f
/27 is selected as the count clock
R
OperableNote 2 Operable
OperableNote 2 OperableNote 3 Not operable OperableNote 3 Not operable
Watchdog
timer
Ring-OSC cannot
be stoppedNote 4
− Operable
Ring-OSC can be
stoppedNote 4
Operation stopped
A/D converter
Operable
Operable
Operable
Operable
Not operable
Serial
UART0
UART6
CSI10
Operable only when TO50 is selected as the serial
clock during TM50 operation
interface
Operable only when external SCK10 is selected as the
serial clock
Clock monitor
Operable
Operable
Operable
Operable
Operation stopped
Operable
Operation stopped
Power-on-clear functionNote 5
Low-voltage detection function
External interrupt
Notes 1. When “Stopped by software” is selected for Ring-OSC by a mask option and Ring-OSC is stopped by
software (for mask options, see CHAPTER 22 MASK OPTIONS).
2. Operable when the X1 input clock is selected.
3. Operable when the subsystem clock is selected.
4. “Ring-OSC cannot be stopped” or “Ring-OSC can be stopped by software” can be selected by a mask
option.
5. When “POC used” is selected by a mask option.
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Table 17-2. Operating Statuses in HALT Mode (2/2)
HALT Mode Setting
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock
When X1 Input Clock Oscillation Continues
When X1 Input Clock Oscillation Stopped
When Ring-OSC
When Ring-OSC
Oscillation StoppedNote 1
When Ring-OSC
When Ring-OSC
Oscillation StoppedNote 1
Item
Oscillation Continues
Oscillation Continues
System clock
The X1 oscillator, Ring-OSC oscillator, and subsystem clock oscillator are able to oscillate. Clock supply to the
CPU is stopped.
CPU
Operation stopped
Port (latch)
Status before HALT mode was set is retained
16-bit timer/event counter 00
8-bit timer/event counter 50
8-bit timer/event counter 51
8-bit timer H0
Operable
Operable
Operable
Operable
Operation stopped
Operable only when TI50 is selected as the count clock
Operable only when TI51 is selected as the count clock
Operable only when TO50 is selected as the count
clock during 8-bit timer/event counter 50 operation
8-bit timer H1
Operable
Operable only when the
X1 input clock is selected
as the count clock
Operable only when f
R
/27
Operation stopped
is selected as the count
clock
Watch timer
Operable
Operable
Operable only when subsystem clock is selected
Ring-OSC cannot
be stoppedNote 2
−
Operable
−
Watchdog
timer
Ring-OSC can be
stoppedNote 2
Operation stopped
A/D converter
Operable
Operable
Operable
Operable
Not operable
Serial
UART0
UART6
CSI10
Operable only when TO50 is selected as the serial
clock during TM50 operation
interface
Operable only when external clock is selected as the
serial clock
Clock monitor
Operable
Operable
Operable
Operable
Operation stopped
Power-on-clear functionNote 3
Low-voltage detection function
External interrupt
Notes 1. When “Stopped by software” is selected for Ring-OSC by a mask option and Ring-OSC is stopped by
software (for mask options, see CHAPTER 22 MASK OPTIONS).
2. “Ring-OSC cannot be stopped” or “Ring-OSC can be stopped by software” can be selected by a mask
option.
3. When “POC used” is selected by a mask option.
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt
acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is
disabled, the next address instruction is executed.
Figure 17-4. HALT Mode Release by Interrupt Request Generation
Interrupt
request
HALT
instruction
Wait
Wait
Standby
release signal
Operating mode
HALT mode
Operating mode
CPU clock
Oscillation
X1 input clock,
Ring-OSC clock,
or subsystem clock
Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby
mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 8 or 9 clocks
• When vectored interrupt servicing is not carried out: 2 or 3 clocks
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(b) Release by RESET input
When the RESET signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 17-5. HALT Mode Release by RESET Input
(1) When X1 input clock is used as CPU clock
HALT
instruction
RESET signal
Operation
stopped
Reset
period
CPU clock
Operating mode
(X1 input clock)
HALT mode
Oscillates
Operating mode
(Ring-OSC clock)
(17/f )
R
Oscillation
stopped
Oscillates
X1 input clock
Oscillation stabilization time
(211/f to 216/f
X
X
)
(2) When Ring-OSC clock or subsystem clock is used as CPU clock
HALT
instruction
RESET signal
Reset Operation
Operating mode
CPU clock
HALT mode
Oscillates
Operating mode
(Ring-OSC clock)
period
stopped
Ring-OSC clock
or
(17/f )
R
Ring-OSC clock
or
subsystem clock
Oscillation
stopped
Oscillates
subsystem clock
Remarks 1. fX: X1 input clock oscillation frequency
2. fR: Ring-OSC clock oscillation frequency
Table 17-3. Operation After HALT Mode Release
Release Source
MK××
PR××
IE
0
ISP
Operation
Next address
Maskable interrupt
request
0
0
×
instruction execution
0
0
1
×
Interrupt servicing
execution
0
0
0
1
1
1
0
×
1
1
0
1
Next address
instruction execution
Interrupt servicing
execution
1
×
−
×
×
×
×
HALT mode held
Reset processing
RESET input
−
×: Don’t care
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17.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the X1 input clock or Ring-OSC clock.
Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is
immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after
execution of the STOP instruction and the system returns to the operating mode as soon as the
wait time set using the oscillation stabilization time select register (OSTS) has elapsed.
The operating statuses in the STOP mode are shown below.
Table 17-4. Operating Statuses in STOP Mode
STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on X1 Input Clock When STOP Instruction Is Executed
While CPU Is Operating on Ring-
When Ring-OSC Oscillation
Continues
When Ring-OSC Oscillation
StoppedNote 1
OSC Clock
When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem When Subsystem
Clock Used Clock Not Used Clock Used Clock Not Used Clock Used Clock Not Used
Item
System clock
Only X1 oscillator oscillation is stopped. Clock supply to the CPU is stopped.
Operation stopped
CPU
Port (latch)
Status before STOP mode was set is retained
Operation stopped
16-bit timer/event counter 00
8-bit timer/event counter 50
8-bit timer/event counter 51
8-bit timer H0
Operable only when TI50 is selected as the count clock
Operable only when TI51 is selected as the count clock
Operable only when TO50 is selected as the count clock during 8-bit timer/event counter 50 operation
8-bit timer H1
OperableNote 2
OperableNote 3
Operable
Operation stopped
Operation stopped OperableNote 3
OperableNote 2
Operation stopped OperableNote 3
− Operable
Watch timer
Operation stopped
Watchdog Ring-OSC cannot
timer
be stoppedNote 4
Ring-OSC can be
stoppedNote 4
Operation stopped
A/D converter
Operation stopped
Serial interface
UART0
UART6
CSI10
Operable only when TO50 is selected as the serial clock during TM50 operation
Operable only when external SCK10 is selected as the serial clock
Clock monitor
Operation stopped
Operable
Power-on-clear functionNote 5
Low-voltage detection function
External interrupt
Operable
Operable
Notes 1. When “Stopped by software” is selected for Ring-OSC by a mask option and Ring-OSC is stopped by
software (for mask options, see CHAPTER 22 MASK OPTIONS).
2. Operation continues only when fR/27 is selected as the count clock.
3. Operable when the subsystem clock is selected.
4. “Ring-OSC cannot be stopped” or “Ring-OSC can be stopped by software” can be selected by a mask
option.
5. When “POC used” is selected by a mask option.
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(2) STOP mode release
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation
stabilization time has elapsed, if interrupt acknowledgement is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Figure 17-6. STOP Mode Release by Interrupt Request Generation
(1) When X1 input clock is used as CPU clock
Wait
(set by OSTS)
STOP
instruction
Standby release signal
Oscillation stabilization
CPU clock
Operating mode
(X1 input clock)
Operating mode
wait status
STOP mode
(X1 input clock)
Oscillates
Oscillates
Oscillation stopped
X1 input clock
Oscillation stabilization time (set by OSTS)
(2) When Ring-OSC clock is used as CPU clock
STOP
instruction
Standby release signal
Operation
Operating mode
Operating mode
(Ring-OSC clock)
stopped
STOP mode
CPU clock
(Ring-OSC clock)
(17/ f )
R
Oscillates
Ring-OSC clock
Remark The broken lines indicate the case when the interrupt request that has released the standby mode
is acknowledged.
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(b) Release by RESET input
When the RESET signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 17-7. STOP Mode Release by RESET Input
(1) When X1 input clock is used as CPU clock
STOP
instruction
RESET signal
Reset
period
Operation
stopped
CPU clock
Operating mode
(X1 input clock)
Oscillates
STOP mode
Operating mode
(Ring-OSC clock)
(17/f
R
)
Oscillation
stopped
Oscillation stopped
Oscillates
X1 input clock
Oscillation stabilization time (211/
f
X
to 216/f
)
X
(2) When Ring-OSC clock is used as CPU clock
STOP
instruction
RESET signal
Reset
period
Operation
stopped
CPU clock
Operating mode
(Ring-OSC clock)
STOP mode
Oscillates
Operating mode
(Ring-OSC clock)
(17/f )
R
Oscillation
stopped
Oscillates
Ring-OSC clock
Table 17-5. Operation After STOP Mode Release
Release Source
MK××
PR××
IE
0
ISP
Operation
Next address
Maskable interrupt
request
0
0
×
instruction execution
0
0
1
×
Interrupt servicing
execution
0
0
0
1
1
1
0
×
1
1
0
1
Next address
instruction execution
Interrupt servicing
execution
1
×
−
×
×
×
×
STOP mode held
Reset processing
RESET input
−
×: Don’t care
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CHAPTER 18 RESET FUNCTION
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by clock monitor X1 clock oscillation stop detection
(4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets have no functional differences. In both cases, program execution starts at the address
at 0000H and 0001H when the reset signal is input.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, X1 clock oscillation
stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each item of hardware is set to
the status shown in Table 18-1. Each pin is high impedance during reset input or during the oscillation stabilization
time just after reset release, except for P130, which is low-level output.
When a high level is input to the RESET pin, the reset is released and program execution starts using the Ring-
OSC clock after the CPU clock operation has stopped for 17/fR (s). A reset generated by the watchdog timer and
clock monitor sources is automatically released after the reset, and program execution starts using the Ring-OSC
clock after the CPU clock operation has stopped for 17/fR (s) (see Figures 18-2 to 18-4). Reset by POC and LVI
circuit power supply detection is automatically released when VDD > VPOC or VDD > VLVI after the reset, and program
execution starts using the Ring-OSC clock after the CPU clock operation has stopped for 17/fR (s) (see CHAPTER 20
POWER-ON-CLEAR CIRCUIT and CHAPTER 21 LOW-VOLTAGE DETECTOR).
Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.
2. During reset input, the X1 input clock and Ring-OSC clock stop oscillating.
3. When the STOP mode is released by a reset, the STOP mode contents are held during reset
input. However, the port pins become high-impedance, except for P130, which is set to low-
level output.
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Figure 18-1. Block Diagram of Reset Function
Internal bus
Reset control flag register (RESF)
WDTRF
Set
CLMRF
Set
LVIRF
Set
WDTRES
(Watchdog timer reset signal)
Clear
Clear
Clear
CLMRESB
(Clock monitor reset signal)
Reset signal
RESET
Reset signal to LVIM/LVIS register
Reset signal
POCRESB
(Power-on-clear circuit reset signal)
LVIRESB
(Low-voltage detector reset signal)
Caution An LVI circuit internal reset does not reset the LVI circuit.
Remarks 1. LVIM: Low-voltage detection register
2. LVIS: Low-voltage detection level selection register
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Figure 18-2. Timing of Reset by RESET Input
X1
Normal operation
(Reset processing,
Ring-OSC clock)
Operation stop
(17/f
Reset period
(Oscillation stop)
CPU clock
RESET
Normal operation
R
)
Internal
reset signal
Delay
Delay
Hi-ZNote
Port pin
Figure 18-3. Timing of Reset Due to Watchdog Timer Overflow
X1
Normal operation
(Reset processing,
Ring-OSC clock)
Operation stop
(17/f
Reset period
(Oscillation stop)
Normal operation
CPU clock
R
)
Watchdog
timer
overflow
Internal
reset signal
Hi-ZNote
Port pin
Caution A watchdog timer internal reset resets the watchdog timer.
Figure 18-4. Timing of Reset in STOP Mode by RESET Input
X1
STOP instruction execution
Normal operation
(Reset processing,
Ring-OSC clock)
Operation stop
(17/f
Stop status
(Oscillation stop)
Reset period
(Oscillation stop)
CPU clock Normal operation
RESET
R
)
Internal
reset signal
Delay
Delay
Hi-ZNote
Port pin
Note The port pins become high impedance, except for P130, which is set to low-level output.
Remark For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 20 POWER-
ON-CLEAR CIRCUIT and CHAPTER 21 LOW-VOLTAGE DETECTOR.
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Table 18-1. Hardware Statuses After Reset (1/2)
Hardware
Status After Reset
Program counter (PC)Note 1
The contents of the
reset vector table
(0000H, 0001H) are
set.
Stack pointer (SP)
Undefined
02H
Program status word (PSW)
RAM
Data memory
General-purpose registers
UndefinedNote 2
UndefinedNote 2
00H
Ports (P0 to P3, P6, P7, P12, P13) (output latches)
Port mode registers (PM0, PM1, PM3, PM6, PM7, PM12)
Pull-up resistor option registers (PU0, PU1, PU3 to PU7, PU12)
Input switch control register (ISC)
FFH
00H
00H
Internal memory size switching register (IMS)
Processor clock control register (PCC)
CFH
00H
Ring-OSC mode register (RCM)
00H
Main clock mode register (MCM)
00H
Main OSC control register (MOC)
00H
Oscillation stabilization time select register (OSTS)
Oscillation stabilization time counter status register (OSTC)
05H
00H
16-bit timer/event
counter 00
Timer counter 00 (TM00)
0000H
0000H
00H
Capture/compare registers 000, 010 (CR000, CR010)
Mode control register 00 (TMC00)
Prescaler mode register 00 (PRM00)
Capture/compare control register 00 (CRC00)
Timer output control register 00 (TOC00)
Timer counters 50, 51 (TM50, TM51)
Compare registers 50, 51 (CR50, CR51)
Timer clock selection registers 50, 51 (TCL50, TCL51)
Mode control registers 50, 51 (TMC50, TMC51)
Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11)
Mode registers (TMHMD0, TMHMD1)
Carrier control register 1 (TMCYC1)Note 3
Operation mode register (WTM)
00H
00H
00H
8-bit timer/event
counters 50, 51
00H
00H
00H
00H
8-bit timers H0, H1
00H
00H
00H
Watch timer
00H
Watchdog timer
Mode register (WDTM)
67H
Enable register (WDTE)
9AH
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses
become undefined. All other hardware statuses remain unchanged after reset.
2. When a reset is executed in the standby mode, the pre-reset status is held even after reset.
3. 8-bit timer H1 only.
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Table 18-1. Hardware Statuses After Reset (2/2)
Hardware
Status After Reset
Undefined
00H
A/D converter
Conversion result register (ADCR)
Mode register (ADM)
Analog input channel specification register (ADS)
Power-fail comparison mode register (PFM)
Power-fail comparison threshold register (PFT)
Receive buffer register 0 (RXB0)
00H
00H
00H
Serial interface UART0
Serial interface UART6
FFH
Transmit shift register 0 (TXS0)
FFH
Asynchronous serial interface operation mode register 0 (ASIM0)
Baud rate generator control register 0 (BRGC0)
Receive buffer register 6 (RXB6)
01H
1FH
FFH
Transmit buffer register 6 (TXB6)
FFH
Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
01H
00H
00H
00H
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
Transmit buffer register 10 (SOTB10)
FFH
16H
Serial interface CSI10
Undefined
00H
Serial I/O shift register 10 (SIO10)
Serial operation mode register 10 (CSIM10)
Serial clock selection register 10 (CSIC10)
Key return mode register (KRM)
00H
00H
Key interrupt
00H
Clock monitor
Mode register (CLM)
00H
Reset function
Low-voltage detector
Reset control flag register (RESF)
00HNote
00HNote
00HNote
00H
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L)
Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L)
Priority specification flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
Interrupt
FFH
FFH
00H
00H
Note These values vary depending on the reset source.
Reset Source
RESET Input
Reset by POC
Cleared (00H)
Reset by WDT
Cleared (00H)
Reset by CLM
Cleared (00H)
Reset by LVI
Register
RESF
LVIM
See Table 18-2.
Cleared (00H)
Held
LVIS
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18.1 Register for Confirming Reset Source
Many internal reset generation sources exist in the 78K0/KC1 Series. The reset control flag register (RESF) is
used to store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Figure 18-5. Format of Reset Control Flag Register (RESF)
Address: FFACH After reset: 00HNote
R
Symbol
RESF
7
0
6
0
5
0
4
3
0
2
0
1
0
WDTRF
CLMRF
LVIRF
WDTRF
Internal reset request by watchdog timer (WDT)
0
1
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
CLMRF
Internal reset request by clock monitor (CLM)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
0
1
LVIRF
Internal reset request by low-voltage detector (LVI)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
0
1
Note The value after reset varies depending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 18-2.
Table 18-2. RESF Status When Reset Request Is Generated
Reset Source
RESET input
Reset by POC
Reset by WDT
Reset by CLM
Reset by LVI
Flag
WDTRF
CLMRF
LVIRF
Cleared (0)
Cleared (0)
Set (1)
Held
Held
Held
Set (1)
Held
Held
Held
Set (1)
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CHAPTER 19 CLOCK MONITOR
19.1 Functions of Clock Monitor
The clock monitor samples the X1 input clock using the on-chip Ring-OSC, and generates an internal reset signal
when the X1 input clock is stopped.
When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set
to 1. For details of RESF, refer to CHAPTER 18 RESET FUNCTION.
The clock monitor automatically stops under the following conditions.
•
•
•
•
In STOP mode and during the oscillation stabilization time
When the X1 input clock is stopped by software (when MSTOP = 1 or MCC = 1)
During the oscillation stabilization time after reset is released
When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
19.2 Configuration of Clock Monitor
Clock monitor consists of the following hardware.
Table 19-1. Configuration of Clock Monitor
Configuration
Item
Control register
Clock monitor mode register (CLM)
Figure 19-1. Block Diagram of Clock Monitor
X1 input clock
Internal reset signal
Ring-OSC clock
Enable/disable
CLME
Clock monitor mode register (CLM)
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19.3 Registers Controlling Clock Monitor
Clock monitor is controlled by the clock monitor mode register (CLM).
(1) Clock monitor mode register (CLM)
This register sets the operation mode of the clock monitor.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 19-2. Format of Clock Monitor Mode Register (CLM)
Address: FFA9H After reset: 00H R/W
Symbol
CLM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
CLME
Enables/disables clock monitor operation
CLME
0
1
Disables clock monitor operation
Enables clock monitor operation
Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal
reset signal.
2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF)
of the reset control flag register (RESF) is set to 1. CLMRF is read by software and then
automatically cleared to 0. CLMRF is cleared under the following conditions.
•
•
•
RESET input
Internal reset signal generation by POC
After read by software
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19.4 Operation of Clock Monitor
This section explains the functions of the clock monitor. The start and stop conditions are as follows.
<Start condition>
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to operation enabled (1).
<Stop condition>
•
•
•
•
In STOP mode and during the oscillation stabilization time
When the X1 input clock is stopped by software (when MSTOP = 1 or MCC = 1)
During the oscillation stabilization time after reset is released
When the Ring-OSC clock is stopped
Remark MSTOP: Bit 7 of the main OSC control register (MOC)
Table 19-2. Operation Status of Clock Monitor (When CLME = 1)
CPU Operation Clock Operation Mode
X1 Input Clock Status
Stopped
Ring-OSC Clock Status
Oscillating
Clock Monitor Status
Stopped
X1 input clock
STOP mode
RESET input
HALT mode
StoppedNote
Oscillating
StoppedNote
Oscillating
Stopped
Oscillating
Operating
Stopped
Stopped
StoppedNote
Ring-OSC clock
STOP mode
RESET input
HALT mode
Oscillating
Oscillating
Stopped
Operating
Stopped
Note The Ring-OSC clock is stopped only when the “Ring-OSC can be stopped by software” is selected by a
mask option. If “Ring-OSC cannot be stopped” is selected, the Ring-OSC clock cannot be stopped.
The clock monitor timing is as shown in Figure 19-3.
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Figure 19-3. Timing of Clock Monitor (1/3)
(1) When internal reset is executed by oscillation stop of X1 input clock
4 clocks of Ring-OSC clock
X1 input clock
Ring-OSC clock
Internal reset signal
CLME
CLMRFNote
Note CLMRF is read by software and then automatically cleared to 0. CLMRF is cleared under the following
conditions.
• RESET input
• Internal reset signal generation by POC
• After read by software
(2) Clock monitor status after STOP mode is released
(CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode)
Normal
operation
Normal operation
Oscillation stabilization time
CPU operation
X1 input clock
STOP
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
Ring-OSC clock
CLME
Clock monitor status
Monitoring
Monitoring stopped
Monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
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Figure 19-3. Timing of Clock Monitor (2/3)
(3) Clock monitor status after STOP mode is released
(CLME = 1 is set when CPU clock operates on Ring-OSC clock and before entering STOP mode)
Clock supply
stopped
Normal
operation
Normal operation (Ring-OSC clock)
STOP
CPU operation
X1 input clock
Oscillation
stopped
Oscillation stabilization time
(set by OSTS register)
Ring-OSC clock
17 clocks
CLME
Clock monitor status
Monitoring
Monitoring
stopped
Monitoring stopped
Monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
(4) Clock monitor status after RESET input
(CLME = 1 is set after RESET input and during X1 input clock oscillation stabilization time)
Clock supply
stopped
Normal
operation
Normal operation (Ring-OSC clock)
CPU operation
X1 input clock
Reset
Oscillation
stopped
Oscillation stabilization time
Ring-OSC clock
RESET
Oscillation
stopped
17 clocks
Set to 1 by software
CLME
Clock monitor status
Monitoring
Monitoring stopped
Monitoring
Waiting for end
of oscillation
stabilization time
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
operation. Even if CLME is set to 1 by software during the oscillation stabilization time of the X1 input clock,
monitoring is not performed until the oscillation stabilization time of the X1 input clock ends. Monitoring is
automatically started at the end of the oscillation stabilization time.
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Figure 19-3. Timing of Clock Monitor (3/3)
(5) Clock monitor status after RESET input
(CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time)
Normal
operation
Clock supply
stopped
CPU operation
X1 input clock
Normal operation (Ring-OSC clock)
Reset
Oscillation stabilization time
Ring-OSC clock
RESET
17 clocks
Set to 1 by software
CLME
Clock monitor status
Monitoring
Monitoring stopped
Monitoring
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
operation. When CLME is set to 1 by software at the end of the oscillation stabilization time of the X1 input clock,
monitoring is started.
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CHAPTER 20 POWER-ON-CLEAR CIRCUIT
20.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
• Generates internal reset signal at power on.
• Compares supply voltage (VDD) and detection voltage (VPOC), and generates internal reset signal when VDD <
VPOC.
• The following can be selected by a mask option.
• POC disabled
• POC used (detection voltage: VPOC = 2.85 V 0.15 V)
• POC used (detection voltage: VPOC = 3.5 V 0.2 V)
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF) is
cleared to 00H.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), low-voltage-detection (LVI) circuit, or clock monitor.
RESF is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT,
LVI, or the clock monitor.
For details of the RESF, refer to CHAPTER 18 RESET FUNCTION.
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20.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 20-1.
Figure 20-1. Block Diagram of Power-on-Clear Circuit
V
DD
V
DD
+
Internal reset signal
–
Detection
voltage source
(VPOC
)
20.3 Operation of Power-on-Clear Circuit
In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC) are compared, and when VDD <
VPOC, an internal reset signal is generated.
Figure 20-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Supply voltage (VDD
)
POC detection voltage
(VPOC
)
2.7 V
Time
Internal reset signal
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20.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 20-3. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
; The Ring-OSC clock is set as the CPU clock when the reset signal is generated
Reset
Checking cause
of resetNote 2
; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
can be identified by the RESF register.
Power-on-clear
; 8-bit timer H1 can operate with the Ring-OSC clock.
Start timer
(set to 50 ms)
Source: f
R
(240 kHz)/27 × compare 100 = 53 ms
(fR: Ring-OSC clock oscillation frequency)
Checking stabilization
of oscillation
; Check the stabilization of oscillation of the X1 input clock by using the
OSTC register.
Note 1
; Change the CPU clock from the Ring-OSC clock to the X1 input clock.
Change CPU clock
No
50 ms has passed?
(TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated.
Yes
Initialization
processing
; Initialization of ports
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
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Figure 20-3. Example of Software Processing After Release of Reset (2/2)
• Checking cause of reset
Check cause of reset
Yes
Yes
Yes
WDTRF of RESF
register = 1?
No
Reset processing by
watchdog timer
CLMRF of RESF
register = 1?
No
Reset processing by
clock monitor
LVIRF of RESF
register = 1?
No
Reset processing by
low-voltage detector
Power-on-clear/external
reset generated
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CHAPTER 21 LOW-VOLTAGE DETECTOR
21.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has following functions.
•
Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or
internal reset signal when VDD < VLVI.
•
•
•
Detection levels (seven levels) of supply voltage can be changed by software.
Interrupt or reset function can be selected by software.
Operable in STOP mode.
When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, refer to CHAPTER 18 RESET FUNCTION.
21.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown below.
Figure 21-1. Block Diagram of Low-Voltage Detector
V
DD
V
DD
N-ch
Internal reset signal
+
–
INTLVI
Detection
voltage source
(VLVI
)
3
LVIF
LVIMD
LVIS1 LVIS0
LVION LVIE
LVIS2
Low-voltage detection level
selection register (LVIS)
Low-voltage detection register
(LVIM)
Internal bus
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21.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
•
•
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
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(1) Low-voltage detection register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears LVIM to 00H.
Figure 21-2. Format of Low-Voltage Detection Register (LVIM)
Address: FFBEH After reset: 00H R/WNote 1
7
6
0
5
0
4
3
0
2
0
1
0
Symbol
LVIM
LVION
LVIE
LVIMD
LVIF
LVIONNotes 2, 3
Enables low-voltage detection operation
Specifies reference voltage generator
0
1
Disables operation
Enables operation
LVIENotes 2, 4, 5
0
1
Disables operation
Enables operation
LVIMDNote 2
Low-voltage detection operation mode selection
Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI)
0
1
Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)
LVIFNote 6
Low-voltage detection flag
Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled
Supply voltage (VDD) < detection voltage (VLVI)
0
1
Notes 1. Bit 0 is read-only.
2. LVION, LVIE, and LVIMD are cleared to 0 at a reset other than an LVI reset. These are not
cleared to 0 at an LVI reset.
3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is
confirmed at LVIF.
4. When LVIE is set to 1, a reference voltage generator operation in the LVI circuit is started.
Use software to instigate a wait of at least 2 ms from when LVIE is set to 1 until LVION is set
to 1.
5. If “use POC” is selected by a mask option, leave LVIE as 0. A wait time (2 ms) until LVION is
set to 1 is not necessary.
6. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Caution To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0 first and then
clear LVIE to 0.
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(2) Low-voltage detection level selection register (LVIS)
This register selects the low-voltage detection level.
This register can be set by an 8-bit memory manipulation instruction.
RESET input clears LVIS to 00H.
Figure 21-3. Format of Low-Voltage Detection Level Selection Register (LVIS)
Address: FFBFH After reset: 00H R/W
7
0
6
0
5
0
4
0
3
0
2
1
0
Symbol
LVIS
LVIS2
LVIS1
LVIS0
LVIS2
LVIS1
LVIS0
Detection level
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VLVI0 (4.3 V 0.2 V)
VLVI1 (4.1 V 0.2 V)
VLVI2 (3.9 V 0.2 V)
VLVI3 (3.7 V 0.2 V)
VLVI4 (3.5 V 0.2 V)Note
VLVI5 (3.3 V 0.2 V)Note
VLVI6 (3.1 V 0.15 V)Note
Setting prohibited
Note When the detection voltage of the POC circuit is specified as VPOC = 3.5 V 0.2 V by a mask
option, do not select VLVI4 to VLVI6 as the LVI detection voltage. Even if VLVI4 to VLVI6 are selected,
POC circuit has priority.
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21.4 Operation of Low-Voltage Detector
The low-voltage detector can be used in the following two modes.
•
•
Used as reset
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when
VDD < VLVI.
Used as interrupt
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI)
when VDD < VLVI.
The operation is set as follows.
(1) When used as reset
•
When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator
operation).
<4> Use software to instigate a wait of at least 2 ms.
<5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<6> Use software to instigate a wait of at least 0.2 ms.
<7> Confirm that “supply voltage (VDD) > detection voltage (VLVI)” at bit 0 (LVIF) of LVIM.
<8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection
voltage (VLVI)).
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <5>.
2. If "use POC" is selected by a mask option, procedures <3> and <4> are not required.
3. If supply voltage (VDD) > detection voltage (VLVI) when LVIM is set to 1, an internal reset
signal is not generated.
•
When stopping operation
Either of the following procedures must be executed.
•
When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
•
When using 1-bit memory manipulation instruction:
Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order.
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Figure 21-4. Timing of Low-Voltage Detector Internal Reset Signal Generation
Supply voltage (VDD
)
LVI detection voltage
(VLVI
POC detection voltage
(VPOC
)
)
2.7 V
Time
<2>
LVIMK flag
(set by software)
<1>
LVIE flag
(set by software)
Not cleared
Not cleared
Not cleared
<3>
Clear
Clear
<4> 2 ms or longer
Not cleared
LVION flag
(set by software)
<5>
<6> 0.2 ms or longer
LVIF flag
<7>
Clear
Clear
LVIMD flag
(set by software)
Not cleared
Not cleared
<8>
LVIRF flagNote
LVI reset signal
POC reset signal
Cleared by
software
Cleared by
software
Internal reset signal
Note LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 18 RESET
FUCNTION.
Remark <1> to <8> in Figure 21-4 above correspond to <1> to <8> in the description of "when starting operation"
in 21.4 (1) When used as reset.
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(2) When used as interrupt
When starting operation
•
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection
register (LVIS).
<3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator
operation).
<4> Use software to instigate a wait of at least 2 ms.
<5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<6> Use software to instigate a wait of at least 0.2 ms.
<7> Confirm that “supply voltage (VDD) > detection voltage (VLVI)” at bit 0 (LVIF) of LVIM.
<8> Clear the interrupt request flag of LVI (LVIIF) to 0.
<9> Release the interrupt mask flag of LVI (LVIMK).
<10> Execute the EI instruction (when vector interrupts are used).
Caution If “use POC” is selected by a mask option, procedures <3> and <4> are not required.
•
When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction:
Write 00H to LVIM.
• When using 1-bit memory manipulation instruction:
Clear LVION to 0 first, and then clear LVIE to 0.
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Figure 21-5. Timing of Low-Voltage Detector Interrupt Signal Generation
Supply voltage (VDD)
LVI detection voltage
(VLVI)
POC detection voltage
(VPOC)
2.7 V
Time
<2>
LVIMK flag
(set by software)
<1>
<9> Cleared by software
LVIE flag
(set by software)
<3>
<4> 2 ms or longer
LVION flag
(set by software)
<5>
<6> 0.2 ms or longer
LVIF flag
INTLVI
<7>
LVIIF flag
<8>
Cleared by software
Internal reset signal
Remark <1> to <9> in Figure 21-5 above correspond to <1> to <9> in the description of “when starting operation”
in 21.4 (2) When used as interrupt.
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21.5 Cautions for Low-Voltage Detector
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage
(VLVI), the operation is as follows depending on how the low-voltage detector is used.
(1) When used as reset
The system may be repeatedly reset and released from the reset status.
In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set
by taking action (1) below.
(2) When used as interrupt
Interrupt requests may be frequently generated. Take action (2) below.
In this system, take the following actions.
<Action>
(1) When used as reset
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
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Figure 21-6. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
;
The Ring-OSC clock is set as the CPU clock when the reset signal is generated
Reset
Checking cause
of resetNote 2
;
The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
can be identified by the RESF register.
LVI
;
8-bit timer H1 can operate with the Ring-OSC clock.
Start timer
(set to 50 ms)
Source: f
R
(240 kHz)/27 × compare 100 = 53 ms
(fR: Ring-OSC clock oscillation frequency)
Checking stabilization
of oscillation
;
;
Check the stabilization of oscillation of the X1 input clock by using the
OSTC register.
Note 1
Change the CPU clock from the Ring-OSC clock to the X1 input clock.
Change CPU clock
No
50 ms has passed?
(TMIFH1 = 1?)
;
;
TMIFH1 = 1: Interrupt request is generated.
Yes
Initialization
processing
Initialization of ports
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
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Figure 21-6. Example of Software Processing After Release of Reset (2/2)
• Checking cause of reset
Check cause of reset
Yes
Yes
No
WDTRF of RESF
register = 1?
No
Reset processing by
watchdog timer
CLMRF of RESF
register = 1?
No
Reset processing by
clock monitor
LVIRF of RESF
register = 1?
Yes
Power-on-clear/external
reset generated
Reset processing by
low-voltage detector
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(2) When used as interrupt
Disable interrupts (DI) in the servicing routine of the LVI interrupt, and check to see if “supply voltage (VDD) >
detection voltage (VLVI)”, by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Then enable interrupts
(EI).
In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, disable
interrupts (DI), wait for the supply voltage fluctuation period, check that “supply voltage (VDD) > detection voltage
(VLVI)” with the LVIF flag, and then enable interrupts (EI).
Figure 21-7. Example of Software Processing of LVI Interrupt
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
LVI interrupt
DI
; Disable interrupts.
Start timer
(set to 50 ms)
LVI interrupt servicing
No
50 ms has passed?
(TMIFH1 = 1?)
; TMIFH1 = 1: Interrupt request is generated
Yes
No
LVIF1 of LVIM
register = 0?
; Check that supply voltage (VDD) > detection voltage (VLVI).
Yes
EI
; Enable interrupts.
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CHAPTER 22 MASK OPTIONS
Mask ROM versions are provided with the following mask options.
1. Power-on-clear (POC) circuit
•
•
•
POC cannot be used
POC used (detection voltage: VPOC = 2.85 V 0.15 V)
POC used (detection voltage: VPOC = 3.5 V 0.2 V)
2. Ring-OSC
•
•
Cannot be stopped
Can be stopped by software
3. Pull-up resistor of P60 to P63 pins
•
Pull-up resistor can be incorporated in 1-bit units
(Pull-up resistors are not available for the flash memory versions.)
Flash memory versions that support the mask options of the mask ROM versions are as follows.
Table 22-1. Flash Memory Versions Supporting Mask Options of Mask ROM Versions
Mask Option
Flash Memory Version
POC Circuit
POC cannot be used
Ring-OSC
Cannot be stopped
µPD78F0114M1
Can be stopped by software
Cannot be stopped
µPD78F0114M2
µPD78F0114M3
µPD78F0114M4
µPD78F0114M5
µPD78F0114M6
POC used (VPOC = 2.85 V 0.15 V)
POC used (VPOC = 3.5 V 0.2 V)
Can be stopped by software
Cannot be stopped
Can be stopped by software
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CHAPTER 23 µPD78F0114
The µPD78F0114 is provided as the flash memory version of the 78K0/KC1 Series.
The µPD78F0114 replaces the internal mask ROM of the µPD780114 with flash memory to which a program can
be written, erased, and overwritten while mounted on the board. Table 23-1 lists the differences between the
µPD78F0114 and the mask ROM versions.
Table 23-1. Differences Between µPD78F0114 and Mask ROM Versions
Item
µPD78F0114
Flash memory
Mask ROM Versions
Mask ROM
Internal ROM configuration
Internal ROM capacity
32 KBNote
µPD780111: 8 KB
µPD780112: 16 KB
µPD780113: 24 KB
µPD780114: 32 KB
Internal high-speed RAM capacity
1024 bytesNote
µPD780111: 512 bytes
µPD780112: 512 bytes
µPD780113: 1024 bytes
µPD780114: 1024 bytes
IC pin
None
Available
None
VPP pin
Available
Electrical specifications
Refer to CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES).
Note The same capacity as the mask ROM versions can be specified by means of the internal memory size
switching register (IMS).
Caution There are differences in noise immunity and noise radiation between the flash memory and
mask ROM versions. When pre-producing an application set with the flash memory version
and then mass-producing it with the mask ROM version, be sure to conduct sufficient
evaluations for the commercial samples (not engineering samples) of the mask ROM versions.
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CHAPTER 23 µPD78F0114
23.1 Internal Memory Size Switching Register
The µPD78F0114 allows users to select the internal memory capacity using the internal memory size switching
register (IMS) so that the same memory map as that of the mask ROM versions with a different internal memory
capacity can be achieved.
IMS is set by an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Caution Be sure to set the value of the relevant mask ROM version at initialization.
Figure 23-1. Format of Internal Memory Size Switching Register (IMS)
Address: FFF0H After reset: CFH R/W
Symbol
IMS
7
6
5
4
0
3
2
1
0
RAM2
RAM1
RAM0
ROM3
ROM2
ROM1
ROM0
RAM2
RAM1
RAM0
Internal high-speed RAM capacity selection
0
1
1
0
0
512 bytes
1
1024 bytes
Other than above
Setting prohibited
ROM3
ROM2
ROM1
ROM0
Internal ROM capacity selection
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
0
8 KB
16 KB
24 KB
32 KB
Other than above
Setting prohibited
The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 23-2.
Table 23-2. Internal Memory Size Switching Register Settings
Target Mask ROM Versions
µPD780111
IMS Setting
42H
µPD780112
44H
µPD780113
C6H
µPD780114
C8H
Caution When using a mask ROM version, be sure to set the value indicated in Table 23-2 to IMS.
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CHAPTER 23 µPD78F0114
23.2 Flash Memory Programming
On-board writing of flash memory (with device mounted on target system) is supported.
On-board writing is performed after connecting a dedicated flash programmer (Flashpro III (FL-PR3, PG-
FP3)/Flashpro IV (FL-PR4, PG-FP4)) to the host machine and target system.
Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to
Flashpro III/Flashpro IV.
Remarks 1. FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd.
2. USB is supported only by Flashpro IV.
23.2.1 Selection of communication mode
Writing to flash memory is performed using Flashpro III/Flashpro IV and serial communication. Select the
communication mode for writing from Table 23-3. For the selection of the communication mode, a format like the one
shown in Figure 23-2 is used. The communication mode are selected according to the number of VPP pulses shown in
Table 23-3.
Table 23-3. Communication Mode List
Communication Mode
3-wire serial I/O
Number of Channels
1
Pin UsedNote
Number of VPP Pulses
0
SCK10/TxD0/P10
SI10/RxD0/P11
SO10/P12
SCK10/TxD0/P10
SI10/RxD0/P11
SO10/P12
3
HS/P15/TOH0
UART (UART0)
UART (UART6)
1
1
TxD0/SCK10/P10
RxD0/SI10/P11
8
TxD0/SCK10/P10
RxD0/SI10/P11
HS/P15/TOH0
11
TxD6/P13
RxD6/P14
9
Note After shifting to flash memory programming mode, all pins not used for flash memory programming are set
to the same state as after reset. Therefore, since all ports become output high-impedance, pin processing,
such as connecting to VDD or VSS via a resistor is required if the output high-impedance state is not
acknowledged by external devices.
Cautions 1. Be sure to select the number of VPP pulses shown in Table 23-3 for the communication mode.
2. When writing to flash memory using the UART communication mode, set the X1 input clock
oscillation frequency to 3 MHz or higher.
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CHAPTER 23 µPD78F0114
Figure 23-2. Communication Mode Selection Format
VPP pulses
10 V
VDD
VPP
VSS
VDD
RESET
Flash memory write mode
VSS
23.2.2 Flash memory programming function
Flash memory writing is performed via command and data transmit/receive operations using the selected
communication mode. The main functions are listed in Table 23-4.
Table 23-4. Main Functions of Flash Memory Programming
Function
Description
Used to detect write stop and transmission synchronization.
Compares entire memory contents and input data.
Erases the entire memory contents.
Reset
Batch verify
Batch erase
Batch blank check
High-speed write
Checks the erase status of the entire memory.
Performs writing to flash memory according to write start address and number of write data
(bytes).
Continuous write
Status
Performs successive write operations using the data input with high-speed write operation.
Checks the current operation mode and operation end.
Oscillation frequency setting
Delete time setting
Baud rate setting
Silicon signature read
Inputs the resonator oscillation frequency information.
Inputs the memory delete time.
Sets the communication rate when the UART method is used.
Outputs the device name, memory capacity, and device block information.
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CHAPTER 23 µPD78F0114
23.2.3 Connecting Flashpro III/Flashpro IV
The connection between Flashpro III/Flashpro IV and the µPD78F0114 differs depending on the communication
mode (3-wire serial I/O or UART). Figures 23-3 to 23-7 show the connection diagrams of each case.
Figure 23-3. Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode
Flashpro III/Flashpro IV
µ
PD78F0114
VPP
VDD
V
PP
V
DD/EVDD/AVREF
RESET
RESET
SCK
SO
SCK10
SI10
SI
SO10
GND
VSS/EVSS/AVSS
Figure 23-4. Connection of Flashpro III/Flashpro IV in 3-Wire Serial I/O Mode (Using Handshake)
Flashpro III/Flashpro IV
µ
PD78F0114
VPP
VDD
V
PP
V
DD/EVDD/AVREF
RESET
RESET
SCK
SO
SCK10
SI10
SI
SO10
HS
HS (P15)
GND
VSS/EVSS/AVSS
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CHAPTER 23 µPD78F0114
Figure 23-5. Connection of Flashpro III/Flashpro IV in UART (UART0) Mode
Flashpro III/Flashpro IV
µ
PD78F0114
VPP
VDD
RESET
SO
V
V
PP
DD/EVDD/AVREF
RESET
RxD0
TxD0
SI
GND
VSS/EVSS/AVSS
Figure 23-6. Connection of Flashpro III/Flashpro IV in UART (UART0) Mode (Using Handshake)
Flashpro III/Flashpro IV
µ
PD78F0114
VPP
VDD
RESET
SO
V
V
PP
DD/EVDD/AVREF
RESET
RxD0
SI
TxD0
HS
HS (P15)
GND
VSS/EVSS/AVSS
Figure 23-7. Connection of Flashpro III/Flashpro IV in UART (UART6) Mode
Flashpro III/Flashpro IV
PD78F0114
µ
VPP
VDD
RESET
SO
V
V
PP
DD/EVDD/AVREF
RESET
RxD6
TxD6
SI
GND
VSS/EVSS/AVSS
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CHAPTER 23 µPD78F0114
23.2.4 Connection on adapter for flash memory writing
Examples of the recommended connection when using the adapter for flash memory writing are shown below.
Figure 23-8. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode
VDD (2.7 to 5.5 V)
GND
VDD2 (LVDD)
VDD
GND
44 43 42 41 40 39 38
37
36
34
35
1
33
32
31
30
29
28
27
2
3
4
5
6
7
8
µ
PD78F0114
26
25
24
23
9
10
11
13 14 15 16 17 18 19 20 21 22
12
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 23 µPD78F0114
Figure 23-9. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O Mode
(Using Handshake)
VDD (2.7 to 5.5 V)
GND
VDD2 (LVDD)
VDD
GND
44 43 42 41 40 39 38
37
36
34
35
1
33
32
31
30
29
28
27
2
3
4
5
6
7
8
µPD78F0114
26
25
24
23
9
10
11
13 14 15 16 17 18 19 20 21 22
12
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 23 µPD78F0114
Figure 23-10. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode
VDD (2.7 to 5.5 V)
GND
VDD2 (LVDD)
VDD
GND
44 43 42 41 40 39 38
37
36
34
35
1
33
32
31
30
29
28
27
2
3
4
5
6
7
8
µPD78F0114
26
25
24
23
9
10
11
13 14 15 16 17 18 19 20 21 22
12
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 23 µPD78F0114
Figure 23-11. Example of Wiring Adapter for Flash Memory Writing in UART (UART0) Mode
(Using Handshake)
VDD (2.7 to 5.5 V)
GND
VDD2 (LVDD)
VDD
GND
44 43 42 41 40 39 38
37
36
34
35
1
33
32
31
30
29
28
27
2
3
4
5
6
7
8
µPD78F0114
26
25
24
23
9
10
11
13 14 15 16 17 18 19 20 21 22
12
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 23 µPD78F0114
Figure 23-12. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode
VDD (2.7 to 5.5 V)
GND
VDD2 (LVDD)
VDD
GND
44 43 42 41 40 39 38
37
36
34
35
1
33
32
31
30
29
28
27
2
3
4
5
6
7
8
µ
PD78F0114
26
25
24
23
9
10
11
13 14 15 16 17 18 19 20 21 22
12
SI
SO SCK CLKOUT RESET VPP RESERVE/HS
WRITER INTERFACE
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CHAPTER 24 INSTRUCTION SET
This chapter lists each instruction set of the 78K0/KC1 Series in table form. For details of each operation and
operation code, refer to the separate document 78K/0 Series Instruction User’s Manual (U12326E).
24.1 Conventions Used in Operation List
24.1.1 Operand identifiers and specification methods
Operands are written in the “Operand” column of each instruction in accordance with the specification method of
the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
methods, select one of them. Upper case letters and the symbols #, !, $ and [ ] are keywords and must be written as
they are. Each symbol has the following meaning.
•
•
•
•
#: Immediate data specification
!: Absolute address specification
$: Relative address specification
[ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
write the #, !, $, and [ ] symbols.
For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for specification.
Table 24-1. Operand Identifiers and Specification Methods
Identifier
Specification Method
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
rp
sfr
sfrp
Special function register symbolNote
Special function register symbol (16-bit manipulatable register even addresses only)Note
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even address only)
addr16
0000H to FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
0800H to 0FFFH Immediate data or labels
addr11
addr5
0040H to 007FH Immediate data or labels (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn
RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark For special function register symbols, refer to Table 3-5 Special Function Register List.
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CHAPTER 24 INSTRUCTION SET
24.1.2 Description of operation column
A:
A register; 8-bit accumulator
X register
X:
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
PSW: Program status word
CY:
AC:
Z:
Carry flag
Auxiliary carry flag
Zero flag
RBS:
IE:
Register bank select flag
Interrupt request enable flag
NMIS: Non-maskable interrupt servicing flag
( ): Memory contents indicated by address or register contents in parentheses
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
∧:
∨:
Logical product (AND)
Logical sum (OR)
∨:
Exclusive logical sum (exclusive OR)
Inverted data
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
24.1.3 Description of flag operation column
(Blank): Not affected
0:
1:
×:
R:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
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CHAPTER 24 INSTRUCTION SET
24.2 Operation List
Clocks
Bytes
Flag
Instruction
Mnemonic
Group
Operands
r, #byte
Operation
Z AC CY
Note 1 Note 2
8-bit data
transfer
MOV
2
3
3
1
1
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
1
1
1
1
2
2
3
1
1
2
2
2
4
6
−
2
2
4
4
−
−
8
8
−
−
−
4
4
4
4
8
8
6
6
6
6
2
4
−
8
4
4
8
8
8
−
7
7
−
−
5
5
5
5
r ← byte
saddr, #byte
sfr, #byte
A, r
(saddr) ← byte
sfr ← byte
A ← r
Note 3
Note 3
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
9 + n A ← (addr16)
9 + m (addr16) ← A
7
5
5
PSW ← byte
A ← PSW
PSW ← A
×
×
×
×
×
×
PSW, A
A, [DE]
5 + n A ← (DE)
[DE], A
5 + m (DE) ← A
A, [HL]
5 + n A ← (HL)
[HL], A
5 + m (HL) ← A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
9 + n A ← (HL + byte)
9 + m (HL + byte) ← A
7 + n A ← (HL + B)
7 + m (HL + B) ← A
7 + n A ← (HL + C)
7 + m (HL + C) ← A
Note 3
XCH
−
6
6
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ (sfr)
A, !addr16
A, [DE]
10 + n + m A ↔ (addr16)
6 + n + m A ↔ (DE)
A, [HL]
6 + n + m A ↔ (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
10 + n + m A ↔ (HL + byte)
10 + n + m A ↔ (HL + B)
10 + n + m A ↔ (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
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CHAPTER 24 INSTRUCTION SET
Clocks
Bytes
Flag
Instruction
Group
Mnemonic
Operands
rp, #word
Operation
Z AC CY
Note 1 Note 2
16-bit data MOVW
3
4
4
2
2
2
2
1
1
3
3
1
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
6
8
−
6
6
−
−
4
4
−
10
10
8
rp ← word
transfer
saddrp, #word
sfrp, #word
AX, saddrp
saddrp, AX
AX, sfrp
(saddrp) ← word
sfrp ← word
AX ← (saddrp)
(saddrp) ← AX
AX ← sfrp
8
8
sfrp, AX
8
sfrp ← AX
Note 3
Note 3
AX, rp
−
AX ← rp
rp, AX
−
rp ← AX
AX, !addr16
!addr16, AX
AX, rp
10 12 + 2n AX ← (addr16)
10 12 + 2m (addr16) ← AX
Note 3
XCHW
4
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
−
−
8
−
−
5
AX ↔ rp
8-bit
ADD
A, #byte
A, CY ← A + byte
(saddr), CY ← (saddr) + byte
A, CY ← A + r
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
operation
saddr, #byte
A, r
Note 4
r, A
r, CY ← r + A
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
9 + n A, CY ← A + (addr16)
5 + n A, CY ← A + (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
9 + n A, CY ← A + (HL + byte)
9 + n A, CY ← A + (HL + B)
9 + n A, CY ← A + (HL + C)
ADDC
−
8
−
−
5
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
saddr, #byte
A, r
Note 4
r, A
r, CY ← r + A + CY
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr) + CY
9 + n A, CY ← A + (addr16) + C
5 + n A, CY ← A + (HL) + CY
A, [HL + byte]
A, [HL + B]
A, [HL + C]
9 + n A, CY ← A + (HL + byte) + CY
9 + n A, CY ← A + (HL + B) + CY
9 + n A, CY ← A + (HL + C) + CY
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
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CHAPTER 24 INSTRUCTION SET
Clocks
Bytes
Flag
Instruction
Group
Mnemonic
Operands
A, #byte
Operation
A, CY ← A − byte
Z AC CY
Note 1 Note 2
8-bit
SUB
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
−
8
−
−
5
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
operation
saddr, #byte
A, r
(saddr), CY ← (saddr) − byte
A, CY ← A − r
Note 3
Note 3
Note 3
r, A
r, CY ← r − A
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr)
9 + n A, CY ← A − (addr16)
5 + n A, CY ← A − (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A, CY ← A − (HL + byte)
9 + n A, CY ← A − (HL + B)
9 + n A, CY ← A − (HL + C)
SUBC
−
8
−
−
5
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
r, A
r, CY ← r − A − CY
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr) − CY
9 + n A, CY ← A − (addr16) − CY
5 + n A, CY ← A − (HL) − CY
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A, CY ← A − (HL + byte) − CY
9 + n A, CY ← A − (HL + B) − CY
9 + n A, CY ← A − (HL + C) − CY
AND
−
8
−
−
5
A ← A ∧ byte
(saddr) ← (saddr) ∧ byte
A ← A ∧ r
r, A
r ← r ∧ A
A, saddr
A, !addr16
A, [HL]
A ← A ∧ (saddr)
9 + n A ← A ∧ (addr16)
5 + n A ← A ∧ [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
9 + n A ← A ∧ [HL + byte]
9 + n A ← A ∧ [HL + B]
9 + n A ← A ∧ [HL + C]
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
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CHAPTER 24 INSTRUCTION SET
Clocks
Bytes
Flag
Instruction
Group
Mnemonic
Operands
A, #byte
Operation
Z AC CY
Note 1 Note 2
8-bit
OR
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
−
8
−
−
5
A ← A ∨ byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
operation
saddr, #byte
A, r
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
Note 3
Note 3
Note 3
r, A
r ← r ∨ A
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
9 + n A ← A ∨ (addr16)
5 + n A ← A ∨ (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A ← A ∨ (HL + byte)
9 + n A ← A ∨ (HL + B)
9 + n A ← A ∨ (HL + C)
XOR
−
8
−
−
5
A ← A ∨ byte
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
r, A
r ← r ∨ A
A, saddr
A, !addr16
A, [HL]
A ← A ∨ (saddr)
9 + n A ← A ∨ (addr16)
5 + n A ← A ∨ (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
9 + n A ← A ∨ (HL + byte)
9 + n A ← A ∨ (HL + B)
9 + n A ← A ∨ (HL + C)
CMP
−
8
−
−
5
A − byte
(saddr) − byte
A − r
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
r, A
r − A
A, saddr
A, !addr16
A, [HL]
A − (saddr)
9 + n A − (addr16)
5 + n A − (HL)
A, [HL + byte]
A, [HL + B]
A, [HL + C]
9 + n A − (HL + byte)
9 + n A − (HL + B)
9 + n A − (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
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CHAPTER 24 INSTRUCTION SET
Clocks
Bytes
Flag
Instruction
Group
Mnemonic
Operands
AX, #word
Operation
AX, CY ← AX + word
Z AC CY
Note 1 Note 2
16-bit
ADDW
SUBW
CMPW
MULU
DIVUW
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
2
6
6
−
−
−
−
−
−
6
−
6
−
−
−
−
−
−
×
×
×
×
×
×
×
×
×
operation
AX, #word
AX, CY ← AX − word
AX − word
AX, #word
6
Multiply/
divide
X
16
25
2
AX ← A × X
C
AX (Quotient), C (Remainder) ← AX ÷ C
r ← r + 1
Increment/ INC
r
×
×
×
×
×
×
×
×
decrement
saddr
r
4
(saddr) ← (saddr) + 1
r ← r − 1
DEC
2
saddr
rp
4
(saddr) ← (saddr) − 1
rp ← rp + 1
INCW
4
DECW
rp
4
rp ← rp − 1
Rotate
ROR
A, 1
A, 1
A, 1
A, 1
[HL]
2
(CY, A7 ← A0, Am − 1 ← Am) × 1 time
(CY, A0 ← A7, Am + 1 ← Am) × 1 time
(CY ← A0, A7 ← CY, Am − 1 ← Am) × 1 time
(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time
×
×
×
×
ROL
2
RORC
ROLC
ROR4
2
2
10 12 + n + m A3 − 0 ← (HL)3 − 0, (HL)7 − 4 ← A3 − 0,
(HL)3 − 0 ← (HL)7 − 4
ROL4
[HL]
2
10 12 + n + m A3 − 0 ← (HL)7 − 4, (HL)3 − 0 ← A3 − 0,
(HL)7 − 4 ← (HL)3 − 0
BCD
ADJBA
ADJBS
MOV1
2
2
3
3
2
3
2
3
3
2
3
2
4
4
6
−
4
−
6
6
−
4
−
6
−
−
7
7
−
7
Decimal Adjust Accumulator after Addition
Decimal Adjust Accumulator after Subtract
CY ← (saddr.bit)
×
×
×
×
×
×
×
×
×
×
×
adjustment
Bit
CY, saddr.bit
CY, sfr.bit
manipulate
CY ← sfr.bit
CY, A.bit
CY ← A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
CY ← PSW.bit
7 + n CY ← (HL).bit
8
8
−
8
(saddr.bit) ← CY
sfr.bit ← CY
A.bit, CY
A.bit ← CY
PSW.bit, CY
[HL].bit, CY
PSW.bit ← CY
×
×
8 + n + m (HL).bit ← CY
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
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CHAPTER 24 INSTRUCTION SET
Clocks
Bytes
Flag
Instruction
Group
Mnemonic
Operands
CY, saddr.bit
Operation
CY ← CY ∧ saddr.bit)
Z AC CY
Note 1 Note 2
Bit
manipulate
AND1
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
6
−
4
−
6
6
−
4
−
6
6
−
4
−
6
4
−
4
−
6
4
−
4
−
6
2
2
2
7
7
−
7
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
saddr.bit
sfr.bit
CY ← CY ∧ sfr.bit
CY ← CY ∧ A.bit
CY ← CY ∧ PSW.bit
7 + n CY ← CY ∧ (HL).bit
OR1
7
7
−
7
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
7 + n CY ← CY ∨ (HL).bit
XOR1
SET1
CLR1
7
7
−
7
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
7 + n CY ← CY ∨ (HL).bit
6
8
−
6
(saddr.bit) ← 1
sfr.bit ← 1
A.bit
A.bit ← 1
PSW.bit
[HL].bit
PSW.bit ← 1
×
×
×
×
×
8 + n + m (HL).bit ← 1
saddr.bit
sfr.bit
6
8
−
6
(saddr.bit) ← 0
sfr.bit ← 0
A.bit
A.bit ← 0
PSW.bit
[HL].bit
PSW.bit ← 0
×
8 + n + m (HL).bit ← 0
SET1
CLR1
NOT1
CY
−
−
−
CY ← 1
CY ← 0
CY ← CY
1
0
×
CY
CY
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
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CHAPTER 24 INSTRUCTION SET
Clocks
Bytes
Flag
Instruction
Group
Mnemonic
Operands
!addr16
Operation
Z AC CY
Note 1 Note 2
Call/return CALL
3
2
7
5
−
−
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLF
!addr11
[addr5]
(SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L,
PC15 − 11 ← 00001, PC10 − 0 ← addr11,
SP ← SP − 2
CALLT
BRK
1
1
6
6
−
−
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP − 2
(SP − 1) ← PSW, (SP − 2) ← (PC + 1)H,
(SP − 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP − 3, IE ← 0
RET
1
1
6
6
−
−
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
R
R
R
R
R
R
−
RETB
1
6
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3
−
−
Stack
PUSH
POP
PSW
rp
1
1
2
4
(SP − 1) ← PSW, SP ← SP − 1
manipulate
(SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP − 2
−
−
PSW
rp
1
1
2
4
PSW ← (SP), SP ← SP + 1
R
R
R
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
−
−
−
6
6
8
6
6
6
6
MOVW
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
4
2
2
3
2
2
2
2
2
2
10
8
8
−
SP ← word
SP ← AX
AX ← SP
Unconditional BR
PC ← addr16
branch
−
PC ← PC + 2 + jdisp8
PCH ← A, PCL ← X
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
−
−
Conditional BC
$addr16
$addr16
$addr16
$addr16
branch
−
BNC
−
BZ
−
BNZ
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
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CHAPTER 24 INSTRUCTION SET
Clocks
Bytes
Flag
Instruction
Group
Mnemonic
Operands
Operation
Z AC CY
Note 1 Note 2
Conditional BT
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
3
4
3
3
3
4
4
3
4
3
4
8
−
9
11
−
PC ← PC + 3 + jdisp8 if(saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 3 + jdisp8 if PSW.bit = 1
branch
8
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
−
9
10
10
−
11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 1
BF
11
11
−
PC ← PC + 4 + jdisp8 if(saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
8
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
−
11
10
10
11 + n PC ← PC + 3 + jdisp8 if (HL).bit = 0
BTCLR
12
PC ← PC + 4 + jdisp8
if(saddr.bit) = 1
then reset(saddr.bit)
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
4
3
4
3
2
2
3
−
8
−
12
−
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
12
PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
×
×
×
10 12 + n + m PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
DBNZ
6
6
8
−
−
B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
C ← C −1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16
RBn
10
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if(saddr) ≠ 0
CPU
SEL
NOP
EI
2
1
2
2
2
2
4
2
−
−
6
6
−
−
6
6
−
−
RBS1, 0 ← n
control
No Operation
IE ← 1(Enable Interrupt)
IE ← 0(Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written.
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CHAPTER 24 INSTRUCTION SET
24.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second Operand
#byte
A
rNote
sfr
saddr !addr16 PSW
[DE]
[HL] [HL+byte] $addr16
[HL + B]
1
None
First Operand
[HL + C]
MOV MOV MOV MOV
ROR
A
ADD
ADDC
SUB
SUBC
AND
OR
MOV MOV MOV MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XCH
XCH
ADD
XCH
ADD
XCH
XCH
ADD
XCH
ADD
ROL
RORC
ROLC
ADDC ADDC
SUB SUB
SUBC SUBC
ADDC ADDC
SUB SUB
SUBC SUBC
XOR
CMP
AND
OR
AND
OR
AND
OR
AND
OR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C
sfr
DBNZ
DBNZ
MOV MOV
saddr
MOV MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL + byte]
[HL + B]
MOV
[HL + C]
X
C
MULU
DIVUW
Note Except r = A
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CHAPTER 24 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
#word
AX
rpNote
sfrp
saddrp
!addr16
SP
None
AX
ADDW
MOVW
XCHW
MOVW
MOVW
MOVW
MOVW
SUBW
CMPW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
MOV1
MOV1
MOV1
MOV1
MOV1
$addr16
None
A.bit
BT
SET1
CLR1
BF
BTCLR
sfr.bit
BT
SET1
CLR1
BF
BTCLR
saddr.bit
PSW.bit
[HL].bit
CY
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
MOV1
MOV1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
SET1
CLR1
NOT1
AND1
OR1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
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CHAPTER 24 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
AX
!addr16
!addr11
[addr5]
$addr16
Basic instruction
BR
CALL
BR
CALLF
CALLT
BR
BC
BNC
BZ
BNZ
Compound
instruction
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
These specifications are only target values, and may not be satisfied by mass-produced products.
The electrical specifications (target values) of (A1) products are under evaluation.
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
Ratings
−0.3 to +6.5
Unit
V
EVDD
VSS
−0.3 to +6.5
V
−0.3 to +0.3
V
EVSS
AVREF
AVSS
VPP
−0.3 to +0.3
−0.3 to VDD + 0.3Note 1
V
V
−0.3 to +0.3
V
µPD78F0114 only Note 2
−0.3 to +10.5
−0.3 to VDD + 0.3Note 1
V
Input voltage
VI1
P00, P01, P10 to P17, P20 to P27, P30 to P33,
P60, P61, P70 to P73, P120, P130, X1, X2,
XT1, XT2, RESET
V
VI2
VI3
P62, P63
N-ch open drain
−0.3 to +13
−0.3 to VDD + 0.3Note 1
−0.3 to +10.5
V
V
On-chip pull-up resistor
VPP in flash programming mode
(µPD78F0114 only)
Output voltage
VO
−0.3 to VDD + 0.3Note 1
V
V
Analog input voltage
VAN
AVSS − 0.3 to AVREF + 0.3Note 1
and −0.3 to VDD + 0.3Note 1
Output current, high
Output current, low
IOH
Per pin
−10
−30
−30
20
mA
mA
mA
mA
Total of all
P00, P01, P10 to P16, P70 to P73
pins −60 mA
P17, P30 to P33, P120, P130
IOL
Per pin
P00, P01, P10 to P17, P30 to
P33, P70 to P73, P120, P130
P60 to P63
30
35
35
mA
mA
mA
Total of all
pins 70 mA
P00, P01, P10 to P16, P70 to P73
P17, P30 to P33, P60 to P63,
P120, P130
Operating ambient
temperature
TA
In normal operation mode
−40 to +85
°C
°C
Storage temperature
Tstg
µPD780111, 780112, 780113, 780114
µPD78F0114
−65 to +150
−40 to +125
Notes 1. Must be 6.5 V or lower.
(Refer to Note 2 on the next page.)
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Notes 2. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash
memory is written.
• When supply voltage rises
VPP must exceed VDD 10 µs or more after VDD has reached the lower-limit value (2.7 V) of the operating
voltage range (see a in the figure below).
• When supply voltage drops
VDD must be lowered 10 µs or more after VPP falls below the lower-limit value (2.7 V) of the operating
voltage range of VDD (see b in the figure below).
2.7 V
V
DD
0 V
a
b
VPP
2.7 V
0 V
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
X1 Oscillator Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Resonator Recommended Circuit
Parameter
Conditions
4.0 V ≤ VDD ≤ 5.5 V
MIN.
2.0
TYP. MAX.
Unit
IC
Ceramic
Oscillation
frequency (fXP)Note
10
8.38
5.0
MHz
X1
)
X2
(VPP
resonator
3.3 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.3 V
2.0
2.0
C2
C1
IC
Crystal
Oscillation
4.0 V ≤ VDD ≤ 5.5 V
3.3 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.3 V
2.0
2.0
2.0
10
8.38
5.0
MHz
X1
)
X2
(VPP
resonator
frequency (fXP)Note
C2
C1
X1
External
clock
X1 input
frequency (fXP)Note
4.0 V ≤ VDD ≤ 5.5 V
3.3 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.3 V
4.0 V ≤ VDD ≤ 5.5 V
3.3 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.3 V
2.0
2.0
2.0
46
10
8.38
5.0
MHz
ns
X2
X1 input high-
/low-level width
(tXPH, tXPL)
500
500
500
56
96
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the Ring-OSC after reset, check the oscillation stabilization time of
the X1 input clock using the oscillation stabilization time status register (OSTC). Determine the
oscillation stabilization time of the OSTC register and oscillation stabilization time select
register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator
to be used.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
Ring-OSC Oscillator Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Resonator
Parameter
Conditions
MIN.
120
TYP. MAX.
240 480
Unit
kHz
On-chip Ring-OSC oscillator
Oscillation frequency (fR)
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Subsystem Clock Oscillator Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Resonator
Crystal
Recommended Circuit
IC
Parameter
Conditions
MIN.
32
TYP. MAX.
Unit
kHz
Oscillation frequency
(fXT)Note
32.768
35
(VPP
)
XT2 XT1
resonator
Rd
C4
C3
XT2
XT1
External clock
XT1 input frequency
(fXT)Note
32
12
38.5
15
kHz
XT1 input high-/low-level
width (tXTH, tXTL)
µs
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken
lines in the above figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current
consumption, and is more prone to malfunction due to noise than the main system clock
oscillator. Particular care is therefore required with the wiring method when the subsystem
clock is used.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
DC Characteristics (1/4)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
IOH
Conditions
MIN.
TYP.
MAX.
−5
Unit
mA
mA
Output current, high
Per pin
4.0 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD ≤ 5.5 V
Total of P00, P01, P10 to
P16, P70 to P73
−25
Total of P17, P30 to P33,
P120, P130
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
−25
mA
All pins
−10
mA
mA
Output current, low
IOL
Per pin for P00, P01, P10 to 4.0 V ≤ VDD ≤ 5.5 V
P17, P30 to P33, P70 to
10
P73, P120, P130
Per pin for P60 to P63
4.0 V ≤ VDD ≤ 5.5 V
4.0 V ≤ VDD ≤ 5.5 V
15
30
mA
mA
Total of P00, P01, P10 to
P16, P70 to P73
Total of P17, P30 to P33,
P60 to P63, P120, P130
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
30
mA
All pins
10
mA
V
Input voltage, high
VIH1
VIH2
P12, P13, P15
0.7VDD
0.8VDD
VDD
VDD
P00, P01, P10, P11, P14, P16, P17, P30 to
P33, P70 to P73, P120, RESET
V
VIH3
VIH4
VIH5
VIH6
VIL1
VIL2
P20 to P27Note
0.7AVREF
0.7VDD
0.7VDD
VDD − 0.5
0
AVREF
VDD
V
V
V
V
V
V
P60, P61
P62, P63
12
X1, X2, XT1, XT2
P12, P13, P15
VDD
Input voltage, low
0.3VDD
0.2VDD
P00, P01, P10, P11, P14, P16, P17, P30 to
P33, P70 to P73, P120, RESET
0
VIL3
VIL4
VIL5
VIL6
P20 to P27Note
0
0
0
0
0.3AVREF
0.3VDD
0.3VDD
0.4
V
V
V
V
P60, P61
P62, P63
X1, X2, XT1, XT2
Note When used as A/D converter analog input pins, set AVREF = VDD.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
DC Characteristics (2/4)
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
VOH
Conditions
4.0 V ≤ VDD ≤ 5.5 V,
MIN.
TYP.
MAX.
Unit
V
Output voltage, high
P00, P01, P10 to
P16, P70 to P73
Total IOH = −25 mA
VDD − 1.0
IOH = −5 mA
P17, P30 to P33,
P120, P130
4.0 V ≤ VDD ≤ 5.5 V,
IOH = −5 mA
VDD − 1.0
VDD − 0.5
V
Total IOH = −25 mA
IOH = −100 µA
2.7 V ≤ VDD < 4.0 V
V
V
Output voltage, low
VOL1
P00, P01, P10 to
P16, P70 to P73
Total IOL = 30 mA
4.0 V ≤ VDD ≤ 5.5 V,
IOL = 10 mA
1.3
1.3
P17, P30 to P33, P60 4.0 V ≤ VDD ≤ 5.5 V,
V
to P63, P120, P130
Total IOL = 30 mA
IOL = 10 mA
IOL = 400 µA
P60 to P63
VI = VDD
2.7 V ≤ VDD < 4.0 V
0.4
2.0
3
V
V
VOL2
ILIH1
IOL = 15 mA
Input leakage current,
high
P00, P01, P10 to P17, P30
to P33, P60, P61, P70 to
P73, P120, P130, RESET
µA
VI = AVREF
VI = VDD
VI = 12 V
VI = 0 V
P20 to P27
3
20
3
µA
µA
µA
µA
ILIH2
ILIH3
ILIL1
X1, X2, XT1, XT2
P62, P63 (N-ch open drain)
Input leakage current,
low
P00, P01, P10 to P17, P20
to P27, P30 to P33, P60,
P61, P70 to P73, P120,
P130, RESET
−3
ILIL2
ILIL3
X1, X2, XT1, XT2
−20
−3Note
3
µA
µA
µA
P62, P63 (N-ch open drain)
Output leakage current, ILOH
high
VO = VDD
VO = 0 V
VI = 0 V
Output leakage current, ILOL
low
−3
µA
Pull-up resistor
RL
10
0
30
100
kΩ
VPP supply voltage
VPP1
In normal operation mode
0.2VDD
V
(µPD78F0114 only)
Note If there is no on-chip pull-up resistor for P62 and P63 (specified by a mask option) and if port 6 has been set to
input mode when a read instruction is executed to read from port 6, a low-level input leakage current of up to
−45 µA flows during only one cycle. At all other times, the maximum leakage current is −3 µA.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
DC Characteristics (3/4): µPD78F0114
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Supply
currentNote 1
Symbol
IDD1
Conditions
MIN. TYP. MAX. Unit
11.5 24.2 mA
X1 crystal
oscillation
operating
modeNote 2
fXP = 10 MHz
When A/D converter is stopped
VDD = 5.0 V 10%Note 3
When A/D converter is
operatingNote 4
12.5 26.3 mA
fXP = 5 MHz
When A/D converter is stopped
5.5 11.6 mA
6.5 13.7 mA
VDD = 3.0 V 10%Note 3
When A/D converter is
operatingNote 4
IDD2
X1 crystal
fXP = 10 MHz
1.6
0.9
3.2
6.4
1.8
3.6
2.1
1.2
mA
mA
mA
mA
mA
mA
When peripheral functions are stopped
When peripheral functions are operating
When peripheral functions are stopped
When peripheral functions are operating
oscillation HALT VDD = 5.0 V 10%Note 3
mode
fXP = 5 MHz
VDD = 3.0 V 10%Note 3
IDD3
Ring-OSC
operating
modeNote 5
VDD = 5.0 V 10%
VDD = 3.0 V 10%
0.7
0.4
IDD4
32.768 kHz
crystal oscillation
operating
VDD = 5.0 V 10%
VDD = 3.0 V 10%
120 240
100 200
µA
µA
modeNotes 5, 7
IDD5
32.768 kHz
VDD = 5.0 V 10%
VDD = 3.0 V 10%
35
7
70
21
µA
µA
crystal oscillation
HALT modeNotes 5, 7
IDD6
STOP mode
VDD = 5.0 V 10%
POC: OFF, RING: OFF
POC: OFF, RING: ON
POC: ONNote 6, RING: OFF
POC: ONNote 6, RING: ON
POC: OFF, RING: OFF
POC: OFF, RING: ON
POC: ONNote 6, RING: OFF
POC: ONNote 6, RING: ON
0.1
14
30
58
µA
µA
3.5 35.5 µA
17.5 63.5 µA
VDD = 3.0 V 10%
0.05 10
7.5 25
µA
µA
3.5 15.5 µA
11 30.5 µA
Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
2. IDD1 includes peripheral operation current.
3. When PCC = 00H.
4. Including the current that flows through the AVREF pin.
5. When main system clock is stopped.
6. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option.
7. When POC-OFF (including LVIE = 0) is selected by a mask option and Ring-OSC oscillation is stopped.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
DC Characteristics (4/4): µPD780111, 780112, 780113, and 780114
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Supply
currentNote 1
Symbol
IDD1
Conditions
MIN. TYP. MAX. Unit
5.8 13.3 mA
X1 crystal
oscillation
operating
modeNote 2
fXP = 10 MHz
When A/D converter is stopped
VDD = 5.0 V 10%Note 3
When A/D converter is
operatingNote 4
6.8 15.5 mA
fXP = 5 MHz
When A/D converter is stopped
1.8
2.8
4.2
6.5
mA
mA
VDD = 3.0 V 10%Note 3
When A/D converter is
operatingNote 4
IDD2
X1 crystal
fXP = 10 MHz
1.2
0.7
0.3
2.4
4.8
1.4
2.8
0.9
mA
mA
mA
mA
mA
When peripheral functions are stopped
When peripheral functions are operating
When peripheral functions are stopped
When peripheral functions are operating
oscillation HALT VDD = 5.0 V 10%Note 3
mode
fXP = 5 MHz
VDD = 3.0 V 10%Note 3
IDD3
Ring-OSC
operating
modeNote 5
VDD = 5.0 V 10%
VDD = 3.0 V 10%
0.19 0.57 mA
IDD4
32.768 kHz
crystal oscillation
operating
VDD = 5.0 V 10%
VDD = 3.0 V 10%
45
25
90
50
µA
µA
modeNotes 5, 7
IDD5
32.768 kHz
VDD = 5.0 V 10%
VDD = 3.0 V 10%
30
7
60
21
µA
µA
crystal oscillation
HALT modeNotes 5, 7
IDD6
STOP mode
VDD = 5.0 V 10%
POC: OFF, RING: OFF
POC: OFF, RING: ON
POC: ONNote 6, RING: OFF
POC: ONNote 6, RING: ON
POC: OFF, RING: OFF
POC: OFF, RING: ON
POC: ONNote 6, RING: OFF
POC: ONNote 6, RING: ON
0.1
14
30
58
µA
µA
3.5 35.5 µA
17.5 63.5 µA
VDD = 3.0 V 10%
0.05 10
7.5 25
µA
µA
3.5 15.5 µA
11 30.5 µA
Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not included).
2. IDD1 includes peripheral operation current.
3. When PCC = 00H.
4. Including the current that flows through the AVREF pin.
5. When main system clock is stopped.
6. Including when LVIE (bit 4 of LVIM) = 1 with POC-OFF selected by a mask option.
7. When POC-OFF (including LVIE = 0) is selected by a mask option and Ring-OSC oscillation is stopped.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
AC Characteristics
(1) Basic operation (TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
TCY
Conditions
Main system X1 input
4.0 V ≤ VDD ≤ 5.5 V
MIN.
0.2
TYP. MAX.
Unit
µs
Instruction cycle (minimum
instruction execution time)
16
16
16
clock
clock
3.3 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.3 V
0.238
µs
operation
0.4
µs
Ring-OSC clock
4.17
8.33
122
16.67
125
µs
Subsystem clock operation
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
114
µs
TI000, TI010 input high-level
width, low-level width
tTIH0,
tTIL0
2/fsam + 0.1Note
2/fsam + 0.2Note
µs
µs
TI50, TI51 input frequency
fTI5
10
5
MHz
TI50, TI51 input high-level width, tTIH5,
50
100
1
ns
ns
µs
low-level width
tTIL5
Interrupt input high-level width,
low-level width
tINTH,
tINTL
Key return input low-level width tKR
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
50
100
10
ns
ns
µs
RESET low-level width
tRST
Note Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode
register 00 (PRM00). Note that when selecting the TI000 or TI010 valid edge as the count clock, fsam = fXP.
TCY vs. VDD (X1 Input Clock Operation)
20.0
16.0
10.0
µ
5.0
Guaranteed
operation range
2.0
1.0
0.4
0.238
0.2
0.1
5.5
6.0
0
1.0
2.0
3.0
4.0
5.0
2.7 3.3
Supply voltage VDD [V]
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
(2) Serial interface (TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
(a) UART mode (UART6, dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MIN.
MIN.
TYP.
TYP.
TYP.
MAX.
312.5
Unit
kbps
(b) UART mode (UART0, dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Conditions
MAX.
312.5
Unit
kbps
(c) 3-wire serial I/O mode (master mode, SCK10... internal clock output)
Parameter
SCK10 cycle time
Symbol
tKCY1
Conditions
4.0 V ≤ VDD ≤ 5.5 V
3.3 V ≤ VDD < 4.0 V
2.7 V ≤ VDD < 3.3 V
MIN.
200
MAX.
Unit
ns
240
ns
400
ns
SCK10 high-/low-level width
tKH1,
tKL1
tKCY1/2 − 10
ns
SI10 setup time (to SCK10↑)
SI10 hold time (from SCK10↑)
tSIK1
tKSI1
tKSO1
30
30
ns
ns
ns
Delay time from SCK10↓ to
SO10 output
C = 100 pFNote
30
MAX.
120
Note C is the load capacitance of the SCK10 and SO10 output lines.
(d) 3-wire serial I/O mode (slave mode, SCK10... external clock input)
Parameter
SCK10 cycle time
Symbol
tKCY2
Conditions
MIN.
400
TYP.
Unit
ns
SCK10 high-/low-level width
tKH2,
tKL2
tKCY2/2
ns
SI10 setup time (to SCK10↑)
SI10 hold time (from SCK10↑)
tSIK2
tKSI2
tKSO2
80
50
ns
ns
ns
Delay time from SCK10↓ to
C = 100 pFNote
SO10 output
Note C is the load capacitance of the SO10 output line.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/fXP
t
XPL
t
XPH
V
IH6 (MIN.)
IL6 (MAX.)
X1 input
V
1/fXT
t
XTL
tXTH
V
IH6 (MIN.)
XT1 input
VIL6 (MAX.)
TI Timing
t
TIL0
t
TIH0
TI00, TI010
1/fTI5
t
TIL5
t
TIH5
TI50, TI51
Interrupt Request Input Timing
t
INTL
t
INTH
INTP0 to INTP5
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
RESET Input Timing
t
RSL
RESET
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
SCK10
t
SIKm
t
KSIm
SI10
Input data
t
KSOm
SO10
Output data
Remark m = 1, 2
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
A/D Converter Characteristics
(TA = −40 to +85°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Resolution
Overall errorNotes 1, 2
4.0 V ≤ AVREF ≤ 5.5 V
0.2
0.3
0.4
%FSR
%FSR
µs
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
4.0 V ≤ AVREF ≤ 5.5 V
2.7 V ≤ AVREF < 4.0 V
0.6
Conversion time
tCONV
14
17
100
100
0.4
µs
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
V
0.6
0.4
0.6
Integral non-linearity errorNote 1
Differential non-linearity errorNote 1
Analog input voltage
2.5
4.5
1.5
2.0
VIAN
AVSS
AVREF
Notes 1. Excludes quantization error ( 1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
POC Circuit Characteristics (TA = −40 to +85°C)
Parameter
Detection voltage
Symbol
VPOC0
VPOC1
tPTH
Conditions
Mask option = 3.5 V
MIN.
3.3
TYP.
3.5
MAX.
3.7
Unit
V
Mask option = 2.85 V
VDD: 0 V → 2.7 V
VDD: 0 V → 3.3 V
2.7
2.85
3.0
V
Power supply rise time
0.0015
0.002
1500
1800
3.0
ms
ms
ms
Response delay time 1Note
tPTHD
When power supply rises, after reaching
detection voltage (MAX.)
Response delay time 2Note
Minimum pulse width
tPD
When power supply falls, VDD = 1.7 V
1.0
ms
ms
tPW
0.2
Note Time required from voltage detection to reset release.
POC Circuit Timing
Supply voltage
(VDD
)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
tPW
tPTH
tPTHD
tPD
Time
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
LVI Circuit Characteristics (TA = −40 to +85°C)
Parameter
Detection voltage
Symbol
VLVI0
VLVI1
VLVI2
VLVI3
VLVI4
VLVI5
VLVI6
tLD
Conditions
MIN.
4.1
TYP.
4.3
4.1
3.9
3.7
3.5
3.3
3.1
0.2
MAX.
4.5
Unit
V
3.9
4.3
V
3.7
4.1
V
3.5
3.9
V
3.3
3.7
V
3.15
2.95
3.45
3.25
2.0
V
V
Response timeNote 1
ms
ms
ms
Minimum pulse width
tLW
0.2
Reference voltage stabilization wait tLWAIT0
timeNote 2
0.5
0.1
2.0
0.2
Operation stabilization wait timeNote 3 tLWAIT1
ms
Notes 1. Time required from voltage detection to interrupt output or RESET output.
2. Time required from setting LVIE to 1 to reference voltage stabilization when POC = OFF is selected by
the POC mask option.
3. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. VLVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6
2. VPOCn < VLVm (n = 0, 1, m = 0 to 6)
LVI Circuit Timing
Supply voltage
(VDD
)
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
tLW
tWAIT0
tWAIT1
tLD
LVIE ← 1 LVION ← 1
Time
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter
Symbol
VDDDR
tSREL
Conditions
MIN.
1.6
0
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
Release signal set time
µs
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Flash Memory Programming Characteristics: µPD78F0114
(TA = +10 to +60°C, 2.7 V ≤ VDD = EVDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = EVSS = AVSS = 0 V)
(1) Write erase characteristics
Parameter
VPP supply voltage
Symbol
VPP2
IDD
Conditions
During flash memory programming
When VPP = VPP2, fXP = 10 MHz, VDD = 5.5 V
VPP = VPP2
MIN.
9.7
TYP.
10.0
MAX.
10.3
37
Unit
V
VDD supply current
VPP supply current
Step erase timeNote 1
Overall erase timeNote 2
Writeback timeNote 3
mA
mA
s
IPP
100
0.201
20
Ter
0.199
49.4
0.2
50
Tera
Twb
When step erase time = 0.2 s
When writeback time = 50 ms
s/chip
ms
50.6
60
Number of writebacks per
writeback commandNote 4
Cwb
Times
Number of erases/writebacks
Step write timeNote 5
Cerwb
Twr
16
52
Times
µs
48
48
50
Overall write time per wordNote 6
Twrw
When step write time = 50 µs (1 word = 1
520
µs
byte)
Number of rewrites per chipNote 7
Cerwr
1 erase + 1 write after erase = 1 rewrite
20
Times
Notes 1. The recommended setting value of the step erase time is 0.2 s.
2. The prewrite time before erasure and the erase verify time (writeback time) are not included.
3. The recommended setting value of the writeback time is 50 ms.
4. Writeback is executed once by the issuance of the writeback command. Therefore, the number of retries
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step write time is 50 µs.
6. The actual write time per word is 100 µs longer. The internal verify time during or after a write is not
included.
7. When a product is first written after shipment, “erase → write” and “write only” are both taken as one
rewrite.
Example: P: Write, E: Erase
Shipped product
→ P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
Remark The range of the operating clock during flash memory programming is the same as the range during normal
operation.
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CHAPTER 25 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
(2) Serial write operation characteristics
Parameter
Symbol
tDP
tPR
Conditions
MIN.
10
10
2
TYP.
MAX.
Unit
µs
µs
ms
µs
ms
V
Set time from VDD↑ to VPP↑
Release time from VPP↑ to RESET↑
VPP pulse input start time from RESET↑ tRP
VPP pulse high-/low-level width
tPW
8
VPP pulse input end time from RESET↑
VPP pulse low-level input voltage
VPP pulse high-level input voltage
tRPE
VPPL
VPPH
20
0.8VDD
9.7
1.2VDD
10.3
10.0
V
Flash Write Mode Setting Timing
VDD
VDD
0 V
tDP
tRP
tPW
VPPH
VPP
VPP
VPPL
tPW
tPR
tRPE
VDD
RESET (input)
0 V
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CHAPTER 26 PACKAGE DRAWING
44 PIN PLASTIC LQFP (10x10)
A
B
detail of lead end
23
22
33
34
S
P
T
C
D
R
L
12
11
44
U
1
Q
F
J
M
G
H
I
K
M
N
S
S
ITEM MILLIMETERS
NOTE
Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
12.0 0.2
10.0 0.2
10.0 0.2
12.0 0.2
1.0
G
1.0
+0.08
H
0.37
−0.07
I
0.20
J
K
L
0.8 (T.P.)
1.0 0.2
0.5
+0.03
0.17
M
−0.06
N
P
Q
0.10
1.4 0.05
0.1 0.05
+4°
3°
R
−3°
S
T
1.6 MAX.
0.25 (T.P.)
0.6 0.15
U
S44GB-80-8ES-2
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CHAPTER 27 CAUTIONS FOR WAIT
27.1 Cautions for Wait
This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data
may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes
processing, until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of
execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to Table
27-1). This must be noted when real-time processing is performed.
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CHAPTER 27 CAUTIONS FOR WAIT
27.2 Peripheral Hardware That Generates Wait
Table 27-1 lists the registers that issue a wait when accessed by the CPU, and the number of CPU wait clocks.
Table 27-1. Registers That Generate Wait and Number of CPU Wait Clocks
Peripheral Hardware
Watchdog timer
Register
Access
Number of Wait Clocks
3 clocks (fixed)
WDTM
ASIS0
ASIS6
ADM
Write
Read
Read
Write
Write
Write
Write
Read
Serial interface UART0
Serial interface UART6
A/D converter
1 clock (fixed)
1 clock (fixed)
2 to 5 clocksNote
(when ADM.5 flag = “1”)
2 to 9 clocksNote
ADS
PFM
(when ADM.5 flag = “0”)
PFT
ADCR
1 to 5 clocks
(when ADM.5 flag = “1”)
1 to 9 clocks
(when ADM.5 flag = “0”)
<Calculating maximum number of wait clocks>
{(1/fMACRO) × 2/(1/fCPU)} + 1
*The result after the decimal point is truncated if it is less than tCPUL after it has been multiplied by
(1/fCPU), and is rounded up if it exceeds tCPUL.
fMACRO:
Macro operating frequency
(When bit 5 (FR2) of ADM = “1”: fX/2, when bit 5 (FR2) of ADM = “0”: fX/22)
fCPU:
CPU clock frequency
tCPUL:
Low-level width of CPU clock
Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1.
Remark The clock is the CPU clock (fCPU).
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CHAPTER 27 CAUTIONS FOR WAIT
27.3 Example of Wait Occurrence
<1> Watchdog timer
<On execution of MOV WDTM, A>
Number of execution clocks: 8
(5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).)
<On execution of MOV WDTM, #byte>
Number of execution clocks: 10
(7 clocks when data is written to a register that does not issue a wait (MOV sfr, #byte).)
<2> Serial interface UART6
<On execution of MOV A, ASIS6>
Number of execution clocks: 6
(5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).)
<3> A/D converter
Table 27-2. Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter)
<On execution of MOV ADM, A; MOV ADS, A; or MOV A, ADCR>
• When fX = 10 MHz, tCPUL = 50 ns
Value of Bit 5 (FR2)
fCPU
Number of Wait Clocks
9 clocks
Number of Execution Clocks
14 clocks
of ADM Register
0
1
fX
fX/2
fX/22
fX/23
fX/24
fX
5 clocks
10 clocks
3 clocks
8 clocks
2 clocks
7 clocks
0 clocks (1 clockNote
)
5 clocks (6 clocksNote
)
5 clocks
10 clocks
fX/2
fX/22
fX/23
fX/24
3 clocks
8 clocks
2 clocks
7 clocks
0 clocks (1 clockNote
0 clocks (1 clockNote
)
)
5 clocks (6 clocksNote
5 clocks (6 clocksNote
)
)
Note On execution of MOV A, ADCR
Remark The clock is the CPU clock (fCPU).
fX: X1 input clock frequency
tCPUL: Low-level width of CPU clock
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APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the 78K0/KC1 Series.
Figure A-1 shows the development tool configuration.
•
Support for PC98-NX series
Unless otherwise specified, products supported by IBM PC/ATTM compatibles are compatible with PC98-NX
series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.
•
Windows
Unless otherwise specified, “Windows” means the following OSs.
•
•
•
Windows 3.1
Windows 95, 98, 2000
Windows NTTM Ver 4.0
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APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration
Language Processing Software
• Assembler package
• C compiler package
• C library source file
• Device file
Debugging Tool
• System simulator
• Integrated debugger
• Device file
Embedded Software
• Real-time OS
Host Machine (PC)
Interface adapter,
PC card interface, etc.
Flash Memory
Write Environment
In-Circuit Emulator
Flash programmer
Emulation board
Power supply unit
Flash memory
write adapter
Performance board
On-chip flash
memory version
Emulation probe
Conversion socket or
conversion adapter
Target system
Remark The item in the broken-line box differs according to the development environment. See A.4.1
Hardware.
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APPENDIX A DEVELOPMENT TOOLS
A.1 Software Package
SP78K0
Development tools (software) common to the 78K/0 Series are combined in this package.
78K/0 Series software package
Part number: µS××××SP78K0
Remark ×××× in the part number differs depending on the host machine and OS used.
µS××××SP78K0
××××
AB17
BB17
Host Machine
PC-9800 series,
IBM PC/AT compatibles
OS
Supply Medium
Windows (Japanese version) CD-ROM
Windows (English version)
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APPENDIX A DEVELOPMENT TOOLS
A.2 Language Processing Software
RA78K0
This assembler converts programs written in mnemonics into object codes executable
with a microcontroller.
Assembler package
This assembler is also provided with functions capable of automatically creating symbol
tables and branch instruction optimization.
This assembler should be used in combination with a device file (DF780114) (sold
separately).
<Precaution when using RA78K0 in PC environment>
This assembler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
Part number: µS××××RA78K0
CC78K0
This compiler converts programs written in C language into object codes executable with
a microcontroller.
C compiler package
This compiler should be used in combination with an assembler package and device file
(both sold separately).
<Precaution when using CC78K0 in PC environment>
This C compiler package is a DOS-based application. It can also be used in Windows,
however, by using the Project Manager (included in assembler package) on Windows.
Part number: µS××××CC78K0
DF780114Notes 1, 2
Device file
This file contains information peculiar to the device.
This device file should be used in combination with a tool (RA78K0, CC78K0, SM78K0,
ID78K0-NS, and ID78K0) (all sold separately).
The corresponding OS and host machine differ depending on the tool to be used (all sold
separately).
Part number: µS××××DF780114
CC78K/0-LNote 3
This is a source file of the functions that configure the object library included in the C
compiler package (CC78K0).
C library source file
This file is required to match the object library included in the C compiler package to the
user’s specifications.
Part number: µS××××CC78K0-L
Notes 1. The DF780114 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and
ID78K0.
2. Under development
3. The CC78K0-L is not included in the software package (SP78K0).
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APPENDIX A DEVELOPMENT TOOLS
Remark ×××× in the part number differs depending on the host machine and OS used.
µS××××RA78K0
µS××××CC78K0
××××
AB13
Host Machine
PC-9800 series,
OS
Supply Medium
Windows (Japanese version) 3.5-inch 2HD FD
Windows (English version)
IBM PC/AT compatibles
BB13
AB17
BB17
3P17
3K17
Windows (Japanese version) CD-ROM
Windows (English version)
HP9000 series 700TM
SPARCstationTM
HP-UXTM (Rel. 10.10)
SunOSTM (Rel. 4.1.4)
SolarisTM (Rel. 2.5.1)
µS××××DF780114
µS××××CC78K0-L
××××
Host Machine
OS
Supply Medium
AB13
BB13
3P16
3K13
3K15
PC-9800 series,
Windows (Japanese version) 3.5-inch 2HD FD
Windows (English version)
IBM PC/AT compatibles
HP9000 series 700
SPARCstation
HP-UX (Rel. 10.10)
DAT
SunOS (Rel. 4.1.4)
Solaris (Rel. 2.5.1)
3.5-inch 2HD FD
1/4-inch CGMT
A.3 Flash Memory Writing Tools
Flashpro III
Flash programmer dedicated to microcontrollers with on-chip flash memory.
(part number: FL-PR3, PG-FP3)
Flashpro IV
(part number: FL-PR4, PG-FP4)
Flash programmer
FA-44GB-8ES
Flash memory writing adapter used connected to the Flashpro III/Flashpro IV.
Flash memory writing adapter
• FA-44GB-8ES: For 44-pin plastic LQFP (GB-8ES type)
Remark FL-PR3, FL-PR4, and FA-44GB-8ES are products of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
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APPENDIX A DEVELOPMENT TOOLS
A.4 Debugging Tools
A.4.1 Hardware
IE-78K0-NS
The in-circuit emulator serves to debug hardware and software when developing
application systems using a 78K/0 Series product. It corresponds to the integrated
debugger (ID78K0-NS). This emulator should be used in combination with a power
supply unit, emulation probe, and the interface adapter required to connect this emulator
to the host machine.
In-circuit emulator
IE-78K0-NS-PA
This board is connected to the IE-78K0-NS to expand its functions. Adding this board
adds a coverage function and enhances debugging functions such as tracer and timer
functions.
Performance board
IE-78K0-NS-A
Product that combines the IE-78K0-NS and IE-78K0-NS-PA
In-circuit emulator
IE-70000-MC-PS-B
Power supply unit
This adapter is used for supplying power from a 100 V to 240 V AC outlet.
IE-70000-98-IF-C
Interface adapter
This adapter is required when using a PC-9800 series computer (except notebook type)
as the IE-78K0-NS(-A) host machine (C bus compatible).
IE-70000-CD-IF-A
PC card interface
This is PC card and interface cable required when using a notebook-type computer as
the IE-78K0-NS(-A) host machine (PCMCIA socket compatible).
IE-70000-PC-IF-C
Interface adapter
This adapter is required when using an IBM PC compatible computer as the IE-78K0-
NS(-A) host machine (ISA bus compatible).
IE-70000-PCI-IF-A
Interface adapter
This adapter is required when using a computer with a PCI bus as the IE-78K0-NS(-A)
host machine.
IE-780148-NS-EM1Note
Emulation board
This board emulates the operations of the peripheral hardware peculiar to a device. It
should be used in combination with an in-circuit emulator.
NP-44GB-TQ
This probe is used to connect the in-circuit emulator to a target system and is designed
for use with 44-pin plastic LQFP (GB-8ES type).
Emulation probe
TGB-044SAP
This conversion socket connects the NP-44BG-TQ to a target system board designed for
Conversion adapter a 44-pin plastic LQFP (GB-8ES type).
Note Under development
Remarks 1. NP-44GB-TQ is a product of Naito Densei Machida Mfg. Co., Ltd.
TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.
2. TGB-044SAP is a product made by TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
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APPENDIX A DEVELOPMENT TOOLS
A.4.2 Software
SM78K0
This system simulator is used to perform debugging at C source level or assembler level
while simulating the operation of the target system on a host machine.
This simulator runs on Windows.
System simulator
Use of the SM78K0 allows the execution of application logical testing and performance
testing on an independent basis from hardware development without having to use an in-
circuit emulator, thereby providing higher development efficiency and software quality.
The SM78K0 should be used in combination with a device file (DF780114) (sold
separately).
Part number: µS××××SM78K0
ID78K0-NS
This debugger is a control program used to debug 78K/0 Series microcontrollers.
It adopts a graphical user interface, which is equivalent visually and operationally to
Windows or OSF/MotifTM. It also has an enhanced debugging function for C language
programs, and thus trace results can be displayed on screen at C-language level by
using the windows integration function which links a trace result with its source program,
disassembled display, and memory display. In addition, by incorporating function
modules such as a task debugger and system performance analyzer, the efficiency of
debugging programs that run on real-time OSs can be improved.
Integrated debugger
(supporting in-circuit emulator
IE-78K0-NS(-A))
It should be used in combination with a device file (sold separately).
Part number: µS××××ID78K0-NS
Remark ×××× in the part number differs depending on the host machine and OS used.
µS××××SM78K0
µS××××ID78K0-NS
××××
AB13
Host Machine
PC-9800 series,
IBM PC/AT compatibles
OS
Supply Medium
Windows (Japanese version) 3.5-inch 2HD FD
Windows (English version)
BB13
AB17
BB17
Windows (Japanese version) CD-ROM
Windows (English version)
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APPENDIX B EMBEDDED SOFTWARE
The following embedded products are available for efficient development and maintenance of the 78K0/KC1
Series.
Real-Time OS
RX78K0
The RX78K0 is a real-time OS conforming to the µITRON specifications.
A tool (configurator) for generating the nucleus of the RX78K0 and multiple information
tables is supplied.
Real-time OS
Used in combination with an assembler package (RA78K0) and device file (DF780114)
(both sold separately).
<Precaution when using RX78K0 in PC environment>
The real-time OS is a DOS-based application. It should be used in the DOS prompt when
using it in Windows.
Part number: µS××××RX78013-∆∆∆∆
Caution To purchase the RX78K0, first fill in the purchase application form and sign the user agreement.
Remark ×××× and ∆∆∆∆ in the part number differ depending on the host machine and OS used.
µS××××RX78013-∆∆∆∆
∆∆∆∆
001
Product Outline
Evaluation object
Maximum Number for Use in Mass Production
Do not use for mass-produced product.
0.1 million units
100K
001M
010M
S01
Mass-production object
1 million units
10 million units
Source program
Host Machine
Object source program for mass production
∆∆∆∆
AA13
AB13
BB13
3P16
3K13
3K15
OS
Supply Medium
3.5-inch 2HD FD
PC-9800 series
Windows (Japanese version)Note
Windows (Japanese version)Note
Windows (English version)Note
HP-UX (Rel. 10.10)
IBM PC/AT compatibles
3.5-inch 2HD FD
HP9000 series 700
SPARCstation
DAT
SunOS (Rel. 4.1.4),
Solaris (Rel. 2.5.1)
3.5-inch 2HD FD
1/4-inch CGMT
Note Can also be operated in DOS environment.
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APPENDIX C REGISTER INDEX
C.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A]
A/D conversion result register (ADCR) .......................................................................................................................216
A/D converter mode register (ADM)............................................................................................................................218
Analog input channel specification register (ADS)......................................................................................................220
Asynchronous serial interface control register 6 (ASICL6)..................................................................................271, 278
Asynchronous serial interface operation mode register 0 (ASIM0).............................................................239, 243, 244
Asynchronous serial interface operation mode register 6 (ASIM6).............................................................265, 273, 274
Asynchronous serial interface reception error status register 0 (ASIS0).............................................................241, 246
Asynchronous serial interface reception error status register 6 (ASIS6).............................................................267, 276
Asynchronous serial interface transmission status register 6 (ASIF6) ................................................................268, 277
[B]
Baud rate generator control register 0 (BRGC0).................................................................................................242, 253
Baud rate generator control register 6 (BRGC6).................................................................................................270, 295
[C]
Capture/compare control register 00 (CRC00) ...........................................................................................................132
Clock monitor mode register (CLM) ............................................................................................................................351
Clock selection register 6 (CKSR6).....................................................................................................................269, 294
[E]
8-bit timer compare register 50 (CR50).......................................................................................................................161
8-bit timer compare register 51 (CR51).......................................................................................................................161
8-bit timer counter 50 (TM50) .....................................................................................................................................161
8-bit timer counter 51 (TM51) .....................................................................................................................................161
8-bit timer H carrier control register 1 (TMCYC1)........................................................................................................180
8-bit timer H compare register 00 (CMP00) ................................................................................................................177
8-bit timer H compare register 01 (CMP01) ................................................................................................................177
8-bit timer H compare register 10 (CMP10) ................................................................................................................177
8-bit timer H compare register 11 (CMP11) ................................................................................................................177
8-bit timer H mode register 0 (TMHMD0)....................................................................................................................178
8-bit timer H mode register 1 (TMHMD1)....................................................................................................................178
8-bit timer mode control register 50 (TMC50) .............................................................................................................164
8-bit timer mode control register 51 (TMC51) .............................................................................................................164
External interrupt falling edge enable register (EGN)..................................................................................................322
External interrupt rising edge enable register (EGP)...................................................................................................322
[I]
Input switch control register (ISC).................................................................................................................................99
Internal memory size switching register (IMS) ............................................................................................................374
Interrupt mask flag register 0H (MK0H) ......................................................................................................................320
Interrupt mask flag register 0L (MK0L)........................................................................................................................320
Interrupt mask flag register 1L (MK1L)........................................................................................................................320
425
Preliminary User’s Manual U16227EJ1V0UD
APPENDIX C REGISTER INDEX
Interrupt request flag register 0H (IF0H) .................................................................................................................... 319
Interrupt request flag register 0L (IF0L)...................................................................................................................... 319
Interrupt request flag register 1L (IF1L)...................................................................................................................... 319
[K]
Key return mode register (KRM) ................................................................................................................................ 332
[L]
Low-voltage detection level selection register (LVIS)................................................................................................. 363
Low-voltage detection register (LVIM)........................................................................................................................ 362
[M]
Main clock mode register (MCM) ............................................................................................................................... 106
Main OSC control register (MOC) .............................................................................................................................. 107
[O]
Oscillation stabilization time counter status register (OSTC) ..............................................................................107, 335
Oscillation stabilization time select register (OSTS)............................................................................................108, 336
[P]
Port 0 (P0).................................................................................................................................................................... 81
Port 1 (P1).................................................................................................................................................................... 83
Port 12 (P12)................................................................................................................................................................ 94
Port 13 (P13)................................................................................................................................................................ 95
Port 2 (P2).................................................................................................................................................................... 89
Port 3 (P3).................................................................................................................................................................... 90
Port 6 (P6).................................................................................................................................................................... 92
Port 7 (P7).................................................................................................................................................................... 93
Port mode register 0 (PM0)...................................................................................................................................96, 135
Port mode register 1 (PM1)...................................................................................................................................96, 167
Port mode register 12 (PM12)...................................................................................................................................... 96
Port mode register 3 (PM3)...................................................................................................................................96, 167
Port mode register 6 (PM6).......................................................................................................................................... 96
Port mode register 7 (PM7).......................................................................................................................................... 96
Power-fail comparison mode register (PFM).............................................................................................................. 221
Power-fail comparison threshold register (PFT)......................................................................................................... 221
Prescaler mode register 00 (PRM00)......................................................................................................................... 134
Priority specification flag register 0H (PR0H)............................................................................................................. 321
Priority specification flag register 0L (PR0L) .............................................................................................................. 321
Priority specification flag register 1L (PR1L) .............................................................................................................. 321
Processor clock control register (PCC) ...................................................................................................................... 103
Pull-up resistor option register 0 (PU0) ........................................................................................................................ 98
Pull-up resistor option register 1 (PU1) ........................................................................................................................ 98
Pull-up resistor option register 12 (PU12) .................................................................................................................... 98
Pull-up resistor option register 3 (PU3) ........................................................................................................................ 98
Pull-up resistor option register 7 (PU7) ........................................................................................................................ 98
[R]
Receive buffer register 0 (RXB0) ............................................................................................................................... 238
426
Preliminary User’s Manual U16227EJ1V0UD
APPENDIX C REGISTER INDEX
Receive buffer register 6 (RXB6)................................................................................................................................264
Reset control flag register (RESF) ..............................................................................................................................349
Ring-OSC mode register (RCM) .................................................................................................................................105
[S]
Serial clock selection register 10 (CSIC10).........................................................................................................304, 307
Serial I/O shift register 10 (SIO10)..............................................................................................................................302
Serial operation mode register 10 (CSIM10)...............................................................................................303, 305, 306
16-bit timer capture/compare register 000 (CR000)....................................................................................................128
16-bit timer capture/compare register 010 (CR010)....................................................................................................129
16-bit timer counter 00 (TM00) ...................................................................................................................................128
16-bit timer mode control register 00 (TMC00) ...........................................................................................................130
16-bit timer output control register 00 (TOC00) ..........................................................................................................132
[T]
Timer clock selection register 50 (TCL50) ..................................................................................................................162
Timer clock selection register 51 (TCL51) ..................................................................................................................162
Transmit buffer register 10 (SOTB10).........................................................................................................................302
Transmit buffer register 6 (TXB6)................................................................................................................................264
Transmit shift register 0 (TXS0)..................................................................................................................................238
[W]
Watch timer operation mode register (WTM)..............................................................................................................199
Watchdog timer enable register (WDTE) ....................................................................................................................208
Watchdog timer mode register (WDTM) .....................................................................................................................207
427
Preliminary User’s Manual U16227EJ1V0UD
APPENDIX C REGISTER INDEX
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
[A]
ADCR:
ADM:
A/D conversion result register ................................................................................................................ 216
A/D converter mode register................................................................................................................... 218
Analog input channel specification register ............................................................................................ 220
Asynchronous serial interface control register 6..............................................................................271, 278
Asynchronous serial interface transmission status register 6..........................................................268, 277
Asynchronous serial interface operation mode register 0........................................................239, 243, 244
Asynchronous serial interface operation mode register 6........................................................265, 273, 274
Asynchronous serial interface reception error status register 0.......................................................241, 246
Asynchronous serial interface reception error status register 6.......................................................267, 276
ADS:
ASICL6:
ASIF6:
ASIM0:
ASIM6:
ASIS0:
ASIS6:
[B]
BRGC0:
BRGC6:
Baud rate generator control register 0.............................................................................................242, 253
Baud rate generator control register 6.............................................................................................270, 295
[C]
CKSR6:
CLM:
Clock selection register 6 ................................................................................................................269, 294
Clock monitor mode register................................................................................................................... 351
8-bit timer H compare register 00........................................................................................................... 177
8-bit timer H compare register 01........................................................................................................... 177
8-bit timer H compare register 10........................................................................................................... 177
8-bit timer H compare register 11........................................................................................................... 177
16-bit timer capture/compare register 000.............................................................................................. 128
16-bit timer capture/compare register 010.............................................................................................. 129
8-bit timer compare register 50............................................................................................................... 161
8-bit timer compare register 51............................................................................................................... 161
Capture/compare control register 00...................................................................................................... 132
Serial clock selection register 10.....................................................................................................304, 307
Serial operation mode register 10 ...........................................................................................303, 305, 306
CMP00:
CMP01:
CMP10:
CMP11:
CR000:
CR010:
CR50:
CR51:
CRC00:
CSIC10:
CSIM10:
[E]
EGN:
EGP:
External interrupt falling edge enable register ........................................................................................ 322
External interrupt rising edge enable register......................................................................................... 322
[I]
IF0H:
IF0L:
IF1L:
IMS:
ISC:
Interrupt request flag register 0H............................................................................................................ 319
Interrupt request flag register 0L ............................................................................................................ 319
Interrupt request flag register 1L ............................................................................................................ 319
Internal memory size switching register.................................................................................................. 374
Input switch control register...................................................................................................................... 99
[K]
KRM:
Key return mode register........................................................................................................................ 332
[L]
LVIM:
LVIS:
428
Low-voltage detection register................................................................................................................ 362
Low-voltage detection level selection register ........................................................................................ 363
Preliminary User’s Manual U16227EJ1V0UD
APPENDIX C REGISTER INDEX
[M]
MCM:
MK0H:
MK0L:
MK1L:
MOC:
Main clock mode register ........................................................................................................................106
Interrupt mask flag register 0H................................................................................................................320
Interrupt mask flag register 0L.................................................................................................................320
Interrupt mask flag register 1L.................................................................................................................320
Main OSC control register.......................................................................................................................107
[O]
OSTC:
OSTS:
Oscillation stabilization time counter status register........................................................................107, 335
Oscillation stabilization time select register.....................................................................................108, 336
[P]
P0:
Port 0 ........................................................................................................................................................81
Port 1 ........................................................................................................................................................83
Port 12 ......................................................................................................................................................94
Port 13 ......................................................................................................................................................95
Port 2 ........................................................................................................................................................89
Port 3 ........................................................................................................................................................90
Port 6 ........................................................................................................................................................92
Port 7 ........................................................................................................................................................93
Processor clock control register ..............................................................................................................103
Power-fail comparison mode register......................................................................................................221
Power-fail comparison threshold register................................................................................................221
Port mode register 0..........................................................................................................................96, 135
Port mode register 1..........................................................................................................................96, 167
Port mode register 12................................................................................................................................96
Port mode register 3..........................................................................................................................96, 167
Port mode register 6..................................................................................................................................96
Port mode register 7..................................................................................................................................96
Priority specification flag register 0H.......................................................................................................321
Priority specification flag register 0L........................................................................................................321
Priority specification flag register 1L........................................................................................................321
Prescaler mode register 00 .....................................................................................................................134
Pull-up resistor option register 0................................................................................................................98
Pull-up resistor option register 1................................................................................................................98
Pull-up resistor option register 12..............................................................................................................98
Pull-up resistor option register 3................................................................................................................98
Pull-up resistor option register 7................................................................................................................98
P1:
P12:
P13:
P2:
P3:
P6:
P7:
PCC:
PFM:
PFT:
PM0:
PM1:
PM12:
PM3:
PM6:
PM7:
PR0H:
PR0L:
PR1L:
PRM00:
PU0:
PU1:
PU12:
PU3:
PU7:
[R]
RCM:
RESF:
RXB0:
RXB6:
Ring-OSC mode register.........................................................................................................................105
Reset control flag register .......................................................................................................................349
Receive buffer register 0.........................................................................................................................238
Receive buffer register 6.........................................................................................................................264
[S]
SIO10:
Serial I/O shift register 10........................................................................................................................302
SOTB10: Transmit buffer register 10 ......................................................................................................................302
429
Preliminary User’s Manual U16227EJ1V0UD
APPENDIX C REGISTER INDEX
[T]
TCL50:
TCL51:
TM00:
TM50:
TM51:
TMC00:
TMC50:
TMC51:
Timer clock selection register 50............................................................................................................ 162
Timer clock selection register 51............................................................................................................ 162
16-bit timer counter 00............................................................................................................................ 128
8-bit timer counter 50 ............................................................................................................................. 161
8-bit timer counter 51 ............................................................................................................................. 161
16-bit timer mode control register 00...................................................................................................... 130
8-bit timer mode control register 50........................................................................................................ 164
8-bit timer mode control register 51........................................................................................................ 164
TMCYC1: 8-bit timer H carrier control register 1..................................................................................................... 180
TMHMD0: 8-bit timer H mode register 0.................................................................................................................. 178
TMHMD1: 8-bit timer H mode register 1.................................................................................................................. 178
TOC00:
TXB6:
TXS0:
16-bit timer output control register 00..................................................................................................... 132
Transmit buffer register 6 ....................................................................................................................... 264
Transmit shift register 0.......................................................................................................................... 238
[W]
WDTE:
WDTM:
WTM:
Watchdog timer enable register.............................................................................................................. 208
Watchdog timer mode register ............................................................................................................... 207
Watch timer operation mode register ..................................................................................................... 199
430
Preliminary User’s Manual U16227EJ1V0UD
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CS 02.3
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