UPD750006CU-XXX-A [NEC]

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PDIP42, 0.600 INCH, SHRINK, LEAD FREE, PLASTIC, DIP-42;

UPD750006CU-XXX-A


型号：	UPD750006CU-XXX-A
厂家：	NEC
描述：	Microcontroller, 4-Bit, MROM, 6MHz, MOS, PDIP42, 0.600 INCH, SHRINK, LEAD FREE, PLASTIC, DIP-42 时钟微控制器光电二极管外围集成电路
文件：	总84页 (文件大小：567K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD750004,750006,750008,750004(A),750006(A),750008(A)

4 BIT SINGLE-CHIP MICROCONTROLLER

The µPD750008 is one of the 75XL series 4-bit single-chip microcontrollers, which provide data processing

capability equal to that of an 8-bit microcontroller.

The µPD750008 is an advanced model of the µPD75008. It features an enhanced CPU function and enables high-

speed operation at a low voltage of 2.2 V. It can be substituted for the µPD75008. In addition, it is best suited to

applications using batteries. The µPD750008(A) has a higher reliability than the µPD750008.

A built-in one-time PROM product, µPD75P0016, is also available. It is suitable for small-scale production and

evaluation of application systems.

The following user’s manual describes the details of the functions of the µPD750008. Be sure to read it

before designing application systems.

µPD750008 User’s Manual: U10740E

FEATURES

• Capable of low-voltage operation: VDD = 2.2 to 5.5 V

• Internal memory

•

Function for specifying the instruction execution time

(useful for high-speed operation and saving power)

0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (when operating at

4.19 MHz)

Program memory (ROM)

: 4096 × 8 bits (µPD750004 and µPD750004(A))

: 6144 × 8 bits (µPD750006 and µPD750006(A))

: 8192 × 8 bits (µPD750008 and µPD750008(A))

Data memory (RAM)

0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (when operating at

6.0 MHz)

122 µs (when operating at 32.768 kHz)

• Enhanced timer function (4 channels)

• Can be easily substituted for the µPD75008 because

this product succeeds to the functions and instructions

of the µPD75008.

: 512 × 4 bits

APPLICATIONS

• µPD750004, µPD750006, and µPD750008

Cordless telephones, radio devices, audio products, and home electric appliances

• µPD750004(A), µPD750006(A), and µPD750008(A)

Electrical equipment for automobiles

The µPD750004, µPD750006, µPD750008, µPD750004(A), µPD750006(A), and µPD750008(A) differ only in

quality grade. In this manual, the µPD750008 is described unless otherwise specified. Users of other than the

µPD750008 should read µPD750008 as referring to the pertinent product.

When the description differs among µPD750004, µPD750006, and µPD750008, they also refer to the pertinent

(A) products.

µPD750004 → µPD750004(A), µPD750006 → µPD750006(A), µPD750008 → µPD750008(A)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. U10738EJ3V2DS00 (3rd edition)

Date Published August 2005 N CP (K)

Printed in Japan

The mark

shows major revised points.

1994

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

ORDERING INFORMATION

Part number

Package

Quality grade

µPD750004CU-×××

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Standard

Standard

Standard

Standard

Standard

Standard

Standard

Standard

Standard

Standard

Standard

Standard

Special

µPD750004CU-×××-A

µPD750004GB-×××-3BS-MTX

µPD750004GB-×××-3BS-MTX-A

µPD750006CU-×××

µPD750006CU-×××-A

µPD750006GB-×××-3BS-MTX

µPD750006GB-×××-3BS-MTX-A

µPD750008CU-×××

µPD750008CU-×××-A

µPD750008GB-×××-3BS-MTX

µPD750008GB-×××-3BS-MTX-A

µPD750004CU(A)-×××

µPD750004GB(A)-×××-3BS-MTX

µPD750006CU(A)-×××

Special

Special

µPD750006GB(A)-×××-3BS-MTX

µPD750008CU(A)-×××

Special

Special

µPD750008GB(A)-×××-3BS-MTX

Special

Remarks 1. Products with “-A” at the end of the part number are lead-free products.

2. ××× is a mask ROM code number.

Please refer to “Quality Grades on NEC Semiconductor Devices” (Document No. C11531E) published by NEC

Electronics Corporation to know the specification of quality grade on the devices and its recommended applications.

DIFFERENCES BETWEEN µPD75000× AND µPD75000×(A)

µPD750004

µPD750006

µPD750008

µPD750004(A)

µPD750006(A)

µPD750008(A)

Product number

Item

Quality grade

Standard

Special

Data Sheet U10738EJ3V2DS

2

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

FUNCTIONS

Function

Item

• 0.95, 1.91, 3.81, 15.3 µs (when the main system clock operates at 4.19 MHz)

• 0.67, 1.33, 2.67, 10.7 µs (when the main system clock operates at 6.0 MHz)

• 122 µs (when the subsystem clock operates at 32.768 kHz)

Command execution

time

Internal memory

ROM 4096 × 8 bits (µPD750004)

6144 × 8 bits (µPD750006)

8192 × 8 bits (µPD750008)

RAM 512 × 4 bits

General-purpose

register

• When operating in 4 bits: 8 × 4 banks

• When operating in 8 bits: 4 × 4 banks

CMOS input

I/O port

8

Can incorporate 7 pull-up resistors that are specified with the software.

CMOS I/O

18

Can directly drive the LED.

Can incorporate 18 pull-up resistors that are specified with the software.

N-ch open

drain I/O

8

Can directly drive the LED.

Can withstand 13 V.

Can incorporate pull-up resistors that are specified with the mask option.

Total

34

Timer

4 channels

• 8-bit timer/event counter: 1 channel

• 8-bit timer counter: 1 channel

• Basic interval timer/watchdog timer: 1 channel

• lock timer: 1 channel

• Three-wire serial I/O mode ... switchable between the start LSB and the start MSB

Serial interface

• Two-wire serial I/O mode

• SBI mode

16 bits

Bit sequential buffer (BSB)

Clock output (PCL)

• Φ, 524 kHz, 262 kHz, 65.5 kHz (when the main system clock operates at 4.19 MHz)

• Φ, 750 kHz, 375 kHz, 93.8 kHz (when the main system clock operates at 6.0 MHz)

• 2 kHz, 4 kHz, 32 kHz (when the main system clock operates at 4.19 MHz or when the

subsystem clock operates at 32.768 kHz)

Buzzer output (BUZ)

• 2.93 kHz, 5.86 kHz, 46.9 kHz (when the main system clock operates at 6.0 MHz)

External :

Internal :

3

4

Vectored interrupt

Test input

External :

Internal :

1

1

• Ceramic or crystal oscillator for main system clock

• Crystal oscillator for subsystem clock

System clock oscillator

Standby

STOP/HALT mode

TA = -40 to +85 °C

Operating ambient

temperature range

VDD = 2.2 to 5.5 V

Supply voltage

Package

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Data Sheet U10738EJ3V2DS

3

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) .........................................................................................

2. BLOCK DIAGRAM .....................................................................................................................

3. PIN FUNCTIONS ........................................................................................................................

6

8

9

9

3.1

3.2

3.3

3.4

PORT PINS ......................................................................................................................................

NON-PORT PINS ............................................................................................................................

PIN INPUT/OUTPUT CIRCUITS .....................................................................................................

CONNECTION OF UNUSED PINS ................................................................................................

10

11

13

4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION........................................................................ 14

4.1

DIFFERENCES BETWEEN Mk Ι MODE AND Mk ΙΙ MODE ........................................................

14

4.2

SETTING OF THE STACK BANK SELECTION REGISTER (SBS) ............................................

15

5. MEMORY CONFIGURATION .................................................................................................... 16

6. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 21

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

6.9

DIGITAL I/O PORTS .......................................................................................................................

CLOCK GENERATOR ....................................................................................................................

CONTROL FUNCTIONS OF SUBSYSTEM CLOCK OSCILLATOR............................................

CLOCK OUTPUT CIRCUIT ............................................................................................................

BASIC INTERVAL TIMER/WATCHDOG TIMER...........................................................................

CLOCK TIMER ................................................................................................................................

TIMER/EVENT COUNTER ..............................................................................................................

SERIAL INTERFACE ......................................................................................................................

BIT SEQUENTIAL BUFFER ...........................................................................................................

21

21

23

24

25

26

27

30

32

7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS ............................................................... 33

8. STANDBY FUNCTION ............................................................................................................... 35

9. RESET FUNCTION..................................................................................................................... 36

10. MASK OPTION ........................................................................................................................... 39

11. INSTRUCTION SET.................................................................................................................... 40

12. ELECTRICAL CHARACTERISTICS ......................................................................................... 53

13. CHARACTERISTIC CURVE (REFERENCE VALUES) ............................................................ 67

Data Sheet U10738EJ3V2DS

4

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

14. PACKAGE DRAWINGS ............................................................................................................. 70

15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 73

APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016 ..................... 75

APPENDIX B DEVELOPMENT TOOLS.......................................................................................... 77

APPENDIX C RELATED DOCUMENTS ......................................................................................... 81

Data Sheet U10738EJ3V2DS

5

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

1. PIN CONFIGURATION (TOP VIEW)

•

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

µPD750004CU-×××, µPD750004CU-×××-A, µPD750004CU(A)-×××

µPD750006CU-×××, µPD750006CU-×××-A, µPD750006CU(A)-×××

µPD750008CU-×××, µPD750008CU-×××-A, µPD750008CU(A)-×××

XT1

XT2

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

VSS

2

P40

RESET

X1

3

P41

4

P42

X2

5

P43

P33

6

P50

P32

7

P51

P31

8

P52

P30

9

P53

P81

10

11

12

13

14

15

16

17

18

19

20

21

P60/KR0

P61/KR1

P62/KR2

P63/KR3

P70/KR4

P71/KR5

P72/KR6

P73/KR7

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

P80

P03/SI/SB1

P02/SO/SB0

P01/SCK

P00/INT4

P13/TI0

P12/INT2

P11/INT1

P10/INT0

IC

V^DD

IC : Internally connected (Connect directly to V^DD.)

Data Sheet U10738EJ3V2DS

6

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

•

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

µPD750004GB-×××-3BS-MTX, µPD750004GB-×××-3BS-MTX-A, µPD750004GB(A)-×××-3BS-MTX

µPD750006GB-×××-3BS-MTX, µPD750006GB-×××-3BS-MTX-A, µPD750006GB(A)-×××-3BS-MTX

µPD750008GB-×××-3BS-MTX, µPD750008GB-×××-3BS-MTX-A, µPD750008GB(A)-×××-3BS-MTX

44 43 42 41 40 39 38 37 36 35 34

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

P60/KR0

P53

1

33

32

31

30

29

28

27

26

25

24

23

P13/TI0

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P80

2

3

4

5

6

7

P81

8

P30

P52

9

P31

P51

10

P32

P50

11

P33

12 13 14 15 16 17 18 19 20 21 22

IC : Internally connected (Connect directly to VDD.)

PIN NAMES

P00 - 03

P10 - 13

P20 - 23

P30 - 33

P40 - 43

P50 - 53

P60 - 63

P70 - 73

P80, 81

:

:

:

:

:

:

:

:

:

Port 0

SO

:

:

:

:

Serial Output

Serial Data Bus 0, 1

Reset

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

SB0, SB1

RESET

TI0

Timer Input 0

PTO0, PTO1 : Programmable Timer Output 0, 1

BUZ

:

:

:

:

:

:

:

:

Buzzer Clock

PCL

Programmable Clock

INT0, 1, 4

INT2

External Vectored Interrupt 0, 1, 4

External Test Input 2

KR0 - KR7 : Key Return 0 - 7

X1, X2

XT1, XT2

NC

Main System Clock Oscillation 1, 2

Subsystem Clock Oscillation 1, 2

No Connection

SCK

SI

:

:

Serial Clock

Serial Input

IC

Internally Connected

Data Sheet U10738EJ3V2DS

7

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

2. BLOCK DIAGRAM

BIT SEQ.

BUFFER (16)

BASIC INTERVAL

TIMER/

WATCHDOG

TIMER

PROGRAM

COUNTER

INTBT

SP (8)

PORT 0

PORT 1

4

4

P00 - P03

P10 - P13

CY

SBS

8-BIT

TI0/P13

ALU

TIMER/EVENT

COUNTER #0

PTO0/P20

BANK

INTT0 TOUT0

PORT 2

PORT 3

PORT 4

PORT 5

4

4

4

4

8-BIT TIMER

COUNTER #1

P20 - P23

P30 - P33

PTO1/P21

GENERAL

REGISTER

INTT1

PROGRAM

MEMORY^Note

(ROM)

SI/SB1/P03

SO/SB0/P02

SCK/P01

CLOCKED

SERIAL

INTERFACE

DECODE

AND

CONTROL

DATA

MEMORY

(RAM)

P40 - P43

P50 - P53

512 × 4 BITS

INTCSI

TOUT0

INT0/P10

INT1/P11

INT2/P12

INTERRUPT

CONTROL

PORT 6

PORT 7

PORT 8

4

4

2

P60 - P63

P70 - P73

P80, P81

INT4/P00

KR0/P60-

KR7/P73

8

fx/2^N

CPU CLOCK

Φ

SYSTEM CLOCK

GENERATOR

WATCH

TIMER

CLOCK

OUTPUT

CONTROL

BUZ/P23

CLOCK

DIVIDER

STAND BY

CONTROL

SUB

MAIN

INTW

PCL/P22

IC

V

XT1 XT2

X1 X2

DD VSS RESET

Note The ROM capacity depends on the product.

Data Sheet U10738EJ3V2DS

8

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3. PIN FUNCTIONS

3.1 PORT PINS

8-bit

I/O

I/O circuit

type^{Note 1}

Shared

pin

Input/

When reset

Input

Pin name

Function

output

Input

I/O

B

×

×

×

×

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

INT4

SCK

SO/SB0

SI/SB1

INT0

INT1

INT2

TI0

4-bit input port (PORT0).

For P01 - P03, built-in pull-up resistors

can be connected by software in units

of 3 bits.

F

F

-A

-B

-C

-C

I/O

M

B

I/O

Input

Input

Input

Input

4-bit input port (PORT1).

Built-in pull-up resistors can be

connected by software in units of 4 bits.

A noise eliminator can be selected only

when the P10/INT0 pin is used.

PTO0

PTO1

PCL

E-B

I/O

4-bit I/O port (PORT2).

Built-in pull-up resistors can be

connected by software in units of 4 bits.

BUZ

-

E-B

M-D

M-D

I/O

I/O

I/O

I/O

Programmable 4-bit I/O port (PORT3).

I/O can be specified bit by bit. Built-in

pull-up resistors can be connected by

software in units of 4 bits.

P30 - P33

P40 - P43^{Notes 2}

-

-

High level (when

pull-up resistors

are provided) or

high impedance

N-ch open-drain 4-bit I/O port (PORT4).

A pull-up resistor can be provided bit by

bit (mask option). Withstand voltage is

13 V in open-drain mode.

P50 - P53^{Notes 2}

High level (when

pull-up resistors

are provided) or

high impedance

N-ch open-drain 4-bit I/O port (PORT5).

A pull-up resistor can be provided bit by

bit (mask option). Withstand voltage is

13 V in open-drain mode.

F

Input

Input

Input

-A

-A

Programmable 4-bit I/O port (PORT6).

I/O can be specified bit by bit. Built-in

pull-up resistors can be connected by

software in units of 4 bits.

P60

P61

P62

P63

P70

P71

P72

P73

P80

P81

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

-

F

I/O

I/O

4-bit I/O port (PORT7).

Built-in pull-up resistors can be

connected by software in units of 4 bits.

×

E-B

2-bit I/O port (PORT8).

Built-in pull-up resistors can be

connected by software in units of 2

bits.

-

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. When pull-up resistors that can be specified with the mask option are not incorporated (when pins are used

as N-ch open-drain input ports), the input leak low current increases when an input instruction or bit

operation instruction is executed.

Data Sheet U10738EJ3V2DS

9

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3.2 NON-PORT PINS

Input/

Shared

pin

I/O circuit

type^{Note 1}

Pin name

Function

When reset

Input

output

B

TI0

Input

P13

Inputs external event pulse to the timer/event

counter

-C

PTO0

PTO1

PCL

Output

P20

P21

P22

P23

Timer/event counter output

Timer counter output

Clock output

Input

E-B

BUZ

Arbitrary frequency output (for buzzer output or

system clock trimming)

F

F

SCK

I/O

P01

P02

Serial clock I/O

Input

-A

-B

SO/SB0

Serial data output

Serial data bus I/O

M

SI/SB1

INT4

P03

P00

P10

Serial data input

-C

Serial data bus I/O

Input

Input

Edge detection vectored interrupt input (both

rising and falling edges are detected)

B

B

INT0

Edge detection vectored interrupt input

-C

Input

Note 2

(detection edge selectable). A noise eliminator

can be selected when INT0/P10 is used.

Note 3

Note 3

INT1

P11

P12

INT2

Input

I/O

Rising edge detection testable input

KR0 - KR3

KR4 - KR7

X1

P60 - P63 Falling edge detection testable input

P70 - P73 Falling edge detection testable input

Input

Input

-

F

-A

-A

F

I/O

Input

-

Crystal/ceramic connection pin for main system

-

clock generation. When external clock signal is

used, it is applied to X1, and its reverse phase

signal is applied to X2.

X2

-

XT1

Input

-

Crystal connection pin for subsystem clock

generation. When external clock signal is used, it

is applied to XT1, and it reverse phase signal is

applied to XT2.

-

-

XT2

-

XT1 can be used as a 1-bit input (test).

B

RESET

IC

Input

-

System reset input (active low)

-

-

-

-

Internally connected. (To be connected directly to

V^DD)

-

V

V

DD

SS

-

-

-

-

Positive power supply

Ground potential

-

-

-

-

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. With a noise eliminator/asynchronously selectable

3. Asynchronous

Data Sheet U10738EJ3V2DS

10

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3.3 PIN INPUT/OUTPUT CIRCUITS

The input/output circuit of each µPD750008 pin is shown below in a simplified manner.

Type D

Type A

VDD

VDD

Data

P-ch

P-ch

OUT

IN

Output

disable

N-ch

N-ch

Push-pull output which can be set to high-impedance output

(off for both P-ch and N-ch)

CMOS input buffer

Type B

Type E-B

V^DD

P.U.R.

P.U.R.

enable

P-ch

IN

Data

IN/OUT

Type D

Output

disable

Type A

Schmitt trigger input with hysteresis

P.U.R.: Pull-Up Resistor

Type B-C

Type F-A

VDD

V

DD

P.U.R.

P-ch

P.U.R.

P.U.R.

enable

P.U.R.

enable

P-ch

Data

IN/OUT

Type D

Type B

Output

disable

IN

P.U.R.: Pull-Up Resistor

P.U.R.: Pull-Up Resistor

Data Sheet U10738EJ3V2DS

11

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Type M-C

Type F-B

VDD

V

DD

P.U.R.

P-ch

P.U.R.

P-ch

P.U.R.

enable

P.U.R.

enable

Output

disable

(P)

VDD

IN/OUT

P-ch

IN/OUT

Data

N-ch

Data

Output

disable

Output

disable

N-ch

Output

disable

(N)

P.U.R.: Pull-Up Resistor

P.U.R.: Pull-Up Resistor

Type M-D

VDD

P.U.R.

(Mask option)

IN/OUT

N-ch

Data

(Withstand

voltage:

+13 V)

Output

disable

VDD

Input

instruction

P-ch

P.U.R^Note

Voltage

restriction

circuit

(Withstand voltage: +13 V)

P.U.R.: Pull-Up Resistor

Note Pull-up resistor that operates only when pull-up resistors

that can be specified with the mask option are not

incorporated and an input instruction is executed.

(When the pin is low, the current flows from V^DDto the pin.)

Data Sheet U10738EJ3V2DS

12

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3.4 CONNECTION OF UNUSED PINS

Table 3-1 Connection of Unused Pins

Pin name

Recommended connection

P00/INT4

To be connected to VSS or VDD

To be connected to VSS or VDD through a

separate resistor

P01/SCK

P02/SO/SB0

P03/SI/SB1

P10/INT0 - P12/INT2

P13/TI0

To be connected to VSS

To be connected to VSS or VDD

P20/PTO0

P21/PTO1

P22/PCL

Input state

: To be connected to VSS or VDD

through a separate resistor

Output state : To be left open

P23/BUZ

P30 - P33

P40 - P43

Input state

: To be connected to VSS

Output state : To be connected to VSS

(Do not connect to a pull-up

resistor specified with a mask

option.)

P50 - P53

P60/KR0 - P63/KR3

P70/KR4 - P73/KR7

P80, P81

Input state

: To be connected to V^SSor VDD

through a separate resistor

Output state : To be left open

Note

XT1

To be connected to VSS

To be left open

Note

XT2

IC

To be connected directly to VDD

Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-

in feedback resistor).

Data Sheet U10738EJ3V2DS

13

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

4. Mk Ι MODE/Mk ΙΙ MODE SWITCH FUNCTION

4.1 DIFFERENCES BETWEEN Mk Ι MODE AND Mk ΙΙ MODE

The CPU of the µPD750008 has two modes (Mk Ι mode and Mk ΙΙ mode) and which mode is used is selectable.

Bit 3 of the stack bank selection register (SBS) determines the mode.

• Mk Ι mode: This mode has the upward compatibility with the µPD75008.

It can be used in the 75XL CPUs having a ROM of up to 16 KB.

• Mk ΙΙ mode: This mode is not compatible with the µPD75008.

It can be used in all 75XL CPUs, including those having a ROM of 16 KB or more.

Table 4-1 shows the differences between Mk Ι mode and Mk ΙΙ mode.

Table 4-1 Differences between Mk Ι Mode and Mk ΙΙ Mode

Mk Ι mode

2 bytes

Mk ΙΙ mode

3 bytes

Number of stack bytes in a

subroutine instruction

BRA !addr1 instruction

None

Available

CALLA !addr1 instruction

CALL !addr instruction

CALLF !faddr instruction

3 machine cycles

2 machine cycles

4 machine cycles

3 machine cycles

Caution Mk ΙΙ mode can be used to support a program area larger than 16K bytes in the 75X series or 75XL

series. This mode enhances a software compatibility with products whose program area is larger

than 16K bytes. In Mk ΙΙ mode, one more stack byte is required for execution of subroutine call

instructions per stack compared with Mk Ι mode. When a CALL !addr or CALLF !faddr instruction

is executed, it takes one more machine cycle. Therefore, Mk Ι mode should be used for applications

for which RAM efficiency or processing capabilities is more critical than a software compatibility.

Data Sheet U10738EJ3V2DS

14

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

4.2 SETTING OF THE STACK BANK SELECTION REGISTER (SBS)

The Mk Ι mode and Mk ΙΙ mode are switched by stack bank selection register. Fig. 4-1 shows the register

configuration.

The stack bank selection register is set with a 4-bit memory operation instruction. To use the CPU in Mk Ι mode,

initialize the register to 100×B^Noteat the beginning of the program. To use the CPU in Mk ΙΙ mode, initialize it to

000×B^Note

Note Specify the desired value in ×.

Fig. 4-1 Stack Bank Selection Register Format

.

Address

F84H

3

2

1

0

Symbol

SBS

SBS3 SBS2 SBS1 SBS0

Stack area designation

0

0

0

1

Memory bank 0

Memory bank 1

Other settings are inhibited.

0

Bit 2 must be set to 0.

Mode switching designation

0

1

Mk ΙΙ mode

Mk Ι mode

Caution The CPU operates in Mk Ι mode after the RESET signal is issued, because bit 3 of SBS is set to 1.

Set bit 3 of SBS to 0 (Mk ΙΙ mode) to use the CPU in Mk ΙΙ mode.

Data Sheet U10738EJ3V2DS

15

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

5. MEMORY CONFIGURATION

• Program memory (ROM) : 4096 × 8 bits (0000H-0FFFH): µPD750004

6144 × 8 bits (0000H-17FFH): µPD750006

8192 × 8 bits (0000H-1FFFH): µPD750008

• 0000H to 0001H

Vector address table for holding the RBE and MBE values and program start address when a RESET signal is

issued (allowing a reset start at an arbitrary address)

• 0002H to 000DH

Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt

(allowing interrupt processing to be started at an arbitrary address)

• 0020H to 007FH

Table area referenced by the GETI instruction

• Data memory (RAM)

• Data area

: 512 × 4 bits (000H to 1FFH)

• Peripheral hardware area: 128 × 4 bits (F80H to FFFH)

Data Sheet U10738EJ3V2DS

16

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-1 Program Memory Map (in µPD750004)

Address

7

6

5

0

4

0

0

0 0 0 H MBE RBE

0 0 2 H MBE RBE

0 0 4 H MBE RBE

Internal reset start address

Internal reset start address

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

0

0

0

0

INTBT/INT4

INTBT/INT4

start address

start address

INT0

INT0

start address

start address

CALLF

! faddr

instruction

entry

address

Branch address

of BR BCXA, BR

BCDE, BR !addr,

BRA !addr1^Noteor

CALLA !addr1^Note

instruction

0 0 6 H MBE RBE

0 0 8 H MBE RBE

0 0 A H MBE RBE

0 0 C H MBE RBE

0

0

0

0

0

0

0

0

INT1

start address

start address

start address

start address

start address

start address

start address

start address

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

(high-order 4 bits)

(low-order 8 bits)

INT1

INTCSI

INTCSI

INTT0

INTT0

INTT1

INTT1

CALL !addr

instruction

subroutine entry

address

BR $addr

instruction relative

branch address

-15 to -1,

+2 to +16

BRCB

!caddr

instruction

branch

address

0 2 0 H

GETI instruction reference table

0 7 F H

0 8 0 H

Branch destination

address and

subroutine entry

address when

GETI instruction

is executed

7 F F H

8 0 0 H

F F F H

Note Can be used only in the Mk ΙΙ mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with

only the 8 low-order bits of the PC changed.

Data Sheet U10738EJ3V2DS

17

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-2 Program Memory Map (in µPD750006)

Address

7

6

5

0

0

0 0 0 0 H

MBE RBE

Internal reset start address

Internal reset start address

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

0 0 0 2 H MBE RBE

0 0 0 4 H MBE RBE

0

0

INTBT/INT4

INTBT/INT4

INT0

start address

start address

start address

(low-order 8 bits)

(high-order 5 bits)

Branch address

of BR BCXA, BR

BCDE, BR !addr,

BRA !addr1^Noteor

CALLA !addr1^Note

instruction

(low-order 8 bits)

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

INT0

INT1

start address

start address

CALLF

!faddr

instruction

entry

0 0 0 6 H MBE RBE

0 0 0 8 H MBE RBE

0

0

address

INT1

start address

start address

CALL !addr

instruction

subroutine entry

address

INTCSI

(low-order 8 bits)

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

INTCSI

INTT0

start address

start address

BR $addr

instruction relative

branch address

0 0 0 A H MBE RBE

0 0 0 C H MBE RBE

0

0

-15 to -1,

+2 to +16

INTT0

INTT1

start address

start address

(low-order 8 bits)

INTT1

BRCB !caddr

start address

instruction

branch

address

0 0 2 0 H

GETI instruction reference table

0 0 7 F H

0 0 8 0 H

Branch destination

address and

subroutine entry

address when GETI

instruction is executed

0 7 F F H

0 8 0 0 H

0 F F F H

1 0 0 0 H

BRCB !caddr

instruction

branch

address

1 7 F F H

Note

Can be used only in the Mk ΙΙ mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with

only the 8 low-order bits of the PC changed.

Data Sheet U10738EJ3V2DS

18

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-3 Program Memory Map (in µPD750008)

Address

7

6

5

0

0

0 0 0 0 H

MBE RBE

Internal reset start address

Internal reset start address

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

0 0 0 2 H MBE RBE

0 0 0 4 H MBE RBE

0

0

INTBT/INT4

INTBT/INT4

INT0

start address

start address

start address

(low-order 8 bits)

(high-order 5 bits)

Branch address

of BR BCXA, BR

BCDE, BR !addr,

BRA !addr1 or

CALLA !addr1^Note

instruction

(low-order 8 bits)

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

INT0

INT1

start address

start address

CALLF

!faddr

instruction

entry

0 0 0 6 H MBE RBE

0 0 0 8 H MBE RBE

0

0

address

INT1

start address

start address

CALL !addr

instruction

subroutine entry

address

INTCSI

(low-order 8 bits)

(high-order 5 bits)

(low-order 8 bits)

(high-order 5 bits)

INTCSI

INTT0

start address

start address

BR $addr

instruction relative

branch address

0 0 0 A H MBE RBE

0 0 0 C H MBE RBE

0

0

-15 to -1,

+2 to +16

INTT0

INTT1

start address

start address

(low-order 8 bits)

INTT1

BRCB !caddr

start address

instruction

branch

address

0 0 2 0 H

GETI instruction reference table

0 0 7 F H

0 0 8 0 H

Branch destination

address and

subroutine entry

address when GETI

instruction is executed

0 7 F F H

0 8 0 0 H

0 F F F H

1 0 0 0 H

BRCB !caddr

instruction

branch

address

1 F F F H

Note Can be used only in the Mk ΙΙ mode.

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address with

only the 8 low-order bits of the PC changed.

Data Sheet U10738EJ3V2DS

19

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 5-4 Data Memory Map

Data memory

Memory bank

000H

Area for

general-purpose

(32 × 4)

register

01FH

020H

0

256 × 4

(224 × 4)

Data area

Static RAM

(512 × 4)

Stack

area^Note

0FFH

100H

256 × 4

1

1FFH

F80H

Not contained

Peripheral

hardware area

128 × 4

15

FFFH

Note Memory bank 0 or 1 can be selected as the stack area.

Data Sheet U10738EJ3V2DS

20

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6. PERIPHERAL HARDWARE FUNCTIONS

6.1 DIGITAL I/O PORTS

The µPD750008 has the following three types of I/O port:

• 8 CMOS input pins (PORT0 and PORT1)

• 18 CMOS I/O pins (PORT2, PORT3, and PORT6 to PORT8)

• 8 N-ch open-drain I/O pins (PORT4 and PORT5)

Total: 34 pins

Table 6-1 Digital Ports and Their Features

Operation and feature

Remarks

Port name

PORT0

Function

4-bit input

Also used as INT4, SCK,

SO/SB0, or SI/SB1.

When the serial interface function is used, dual-function pins

function as output pins in some operation modes.

Also used as INT0, INTI,

INT2 or TI0.

PORT1

PORT2

4-bit input port

4-bit I/O

Also used as PTO0,

PTO1, PCL, or BUZ.

Allows input or output mode setting in units of 4 bits.

Allows input or output mode setting in units of 1 bit.

-

PORT3

PORT4

4-bit I/O (N-ch

open-drain can

withstand 13 V)

Allows input or output mode setting in

units of 4 bits. Whether to use pull-up

resistors can be specified bit by bit with

the mask option.

Ports 4 and 5 can be

paired, allowing data

I/O in units of 8 bits.

PORT5

PORT6

PORT7

PORT8

4-bit I/O

Allows input or output mode setting in

units of 1 bit.

Ports 6 and 7 can be

paired, allowing data

I/O in units of 8 bits.

Also used as one of KR0

to KR3.

Allows input or output mode setting in

units of 4 bits.

Also used as one of KR4

to KR7.

2-bit I/O

-

Allows input or output mode setting in units of 2 bits.

6.2 CLOCK GENERATOR

The clock generator generates clocks which are supplied to the peripheral hardware in the CPU. Fig. 6-1 shows

the configuration of the clock generator.

Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control

register (SCC).

The main system clock and subsystem clock are used.

The instruction execution time can be made variable.

• 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (when the main system clock is at 4.19 MHz)

• 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (when the main system clock is at 6.0 MHz)

• 122 µs (when the subsystem clock is at 32.768 kHz)

Data Sheet U10738EJ3V2DS

21

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Fig. 6-1 Clock Generator Block Diagram

•

•

•

•

•

•

•

Basic interval timer (BT)

Timer/event counter

Timer counter

Serial interface

Clock timer

XT1

f

f

XT

Subsystem

clock generator

Clock timer

XT2

X1

INT0 noise eliminator

Clock output circuit

X

1/1 to 1/4096

Main system

Frequency divider

clock generator

X2

1/2 1/4 1/16

Selec-

tor

Oscillator

disable

signal

WM.3

SCC

Frequency

divider

SCC3

Selec-

tor

1/4

Φ

CPU

INT0 noise

eliminator

Clock

•

•



SCC0













•

PCC

output

circuit

PCC0

PCC1

PCC2

PCC3

4

HALT flip-flop

S

HALT^Note

STOP^Note

Q

R

PCC2, PCC3

clear signal

STOP flip-flop

Wait release signal from BT

RESET signal

Q

S

R

Standby release signal from

interrupt control circuit

Note Instruction execution

Remarks 1. fX = Main system clock frequency

2. f^XT= Subsystem clock frequency

3. Φ = CPU clock

4. PCC: Processor clock control register

5. SCC: System clock control register

6. One clock cycle (t^CY) of the CPU clock (Φ) is equal to one machine cycle of an instruction.

Data Sheet U10738EJ3V2DS

22

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.3 CONTROL FUNCTIONS OF SUBSYSTEM CLOCK OSCILLATOR

The subsystem clock oscillator of the µPD750008 subseries has two control functions to decrease the supply

current.

• The function to select with the software whether to use the built-in feedback resistor^Note

• The function to suppress the supply current by reducing the drive current of the built-in inverter when the supply

voltage is high (V^DD≥ 2.7 V)

Note When the subsystem clock is not used, set SOS.0 to 1 (not to use the built-in feedback resistor), connect

XT1 to V^SS, and open XT2. This makes it possible to reduce the supply current required by the subsystem

clock oscillator.

Each function can be used by switching bits 0 and 1 in the sub-oscillator control register (SOS). (See Fig. 6-2.)

Fig. 6-2 Subsystem Clock Oscillator

SOS.0

VDD

Feedback resistor

Inverter

SOS.1

XT1

XT2

Data Sheet U10738EJ3V2DS

23

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.4 CLOCK OUTPUT CIRCUIT

The clock output circuit outputs a clock pulse from the P22/PCL pin. This clock pulse is used for remote control

waveform output, peripheral LSIs, etc.

• Clock output (PCL): Φ, 524, 262, or 65.5 kHz (at 4.19 MHz)

Φ, 750, 375, or 93.8 kHz (at 6.0 MHz)

Fig. 6-3 Clock Output Circuit Configuration

From the clock

generator

Φ

Output

f

X

/2³

/2⁴

/2⁶

buffer

Selector

f

f

X

X

PCL/P22

PORT2.2

Bit 2 of PMGB

Port 2 input/

output mode

specification bit

P22 output

latch

CLOM3

0

CLOM1 CLOM0 CLOM

4

Internal bus

Remark Measures are taken to prevent outputting a narrow pulse when selecting clock output enable/disable.

Data Sheet U10738EJ3V2DS

24

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.5 BASIC INTERVAL TIMER/WATCHDOG TIMER

The basic interval timer/watchdog timer has these functions:

• Interval timer operation which generates a reference timer interrupt

• Operation as a watchdog timer for detecting program crashes and resetting the CPU

• Selection of wait time for releasing the standby mode and counting the wait time

• Reading out the count value

Fig. 6-4 Block Diagram of the Basic Interval Timer/Watchdog Timer

From the clock

generator

Clear signal

Clear signal

fX

fX

fX

fX

/2⁵

/2⁷

/2⁹

/2¹²

Set

signal

Basic interval timer

(8-bit frequency divider)

BT interrupt

request flag

MPX

Vectored

interrupt

request

signal

BT

IRQBT

Internal

reset signal

3

Wait release

signal for standby

release

SET1^Note

BTM3

BTM2 BTM1 BTM0

BTM

WDTM

SET1^Note

8

4

1

Internal bus

Note Instruction execution

Data Sheet U10738EJ3V2DS

25

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.6 CLOCK TIMER

The µPD750008 contains one channel for a clock timer. The clock timer provides the following functions:

• Sets the test flag (IRQW) with a 0.5 sec interval. The standby mode can be released by IRQW.

• The 0.5 second interval can be generated from either the main system clock (4.194304 MHz) or subsystem clock

(32.768 kHz).

• The time interval can be made 128 times faster (3.91 ms) by selecting the fast mode. This is convenient for

program debugging, testing, etc.

• Any of the frequencies 2.048 kHz, 4.096 kHz, and 32.768 kHz can be output to the P23/BUZ pin. This can be

used for beep and system clock frequency trimming.

• The frequency divider circuit can be cleared so that a zero-second start of the clock can be made.

Fig. 6-5 Clock Timer Block Diagram

f

2⁷

w

(256 Hz: 3.91 ms)

f

X

f

w

INTW

IRQW

set signal

Selector

f

W

2¹⁴

128

(32.768 kHz)

(32.768 kHz)

From the

clock

Selector

Frequency divider

generator

2 Hz

0.5 sec

f

XT

(4 kHz) (2 kHz)

(32.768 kHz)

fw

f

2⁴

w

Clear

2³

Selector

Output buffer

P23/BUZ

WM

PORT2.3

Bit 2 of PMGB

Port 2 input/

P23 output

latch

WM7

0

WM5 WM4 WM3 WM2 WM1 WM0

output mode

Bit test instruction

8

Internal bus

( ) is for f^X= 4.194304 MHz, fXT = 32.768 kHz.

Data Sheet U10738EJ3V2DS

26

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.7 TIMER/EVENT COUNTER

The µPD750008 contains one channel for a timer/event counter and one channel for a timer counter. Figs.

6-6 and 6-7 show their configurations.

The timer/event counter provides the following functions:

• Programmable interval timer operation

• Outputs square-wave signal of an arbitrary frequency to the PTOn pin (n = 0, 1)

• Event counter operation (channel 0 only)

• Divides the TI0 pin input by N and outputs to the PTO0 pin (frequency divider operation) (channel 0 only)

• Supplies serial shift clock to the serial interface circuit (channel 0 only)

• Count read function

Data Sheet U10738EJ3V2DS

27

Fig. 6-6 Timer/Event Counter Block Diagram

Internal bus

SET1^Note

8

8

8

PORT2.0

Bit 2 of PMGB

TOE0

T0 enable

TM0

TMOD0

P20

Port 2

input/

output

latch

TM06 TM05 TM04 TM03 TM02

flag

Modulo register (8)

8

output

mode

signal

To serial

interface

Port input

buffer

µ

TOUT0

Match

TOUT

flip-flop

Comparator (8)

8

PTO0/P20

Output

buffer

Reset

Input buffer

T0

INTT0

TI0/P13

Count register (8)

fX

fX

fX

fX

/2⁴

IRQT0

set signal

CP

MPX

/2⁶

/2⁸

/2¹⁰

From the clock

generator

Clear signal

Timer operation start signal

RESET

IRQT0 clear

signal

Note Instruction execution

Fig. 6-7 Timer Counter Block Diagram

Internal bus

SET1^Note

8

8

8

TOE1

PORT2.1

Bit 2 of PMGB

TM1

TMOD1

Port 2

P21

T1 enable

input/

output

mode

output

latch

0

TM16 TM15 TM14 TM13 TM12

flag

Modulo register (8)

8

µ

Match

TOUT

Comparator (8)

8

PTO1/P21

flip-flop

Output

buffer

Reset

T1











fX

fX

fX

fX

/2⁶

/2⁸

/2¹⁰

INTT1

Count register (8)

From the clock

generator

IRQT1

set signal

CP

MPX

Clear signal

/2¹²

Timer operation start signal

RESET

IRQT1 clear

signal

Note Instruction execution

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.8 SERIAL INTERFACE

µPD750008 has an 8-bit synchronous serial interface. The serial interface has the following four types of mode.

• Operation stop mode

• Three-wire serial I/O mode

• Two-wire serial I/O mode

• SBI mode

Data Sheet U10738EJ3V2DS

30

Fig. 6-8 Serial Interface Block Diagram

Internal bus

8

Bit

test

Bit manipulation

8/4

Bit test

8

8

CSIM

Slave address register (SVA) (8)

Coincidence

SBIC

µ

RELT

signal

Address comparator

CMDT

(8)

P03/SI/SB1

P02/SO/SB0

SO latch

SET CLR

Selec-

tor

Shift register (SIO)

D

Q

(8)

Busy/

acknowledge

output circuit

Selec-

tor

RELD

CMDD

ACKD

Bus release/

command/

acknowledge

detection circuit

INTCSI

P01/SCK

Serial clock

counter

INTCSI

control circuit

IRQCSI

set signal

f

f

f

x

/2³

/2⁴

/2⁶

P01

output latch

x

x

Serial clock

control circuit

Serial clock

selector

TOUT0

(from timer/event counter)

External SCK

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

6.9 BIT SEQUENTIAL BUFFER: 16 BITS

The bit sequential buffer (BSB) is a data memory specifically provided for bit manipulation. With this buffer,

addresses and bit specifications can be sequentially updated by bit manipulation operation. Therefore, this buffer

is very useful for processing long data in bit units.

Fig. 6-9 Bit Sequential Buffer Format

Address

Bit

FC3H

FC2H

FC1H

FC0H

3

2

1

0

3

2

1

0

3

2

1

0

3

2

1

0

Symbol

BSB3

BSB2

BSB1

BSB0

L register

L = FH

L = CH L = BH

L = 8H L = 7H

L = 4H L = 3H

DECS L

L = 0H

INCS L

Remarks 1. In pmem.@L addressing, bit specification is shifted according to the L register.

2. In pmem.@L addressing, the bit sequential buffer can be manipulated at any time regardless of MBE/

MBS specification.

Data Sheet U10738EJ3V2DS

32

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

7. INTERRUPT FUNCTIONS AND TEST FUNCTIONS

The µPD750008 has seven interrupt sources and two test sources. One test source, INT2, has two types of edge

detection testable input pins.

The interrupt control circuit of the µPD750008 has the following functions.

(1) Interrupt functions

• Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using

the interrupt flag (IE×××) and interrupt master enable flag (IME).

• The interrupt start address can be set arbitrarily.

• Multiple interrupt function which can specify the priority by the interrupt priority specification register (IPS)

• Test function of an interrupt request flag (IRQ×××)

(The software can confirm that an interrupt occurred.)

• Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.)

(2) Test functions

•

•

Whether test request flags (IRQ×××) are issued can be checked with software.

Release of the standby mode (A test source to be released can be selected with test enable flags.)

Data Sheet U10738EJ3V2DS

33

Fig. 7-1 Interrupt Control Circuit Block Diagram

Internal bus

2

1

4

IM2

IM1

IM0

IME

IPS

IST1 IST0

Interrupt enable flag (IE×××)

Decoder

µ

INTBT

IRQBT

IRQ4

Both-edge

detector

VRQn

INT4/P00

Edge

detector

Note

INT0/P10

INT1/P11

IRQ0

Edge

detector

IRQ1

Vector table

address

generator

Priority control circuit

INTCSI

IRQCSI

IRQT0

IRQT1

IRQW

IRQ2

INTT0

INTT1

INTW

Rising edge

detector

INT2/P12

Selec-

tor

Standby release signal

KR0/P60

KR7/P73

Falling edge

detector

IM2

Note Noise eliminator (Standby release is not possible when the noise eliminator is selected.)

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

8. STANDBY FUNCTION

The µPD750008 has two different standby modes (STOP mode and HALT mode) to reduce power dissipation while

waiting for program execution.

Table 8-1 Standby Mode Statuses

Mode

STOP mode

STOP instruction

HALT mode

HALT instruction

Item

Instruction for setting

System clock for setting

Can be set only when operating on the

main system clock.

Can be set either with the main system

clock or the subsystem clock.

Opera-

tion

Clock oscillator

The main system clock stops its operation.

Only the CPU clock Φ stops its operation

(oscillation continues).

status

Basic interval

timer/watchdog

timer

Does not operate.

Can operate only at main system clock

oscillation. (IRQBT is set at reference time

intervals.)

Serial interface

Can operate only when the external SCK

input is selected for the serial clock.

Can operate only when external SCK input

is selected as the serial clock or at main

system clock oscillation.

Timer/event

counter

Can operate only when the TI0 pin input is

selected for the count clock.

Can operate only when TI0 pin input is

specified as the count clock or at main

system clock oscillation.

Note 1

Timer counter

Clock timer

Does not operate.

Can operate.

Can operate when f^XTis selected as the

count clock.

Can operate.

External interrupt

INT1, INT2, and INT4 can operate.

Note 2

Only INT0 cannot operate.

CPU

Does not operate.

Release signal

An interrupt request signal from hardware whose operation is enabled by the interrupt

enable flag or the generation of a RESET signal

Notes 1. Operation is possible only when the main system clock operates.

2. Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode

register (IM0) (when IM02 = 1).

Data Sheet U10738EJ3V2DS

35

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

9. RESET FUNCTION

The µPD750008 is reset with the external reset signal (RESET) or the reset signal received from the basic interval

timer/watchdog timer. When either reset signal is input, the internal reset signal is generated. Fig. 9-1 shows the

configuration of the reset circuit.

Fig. 9-1 Configuration of Reset Functions

RESET

Internal reset signal

Reset signal from basic

interval timer/watchdog timer

WDTM

Internal bus

When the RESET signal is generated, all hardware is initialized as indicated in Table 9-1. Fig. 9-2 shows the reset

operation timing.

Fig. 9-2 Reset Operation by Generation of RESET Signal

Wait^Note

RESET signal is generated

Operating mode or

standby mode

HALT mode

Operating mode

Internal reset operation

Note Either of the following two values can be selected by a mask option:

2¹⁷/fX (21.8 ms at 6.0 MHz, 31.3 ms at 4.19 MHz)

2¹⁵/fX (5.46 ms at 6.0 MHz, 7.81 ms at 4.19 MHz)

Data Sheet U10738EJ3V2DS

36

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Table 9-1 Status of the Hardware after a Reset (1/2)

Generation of a RESET signal in

a standby mode

Generation of a RESET signal

during operation

Hardware

Program counter (PC)

µPD750004

4 low-order bits at address 0000H 4 low-order bits at address 0000H

in program memory are set in PC in program memory are set in PC

bits 11 to 8, and the data at address bits 11 to 8, and the data at address

0001H are set in PC bits 7 to 0.

0001H are set in PC bits 7 to 0.

µPD750006, 750008

5 low-order bits at address 0000H 5 low-order bits at address 0000H

in program memory are set in PC in program memory are set in PC

bits 12 to 8, and the data at address bits 12 to 8, and the data at address

0001H are set in PC bits 7 to 0.

0001H are set in PC bits 7 to 0.

Carry flag (CY)

Skip flags (SK0 to SK2)

PSW

Held

Undefined

0

0

0

0

Interrupt status flags (IST0, IST1)

Bank enable flags (MBE, RBE)

Bit 6 at address 0000H in

program memory is set in RBE,

and bit 7 is set in MBE.

Bit 6 at address 0000H in program

memory is set in RBE, and bit 7 is

set in MBE.

Stack pointer (SP)

Undefined

1000B

Undefined

Undefined

0, 0

Undefined

1000B

Held

Stack bank selection register (SBS)

Data memory (RAM)

General-purpose registers (X, A, H, L, D, E, B, C)

Bank selection register (MBS, RBS)

Held

0, 0

Basic interval

timer/watchdog

timer

Counter (BT)

Undefined

0

Undefined

0

Mode register (BTM)

Watchdog timer enable flag

(WDTM)

0

0

Counter (T0)

0

FFH

0

0

Timer/event

counter

Modulo register (TMOD0)

Mode register (TM0)

TOE0, TOUT flip-flop

Counter (T1)

FFH

0

0, 0

0

0, 0

0

Timer counter

Modulo register (TMOD1)

Mode register (TM1)

TOE1, TOUT flip-flop

Mode register (WM)

FFH

0

FFH

0

0, 0

0

0, 0

Clock timer

0

Serial interface

Shift register (SIO)

Held

0

Undefined

Operation mode register (CSIM)

SBI control register (SBIC)

Slave address register (SVA)

0

0

0

Held

Undefined

Data Sheet U10738EJ3V2DS

37

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Table 9-1 Status of the Hardware after a Reset (2/2)

Generation of a RESET signal in

a standby mode

Generation of a RESET signal

during operation

Hardware

Clockgenerator, Processorclockcontrolregister(PCC)

0

0

clock output cir-

System clock control register (SCC)

0

0

cuit

Clock output mode register (CLOM)

0

0

Sub-oscillator control register (SOS)

0

0

Interrupt request flag (IRQ×××)

Interrupt enable flag (IE×××)

Priority selection register (IPS)

Interrupt

Reset (0)

Reset (0)

0

0

0

0

INT0, INT1, and INT2 mode registers

(IM0, IM1, IM2)

0, 0, 0

0, 0, 0

Output buffer

Output latch

Digital ports

Off

Clear (0)

0

Off

Clear (0)

0

I/O mode registers (PMGA, PMGB,

PMGC)

Pull-upresistorspecificationregisters

(POGA, POGB)

0

0

Bit sequential buffers (BSB0 to BSB3)

Held

Undefined

Data Sheet U10738EJ3V2DS

38

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

10. MASK OPTION

The µPD750008 has the following mask options:

•

•

•

Mask option of P40 to P43 and P50 to P53

Can specify whether to incorporate the pull-up resistor.

1

The pull-up resistor is incorporated bit by bit.

2

The pull-up resistor is not incorporated.

Mask option of standby function

Can specify the wait time with the RESET signal.

2¹⁷/fX (21.8 ms at fX = 6.0 MHz, 31.3 ms at fX = 4.19 MHz)

1

2¹⁵/fX (5.46 ms at fX = 6.0 MHz, 7.81 ms at fX = 4.19 MHz)

2

Mask option of subsystem clock

Can specify whether to enable the built-in feedback resistor.

1

2

The built-in feedback resistor is enabled (it is turned on or off by software).

The built-in feedback resistor is disabled (it is cut by hardware).

Data Sheet U10738EJ3V2DS

39

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

11. INSTRUCTION SET

(1) Operand identifier and its descriptive method

The operands are described in the operand column of each instruction according to the descriptive method for

the operand format of the appropriate instructions. (For details, refer to RA75X Assembler Package User's

Manual: Language (EEU-1363).) For descriptions in which alternatives exist, one element should be selected.

Capital letters and plus and minus signs are keywords; therefore, they should be described as they are.

For immediate data, the appropriate numerical values or labels should be described.

The symbols of register flags can be used as a label instead of mem, fmem, pmem, and bit. (For details, refer

to µPD750008 User’s Manual (U10740E).) However, there are some restrictions on usable labels for fmem and

pmem.

Representation

Description

format

reg

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

reg1

rp

XA, BC, DE, HL

rp1

rp2

rp'

BC, DE, HL

BC, DE

XA, BC, DE, HL, XA', BC', DE', HL'

BC, DE, HL, XA', BC', DE', HL'

rp'1

rpa

HL, HL+, HL-, DE, DL

DE, DL

rpa1

n4

n8

4-bit immediate data or label

8-bit immediate data or label

Note

mem

bit

8-bit immediate data or label

2-bit immediate data or label

fmem

FB0H - FBFH, FF0H - FFFH immediate data or label

FC0H - FFFH immediate data or label

pmem

addr

0000H - 0FFFH immediate data or label (µPD750004)

0000H - 17FFH immediate data or label (µPD750006)

0000H - 1FFFH immediate data or label (µPD750008)

addr1(for Mk ΙΙ

mode only)

0000H - 0FFFH immediate data or label (µPD750004)

0000H - 17FFH immediate data or label (µPD750006)

0000H - 1FFFH immediate data or label (µPD750008)

caddr

faddr

taddr

12-bit immediate data or label

11-bit immediate data or label

20H - 7FH immediate data (however, bit 0 = 0) or label

PORTn

IE×××

RBn

PORT0 - PORT8

IEBT, IET0, IET1, IE0 - IE2, IE4, IECSI, IEW

RB0 - RB3

MBn

MB0, MB1, MB15

Note Only even address can be specified for 8-bit data processing.

Data Sheet U10738EJ3V2DS

40

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

(2) Symbol definitions in operation description

A

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

:

A register; 4-bit accumulator

B

B register

C

C register

D

D register

E

E register

H

H register

L

L register

X

X register

XA

BC

DE

HL

XA'

BC'

DE'

HL'

PC

SP

CY

PSW

MBE

RBE

Register pair (XA); 8-bit accumulator

Register pair (BC)

Register pair (DE)

Register pair (HL)

Extended register pair (XA')

Extended register pair (BC')

Extended register pair (DE')

Extended register pair (HL')

Program counter

Stack pointer

Carry flag; Bit accumulator

Program status word

Memory bank enable flag

Register bank enable flag

PORTn : Port n (n = 0 to 8)

IME

IPS

:

:

:

:

:

:

:

:

:

Interrupt master enable flag

Interrupt priority specification register

Interrupt enable flag

IE×××

RBS

MBS

PCC

.

Register bank selection register

Memory bank selection register

Processor clock control register

Address bit delimiter

(××)

××H

Contents addressed by ××

Hexadecimal data

Data Sheet U10738EJ3V2DS

41

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

(3) Symbols used for the addressing area column

* 1

MB = MBE • MBS (MBS = 0, 1, 15)

* 2

* 3

MB = 0

MBE = 0 : MB = 0 (000H - 07FH), MB = 15 (F80H - FFFH)

Data memory

addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

* 4

* 5

* 6

MB = 15, fmem = FB0H - FBFH, FF0H - FFFH

MB = 15, pmem = FC0H - FFFH

addr = 0000H - 0FFFH (

µ

µ

PD750004), 0000H - 17FFH ( PD750006)

µ

0000H - 1FFFH (

PD750008)

* 7

* 8

addr, addr1 = (Current PC) - 15 to (Current PC) - 1

(Current PC) + 2 to (Current PC) + 16

caddr = 0000H - 0FFFH ( PD750004)

µ

µ

0000H - 0FFFH (PC¹²= 0: PD750006, 750008)

Program memory

addressing

1000H - 17FFH (PC¹²= 1: PD750006)

µ

µ

1000H - 1FFFH (PC¹²= 1: PD750008)

* 9

faddr = 0000H - 07FFH

* 10

taddr = 0020H - 007FH

Mk ΙΙ mode only

* 11

addr1 = 0000H - 0FFFH (

µ

PD750004)

0000H - 17FFH (

µ

PD750006)

µ

0000H - 1FFFH ( PD750008)

Remarks 1. MB indicates the memory bank that can be accessed.

2. For *2, MB = 0 regardless of MBE and MBS settings.

3. For *4 and *5, MB = 15 regardless of MBE and MBS settings.

4. For *6 to *11, each addressable area is indicated.

(4) Description of machine cycle column

S indicates the number of machine cycles necessary for skipping any skip instruction. The value of S changes

as follows:

•

•

•

When no skip is performed

When a 1-byte or 2-byte instruction is skipped : S = 1

When a 3-byte instruction^Noteis skipped

: S = 2

: S = 0

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions.

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle (= t^CY) of the CPU clock (Φ), and four types of times are available for

selection according to the PCC setting.

Data Sheet U10738EJ3V2DS

42

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

Transfer

A, #n4

1

2

2

2

2

1

1

1

1

2

1

2

2

2

2

2

2

2

2

2

1

1

1

1

2

2

2

1

2

1

1

String A

MOV

A ← n4

reg1, #n4

XA, #n8

HL, #n8

rp2, #n8

A, @HL

A, @HL+

A, @HL-

A, @rpa1

XA, @HL

@HL, A

@HL, XA

A, mem

XA, mem

mem, A

mem, XA

A, reg

2

reg1 ← n4

XA ← n8

HL ← n8

rp2 ← n8

A ← (HL)

2

String A

String B

2

2

1

*1

*1

*1

*2

*1

*1

*1

*3

*3

*3

*3

2 + S

L = 0

A ← (HL), then L ← L + 1

A ← (HL), then L ← L - 1

A ← (rpa1)

2 + S

L = FH

1

2

XA ← (HL)

1

(HL) ← A

2

(HL) ← XA

2

A ← (mem)

2

XA ← (mem)

(mem) ← A

2

2

(mem) ← XA

A ← reg

2

XA, rp'

2

XA ← rp'

reg1, A

2

reg1 ← A

rp'1, XA

A, @HL

A, @HL+

A, @HL-

A, @rpa1

XA, @HL

A, mem

XA, mem

A, reg1

2

rp'1 ← XA

1

*1

*1

*1

*2

*1

*3

*3

XCH

A ↔ (HL)

2 + S

L = 0

A ↔ (HL), then L ← L + 1

A ↔ (HL), then L ← L - 1

A ↔ (rpa1)

2 + S

L = FH

1

2

2

2

1

2

3

XA ↔ (HL)

A ↔ (mem)

XA ↔ (mem)

A ↔ reg1

XA, rp'

XA ↔ rp'

Table

XA, @PCDE

MOVT

• µPD750004

reference

XA ← (PC11-8 + DE) ROM

• µPD750006, 750008

XA ← (PC12-8 + DE) ROM

XA, @PCXA

1

3

• µPD750004

XA ← (PC11-8 + XA) ROM

• µPD750006, 750008

XA ← (PC12-8 + XA) ROM

_{XA ← (BCDE) ROM}Note

_{XA ← (BCXA) ROM}Note

XA, @BCDE

XA, @BCXA

1

1

3

3

*6

*6

Note Set register B to 0 in the µPD750004. Only the LSB is valid in register B in the µPD750006 and µPD750008.

Data Sheet U10738EJ3V2DS

43

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address- Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

ing area

condition

monic

Bit transfer

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

fmem.bit, CY

pmem.@L, CY

@H+mem.bit, CY

A, #n4

2

2

2

2

2

2

1

2

1

2

2

1

2

2

1

2

2

1

2

2

2

1

2

2

2

1

2

2

2

1

2

2

1

2

1

1

2

2

1

2

2

*4

*5

*1

*4

*5

*1

MOV1

CY ← (fmem.bit)

2

CY ← (pmem7-2 + L3-2.bit(L1-0))

CY ← (H + mem^3-0.bit)

(fmem.bit) ← CY

2

2

2

(pmem^7-2+ L3-2.bit(L1-0)) ← CY

(H + mem3-0.bit) ← CY

A ← A + n4

2

Arithme-

tic

1 + S

carry

carry

carry

carry

carry

ADDS

XA, #n8

A, @HL

XA, rp'

2 + S

XA ← XA + n8

1 + S

*1

*1

*1

*1

A ← A + (HL)

2 + S

XA ← XA + rp'

rp'1, XA

A, @HL

XA, rp'

2 + S

rp'1 ← rp'1 + XA

1

ADDC

SUBS

SUBC

AND

A, CY ← A + (HL) + CY

XA, CY ← XA + rp' + CY

rp'1, CY ← rp'1 + XA + CY

A ← A - (HL)

2

rp'1, XA

A, @HL

XA, rp'

2

1 + S

borrow

borrow

borrow

2 + S

XA ← XA - rp'

rp'1, XA

A, @HL

XA, rp'

2 + S

rp'1 ← rp'1 - XA

1

A, CY ← A - (HL) - CY

XA, CY ← XA - rp' - CY

rp'1, CY ← rp'1 - XA - CY

2

rp'1, XA

A, #n4

2

2

A ← A

A ← A

∧

∧

n4

A, @HL

XA, rp'

1

*1

*1

*1

(HL)

2

XA ← XA

∧

rp'

rp'1, XA

A, #n4

2

rp'1 ← rp'1

∧

XA

XA

2

OR

A ← A

A ← A

∨

∨

n4

A, @HL

XA, rp'

1

(HL)

2

2

XA ← XA

∨

rp'

rp'1, XA

A, #n4

rp'1 ← rp'1

∨

2

XOR

A ← A ∨ n4

A ← A ∨ (HL)

XA ← XA ∨ rp'

rp'1 ← rp'1 ∨ XA

CY ← A0, A3 ← CY, An-1 ← An

A ← A

A, @HL

XA, rp'

1

2

rp'1, XA

A

2

Accumulator

manipulation

1

RORC

NOT

A

2

Increment/

decrement

reg

1 + S

1 + S

2 + S

2 + S

1 + S

2 + S

reg = 0

INCS

reg ← reg + 1

rp1

rp1 = 00H

(HL) = 0

(mem) = 0

reg = FH

rp' = FFH

rp1 ← rp1 + 1

@HL

*1

*3

(HL) ← (HL) + 1

(mem) ← (mem) + 1

reg ← reg - 1

mem

reg

DECS

rp'

rp' ← rp' - 1

Data Sheet U10738EJ3V2DS

44

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address- Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

ing area

condition

monic

Compari-

son

reg, #n4

2

2

1

2

2

2

1

1

1

1

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2 + S

reg = n4

(HL) = n4

A = (HL)

XA = (HL)

A = reg

SKE

Skip if reg = n4

@HL, #n4

A, @HL

2 + S

*1

*1

*1

Skip if (HL) = n4

1 + S

Skip if A = (HL)

XA, @HL

A, reg

2 + S

Skip if XA = (HL)

2 + S

Skip if A = reg

XA, rp'

2 + S

XA = rp'

Skip if XA = rp'

Carry flag

manipula-

tion

CY

1

SET1

CLR1

SKT

CY ← 1

CY

1

CY ← 0

CY

1 + S

CY = 1

Skip if CY = 1

CY

1

NOT1

SET1

CY ← CY

Memory

bit

mem.bit

2

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*3

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

*4

*5

*1

(mem.bit) ← 1

fmem.bit

2

(fmem.bit) ← 1

manipula-

tion

pmem.@L

@H+mem.bit

mem.bit

2

(pmem^7-2+ L3-2.bit(L1-0)) ← 1

(H + mem^3-0.bit) ← 1

(mem.bit) ← 0

2

2

2

CLR1

SKT

fmem.bit

(fmem.bit) ← 0

pmem.@L

@H+mem.bit

mem.bit

2

(pmem^7-2+ L3-2.bit(L1-0)) ← 0

(H + mem3-0.bit) ← 0

Skip if (mem.bit) = 1

Skip if (fmem.bit) = 1

Skip if (pmem^7-2+ L3-2.bit(L1-0)) = 1

Skip if (H + mem3-0.bit) = 1

Skip if (mem.bit) = 0

Skip if (fmem.bit) = 0

Skip if (pmem^7-2+ L3-2.bit(L1-0)) = 0

Skip if (H + mem^3-0.bit) = 0

Skip if (fmem.bit) = 1 and clear

Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear

Skip if (H + mem3-0.bit) = 1 and clear

CY ← CY ∧ (fmem.bit)

2

2 + S

2 + S

2 + S

2 + S

2 + S

2 + S

2 + S

2 + S

2 + S

2 + S

2 + S

2

(mem.bit) = 1

(fmem.bit) = 1

(pmem.@L) = 1

(@H + mem.bit) = 1

(mem.bit) = 0

(fmem.bit) = 0

(pmem.@L) = 0

(@H + mem.bit) = 0

(fmem.bit) = 1

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

SKF

fmem.bit

pmem.@L

@H+mem.bit

fmem.bit

SKTCLR

AND1

OR1

pmem.@L

@H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

CY, fmem.bit

CY, pmem.@L

CY, @H+mem.bit

(pmem.@L) = 1

(@H + mem.bit) = 1

2

CY ← CY

∧

(pmem7-2 + L3-2.bit(L1-0))

2

CY ← CY ∧ (H + mem3-0.bit)

CY ← CY ∨ (fmem.bit)

2

2

CY ← CY

∨

(pmem7-2 + L3-2.bit(L1-0))

2

CY ← CY ∨ (H + mem3-0.bit)

CY ← CY ∨ (fmem.bit)

2

XOR1

2

CY ← CY

∨

(pmem7-2 + L3-2.bit(L1-0))

2

CY ← CY ∨ (H + mem3-0.bit)

Data Sheet U10738EJ3V2DS

45

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

Note

Branch

addr

-

-

*6

BR

• µPD750004

PC11-0 ← addr

The assembler selects the most

adequate instruction from BR !addr,

BRCB !caddr, or BR $addr.

• µPD750006, 750008

PC^12-0← addr

The assembler selects the most

adequate instruction from BR !addr,

BRCB !caddr, or BR $addr.

addr1

-

-

• µPD750004

*11

PC^11-0← addr1

The assembler selects the most

adequate instruction from

instructions below.

• BR !addr

• BRA !addr1

• BRCB !caddr

• BR $addr1

• µPD750006, 750008

PC12-0 ← addr1

The assembler selects the most

adequate instruction from

instructions below.

• BR !addr

• BRA !addr1

• BRCB !caddr

• BR $addr1

!addr

3

1

1

3

2

2

• µPD750004

*6

*7

PC11-0 ← addr

• µPD750006, 750008

PC12-0 ← addr

$addr

$addr1

• µPD750004

PC11-0 ← addr

• µPD750006, 750008

PC12-0 ← addr

• µPD750004

PC11-0 ← addr1

• µPD750006, 750008

PC12-0 ← addr1

Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.

Data Sheet U10738EJ3V2DS

46

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

Branch

BR

PCDE

2

2

2

2

3

2

3

3

3

3

3

3

2

3

• µPD750004

PC11-0 ← PC11-8 + DE

• µPD750006, 750008

PC^12-0← PC12-8 + DE

• µPD750004

PCXA

BCDE

BCXA

!addr1

!caddr

!addr1

PC^11-0← PC11-8 + XA

• µPD750006, 750008

PC^12-0← PC12-8 + XA

• µPD750004

*6

*6

Note 1

PC^11-0← BCDE

• µPD750006, 750008

Note 2

PC^12-0← BCDE

• µPD750004

Note 1

PC11-0 ← BCXA

• µPD750006, 750008

Note 2

PC^12-0← BCXA

BRA^{Note 3}

• µPD750004

*11

*8

PC11-0 ← addr1

• µPD750006, 750008

PC12-0 ← addr1

• µPD750004

BRCB

PC^11-0← caddr11-0

• µPD750006, 750008

PC12-0 ← PC12 + caddr11-0

• µPD750004

CALLA^{Note 3}

*11

Subrou-

tine stack

control

(SP - 2) ← ×, ×, MBE, RBE

(SP - 6) (SP - 3) (SP - 4) ← PC11-0

(SP - 5) ← 0, 0, 0, 0

PC11-0 ← addr1, SP ← SP - 6

• µPD750006, 750008

(SP - 2) ← ×, ×, MBE, RBE

(SP - 6) (SP - 3) (SP - 4) ← PC11-0

(SP - 5) ← 0, 0, 0, PC12

PC12-0 ← addr1, SP ← SP - 6

Notes 1. Set register B to 0.

2. Only the LSB is valid in register B.

3. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.

Data Sheet U10738EJ3V2DS

47

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

Note

Subrou-

tine stack

control

CALL

!addr

3

3

• µPD750004

*6

(SP - 3) ← MBE, RBE, 0, 0

(SP - 4) (SP - 1) (SP - 2) ← PC^11-0

PC11-0 ← addr, SP ← SP - 4

• µPD750006, 750008

(SP - 3) ← MBE, RBE, 0, PC12

(SP - 4) (SP - 1) (SP - 2) ← PC11-0

PC12-0 ← addr, SP ← SP - 4

• µPD750004

4

(SP - 2) ← ×, ×, MBE, RBE

(SP - 6) (SP - 3) (SP - 4) ← PC^11-0

(SP - 5) ← 0, 0, 0, 0

PC11-0 ← addr, SP ← SP - 6

• µPD750006, 750008

(SP - 2) ← ×, ×, MBE, RBE

(SP - 6) (SP - 3) (SP - 4) ← PC11-0

(SP - 5) ← 0, 0, 0, PC12

PC12-0 ← addr, SP ← SP - 6

• µPD750004

Note

!faddr

2

2

*9

CALLF

(SP - 3) ← MBE, RBE, 0, 0

(SP - 4) (SP - 1) (SP - 2) ← PC^11-0

PC11-0 ← 0 + faddr, SP ← SP - 4

• µPD750006, 750008

(SP - 3) ← MBE, RBE, 0, PC12

(SP - 4) (SP - 1) (SP - 2) ← PC11-0

PC12-0 ← 00 + faddr, SP ← SP - 4

• µPD750004

3

(SP - 2) ← ×, ×, MBE, RBE

(SP - 6) (SP - 3) (SP - 4) ← PC11-0

(SP - 5) ← 0, 0, 0, 0

PC11-0 ← 0 + faddr, SP ← SP - 6

• µPD750006, 750008

(SP - 2) ← ×, ×, MBE, RBE

(SP - 6) (SP - 3) (SP - 4) ← PC11-0

(SP - 5) ← 0, 0, 0, PC12

PC12-0 ← 00 + faddr, SP ← SP - 6

Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.

Data Sheet U10738EJ3V2DS

48

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

Note

Subrou-

tine stack

control

RET

1

3

• µPD750004

PC^11-0← (SP) (SP + 3) (SP + 2)

MBE, RBE, 0, 0 ← (SP + 1), SP ← SP + 4

• µPD750006, 750008

PC^11-0← (SP) (SP + 3) (SP + 2)

MBE, RBE, 0, PC¹²← (SP + 1)

SP ← SP + 4

3

• µPD750004

×, ×, MBE, RBE ← (SP + 4)

0, 0, 0, 0 ← (SP + 1)

PC^11-0← (SP) (SP + 3) (SP + 2)

SP ← SP + 6

• µPD750006, 750008

×, ×, MBE, RBE ← (SP + 4)

MBE, 0, 0, PC¹²← (SP + 1)

PC11-0 ← (SP) (SP + 3) (SP + 2)

SP ← SP + 6

Note

1

3 + S

• µPD750004

Uncondition

RETS

MBE, RBE, 0, 0 ← (SP + 1)

PC11-0 ← (SP) (SP + 3) (SP + 2)

SP ← SP + 4

then skip unconditionally

• µPD750006, 750008

MBE, RBE, 0 ← PC¹²← (SP + 1)

PC11-0 ← (SP) (SP + 3) (SP + 2)

SP ← SP + 4

then skip unconditionally

• µPD750004

3 + S

0, 0, 0, 0 ← (SP + 1)

PC11-0 ← (SP) (SP + 3) (SP + 2)

×, ×, MBE, RBE ← (SP + 4)

SP ← SP + 6

then skip unconditionally

• µPD750006, 750008

0, 0, 0, PC12 ← (SP + 1)

PC11-0 ← (SP) (SP + 3) (SP + 2)

×, ×, MBE, RBE ← (SP + 4)

SP ← SP + 4

then skip unconditionally

Note The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.

Data Sheet U10738EJ3V2DS

49

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

RETI^{Note 1}

Subrou-

tine stack

control

1

3

• µPD750004

MBE, RBE, 0, 0 ← (SP + 1)

PC^11-0← (SP) (SP + 3) (SP + 2)

PSW ← (SP + 4) (SP + 5), SP ← SP + 6

• µPD750006, 750008

MBE, RBE, 0, PC12 ← (SP + 1)

PC11-0 ← (SP) (SP + 3) (SP + 2)

PSW ← (SP + 4) (SP + 5), SP ← SP + 6

• µPD750004

0, 0, 0, 0 ← (SP + 1)

PC^11-0← (SP) (SP + 3) (SP + 2)

PSW ← (SP + 4) (SP + 5), SP ← SP + 6

• µPD750006, 750008

0, 0, 0, PC¹²← (SP + 1)

PC11-0 ← (SP) (SP + 3) (SP + 2)

PSW ← (SP + 4) (SP + 5), SP ← SP + 6

(SP - 1)(SP - 2) ← rp, SP ← SP - 2

rp

1

2

1

2

PUSH

POP

BS

(SP - 1) ← MBS, (SP - 2) ← RBS,

SP ← SP - 2

rp

1

2

1

2

rp ← (SP + 1)(SP), SP ← SP + 2

BS

MBS ← (SP + 1), RBS ← (SP),

SP ← SP + 2

2

2

2

2

2

2

2

2

2

2

1

2

2

2

2

2

2

2

2

2

2

1

EI

DI

IME (IPS.3) ← 1

IE××× ← 1

Interrupt

control

IE×××

IME (IPS.3) ← 0

IE××× ← 0

IE×××

Note 2

A, PORTn

XA, PORTn

PORTn, A

PORTn, XA

IN

A ← PORTn

XA ← PORTn+1,PORTn (n = 4, 6)

PORTn ← A (n = 2 - 8)

(n = 0 - 8)

Input/

output

OUT^{Note 2}

PORTn+1,PORTn ← XA (n = 4, 6)

Set HALT Mode (PCC.2 ← 1)

Set STOP Mode (PCC.3 ← 1)

No Operation

HALT

STOP

NOP

CPU

control

Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.

2. When executing the IN/OUT instruction, MBE must be set to 0 or MBE and MBS must be set to 1 and 15,

respectively.

Data Sheet U10738EJ3V2DS

50

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

Special

SEL

RBn

2

2

1

2

2

3

RBS ← n (n = 0 - 3)

MBS ← n (n = 0, 1, 15)

• µPD750004

MBn

GETI^{Notes 1, 2}

*10

taddr

When the TBR instruction is used

PC^11-0← (taddr)3-0 + (taddr + 1)

........................................................

When the TCALL instruction is used

(SP - 4) (SP - 1) (SP - 2) ← PC11-0

(SP - 3) ← MBE, RBE, 0, 0

PC11-0 ← (taddr)3-0 + (taddr + 1)

SP ← SP - 4

........................................................

.....................

Depends

When an instruction other than the

TBR and TCALL instructions is used

on the

referenced

instruction.

Execution of (taddr)(taddr + 1)

instruction

• µPD750006, 750008

When the TBR instruction is used

PC^12-0← (taddr)4-0 + (taddr + 1)

........................................................

When the TCALL instruction is used

(SP - 4) (SP - 1) (SP - 2) ← PC11-0

(SP - 3) ← MBE, RBE, 0, PC12

PC12-0 ← (taddr)4-0 + (taddr + 1)

SP ← SP - 4

........................................................

.....................

Depends

When an instruction other than the

TBR and TCALL instructions is used

on the

referenced

instruction.

Execution of (taddr)(taddr + 1)

instruction

3

• µPD750004

*10

When the TBR instruction is used

PC11-0 ← (taddr)3-0 + (taddr + 1)

.......................................................................

4

When the TCALL instruction is used

(SP - 6) (SP - 3) (SP - 4) ← PC11-0

(SP - 5) ← 0, 0, 0, 0

(SP - 2) ← ×, ×, MBE, RBE

PC11-0 ← (taddr)3-0 + (taddr + 1)

SP ← SP - 6

.......................................................................

.....................

Depends

3

When an instruction other than the TBR

and TCALL instructions is used

on the

referenced

instruction.

Execution of (taddr)(taddr + 1)

instruction

Notes 1. The shaded portion is supported in Mk ΙΙ mode only. The other portions are supported in Mk Ι mode only.

2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions.

Data Sheet U10738EJ3V2DS

51

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Machin-

Address-

ing area

Skip

Mne-

Group

Operand

Bytes ing

cycle

Operation

condition

monic

GETI^{Notes 1, 2}

Special

taddr

1

3

• µPD750006, 750008

*10

When the TBR instruction is used

PC^12-0← (taddr)4-0 + (taddr + 1)

.......................................................................

4

When the TCALL instruction is used

(SP - 6) (SP - 3) (SP - 4) ← PC11-0

(SP - 5) ← 0, 0, 0, PC12

(SP - 2) ← ×, ×, MBE, RBE

PC^12-0← (taddr)4-0 + (taddr + 1)

SP ← SP - 6

.......................................................................

.....................

Depends

3

When an instruction other than the TBR

and TCALL instructions is used

on the

referenced

instruction.

Execution of (taddr)(taddr + 1)

instruction

Notes 1. The shaded portion is supported in Mk ΙΙ mode only.

2. TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions.

Data Sheet U10738EJ3V2DS

52

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

12. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Conditions

Rated value

-0.3 to +7.0

-0.3 to V^DD+ 0.3

-0.3 to V^DD+ 0.3

-0.3 to +14

-0.3 to VDD + 0.3

-10

Unit

V

Parameter

Supply voltage

Symbol

V^DD

Other than ports 4 and 5

V

Input voltage

VI1

Ports

With a built-in pull-up resistor

With open drain

V

VI2

4 and 5

V

Output voltage

VO

IOH

V

High-level output current

Each pin

mA

mA

mA

mA

°C

°C

Total of all pins

Each pin

-30

Low-level output current

IOL

30

Total of all pins

220

Operatingambienttemperature

Storage temperature

TA

-40 to +85

-65 to +150

Tstg

Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the

product; if the rated value of any of the parameters in the above table is exceeded, even momentarily,

the quality of the product may deteriorate. Always use the product within its rated values.

CAPACITANCE (T^A= 25 °C, VDD = 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

C^IN

Min.

Typ.

Max.

15

Unit

pF

Conditions

f = 1 MHz

0 V for pins other than pins to be

measured

COUT

CIO

15

pF

15

pF

Data Sheet U10738EJ3V2DS

53

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C)

Recommended

constant

Resonator

Parameter

Conditions

Min.

1.0

Typ.

Max.

Unit

Note 1

Ceramic

Oscillator frequency (fX)

VDD = 2.2 to 5.5 V

6.0^{Note 2}MHz

X1

X2

resonator

Note 3

Oscillation settling time

After V^DDreaches

Min. of the oscillation

voltage range

4

ms

C1

C1

C2

Note 1

Oscillator frequency (fX)

V^DD= 2.2 to 5.5 V

1.0

6.0^{Note 2}MHz

Crystal

X1

X1

X2

Note 3

Oscillation settling time

V^DD= 4.5 to 5.5 V

VDD = 2.2 to 5.5 V

V^DD= 1.8 to 5.5 V

10

30

ms

ms

C2

Note 1

6.0^{Note 4}MHz

External

clock

X1 input frequency (fX)

1.0

X2

X1 input high/low level width V^DD= 1.8 to 5.5 V

(t^XH, tXL)

83.3

500

ns

Notes 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. See the item

of AC characteristics for the instruction execution time.

2. When the supply voltage is 2.2 V ≤ V^DD< 2.7 V and the oscillator frequency is 4.7 MHz < fX ≤ 6.0 MHz,

set the processor clock control register (PCC) to a value other than 0011. When the PCC is set to 0011,

the time for one machine cycle cannot satisfy the defined setting of 0.85 µs.

3. The oscillation settling time means the time required for the oscillation to settle after V^DDis applied or after

the STOP mode is released.

4. When the supply voltage is 1.8 V ≤ V^DD< 2.7 V and the X1 input frequency is 4.19 MHz < fx ≤ 6.0 MHz,

set the PCC to a value other than 0011. When the PCC is set to 0011, the time for one machine cycle cannot

satisfy the defined setting of 0.95 µs.

Caution When the main system clock oscillator is used, conform to the following guidelines when wiring

at the portions surrounded by dotted lines in the figures above to eliminate the influence of the

wiring capacity.

• The wiring must be as short as possible.

• Other signal lines must not run in these areas.

• Any line carrying a high fluctuating current must be kept away as far as possible.

• The grounding point of the capacitor of the oscillator must have the same potential as that of V^SS.

• It must not be grounded to ground patterns carrying a large current.

• No signal must be taken from the oscillator.

Data Sheet U10738EJ3V2DS

54

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (TA = -40 to +85 °C)

Recommended

constant

Resonator

Crystal

Parameter

Conditions

Min.

32

Typ.

Max.

Unit

kHz

Note 1

V^DD= 2.2 to 5.5 V

Oscillator frequency (fXT)

32.768 35

XT1

XT2

R

Note 2

Oscillation settling time

s

s

1.0

2

V^DD= 4.5 to 5.5 V

V^DD= 2.2 to 5.5 V

V^DD= 1.8 to 5.5 V

C3

C4

10

Note 1

32

5

XT1 input frequency (fXT)

External

clock

kHz

100

XT1

XT2

V^DD= 1.8 to 5.5 V

XT1 input high/low level width

(t^XTH, tXTL)

µs

15

Notes 1. The oscillator frequency and input frequency indicate only the oscillator characteristics. See the item of

AC characteristics for the instruction execution time.

2. The oscillation settling time means the time required for the oscillation to settle after V^DDis applied.

Caution When the subsystem clock oscillator is used, conform to the following guidelines when wiring at

the portions of surrounded by dotted lines in the figures above to eliminate the influence of the

wiring capacity.

• The wiring must be as short as possible.

• Other signal lines must not run in these areas.

• Any line carrying a high fluctuating current must be kept away as far as possible.

• The grounding point of the capacitor of the oscillator must have the same potential as that of V^SS

• It must not be grounded to ground patterns carrying a large current.

• No signal must be taken from the oscillator.

When the subsystem clock is used, pay special attention to its wiring; the subsystem clock

oscillator has low amplification to minimize current consumption and is more likely to malfunction

due to noise than the main system clock oscillator.

Data Sheet U10738EJ3V2DS

55

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

RECOMMENDED PARAMETERS FOR THE OSCILLATION CIRCUIT

When a ceramic resonator is used for the main system clock (TA = -40 to +85 °C)

Manufacturer

Product name

Oscillation frequency

(MHz)

Oscillation

Oscillation

Remarks

circuit constant

voltage range

C1 (pF)

100

100

C2 (pF)

100

100

Min. (V)

2.8

Max. (V)

5.5

Note

Murata Mfg.

CSB1000J

1.0

2.0

Rd = 4.7 kΩ

CSA2.00MG040

CST2.00MG040

CSA4.00MG

CST4.00MGW

CSA4.00MGU

CST4.00MGWU

CSA4.19MG

CST4.19MGW

CSA4.19MGU

CST4.19MGWU

CSA6.00MGU

CST6.00MGWU

CSA6.00MG

CST6.00MGW

KBR-1000F/Y

KBR-2.0MS

2.8

2.8

2.8

2.8

2.6

2.6

2.8

2.8

2.8

2.8

2.9

2.9

2.7

2.7

2.45

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.2

2.0

2.2

2.5

Incorporated Incorporated

4.0

30

30

Incorporated Incorporated

30

30

Incorporated Incorporated

4.19

6.0

30

30

Incorporated Incorporated

30

30

Incorporated Incorporated

30

30

Incorporated Incorporated

30

30

Incorporated Incorporated

Kyocera

1.0

2.0

220

82

220

82

5.5

PBRC 2.00A

KBR-4.0MSA

KBR-4.0MKS

PBRC4.00A

82

82

4.0

33

33

Incorporated Incorporated

33

33

PBRC4.00B

Incorporated Incorporated

KBR-6.0MSA

KBR-6.0MKS

PBRC6.00A

6.0

33

33

Incorporated Incorporated

33

33

PBRC6.00B

Incorporated Incorporated

TDK

FCR2.0M3

2.0

4.0

33

15

15

15

33

15

15

15

5.5

FCR4.0M5

FCR4.19M5

4.19

6.0

FCR6.0M5

Note When the CSB1000J (1.0 MHz) manufactured by Murata Mfg. is used, a limiting resistor (Rd = 4.7 kΩ) is

necessary (see the following figure). When one of other resonators is used, no limiting resistor is required.

Data Sheet U10738EJ3V2DS

56

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg.

is used

X1

X2

CSB1000J

Rd

C2

C1

When a crystal is used for the subsystem clock (T^A= -10 to +60 °C)

Manufacturer

Product name

Oscillation

Oscillation

Oscillation

Remarks

frequency (kHz)

circuit constant

voltage range

C3 (pF) C4 (pF) R (kΩ) Min. (V)

Max. (V)

5.5

Daishinku

DT-38

32.768

10

10

220

2.7

2.2

Low-current-drain mode

Low-voltage mode

5.5

Caution The oscillation circuit constant and oscillation voltage range indicate the conditions to settle the

oscillation, not to guarantee the accuracy of the oscillation frequency. When an accuracy

oscillation frequency is needed for the implemented circuit, the oscillation frequency of the

resonator should be adjusted on the circuit. Ask the manufacturer of the resonator you use.

Data Sheet U10738EJ3V2DS

57

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V)

Conditions

Typ.

Max.

15

Parameter

Symbol

I^OL

Min.

Unit

mA

mA

V

Low-level output

current

Each pin

Total of all pins

Ports 2, 3, and 8

150

High-level input

voltage

2.7 V ≤ VDD ≤ 5.5 V

2.2 V ≤ V^DD< 2.7 V

2.7 V ≤ V^DD≤ 5.5 V

2.2 V ≤ V^DD< 2.7 V

2.7 V ≤ V^DD≤ 5.5 V

2.2 V ≤ V^DD< 2.7 V

2.7 V ≤ V^DD≤ 5.5 V

2.2 V ≤ V^DD< 2.7 V

0.7VDD

0.9VDD

0.8VDD

0.9VDD

0.7VDD

0.9VDD

0.7VDD

0.9VDD

VDD - 0.1

0

VDD

VIH1

VIH2

VIH3

VDD

V

Ports 0, 1, 6, and 7 and RESET

VDD

V

VDD

V

Ports 4 and

5

VDD

V

With a Built-in pull-up

resistor

VDD

V

13

V

With N-ch open drain

13

V

VDD

V

VIH4

VIL1

X1, XT1

2.7 V ≤ V^DD≤ 5.5 V

2.2 V ≤ VDD < 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

2.2 V ≤ VDD < 2.7 V

0.3VDD

0.1VDD

0.2VDD

0.1VDD

0.1

V

Low-level input

voltage

Ports 2 to 5, and 8

Ports 0, 1, 6, and 7 and RESET

X1, XT1

0

V

0

V

VIL2

VIL3

0

V

0

V

V^DD- 0.5

V

High-level output voltage VOH

SCK, SO, and ports 0, 2, 3, and 6 to 8 IOH = -1.0 mA

SCK, SO,

and ports

2 to 8

0.2

2.0

0.4

0.2V^DD

3

V

Low-level output

voltage

VOL1

IOL = 15 mA, VDD = 4.5 to 5.5 V

V

I^OL= 1.6 mA

V

VOL2

ILIH1

ILIH2

ILIH3

ILIL1

ILIL2

ILIL3

SB0, SB1

N-ch open drain Pull-up resistor ≥ 1 kΩ

V^IN= VDD

Other than X1 and XT1

X1, XT1

µA

µA

µA

µA

µA

µA

High-level input

leakage current

20

20

V^IN= 13 V Ports 4 and 5 (With N-ch open drain)

-3

VIN = 0 V

Other than X1, XT1, and ports 4 and 5

X1, XT1

Low-level input

leakage current

-20

-3

Ports 4 and 5 (With N-ch open drain)

At other than input instruction execution

Ports 4 and 5 (With N-ch

-30

-27

-8

µA

µA

µA

µA

open drain)

VDD = 5.0 V

-10

-3

When the input instruction

VDD = 3.0 V

is executed

3

ILOH1

V^OUT= VDD SCK, SO/SB0, SB1, and ports 2, 3, and 6

to 8

High-level output

leakage current

Ports 4 and 5 (With a built-in pull-up resistor)

ILOH2

ILOL

VOUT = 13 V Ports 4 and 5 (With N-ch open drain)

VOUT = 0 V

20

-3

µA

µA

Low-level output

leakage current

100

30

50

15

RL1

RL2

VIN = 0 V

Ports 0 to 3 and 6 to 8 (except P00 pin)

Ports 4 and 5 (mask option)

200

60

kΩ

kΩ

Built-in pull-up

resistor

Data Sheet U10738EJ3V2DS

58

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter

Symbol

I^DD1

Conditions

Min.

Typ.

1.9

0.4

0.72

0.27

1.5

0.25

0.7

0.23

12

Max.

6.0

1.3

2.1

0.8

4.0

0.75

2.0

0.7

35

21

24

18

12

25

15

17

12

7

Unit

mA

mA

mA

mA

mA

mA

mA

mA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

µA

Note 3

6.0

MHz

crystal

VDD = 5.0 V 10%

Power supply

Note 2

Note 1

current

Note 4

VDD = 3.0 V 10%

C1 = C2 =

22 pF

HALT mode

VDD = 5.0 V 10%

IDD2

IDD1

IDD2

IDD3

VDD = 3.0 V 10 %

Note 3

4.19

MHz

crystal

V^DD= 5.0 V 10%

VDD = 3.0 V 10%

Note 2

Note 4

C1 = C2 =

22 pF

HALT mode

V^DD= 5.0 V 10%

V^DD= 3.0 V 10%

VDD = 3.0 V 10%

VDD = 2.5 V 10%

VDD = 3.0 V, TA = 25 °C

V^DD= 3.0 V 10%

VDD = 3.0 V, TA = 25 °C

32.768

kHz

crystal

Low-voltage

Note 5

Note 6

mode

7

12

Low-current-

drain

6

6

Note 7

mode

IDD4

8.5

5

HALT mode

Low-volt-

age

VDD = 3.0 V 10%

VDD = 2.5 V 10%

VDD = 3.0 V, TA = 25 °C

V^DD= 3.0 V 10%

VDD = 3.0 V, TA = 25 °C

Note 6

mode

8.5

3.5

3.5

0.05

0.02

0.02

Low-cur-

rent-drain

Note 7

mode

VDD = 5.0 V 10%

VDD = 3.0 V 10%

XT1 =

0 V

IDD5

10

5

Note 8

STOP

mode

3

TA = 25 °C

Notes 1. This current excludes the current which flows through the built-in pull-up resistors.

2. This value applies also when the subsystem clock oscillates.

3. Value when the processor clock control register (PCC) is set to 0011 and the µPD750008 is operated in

the high-speed mode.

4. Value when the PCC is set to 0000 and the µPD750008 is operated in the low-speed mode.

5. This value applies when the system clock control register (SCC) is set to 1001 to stop the main system

clock pulse and to start the subsystem clock pulse.

6. Mode when the sub-oscillator control register (SOS) is set to 0000.

7. Mode when the SOS is set to 0010.

8. This value applies when the SOS is set to 00×1 and the sub-oscillator feedback resistor is not used (× =

don’t care).

Data Sheet U10738EJ3V2DS

59

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter

Symbol

Conditions

Min.

0.67

0.85

0.67

0.95

114

0

Typ.

Max.

64

Unit

µs

When ceramic

or crystal is

used

Operated

by main

system

clock

CPU clock cycle

tCY

V^DD= 2.7 to 5.5 V

Note 1

time

(minimum

64

µs

instruction execution time

= 1 machine cycle)

VDD = 2.7 to 5.5 V

V^DD= 1.8 to 5.5 V

When external

clock is used

64

µs

pulse

64

µs

Operated by subsystem clock pulse

V^DD= 2.7 to 5.5 V

122

125

1.0

275

µs

fTI

TI0 input frequency

MHz

kHz

µs

0

tTIH,

tTIL

TI0 input high/low level

width

V^DD= 2.7 to 5.5 V

0.48

1.8

µs

Note 2

IM02 = 0

INT0

tINTH,

µs

Interrupt input high/low

level width

t^INTL

IM02 = 1

INT1, INT2, and INT4

KR0 to KR7

10

10

10

10

µs

µs

µs

RESET low level width

tRSL

µs

tCY vs. VDD

Notes 1. The cycle time of the CPU clock (Φ)

(minimum instruction execution time) de-

pendsonthefrequencyofconnectedreso-

nator (and external clock), the system

clock control register (SCC), and the proc-

essor clock control register (PCC).

The figure on the right side shows the

cycle time t^CYcharacteristics for the sup-

ply voltage V^DDduring main system clock

operation.

(Main system clock in operation)

64

60

6

5

Operation guaranteed

range

4

3

µ

2. This value becomes 2tCY or 128/fX accord-

ing to the setting of the interrupt mode

register (IM0).

2

1

0.95

0.85

0.67

0.5

0

1

1.8 2

2.2

3

4

5 5.5 6

2.7

Power supply voltage VDD [V]

Remark The shaded portion is guaranteed only when the

external clock is used.

Data Sheet U10738EJ3V2DS

60

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

SERIAL TRANSFER OPERATION

Two-wire and three-wire serial I/O modes (SCK: Internal clock output): (T^A= -40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter

Symbol

Conditions

V^DD= 2.7 to 5.5 V

Min.

1300

3800

tKCY1/2 - 50

tKCY1/2 - 150

150

Typ.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Max.

SCK cycle time

tKCY1

SCK high/low level

width

tKL1,

tKH1

V^DD= 2.7 to 5.5 V

V^DD= 2.7 to 5.5 V

V^DD= 2.7 to 5.5 V

R^L= 1 kΩ

Note 1

tSIK1

tKSI1

tKSO1

SI

setup time

(referred to SCK↑)

500

Note 1

SI

hold time

400

(referred to SCK↑)

600

VDD = 2.7 to 5.5 V

0

Delay time from SCK↓

250

Note 2

Note 1

C^L= 100 pF

to SO

output

0

1000

Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.

2. RL is the resistance of the SO output line load, while CL is the capacitance.

Two-wire and three-wire serial I/O modes (SCK: External clock input): (T^A= -40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter

Symbol

Conditions

V^DD= 2.7 to 5.5 V

Min.

800

3200

400

1600

100

150

400

600

0

Typ.

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Max.

SCK cycle time

tKCY2

SCK high/low level

width

tKL2,

tKH2

VDD = 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

V^DD= 2.7 to 5.5 V

RL = 1 kΩ

Note 1

tSIK2

tKSI2

tKSO2

SI

setup time

(referred to SCK↑)

Note 1

SI

hold time

(referred to SCK↑)

VDD = 2.7 to 5.5 V

Delay time from SCK↓

300

Note 2

Note 1

CL = 100 pF

to SO

output

0

1000

Notes 1. In two-wire serial I/O mode, SO should be read as SB0 or SB1.

2. R^Lis the resistance of the SO output line load, while CL is the capacitance.

Data Sheet U10738EJ3V2DS

61

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

SBI mode (SCK: Internal clock output (master)): (TA = -40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter

Symbol

Conditions

V^DD= 2.7 to 5.5 V

Min.

1300

Typ.

Unit

ns

ns

ns

ns

ns

ns

ns

Max.

SCK cycle time

tKCY3

3800

SCK high/low level

width

tKL3,

tKH3

V^DD= 2.7 to 5.5 V

V^DD= 2.7 to 5.5 V

tKCY3/2 - 50

tKCY3/2 - 150

150

tSIK3

SB0/SB1 setup time

(referred to SCK↑)

500

tKSI3

SB0/SB1 hold time

t^KCY3/2

(referred to SCK↑)

tKSO3

Delay time from SCK↓

to SB0/SB1 output

R^L= 1 kΩ

CL = 100 pF

VDD = 2.7 to 5.5 V

0

ns

ns

ns

ns

ns

ns

250

Note

0

1000

tKSB

tSBK

tSBL

tSBH

From SCK↑ to SB0/SB1↓

From SB0/SB1↓ to SCK↓

SB0/SB1 low level width

t^KCY3

tKCY3

tKCY3

tKCY3

SB0/SB1 high level

width

Note R^Lis the resistance of the SB0/SB1 output line load, while CL is the capacitance.

SBI mode (SCK: External clock input (slave)): (T^A= -40 to +85 °C, VDD = 2.2 to 5.5 V)

Parameter

Symbol

t^KCY4

Conditions

V^DD= 2.7 to 5.5 V

Min.

800

Typ.

Unit

ns

ns

ns

ns

ns

ns

ns

Max.

SCK cycle time

3200

400

SCK high/low level

width

tKL4,

tKH4

V^DD= 2.7 to 5.5 V

VDD = 2.7 to 5.5 V

1600

100

tSIK4

SB0/SB1 setup time

(referred to SCK↑)

150

tKSI4

SB0/SB1 hold time

t^KCY4/2

(referred to SCK↑)

tKSO4

Delay time from SCK↓

to SB0/SB1 output

RL = 1 kΩ

CL = 100 pF

VDD = 2.7 to 5.5 V

0

ns

ns

ns

ns

ns

ns

300

Note

0

1000

tKSB

tSBK

tSBL

tSBH

From SCK↑ to SB0/SB1↓

From SB0/SB1↓ to SCK↓

SB0/SB1 low level width

t^KCY4

tKCY4

tKCY4

tKCY4

SB0/SB1 high level

width

Note RL is the resistance of the SB0/SB1 output line load, while CL is the capacitance.

Data Sheet U10738EJ3V2DS

62

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

AC timing measurement points (excluding X1 and XT1 inputs)

V

IH (Min.)

V

IH (Min.)

IL (Max.)

VIL (Max.)

V

V

OH (Min.)

OL (Max.)

V

OH (Min.)

OL (Max.)

V

V

Clock timing

1/f

X

t

XL

t

XH

V

DD - 0.1 V

X1 input

0.1 V

1/fXT

t

XTL

t

XTH

V

DD - 0.1 V

XT1 input

0.1 V

TI0 timing

1/fTI

tTIL

tTIH

TI0

Data Sheet U10738EJ3V2DS

63

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Serial transfer timing

Three-wire serial I/O mode:

t

t

KCY1

KCY2

t

t

KL1

KL2

t

t

KH1

KH2

SCK

t

t

SIK1

SIK2

t

t

KSI1

KSI2

Input data

SI

t

t^KKS^SO^O2¹

SO

Output data

Two-wire serial I/O mode:

t

t^KKC^CY^Y2¹

t

t^KKL^L2¹

t

t^KKH^H2¹

SCK

t

t^KKS^SI^I2¹

t

t^SSI^IK^K2¹

SB0 and SB1

t

t^KKS^SO^O2¹

Data Sheet U10738EJ3V2DS

64

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Serial transfer timing

Bus release signal transfer:

t

t^KKC^CY^Y4³

t

t

t^KKL^L4³

t^KKH^H4³

SCK

t

t^KKS^SI^I4³

t

t^SSI^IK^K4³

t

KSB

t

SBL

tSBH

t

SBK

SB0 and SB1

t

t^KKS^SO^O4³

Command signal transfer:

t

t^KKC^CY^Y4³

t

t

t^KKL^L4³

t^KKH^H4³

SCK

t

t

t^SSI^IK^K4³

t^KKS^SI^I4³

t

KSB

t

SBK

SB0 and SB1

t

t^KKS^SO^O4³

Interrupt input timing

tINTL

tINTH

INT0, INT1, INT2,

and INT4

KR0 - KR7

RESET input timing

t

RSL

RESET

Data Sheet U10738EJ3V2DS

65

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE

(T^A= -40 to +85 °C)

Parameter

Symbol

tSREL

Min.

0

Max.

Unit

µs

Typ.

Conditions

Release signal setting time

Note 1

Note 2

Note 3

tWAIT

Release by RESET

Release by interrupt request

Oscillation settling time

ms

ms

Notes 1. CPU operation stop time for preventing unstable operation at the beginning of oscillation.

2. Select either 2¹⁷/fX or 2¹⁵/fX with the mask option.

3. This value depends on the settings of the basic interval timer mode register (BTM) shown below.

BTM3

BTM1

BTM2

BTM0

Wait time

At f^X= 4.19 MHz

At fX = 6.0 MHz

-

-

-

-

0

1

1

1

2²⁰/fX (approx. 250 ms)

2¹⁷/fX (approx. 31.3 ms)

2¹⁵/fX (approx. 7.81 ms)

2¹³/fX (approx. 1.95 ms)

2²⁰/fX (approx. 175 ms)

2¹⁷/fX (approx. 21.8 ms)

2¹⁵/fX (approx. 5.46 ms)

2¹³/fX (approx. 1.37 ms)

0

0

1

1

0

1

0

1

Data hold timing (STOP mode release by RESET)

Internal reset operation

HALT mode

STOP mode

Data hold mode

Operation

mode

VDD

tSREL

STOP instruction execution

RESET

tWAIT

Data hold timing (standby release signal: STOP mode release by interrupt signal)

HALT mode

STOP mode

Data hold mode

Operation

mode

V

DD

t

SREL

STOP instruction execution

Standby release signal

(Interrupt request)

t

WAIT

Data Sheet U10738EJ3V2DS

66

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

13. CHARACTERISTIC CURVE (REFERENCE VALUES)

IDD vs. VDD (When the main system clock is operating at 6.0 MHz with a crystal)

(T = 25 °C)

A

10

5.0

PCC = 0011

PCC = 0010

PCC = 0001

PCC = 0000

Main system clock

HALT mode + 32 kHz oscillation

1.0

0.5

0.1

Subsystem clock operating mode

(SOS.1 = 0)

Main system clock

0.05

STOP mode + 32 kHz oscillation,

and subsystem clock HALT mode

(SOS.1 = 0)

Subsystem clock operating mode

(SOS.1 = 1)

Subsystem clock HALT mode

(SOS.1 = 1)

0.01

0.005

X1

X2

Crystal

XT1

XT2

Crystal

330 k

Ω

6.0 MHz

32.768 kHz

22 pF

22 pF

22 pF

22 pF

0.001

0

1

2

3

4

5

6

7

8

Supply voltage

VDD (V)

Data Sheet U10738EJ3V2DS

67

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

IDD vs. VDD (When the main system clock is operating at 4.19 MHz with a crystal)

(TA = 25 °C)

10

5.0

PCC = 0011

PCC = 0010

PCC = 0001

PCC = 0000

Main system clock

HALT mode + 32 kHz oscillation

1.0

0.5

0.1

Subsystem clock operating mode

(SOS.1 = 0)

Main system clock

0.05

STOP mode + 32 kHz oscillation,

and subsystem clock HALT mode

(SOS.1 = 0)

Subsystem clock operating mode

(SOS.1 = 1)

Subsystem clock HALT mode

(SOS.1 = 1)

0.01

0.005

X1

X2

Crystal

XT1

XT2

Crystal

330 k

Ω

4.19 MHz

32.768 kHz

22 pF

22 pF

22 pF

22 pF

0.001

0

1

2

3

4

5

6

7

8

Supply voltage

VDD (V)

Data Sheet U10738EJ3V2DS

68

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

IOH vs. VDD - VOH (Ports 2, 3, 6, 7, and 8)

(TA = 25 °C)

15

10

5

V

DD = 5 V VDD = 4 V

V

DD = 2.2 V

VDD = 3 V

VDD = 5.5 V

V

DD = 1.8 V

0

0

0.5

1.0

1.5

2.0

2.5

3.0

VDD - VOH [V]

I^OLvs. VOL (Ports 2, 3, 6, 7, and 8)

(T

A

= 25 °C)

40

30

20

10

0

V

DD = 5 V VDD = 4 V

V

DD = 5.5 V DD = 3 V

V

V

DD = 2.2 V

V

DD = 1.8 V

0

0.5

1.0

1.5

2.0

VOL [V]

Data Sheet U10738EJ3V2DS

69

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

14. PACKAGE DRAWINGS

Package drawings of mass-produced products (1/2)

44 PIN PLASTIC QFP ( 10)

A

B

23

22

33

34

detail of lead end

S

C

D

R

Q

12

11

44

1

F

J

M

H

G

I

K

M

P

N

L

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.16 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

+0.008

A

B

C

D

13.2 0.2

10.0 0.2

10.0 0.2

13.2 0.2

0.520

0.394

0.394

0.520

–0.009

+0.008

–0.009

+0.008

–0.009

+0.008

–0.009

F

1.0

1.0

0.039

0.039

G

+0.08

+0.003

–0.004

H

0.37

0.015

–0.07

I

0.16

0.007

J

0.8 (T.P.)

1.6 0.2

0.031 (T.P.)

0.063 0.008

K

L

+0.009

0.031

0.8 0.2

–0.008

+0.002

0.007

+0.06

0.17

M

–0.003

–0.05

N

P

Q

0.10

0.004

2.7

0.106

0.125 0.075

0.005 0.003

+7°

3°

+7°

3°

R

S

–3°

–3°

3.0 MAX.

0.119 MAX.

S44GB-80-3BS

Caution The ES version is different from the corresponding mass-produced products in shape and material.

See "ES package drawings."

Data Sheet U10738EJ3V2DS

70

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Package drawings of mass-produced products (2/2)

42PIN PLASTIC SHRINK DIP (600 mil)

42

22

1

21

A

K

L

F

B

R

M

C

D

M

N

NOTES

ITEM MILLIMETERS

INCHES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

A

B

C

39.13 MAX.

1.78 MAX.

1.778 (T.P.)

1.541 MAX.

0.070 MAX.

0.070 (T.P.)

2) Item "K" to center of leads when formed parallel.

+0.004

0.020

D

0.50 0.10

–0.005

F

G

H

I

0.9 MIN.

3.2 0.3

0.035 MIN.

0.126 0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.600 (T.P.)

0.520

0.51 MIN.

4.31 MAX.

5.08 MAX.

15.24 (T.P.)

13.2

J

K

L

+0.004

0.010

+0.10

0.25

M

–0.003

–0.05

N

R

0.17

0.007

0~15°

0~15°

P42C-70-600A-1

Caution The shape and material of the ES version are the same as those of the corresponding mass-

produced products.

Data Sheet U10738EJ3V2DS

71

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

ES package drawing

44 PIN CERAMIC QFP FOR ES (REFERENCE)

11.43

8.0

44

34

1

33

23

11

12

22

0.15

0.8

0.32

(Bottom)

Cautions 1. Find the location of pin 1 by checking the location of pin 17, which is connected to the metal

cap.

2. The metal cap is connected to pin 17. The electrical level of the metal cap is V^SS(GND).

3. The lead length has not been specified because leads are cut without any detailed specifications.

Data Sheet U10738EJ3V2DS

72

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

15. RECOMMENDED SOLDERING CONDITIONS

The µPD750004, µPD750006, andµPD750008shouldbesolderedandmountedunderthefollowingrecommended

conditions.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Table 15-1. Surface Mounting Type Soldering Conditions (1/2)

(1) µPD750004GB-×××-3BS-MTX:

µPD750006GB-×××-3BS-MTX:

µPD750008GB-×××-3BS-MTX:

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

µPD750004GB(A)-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

µPD750006GB(A)-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

µPD750008GB(A)-×××-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Soldering

Recommended

Soldering Conditions

Method

Condition Symbol

Infrared reflow

Package peak temperature: 235˚C, Time: 30 seconds max. (at 210˚C or higher),

Count: Three times or less

IR35-00-3

VP15-00-3

WS60-00-1

—

VPS

Package peak temperature: 215˚C, Time: 40 seconds max. (at 200˚C or higher),

Count: Twice or less

Wave soldering Solder bath temperature: 260˚C max., Time: 10 seconds max., Count: Once

Preheating temperature: 120˚C max. (package surface temperature)

Partial heating

Pin temperature: 350˚C max., Time: 3 seconds max. (per pin row)

Caution Do not use different soldering methods together (except for partial heating).

Remark For soldering methods and conditions other than those recommended above, contact an NEC Electronics

sales representative.

Data Sheet U10738EJ3V2DS

73

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Table 15-1. Surface Mounting Type Soldering Conditions (2/2)

(2) µPD750004GB-×××-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

µPD750006GB-×××-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

µPD750008GB-×××-3BS-MTX-A: 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Soldering

Recommended

Soldering Conditions

Method

Condition Symbol

Infrared reflow

Package peak temperature: 260˚C, Time: 60 seconds max. (at 220˚C or higher),

Count: Three times or less,

Exposure limit: 7 days^Note(after that, prebake at 125˚C for 20 to 72 hours)

IR60-207-3

Wave soldering For details, contact an NEC Electronics sales representative.

Partial heating Pin temperature: 350˚C max., Time: 3 seconds max. (per pin row)

—

—

Note After opening the dry pack, store it at 25˚C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remarks 1. Products with “-A” at the end of the part number are lead-free products.

2. For soldering methods and conditions other than those recommended above, contact an NEC

Electronics sales representative.

Table 15-2. Insertion Type Soldering Conditions

µPD750004CU-×××:

µPD750006CU-×××:

µPD750008CU-×××:

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

µPD750004CU-×××-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

µPD750006CU-×××-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

µPD750008CU-×××-A: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

µPD750004CU(A)-×××: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

µPD750006CU(A)-×××: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

µPD750008CU(A)-×××: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

Soldering Method

Wave soldering (pin only)

Partial heating

Soldering Conditions

Solder bath temperature: 260˚C max., Time: 10 seconds max.

Pin temperature: 300˚C max., Time: 3 seconds max. (for each pin)

Caution Apply wave soldering to pins only. See to it that the jet solder does not contact with the chip directly.

Remarks 1. Products with “-A" at the end of the part number are lead-free products.

2. For soldering methods and conditions other than those recommended above, contact an NEC

Electronics sales representative.

Data Sheet U10738EJ3V2DS

74

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

APPENDIX A FUNCTIONS OF THE µPD75008, µPD750008, AND µPD75P0016

(1/2)

Item

Program memory

µPD75008

Masked ROM

µPD750008

Masked ROM

µPD75P0016

One-time PROM

0000H - 1F7FH

0000H - 1FFFH

0000H - 3FFFH

(8064 × 8 bits)

(8192 × 8 bits)

(16384 × 8 bits)

000H - 1FFH

Data memory

(512 × 4 bits)

CPU

75X standard CPU

75XL CPU

General-purpose register

4 bits × 8 or 8 bits × 4

(4 bits × 8 or 8 bit × 4) × 4 banks

When selecting the main

• 0.95, 1.91, 15.3 µs

(when operating at

4.19 MHz)

• 0.95, 1.91, 3.81, 15.3 µs (when operating at 4.19 MHz)

• 0.67, 1.33, 2.67, 10.7 µs (when operating at 6.0 MHz)

system clock

When selecting the subsys-

tem clock

122 µs (when operating at 32.768 kHz)

SBS register

Not provided

Provided

SBS.3 = 1: Mk Ι mode selection

SBS.3 = 0: Mk ΙΙ mode selection

Stack area

000H - 0FFH

2-byte stack

n00H - nFFH (n = 0, 1)

Stack operation for a

Mk Ι mode: 2-byte stack

Mk ΙΙ mode: 3-byte stack

subroutine call instruction

BRA !addr1

Not available

Mk Ι mode: Not available

Mk ΙΙ mode: Available

CALLA !addr1

MOVT XA, @BCDE

MOVT XA, @BCXA

BR BCDE

Available

BR BCXA

CALL !addr

3 machine cycles

2 machine cycles

Mk Ι mode: 3 machine cycles

Mk ΙΙ mode: 4 machine cycles

CALLF !faddr

Mk Ι mode: 2 machine cycles

Mk ΙΙ mode: 3 machine cycles

Timer

4 channels

3 channels

• Basic interval timer/watchdog timer: 1 channel

• 8-bit timer/event counter: 1 channel

• 8-bit timer counter: 1 channel

• Clock timer: 1 channel

• Basic interval timer:

1 channel

• 8-bit timer/event counter:

1 channel

• Clock timer: 1 channel

Clock output (PCL)

BUZ output (BUZ)

• Φ, 524, 262, 65.5 kHz

(when the main system

clock operates at

4.19 MHz)

• Φ, 524, 262, 65.5 kHz

(when the main system clock operates at 4.19 MHz)

• Φ, 750, 375, 93.8 kHz

(when the main system clock operates at 6.0 MHz)

• 2 kHz

• 2, 4, 32 kHz

(when the main system clock operates at 4.19 MHz)

• 2.93, 5.86, 46.9 kHz

(when the main system clock operates at 6.0 MHz)

Data Sheet U10738EJ3V2DS

75

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

(2/2)

Item

µPD75008

µPD750008

µPD75P0016

Serial interface

3 modes are supported.

• Three-wire serial I/O mode: First transferred bit switchable between the LSB and

MSB

• Two-wire serial I/O mode

• SBI mode

Feedback resistor cut flag

(SOS.0)

Can incorporate feedback

resistors that are specified

with the mask option.

Incorporated

Sub-oscillator current cut flag Not provided

(SOS.1)

Incorporated

Provided

Register bank selection register

(RBS)

Not provided

Standby release with INT0

Disable

Enable

Number of vectored interrupts

Processor clock control register

External: 3, internal: 3

External: 3, internal: 4

Available when PCC is 0 to 3

Available when PCC is 0,

2, or 3

Power supply

V^DD= 2.7 to 6.0 V

V^DD= 2.2 to 5.5 V

Operating ambient temperature

Package

TA = -40 to +85 °C

• 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

• 44-pin plastic QFP (10 × 10 mm, 0.8 mm pitch)

Data Sheet U10738EJ3V2DS

76

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for the development of a system which employs the µPD750008.

In the 75XL series, use the common relocatable assembler together with a device file of each model.

Language processors

RA75X relocatable assembler

Part number

Host machine

Distribution media

3.5-inch 2HD

OS

TM

µS5A13RA75X

PC-9800 series

MS-DOS

Ver. 3.30

to

µS5A10RA75X

5.25-inch 2HD

Note

Ver. 6.2

TM

µS7B13RA75X

µS7B10RA75X

3.5-inch 2HC

5.25-inch 2HC

IBM PC/AT and See "OS for IBM PC."

compatibles

Device file

Host machine

OS

Part number

Distribution media

3.5-inch 2HD

PC-9800 series

MS-DOS

µS5A13DF750008

µS5A10DF750008

Ver. 3.30

to

5.25-inch 2HD

Note

Ver. 6.2

IBM PC/AT and

3.5-inch 2HC

5.25-inch 2HC

µS7B13DF750008

µS7B10DF750008

See "OS for IBM PC."

compatibles

Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later.

Remark The operations of the assembler and device file are guaranteed only on the above host machines and OSs.

Data Sheet U10738EJ3V2DS

77

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

PROM programming tools

Hardware

PG-1500

The PG-1500 PROM programmer is used together with an accessory board and optional

program adapter. It allows the user to program a single chip microcontroller containing

PROM from a standalone terminal or a host machine. The PG-1500 can be used to

program typical 256K-bit to 4M-bit PROMs.

PA-75P008CU

The PA-75P008CU is a PROM programmer adapter provided for the µPD75P0016CU/GB.

It is used in conjunction with the PG-1500.

Software

PG-1500 controller

This program enables the host machine to control the PG-1500 through the serial and

parallel interfaces.

Part number

Host machine

OS

Distribution media

3.5-inch 2HD

µS5A13PG1500

PC-9800 series

MS-DOS

Ver. 3.30

to

µS5A10PG1500

5.25-inch 2HD

Note

Ver. 6.2

µS7B13PG1500

µS7B10PG1500

IBM PC/AT and

compatibles

See "OS for IBM PC." 3.5-inch 2HD

5.25-inch 2HC

Note These software products cannot use the task swap function, which is available in MS-DOS Ver. 5.00 or later.

Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.

Data Sheet U10738EJ3V2DS

78

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Debugging tools

The in-circuit emulators (IE-75000-R and IE-75001-R) are provided to debug programs used for the µPD750008.

The system configuration is shown below.

Note 1

IE-75000-R

The IE-75000-R is an in-circuit emulator used to debug hardware and software when

developing an application system using the 75X series and 75XL series. Use this

emulator together with optional emulation board IE-75300-R-EM and emulation probe

EP-75008CU-R or EP-75008G to develop application systems of the µPD750008

subseries.

For efficient debugging, connect the emulator to the host machine and a PROM

programmer.

The IE-75000-R contains emulation board IE-75000-R-EM. The board is connected

to the IE-75000-R.

IE-75001-R

The IE-75001-R is an in-circuit emulator used to debug hardware and software when

developing an application system using the 75X series and 75XL series. Use this

emulator together with optional emulation board IE-75300-R-EM and emulation probe

EP-75008CU-R or EP-75008GB-R to develop application systems of the µPD750008

subseries.

For efficient debugging, connect the emulator to the host machine and a PROM

programmer.

IE-75300-R-EM

EP-75008CU-R

EP-75008GB-R

The IE-75300-R-EM is an emulation board used to evaluate an application system

using the µPD750008 subseries.

Use this board together with the IE-75000-R or IE-75001-R.

The EP-75008CU-R is an emulation probe for the µPD750008CU.

Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-R-

EM.

The EP-75008GB-R is an emulation probe for the µPD750008GB.

Connect this emulation probe to the IE-75000-R or IE-75001-R, and the IE-75300-R-

EM.

A 44-pin conversion socket, the EV-9200G-44, supplied with this probe facilitates the

connection of the probe to the target system.

EV-9200G-44

IE control program

This program enables the host machine to control the IE-75000-R or IE-75001-R

through the RS-232-C and Centronics interface.

Host machine

Part number

µS5A13IE75X

µS5A10IE75X

Distribution media

3.5-inch 2HD

OS

PC-9800 series

MS-DOS

Ver. 3.30

to

5.25-inch 2HD

Note 2

Ver. 6.2

IBM PC/AT and

compatibles

3.5-inch 2HC

5.25-inch 2HC

See "OS for IBM PC."

µS7B13IE75X

µS7B10IE75X

Notes 1. Maintenance service only

2. These software products cannot use the task swap function, which is available in MS DOS Ver. 5.00 or

later.

Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.

2. The µPD750004, µPD750006, µPD750008, and µPD75P0016 are collectively called the µPD750008

subseries.

Data Sheet U10738EJ3V2DS

79

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

OS for IBM PC

The following IBM PC OSs are supported.

OS

Version

TM

PC DOS

Ver. 3.1 to Ver. 6.3

Note

Note

J6.1/V

to J6.3/V

MS-DOS

IBM DOS

Ver. 5.0 to Ver. 6.22

Note

Note

5.0/V

to 6.2/V

TM

Note

J5.02/V

Note Only English version is supported.

Caution These software products cannot use the task swap function, which is available in MS-DOS

Ver. 5.0 or later.

Data Sheet U10738EJ3V2DS

80

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

APPENDIX C RELATED DOCUMENTS

Some documents are preliminary editions, but they are not so specified in the tables below.

Documents related to devices

Document name

Document number

Japanese

U10738J

English

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) Data

U10738E (This manual)

Sheet

U10328J

U10740J

IEM-5593

U10453J

U10328E

U10740E

-

µPD75P0016 Data Sheet

µPD750008 User’s Manual

µPD750008 Instruction List

75XL Series Selection Guide

U10453E

Documents related to development tools

Document number

Japanese

Document name

English

EEU-1416

Hardware

EEU-846

U11354J

EEU-699

EEU-698

U11940J

EEU-731

EEU-730

EEU-704

EEU-5008

IE-75000-R/IE-75001-R User's Manual

IE-75300-R-EM User's Manual

EP-75008CU-R User's Manual

EP-75008GB-R User's Manual

PG-1500 User's Manual

U11354E

EEU-1317

EEU-1305

EEU-1335

EEU-1346

EEU-1363

EEU-1291

U10540E

RA75X Assembler Package User's

Manual

Operation

Language

Software

PG-1500 Controller

User's Manual

PC-9800 series (MS-DOS) base

IBM PC series (PC DOS) base

Other related documents

Document number

Japanese

Document name

English

C10943X

C10535J

C11531J

C10983J

MEM-539

C11893J

U11416J

IC Package Manual

C10535E

C11531E

C10983E

Semiconductor Device Mounting Technology Manual

Quality Grade on NEC Semiconductor Devices

Reliability and Quality Control of NEC Semiconductor Devices

Electrostatic Discharge (ESD) Test

-

-

Semiconductor Device Quality Guarantee Guide

Microcontroller-Related Products Guide - by third parties

MEI-1202

Caution The above related documents are subject to change without notice. Be sure to use the latest edition

when you design your system.

Data Sheet U10738EJ3V2DS

81

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

NOTES FOR CMOS DEVICES

1

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is

fixed, and also in the transition period when the input level passes through the area between V^IL(MAX)

and V^IH(MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor

GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins

must be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

Data Sheet U10738EJ3V2DS

82

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

•

•

•

•

•

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

[GLOBAL SUPPORT]

http://www.necel.com/en/support/support.html

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics America, Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

NEC Electronics (Europe) GmbH

Duesseldorf, Germany

Tel: 0211-65030

800-366-9782

•

•

•

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Sucursal en España

Madrid, Spain

Tel: 091-504 27 87

Tel: 02-558-3737

Succursale Française

Vélizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics Shanghai Ltd.

Shanghai, P.R. China

Tel: 021-5888-5400

Filiale Italiana

Milano, Italy

Tel: 02-66 75 41

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

•

Branch The Netherlands

Eindhoven, TheNetherlands

Tel: 040-2654010

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore

Tel: 6253-8311

•

•

Tyskland Filial

Taeby, Sweden

Tel: 08-63 87 200

United Kingdom Branch

Milton Keynes, UK

Tel: 01908-691-133

J05.6

Data Sheet U10738EJ3V2DS

83

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

MS-DOS is a trademark of Microsoft Corporation.

IBM DOS, PC/AT, and PC DOS is a trademark of IBM Corporation.

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

•

The information in this document is current as of August, 2005. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

相关型号：

UPD750006CUA

4 BIT SINGLE-CHIP MICROCONTROLLER

NEC

UPD750006CUA-XXX

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PDIP42, 0.600 INCH, SHRINK, PLASTIC, DIP-42

NEC

UPD750006GB

4 BIT SINGLE-CHIP MICROCONTROLLER

NEC

UPD750006GB(A)-XXX-3BS

4-Bit Microcontroller

ETC

UPD750006GB-XXX-3BS

4-Bit Microcontroller

ETC

UPD750006GB-XXX-3BS-MTX

UPD750006GB-XXX-3BS-MTX

RENESAS

UPD750006GB-XXX-3BS-MTX

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44

NEC

UPD750006GB-XXX-3BS-MTX-A

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, PLASTIC, QFP-44

NEC

UPD750006GB-XXX-3BS-MTX-A

UPD750006GB-XXX-3BS-MTX-A

RENESAS

UPD750006GB-XXX3B4

4-Bit Microcontroller

ETC

UPD750006GBA

4 BIT SINGLE-CHIP MICROCONTROLLER

NEC

UPD750006GBA-XXX-3BS-MTX

Microcontroller, 4-Bit, MROM, 6MHz, MOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44

NEC

©2020 ICPDF网联系我们和版权申明