UPD68BMC-XXX-5A4 [NEC]
Microcontroller, 4-Bit, MROM, 4.5MHz, MOS, PDSO20, 0.300 INCH, PLASTIC, SSOP-20;
| 型号： | UPD68BMC-XXX-5A4 |
| 厂家： | 
NEC |
| 描述： | Microcontroller, 4-Bit, MROM, 4.5MHz, MOS, PDSO20, 0.300 INCH, PLASTIC, SSOP-20 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总72页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD67B, 68B
4-BIT SINGLE-CHIP MICROCONTROLLERS
FOR INFRARED REMOTE CONTROL TRANSMISSION
DESCRIPTION
With their 1.65 V low-voltage operation, carrier generator for infrared remote control transmission, standby
release function through key input, and programmable timer, the µPD67B and 68B are ideal for infrared remote
control transmitters.
A one-time PROM product, the µPD6P9, has also been provided for the µPD67B and 68B for program evaluation
or small-quantity production.
FEATURES
• Program memory (ROM)
• µPD67B:
• µPD68B:
1,002 × 10 bits
2,026 × 10 bits
• Data memory (RAM): 32 × 4 bits
• On-chip carrier generator for infrared remote control: Each high-/low-level width can be set from 250 ns to 64
µs (@ fX = 4 MHz operation) via modulo registers
• 9-bit programmable timer: 1 channel
• Instruction execution time: 16 µs (@ fX = 4 MHz operation: ceramic oscillation)
• Stack level:
1 level (stack RAM is also used as data memory RF)
• I/O pins (KI/O):
8
4
• Input pins (KI):
• Sense input pins (S0, S2): 2
• S1/LED pin (I/O):
• Power supply voltage:
1 (when in output mode, this is the remote control transmission display pin)
VDD = 1.65 to 3.6 V
• Operating ambient temperature: TA = –40 to +85°C
• Oscillation frequency: fX = 3.5 to 4.5 MHz
• On-chip POC circuit and RAM retention detector
APPLICATIONS
Infrared remote control transmitters (for AV and household electric appliances)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. U16792EJ1V0DS00 (1st edition)
Date Published January 2004 N CP(K)
Printed in Japan
2004
µPD67B, 68B
ORDERING INFORMATION
Part Number
Package
µPD67BMC-×××-5A4
µPD68BMC-×××-5A4
20-pin plastic SSOP (7.62 mm (300))
20-pin plastic SSOP (7.62 mm (300))
Remark ××× indicates ROM code suffix.
PIN CONFIGURATION (TOP VIEW)
20-pin plastic SSOP (7.62 mm (300))
• µPD67BMC-×××-5A4
• µPD68BMC-×××-5A4
K
I/O6
I/O7
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
K
K
K
K
K
K
K
K
K
K
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
I3
K
S0
S1
/LED
REM
V
DD
XOUT
X
IN
I2
GND
I1
S
2
I0
Caution The pin numbers of KI and KI/O are in the reverse order of those in the µPD6600A.
Data Sheet U16792EJ1V0DS
2
µPD67B, 68B
BLOCK DIAGRAM
4
8
3
4
8
3
Port K
I
K
K
S
I0 to KI3
Carrier
generator
REM
CPU
core
ROM
Port KI/O
Port S
I/O0 to KI/O7
9-bit timer
S /LED
1
0, S1/LED, S
2
RAM
X
IN
System control
XOUT
VDD
GND
LIST OF FUNCTIONS
Item
µPD67B
1,002 × 10 bits
µPD68B
µPD6P9M1
ROM capacity
2,026 × 10 bits
4,074 × 10 bits
One-time PROM
128 × 4 bits
Mask ROM
RAM capacity
Stack
32 × 4 bits
1 level (also used as RF of RAM)
I/O pins
•
•
•
•
Key input (KI):
4
8
3
Key I/O (KI/O):
Key extended input (S0, S1, S2):
Remote control transmission display output (LED): 1 (also used as S1 pin)
Number of keys
Clock frequency
•
•
32
56 (when extended by key extension input)
Ceramic oscillation
fX = 3.5 to 4.5 MHz
16 µs (@ fX = 4 MHz)
•
Instruction execution time
Carrier frequency
Each high-/low-level width can be set from 250 ns to 64 µs (@ fX = 4 MHz operation)
via modulo registers
Timer
9-bit programmable timer: 1 channel, timer clock: fX/64
POC circuit
On-chip
On-chip
RAM retention detector
Capacitor for oscillator (15 pF) Not incorporated
Supply voltage VDD = 1.65 to 3.6 V
Operating ambient temperature TA = –40 to +85°C
Package 20-pin plastic SSOP (7.62 mm (300))
VDD = 2.2 to 3.6 V
Data Sheet U16792EJ1V0DS
3
µPD67B, 68B
CONTENTS
1. PIN FUNCTIONS ............................................................................................................................
1.1 List of Pin Functions ............................................................................................................
1.2 Pin I/O Circuits ......................................................................................................................
1.3 Connection of Unused Pins.................................................................................................
6
6
7
8
2. INTERNAL CPU FUNCTIONS .....................................................................................................
2.1 Program Counter (PC) ..........................................................................................................
2.2 Stack Pointer (SP) .................................................................................................................
2.3 Address Stack Register (ASR (RF))....................................................................................
9
9
9
9
2.4 Program Memory (ROM)....................................................................................................... 10
2.5 Data Memory (RAM) .............................................................................................................. 10
2.6 Data Pointer (DP)................................................................................................................... 11
2.7 Accumulator (A) .................................................................................................................... 11
2.8 Arithmetic and Logic Unit (ALU)......................................................................................... 12
2.9 Flags ....................................................................................................................................... 12
2.9.1 Status flag (F) .............................................................................................................................. 12
2.9.2 Carry flag (CY) ............................................................................................................................ 13
3. PORT REGISTERS (PX) .............................................................................................................. 14
3.1 KI/O Port (P0) ........................................................................................................................... 15
3.2 KI Port/Special Ports (P1)..................................................................................................... 15
3.2.1 KI port (P11: bits 4 to 7 of P1) ..................................................................................................... 15
3.2.2 S0 port (bit 2 of P1) ..................................................................................................................... 16
3.2.3 S1/LED port (bit 3 of P1) ............................................................................................................. 16
3.2.4 S2 port (bit 1 of P1) ..................................................................................................................... 16
3.3 Control Register 0 (P3)......................................................................................................... 17
3.3.1 RAM retention flag (bit 3 of P3) .................................................................................................. 18
3.4 Control Register 1 (P4)......................................................................................................... 19
4. TIMER .............................................................................................................................................. 20
4.1 Timer Configuration.............................................................................................................. 20
4.2 Timer Operation .................................................................................................................... 21
4.3 Carrier Output........................................................................................................................ 23
4.3.1 Carrier output generator.............................................................................................................. 23
4.3.2 Carrier output control .................................................................................................................. 24
4.4 Software Control of Timer Output....................................................................................... 26
5. STANDBY FUNCTION ................................................................................................................... 27
5.1 Outline of Standby Function ............................................................................................... 27
5.2 Standby Mode Setting and Release ................................................................................... 28
5.3 Standby Mode Release Timing ............................................................................................ 30
6. RESET ............................................................................................................................................. 31
Data Sheet U16792EJ1V0DS
4
µPD67B, 68B
7. POC CIRCUIT................................................................................................................................. 32
7.1 Functions of POC Circuit ..................................................................................................... 33
7.2 Oscillation Check at Low Power Supply Voltage .............................................................. 33
8. SYSTEM CLOCK OSCILLATOR.................................................................................................. 34
9. INSTRUCTION SET ....................................................................................................................... 35
9.1 Machine Language Output by Assembler ......................................................................... 35
9.2 Circuit Symbol Description ................................................................................................. 36
9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table ................ 37
9.4 Accumulator Manipulation Instructions ............................................................................ 41
9.5 I/O Instructions ...................................................................................................................... 44
9.6 Data Transfer Instructions ................................................................................................... 45
9.7 Branch Instructions .............................................................................................................. 47
9.8 Subroutine Instructions ....................................................................................................... 48
9.9 Timer Manipulation Instructions......................................................................................... 49
9.10 Other Instructions ................................................................................................................. 52
10. ASSEMBLER RESERVED WORDS ............................................................................................ 54
10.1 Mask Option Quasi-Directives ............................................................................................ 54
10.1.1 OPTION and ENDOP quasi-directives ....................................................................................... 54
10.1.2 Mask option definition quasi-directive ........................................................................................ 54
11. ELECTRICAL SPECIFICATIONS.................................................................................................. 55
12. CHARACTERISTIC CURVES (REFERENCE VALUES)............................................................ 59
13. APPLICATION CIRCUIT EXAMPLE ............................................................................................ 60
14. PACKAGE DRAWING .................................................................................................................... 63
15. RECOMMENDED SOLDERING CONDITIONS........................................................................... 64
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 65
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD67B, 68B,
AND OTHER PRODUCTS......................................................................................... 66
APPENDIX C. EXAMPLE OF REMOTE CONTROL TRANSMISSION FORMAT
(in the case of NEC transmission format in command
one-shot transmission mode) .................................................................................. 67
Data Sheet U16792EJ1V0DS
5
µPD67B, 68B
1. PIN FUNCTIONS
1.1 List of Pin Functions
Pin No.
Symbol
Function
Output Format
CMOS
push-pullNote 1
After Reset
1
KI/O0 to KI/O7 8-bit I/O port. Input/output can be specified in 8-bit units.
In input mode, the use of a pull-down resistor can be
specified.
High-level output
2
15 to 20
In output mode, these pins can be used as key scan
outputs from a key matrix.
3
4
S0
Input port.
—
High-impedance
(OFF mode)
Can also be used as a key return input from a key matrix.
In input mode, the use of a pull-down resistor for the S0
and S1 ports can be specified by software in 2-bit units.
If input mode is canceled by software, this pin is placed
in OFF mode and enters a high-impedance state.
S1/LED
I/O port.
CMOS push-pull
High-level output
(LED)
In input mode (S1), this pin can also be used as a key
return input from a key matrix.
The use of a pull-down resistor for the S0 and S1 ports
can be specified by software in 2-bit units.
In output mode (LED), this pin becomes the remote
control transmission display output (active low). When
the remote control carrier is output from the REM output,
this pin outputs a low level from the LED output in
synchronization with the REM signal.
5
6
REM
Infrared remote control transmission output.
This output is active high.
CMOS push-pull
Low-level output
Each carrier high-/low-level width can be freely set in
a range of 250 ns to 64 µs (@ fX = 4 MHz) by
software.
VDD
Power supply
—
—
—
7
8
XOUT
XIN
Pins for connecting ceramic resonators for the system
clock.
Low level
(oscillation stopped)
GND
9
GND
—
—
—
10
S2
Input
Input port.
(high-impedance,
STOP mode
release cannot be
used)
The use of STOP mode release for the S2 port can be
specified by software. When used as a key input from
a key matrix, enable the use of STOP mode release (at
this time, a pull-down resistor is connected internally).
When STOP mode release is disabled, this pin can be
used as an input port that does not release the STOP
mode even if the release condition is established
(at this time, a pull-down resistor is not connected internally).
Note 2
4-bit input port.
11 to 14
K
I0 to KI3
—
Input (low-level)
These pins can also be used as key return inputs
from a key matrix. The use of a pull-down resistor
can be specified by software in 4-bit units.
Notes 1. Be careful about this because the drive capacity of the low-level output side is held low.
2. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when
POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor
connected).
Data Sheet U16792EJ1V0DS
6
µPD67B, 68B
1.2 Pin I/O Circuits
The I/O circuits of pins of the µPD67B and 68B are shown in partially simplified forms below.
(1) KI/O0 to KI/O7
(4) S0
V
DD
Input buffer
OFF mode
Output
Data
latch
P-ch
N-chNote
Output
disable
Standby
release
N-ch
Pull-down flag
Input buffer
N-ch
(5) S1/LED
V
DD
Note The drive capacity is held low.
REM
output latch
P-ch
(2) KI0 to KI3
Standby
release
Output
disable
N-ch
Input buffer
Standby
release
Input buffer
Pull-down flag
N-ch
N-ch
Pull-down flag
(3) REM
(6) S2
V
DD
Standby
release
Input buffer
P-ch
Output
latch
Data
N-ch
STOP release
ON/OFF
N-ch
Carrier
generator
Data Sheet U16792EJ1V0DS
7
µPD67B, 68B
1.3 Connection of Unused Pins
The following connections are recommended for unused pins.
Table 1-1. Connection of Unused Pins
Pin
Connection
Inside the Microcontroller
Outside the Microcontroller
Leave open.
KI/O
Input mode
—
Output mode
High-level output
REM
S1/LED
S0
—
Output mode (LED) setting
OFF mode setting
Connect directly to GND.
S2
—
—
KI
Caution The I/O mode and the pin output level are recommended to be fixed by setting them
repeatedly in each loop of the program.
Data Sheet U16792EJ1V0DS
8
µPD67B, 68B
2. INTERNAL CPU FUNCTIONS
2.1 Program Counter (PC): 11 Bits
The program counter (PC) is a binary counter that holds the address information of the program memory.
Figure 2-1. Program Counter Configuration
PC PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
The PC contains the address of the instruction that should be executed next. Normally, the counter contents
are automatically incremented in accordance with the instruction length (byte count) each time an instruction is
executed.
However, when executing jump instructions (JMP, JC, JNC, JF, JNF), the PC contains the jump destination
address written in the operand.
When executing the subroutine call instruction (CALL), the call destination address written in the operand is
entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return
instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to
the PC.
After reset, the value of the PC becomes 000H.
2.2 Stack Pointer (SP): 1 Bit
This is a 1-bit register that holds the status of the address stack register.
The stack pointer contents are incremented when the call instruction (CALL) is executed and decremented when
the return instruction (RET) is executed.
After reset, the stack pointer contents are cleared to 0.
When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is defined as hung up, a system
reset signal is generated, and the PC becomes 000H.
As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer
by means of a program.
2.3 Address Stack Register (ASR (RF)): 11 Bits
The address stack register saves the return address of the program after a subroutine call instruction is executed.
The lower 8 bits are allocated in RF of the data memory as a alternate-function RAM. The register holds the
ASR value even after the RET instruction is executed.
After reset, it holds the previous data (undefined when turning on the power).
Caution If RF is accessed as the data memory, the higher 3 bits of the ASR become undefined.
Figure 2-2. Address Stack Register Configuration
RF
ASR ASR10 ASR9 ASR8 ASR7 ASR6 ASR5 ASR4 ASR3 ASR2 ASR1 ASR0
Data Sheet U16792EJ1V0DS
9
µPD67B, 68B
2.4 Program Memory (ROM): 1,002 Steps × 10 Bits (µPD67B)
2,026 Steps × 10 Bits (µPD68B)
The ROM consists of 10 bits per step, and is addressed by the program counter.
The program memory stores programs and table data, etc.
The 22 steps from 7EAH to 7FFH cannot be used in the test program area.
Figure 2-3. Program Memory Map
(a)
µ
PD67B
µ
(b) PD68B
10 bits
10 bits
0
000
H
0 0H
Page 0
Page 0
3
3
3
4
E9H
EAH
F H
F
0 0H
Unmounted areaNote
Test program areaNote
Page 1
7
7
7
7
E9H
EAH
E9H
EAH
Test program areaNote
7
7
FFH
FFH
Note The unmounted area and test program area are designed so that a program or data placed in either of
them by mistake is returned to the 000H address.
2.5 Data Memory (RAM): 32 × 4 Bits
The data memory, which is a static RAM consisting of 32 × 4 bits, is used to retain processed data. The data
memory is sometimes processed in 8-bit units. R0 can be used as the ROM data pointer.
RF is also used as the ASR.
After reset, R0 is cleared to 00H and R1 to RF retain the previous data (undefined when turning on the power).
Data Sheet U16792EJ1V0DS
10
µPD67B, 68B
Figure 2-4. Data Memory Configuration
Page 0
R1n (higher 4 bits) R0n (lower 4 bits)
→DP (refer to 2.6 Data Pointer (DP))
R0
R
R
R
R
R
R
R
R
R
R
R
R
10
11
12
13
14
15
16
17
18
19
1A
1B
R
R
R
R
R
R
R
R
R
R
R
R
00
01
02
03
04
05
06
07
08
09
0A
0B
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
RC
RD
RE
RF
R1C
R1D
R1E
R1F
R0C
R0D
R0E
R0F
→ASR (refer to 2.3 Address Stack Register (ASR (RF)))
2.6 Data Pointer (DP): 12 Bits
The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents.
The lower 8 bits of the ROM address are specified by R0 of the data memory; and the higher 4 bits by bits 4
to 7 of the P3 register (CR0).
After reset, the pointer contents become 000H.
Figure 2-5. Data Pointer Configuration
P3 register
b7
b6
b5
b
4
R10
R00
Note
Note
P3
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DP0
R0
Note Set DP10 and DP11 to 0 in the case of the µPD67B and set DP10 to 0 in the case of the µPD68B.
2.7 Accumulator (A): 4 Bits
The accumulator, which refers to a register consisting of 4 bits, plays a leading role in performing various
operations.
After reset, the accumulator contents are left undefined.
Figure 2-6. Accumulator Configuration
A3
A2
A
1
A
0
A
Data Sheet U16792EJ1V0DS
11
µPD67B, 68B
2.8 Arithmetic and Logic Unit (ALU): 4 Bits
The arithmetic and logic unit (ALU), which refers to an arithmetic circuit consisting of 4 bits, executes simple
(mainly logical) operations.
2.9 Flags
2.9.1 Status flag (F)
Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.
The status flag is set (to 1) in the following cases.
• If the condition specified with the operand is met when the STTS instruction is executed
• When standby mode is released.
• When the release condition is met at the point of executing the HALT instruction. (In this case, the system
does not enter the standby mode.)
Conversely, the status flag is cleared (to 0) in the following cases.
• If the condition specified with the operand is not met when the STTS instruction is executed.
• When the status flag has been set (to 1), the HALT instruction executed, but the release condition is not met
at the point of executing the HALT instruction. (In this case, the system does not enter the standby mode.)
Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction
Operand Value of STTS Instruction
Condition for Status Flag (F) to Be Set
b3
b2
0
b1
0
b0
0
0
High level is input to at least one of KI pins.
0
1
1
High level is input to at least one of KI pins.
High level is input to at least one of KI pins.
The down counter of the timer is 0.
1
1
0
1
0
1
1
Either of the combinations
of b2, b1, and b0 above.
[The following condition is added in addition to the above.]
High level is input to at least one of S0Note 1, S1Note 1, or S2Note 2
pins.
Notes 1. The S0 and S1 pins must be set to input mode (bit 2 and bit 0 of the P4 register are set to 0 and 1,
respectively).
2. The use of STOP mode release for the S2 pin must be enabled (bit 3 of the P4 register is set to 1).
Data Sheet U16792EJ1V0DS
12
µPD67B, 68B
2.9.2 Carry flag (CY)
The carry flag is set (to 1) in the following cases.
• If the ANL instruction or the XRL instruction is executed when bit 3 of the accumulator is 1 and bit 3 of the
operand is 1.
• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 1.
• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is 0FH.
The carry flag is cleared (to 0) in the following cases.
• If the ANL instruction or the XRL instruction is executed when at least either bit 3 of the accumulator or bit
3 of the operand is 0.
• If the RL instruction or the RLZ instruction is executed when bit 3 of the accumulator is 0.
• If the INC instruction or the SCAF instruction is executed when the value of the accumulator is other than 0FH.
• If the ORL instruction is executed.
• When data is written to the accumulator by the MOV instruction or the IN instruction.
Data Sheet U16792EJ1V0DS
13
µPD67B, 68B
3. PORT REGISTERS (PX)
The KI/O port, the KI port, the special ports (S0, S1/LED, S2), and the control registers are treated as port registers.
After reset, the port register values are as shown below.
Figure 3-1. Port Register Configuration
Port register
P0
After reset
FFH
P10
P11
P13
P14
P00
P01
P03
P04
K
I/O7
K
I/O6
K
I/O5
K
I/O4
K
I/O3
K
I/O2
K
I/O1
K
I/O0
P1
××××11×1BNote 1
0000×000BNote 2
26H
K
I3
K
I2
K
I1
K
I0
S
1/LED
S
0
S
2
–
P3 (control register 0)
RAM
retention
flag
DP11
DP10
DP
9
DP
8
–
–
ID0
P4 (control register 1)
K
I
S
0
/S
1
S
2
0
0
S1/LED mode
KI/O mode
S
0
mode
Pull-down Pull-down
STOP release
Notes 1. ×: Refers to the value based on the KI and S2 pin state.
2. ×: Refers to the value based on decrease of power supply voltage (0 when VDD ≤ VID)
Remarks 1. VID: RAM retention detection voltage
2. For details of the RAM retention flag, refer to 3.3.1 RAM retention flag (bit 3 of P3).
Table 3-1. Relationship Between Ports and Reading/Writing
Input Mode
Write
Output Mode
Port Name
Read
Pin state
Pin state
Pin state
Pin state
Pin state
Read
Write
KI/O
Output latch
Output latch
Output latch
KI
—
—
—
—
—
Note
—
—
—
—
S0
S1/LED
S2
Pin state
—
Note When in OFF mode, “1” is always read.
Data Sheet U16792EJ1V0DS
14
µPD67B, 68B
3.1 KI/O Port (P0)
The KI/O port is an 8-bit I/O port for key scan output.
I/O mode is set by bit 1 of the P4 register.
If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can
be read in output mode.
If a write instruction is executed, data can be written to the output latch regardless of input or output mode.
After reset, the port is placed in output mode and the value of the output latch (P0) becomes 1111 1111B.
The KI/O port incorporates a pull-down resistor, allowing pull-down in input mode only.
Caution When a key is double-pressed, a high-level output and a low-level output may conflict at the
KI/O port. To avoid this, the low-level output current of the KI/O port is held low. Therefore, be
careful when using the KI/O port for purposes other than key scan output.
The KI/O port is designed so that even when connected directly to VDD within the normal supply
voltage range (VDD = 1.65 to 3.6 V), no problem occurs.
Table 3-2. KI/O Port (P0)
Bit
b7
b6
b5
b4
b3
b2
b1
b0
Name
KI/O7
KI/O6
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
KI/O0
b0 to b7: When reading: In input mode, the KI/O pin’s state is read.
In output mode, the KI/O pin’s output latch contents are read.
When writing: Data is written to the KI/O pin’s output latch regardless of input or output mode.
3.2 KI Port/Special Ports (P1)
3.2.1 KI port (P11: bits 4 to 7 of P1)
The KI port is a 4-bit input port for key input. The pin state can be read.
The use of a pull-down resistor for the KI port can be specified in 4-bit units by software using bit 5 of the P4
register. After reset, a pull-down resistor is connected.
Table 3-3. KI/Special Port Register (P1)
Bit
b7
b6
b5
b4
b3
/LED
b2
b1
b0
Name
K
I3
K
I2
K
I1
K
I0
S
1
S
0
S
2
Fixed to “1”
b1:
b2:
The state of the S2 pin is read (read only).
In input mode, state of the S0 pin is read (read only).
In OFF mode, this bit is fixed to 1.
b3:
The state of the S1/LED pin is read regardless of input or output mode (read only).
b4 to b7: The state of the KI pin is read (read only).
Caution In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3
when POC is released by supply voltage rising (Can be left open. When open, leave the pull-
down resistor connected).
Data Sheet U16792EJ1V0DS
15
µPD67B, 68B
3.2.2 S0 port (bit 2 of P1)
The S0 port is an input/OFF mode port.
The pin state can be read by setting this port to input mode using bit 0 of the P4 register.
In input mode, the use of a pull-down resistor for the S0 and S1/LED ports can be specified in 2-bit units by software
using bit 4 of the P4 register.
If input mode is released (thus set to OFF mode), the pin becomes high-impedance but is configured so that
through current does not flow internally. In OFF mode, 1 can be read regardless of the pin state.
After reset, S0 is set to OFF mode, thus becoming high-impedance.
3.2.3 S1/LED port (bit 3 of P1)
The S1/LED port is an I/O port.
Input or output mode can be set using bit 2 of the P4 register. The pin state can be read in both input mode
and output mode.
When in input mode, the use of a pull-down resistor for the S0 and S1/LED ports can be specified in 2-bit units
by software using bit 4 of the P4 register.
When in output mode, the pull-down resistor is automatically disconnected and this pin becomes the remote
control transmission display pin (refer to 4. TIMER).
After reset, S1/LED is placed in output mode, and a high level is output.
3.2.4 S2 port (bit 1 of P1)
The S2 port is an input port.
Use of STOP mode release for the S2 port can be specified by bit 3 of the P4 register.
When using the pin as a key input from a key matrix, enable (bit 3 of the P4 register is set to 1) the use of STOP
mode release (at this time, a pull-down resistor is connected internally). When STOP mode release is disabled
(bit 3 of the P4 register is set to 0), it can be used as an input port that does not release the STOP mode even if
the release condition is met (at this time, a pull-down resistor is not connected internally).
The state of the pin can be read in both cases.
After reset, S2 is set to input mode where the STOP mode release is disabled, and enters a high-impedance
state.
Data Sheet U16792EJ1V0DS
16
µPD67B, 68B
3.3 Control Register 0 (P3)
Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.
After reset, the register becomes 0000 ×000BNote
.
Note ×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID)
Remark VID: RAM retention detection voltage
Table 3-4. Control Register 0 (P3)
Note
Note
Bit
b7
b6
b5
b4
b3
b2
b1
b0
RAM
retention
flag
Name
DP (Data Pointer)
—
ID0
DP11
DP10
DP9
0
DP8
0
Setting
0
1
0
1
0
0
1
0
Not retainable Fixed to 0
Retainable
1
1
After reset
0
0
0
0
0
0
b3:
RAM retention flag. For function details, refer to 3.3.1 RAM retention flag (bit 3 of P3).
b4 to b7: Specify the higher bits of the ROM data pointer (DP8 to DP11).
Note Set b7 and b6 to 0 in the case of the µPD67B and set b7 to 0 in the case of the µPD68B.
Data Sheet U16792EJ1V0DS
17
µPD67B, 68B
3.3.1 RAM retention flag (bit 3 of P3)
The RAM retention flag indicates whether the supply voltage has fallen below the level at which the contents
of the RAM are lost while the battery is being exchanged or when the battery voltage has dropped.
This flag is at bit 3 of control register 0 (P3).
It is cleared to 0 if the supply voltage drops below the RAM retention detection voltage (approx. 1.5 V TYP.).
If this flag is 0, it can be judged that the RAM contents have been lost or that power has just been applied. This
flag can be used to initialize the RAM via software. After initializing the RAM and writing the necessary data to it,
set this RAM retention flag to 1 by software. At this time, 1 means that data has been set to the RAM.
Figure 3-2. Supply Voltage Transition and Detection Voltage
V
DD
V
POC/VID
POC detection voltage/
RAM retention detection voltage
V
POC = VID = 1.5 V (TYP.)
(A)
0 V
t
(1)
(2)
(3)
(4)
RAM retention flag
Set to 1
Flag contents
are read
(1) If the supply voltage rises after the battery has been set, and exceeds VPOC (POC detection voltage),
reset is cleared. Because the supply voltage rises from 0 V, which is lower than VID (RAM retention
detection voltage), the RAM retention flag remains in the initial status 0.
(2) The supply voltage has now risen to the level at which the device can operate. Write the necessary data
to the RAM and set the RAM retention flag to 1.
(3) The device is reset if the supply voltage drops below VPOC. At point (A) in the figure, the voltage is lower
than VID. Consequently, the RAM retention flag is cleared to 0.
(4) If the RAM retention flag is checked by software after reset has been cleared, it is 0. This means that
the contents of the RAM may have been lost. If this case, initialize the RAM by software.
Cautions 1. The software developed for the µPD67, 67A, 68, 68A, and 69 (using the RAM retention flag)
can be used for the µPD67B and 68B as is.
2. Unlike the µPD67, 67A, 68, 68A, and 69, the RAM retention detection voltage of the µPD67B
and 68B is the same as the POC detection voltage. When software is newly developed,
it is not necessary to use the RAM retention flag if only the RAM is initialized by reset.
Data Sheet U16792EJ1V0DS
18
µPD67B, 68B
3.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below.
After reset, the register becomes 0010 0110B.
Table 3-5. Control Register 1 (P4)
Bit
b7
b6
b5
KI
b4
b3
S2
b2
b1
b0
S0
Name
—
—
S0/S1
S1/LED KI/O
Pull-down Pull-down STOP release mode
mode
IN
mode
OFF
IN
Setting
0
1
Fixed
to 0
0
Fixed
to 0
0
OFF
ON
1
OFF
ON
0
Disable S1
Enable LED
OUT
1
After reset
0
1
0
b0: Specifies the input mode of the S0 port. 0 = OFF mode (high impedance); 1 = IN (input mode).
b1: Specifies the I/O mode of the KI/O port. 0 = IN (input mode); 1 = OUT (output mode).
b2: Specifies the I/O mode of the S1/LED port. 0 = S1 (input mode); 1 = LED (output mode).
b3: Specifies the use of STOP mode release by S2 port (with/without pull-down resistor). 0 = disable (without
pull-down); 1 = enable (with pull-down).
b4: Specifies the use of a pull-down resistor in S0/S1 port input mode. 0 = OFF (not used); 1 = ON (used).
b5: Specifies the use of a pull-down resistor for the KI port. 0 = OFF (not used); 1 = ON (used).
Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected.
Data Sheet U16792EJ1V0DS
19
µPD67B, 68B
4. TIMER
4.1 Timer Configuration
The timer is the block used for creating a remote control transmission pattern. As shown in Figure 4-1, it consists
of a 9-bit down counter (t8 to t0), a flag (t9) enabling the 1-bit timer output, and a zero detector.
Figure 4-1. Timer Configuration
T
Count
clock
T1
T0
t9
t8
t7
t6
t
5
t4
t
3
t2
t1
t0
fX/64
9-bit down counter
Timer operation end signal
(HALT # ×101B release
signal)
S
1/LED
Zero detector
Carrier
synchronous
circuit
REM
Carrier signal
Data Sheet U16792EJ1V0DS
20
µPD67B, 68B
4.2 Timer Operation
The timer starts (counting down) when a value other than 0 is set for the down counter with a timer manipulation
instruction. The timer manipulation instructions for making the timer start operation are shown below.
MOV T0, A
MOV T1, A
MOV T, #data10
MOV T, @R0
The down counter is decremented (–1) in the cycle of 64/fX. If the value of the down counter becomes 0, the
zero detector generates the timer operation end signal to stop the timer operation. At this time, if the timer is in
HALT mode (HALT #×101B) waiting for the timer to stop its operation, the HALT mode is released and the instruction
following the HALT instruction is executed. The output of the timer operation end signal is continued while the down
counter is 0 and the timer is stopped. The following relational expression applies between the timer’s output time
and the down counter’s set value.
Timer output time = (Set value + 1) × 64/fX – 4/fX
In addition, when the timer is set successively, the timer output time is also 4/fX shorter than the total time. An
example is shown below.
Example When fX = 4 MHz
MOV T, #3FFH
STTS #05H
HALT #05H
MOV T, #232H
STTS #05H
HALT #05H
In the case above, the timer output time is as follows.
(Set value + 1) × 64/fX + (Set value + 1) × 64/fX – 4/fX
= (511 + 1) × 64/4 + (50 + 1) × 64/4 – 4/4
= 9.007 ms
Data Sheet U16792EJ1V0DS
21
µPD67B, 68B
By setting the flag (t9) that enables the timer output to 1, the timer can output its operation status from the S1/
LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation.
Table 4-1. Timer Output (at t9 = 1)
S1/LED Pin
Low level
High level
REM Pin
High level (or carrier outputNote
Low level
Timer operating
Timer halting
)
Note The carrier output results if bit 9 (CARY) of the high-level period setting modulo register (MOD1) is cleared
(to 0).
Figure 4-2. Timer Output (When Carrier Is Not Output)
Timer output time:
4/fX
(Set value + 1) × 64/f
X
– 4/f
X
LED
REM
Data Sheet U16792EJ1V0DS
22
µPD67B, 68B
4.3 Carrier Output
4.3.1 Carrier output generator
The carrier generator consists of a 9-bit counter and two modulo registers for setting the high- and low-level
periods (MOD1 and MOD0 respectively).
Figure 4-3. Configuration of Remote Controller Carrier Generator
M1
M0
M11
M10
M01
M00
t
9
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
0
0
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
0
Modulo register for setting the low-level period (MOD0)Note 1
Modulo register for setting the high-level period (MOD1)
CARY
Carrier signal
Selector
Match
Clear
Comparator
9-bit counter
F/F
Note 2
9
2fX
f
X
t
f
Multiplier
X
Notes 1. Bit 9 of the modulo register for setting the low-level period (MOD0) is fixed to 0.
2. t9: Flag that enables timer output (timer block) (see Figure 4-1 Timer Configuration)
The carrier duty ratio and carrier frequency can be determined by setting the high- and low-level widths using
the respective modulo registers. Each of these widths can be set in a range of 250 ns to 64 µs (@ fX = 4 MHz).
The system clock multiplied by 2 is used for the 9-bit counter input (8 MHz when fX = 4 MHz).
MOD0 and MOD1 are read and written using timer manipulation instructions.
MOV A, M00
MOV A, M01
MOV A, M10
MOV A, M11
MOV M00, A
MOV M01, A
MOV M10, A
MOV M11, A
MOV M0, #data10
MOV M1, #data10
MOV M0, @R0
MOV M1, @R0
The values of MOD0 and MOD1 can be calculated from the following expressions.
MOD0 = (2 × fX × (1 – D) × T) – 1
MOD1 = (2 × fX × D × T) – 1
Caution Be sure to input values in range of 001H to 1FFH to MOD0 and MOD1.
Remark D: Carrier duty ratio (0 < D < 1)
fX: Input clock (MHz)
T: Carrier cycle (µs)
Data Sheet U16792EJ1V0DS
23
µPD67B, 68B
4.3.2 Carrier output control
Remote controller carrier can be output from the REM pin by clearing (0) bit 9 (CARY) of the modulo register
for setting the high-level period (MOD1).
When performing carrier output, be sure to set the timer operation after setting the MOD0 and MOD1 values.
Note that a malfunction may occur if the values of MOD0 and MOD1 are changed while carrier is being output from
the REM pin.
Executing the timer manipulation instruction starts the carrier output from the low level.
If the timer’s down counter reaches 0 during carrier output, carrier output is stopped and the REM pin becomes
low level. If the down counter reaches 0 while the carrier output is high level, carrier output will stop after first
becoming low level following the set period of high level.
Figure 4-4. Timer Output (When Carrier Is Output)
Timer manipulation instruction
Timer output time: (Set value + 1) × 64/f
X
– 4/f
X
LED
REM
t
H
Note
t
L
4/f
X
Note If the down counter reaches 0 while the carrier output is high level, carrier output will stop after becoming
low level.
Data Sheet U16792EJ1V0DS
24
µPD67B, 68B
Output from the REM pin is as follows, in accordance with the values set to bit 9 (CARY) of MOD1 and the timer
output enable flag (t9), and the value of the timer block’s 9-bit down counter (t0 to t8).
Table 4-2. REM Pin Output
MOD1 Bit 9 (CARY)
Timer Output Enable Flag
(Timer Block t9)
9-Bit Down Counter
(Timer Block t0 to t8)
REM Pin
—
—
0
—
0
0
Low-level output
Other than 0
1
Carrier outputNote
High-level output
1
Note Input values in the range of 001H to 1FFH to MOD0 and MOD1.
Caution MOD0 and MOD1 must be set while the REM pin is low level (t9 = 0 or t0 to t8 = 0).
Table 4-3. Example of Carrier Frequency Settings (fX = 4 MHz)
Setting Value
MOD1
tH (µs)
tL (µs)
T (µs)
Duty
fC (kHz)
MOD0
01H
0BH
13H
27H
41H
85H
89H
8BH
8CH
91H
94H
D5H
77H
C7H
FFH
01H
07H
13H
27H
41H
41H
45H
45H
45H
47H
48H
69H
77H
C7H
FFH
0.25
1.0
0.25
1.5
0.5
2.5
1/2
2/5
1/2
1/2
1/2
1/3
1/3
1/3
1/3
1/3
1/3
1/3
1/2
1/2
1/2
2,000
400
200
100
60.6
40
2.5
2.5
5.0
5.0
5.0
10
8.25
8.25
8.75
8.75
8.75
9.0
8.25
16.5
25
16.75
17.25
17.5
26.0
26.25
26.375
27.25
27.75
40.0
30.0
50.0
64.0
38.5
38.10
37.9
36.7
36.0
25
17.625
18.25
18.625
26.75
15.0
9.125
13.25
15.0
25.0
32.0
33.3
20
25.0
32.0
15.6
t
H
t
L
Carrier signal
T
Data Sheet U16792EJ1V0DS
25
µPD67B, 68B
4.4 Software Control of Timer Output
The timer output can be controlled by software. As shown in Figure 4-5, a pulse with a minimum width of
64/fX – 4/fX can be output.
Figure 4-5. Output of Pulse of 1-Instruction Cycle Width
MOV T, #0000000000B; low-level output from the REM pin
MOV T, #1000000000B; high-level output from the REM pin
MOV T, #0000000000B; low-level output from the REM pin
4/f
X
64/f
X
– 4/f
X
LED
REM
Data Sheet U16792EJ1V0DS
26
µPD67B, 68B
5. STANDBY FUNCTION
5.1 Outline of Standby Function
To save power consumption, two types of standby modes, i.e., HALT mode and STOP mode, have been provided
available.
In STOP mode, the system clock stops oscillation. At this time, the XIN and XOUT pins are fixed to a low level.
In HALT mode, CPU operation halts, while the system clock continues oscillation. When in HALT mode, the
timer (including REM output and LED output) operates.
In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port registers, etc.
immediately before the standby mode is set are retained. Therefore, make sure to set the port status for the system
so that the power consumption of the whole system is suppressed before the standby mode is set.
Table 5-1. Statuses During Standby Mode
STOP Mode
HALT instruction
HALT Mode
Setting instruction
Clock oscillator
Oscillation stopped
Oscillation continued
CPU
• Operation halted
Data memory
Accumulator
Flag
• Immediately preceding status retained
• Immediately preceding status retained
Operation
statuses
F
• 0 (When 1, the flag is not placed in the standby mode.)
• Immediately preceding status retained
CY
Port register
Timer
• Immediately preceding status retained
• Operation halted
• Operable
(The count value is reset to “0”)
Cautions 1. Write the NOP instruction as the first instruction after STOP mode is released.
2. When standby mode is released, the status flag (F) is set (to 1).
3. If, at the point the standby mode has been set, its release condition is met, then the system
does not enter the standby mode. However, the status flag (F) is set (1).
Data Sheet U16792EJ1V0DS
27
µPD67B, 68B
5.2 Standby Mode Setting and Release
The standby mode is set with the HALT #b3b2b1b0B instruction for both STOP mode and HALT mode. For the
standby mode to be set, the status flag (F) is required to have been cleared (to 0).
The standby mode is released by the release condition specified with the reset (POC) or the operand of HALT
instruction. If the standby mode is released, the status flag (F) is set (to 1).
Even when the HALT instruction is executed in the state that the status flag (F) has been set (to 1), the standby
mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition
is met, the status flag remains set (to 1).
Even in the case when the release condition has been already met at the point that the HALT instruction is
executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1).
Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be
careful about this. For example, when setting HALT mode after checking the key status with
the STTS instruction, the system does not enter HALT mode as long as the status flag (F)
remains set (to 1) and thus sometimes performs an unintended operation. In this case, the
intended operation can be realized by executing the STTS instruction immediately after setting
the timer to clear (to 0) the status flag.
Example STTS
#03H
;To check the KI pin status.
MOV
T, #0xxH ;To set the timer
STTS
#05H
;To clear the status flag
(During this time, be sure not to execute an instruction that may set the status flag.)
HALT
#05H
;To set HALT mode
Table 5-2. Addresses Executed After Standby Mode Release
Release Condition
Address Executed After Release
Address 0
The address following the HALT instruction
Reset
Release condition shown in Table 5-3
Data Sheet U16792EJ1V0DS
28
µPD67B, 68B
Table 5-3. Standby Mode Setup (HALT #b3b2b1b0B) and Release Conditions
Operand Value of
HALT Instruction
Setting Mode
Precondition for Setup
Release Condition
b3
b2
b1
b0
0
0
0
0
STOP
All KI/O pins are high-level output.
All KI/O pins are high-level output.
The KI/O0 pin is high-level output.
High level is input to at least one
of KI pins.
0
1
1
1
1
0
STOP
High level is input to at least one
of KI pins.
STOPNote 1
STOP
High level is input to at least one
of KI pins.
1
Any of the
[The following condition is added in addition to the above.]
combinations of
b2b1b0 above
—
High level is input to at least one
of S0, S1, and S2 pinsNote 2
When the timer’s down counter is 0
.
0/1
1
0
1
HALT
—
Notes 1. When setting HALT #×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that the
standby mode can be released.
2. At least one of the S0, S1, and S2 pins (the pin used for releasing the standby mode) must be specified
as follows:
S0, S1 pins: Input mode (specified by bits 0 and 2 of the P4 register)
S2 pin:
Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer
output enable flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
Data Sheet U16792EJ1V0DS
29
µPD67B, 68B
5.3 Standby Mode Release Timing
(1) STOP mode release timing
Figure 5-1. STOP Mode Release by Release Condition
Wait
HALT instruction
(STOP mode)
(284/f
X
+ α)
Standby
release signal
Operation
mode
Operation
mode
STOP mode
HALT mode
Oscillation
stopped
Oscillation
Oscillation
α : Oscillation growth time
Clock
Caution When a release condition is met in the STOP mode, the device is released from the STOP mode,
and goes into a wait state. At this time, if the release condition is not held, the device goes
into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP
mode, it is necessary to hold the release condition longer than the wait time.
(2) HALT mode release timing
Figure 5-2. HALT Mode Release by Release Condition
HALT instruction
(HALT mode)
Standby
release signal
Operation
HALT mode
Operation mode
mode
Oscillation
Clock
Data Sheet U16792EJ1V0DS
30
µPD67B, 68B
6. RESET
A system reset is effected by the following causes.
• When the POC circuit has detected low power-supply voltage
• When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed
• When the accumulator is 0H when the RLZ instruction is executed
• When stack pointer overflows or underflows
Table 6-1. Hardware Statuses After Reset
Hardware
• Reset by On-Chip POC Circuit During Operation • Reset by On-Chip POC Circuit in Standby
• Reset by Other FactorsNote 1
Mode
PC (11 bits)
000H
0B
SP (1 bit)
Data
R0 = DP 000H
R1 to RF Undefined
memory
Accumulator (A)
Status flag (F)
Carry flag (CY)
Timer (10 bits)
Port register
Undefined
0B
0B
000H
P0 FFH
P1 ××××11×1BNote 2
Control register P3 0000×000BNote 3
P4 26H
Notes 1. The following resets are available.
• Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
the precondition)
• Reset when executing the RLZ instruction (when A = 0)
• Reset by stack pointer’s overflow or underflow
2. ×: Refers to the value by the KI or S2 pin status.
In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when
POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor
connected).
3. ×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID).
Remark VID: RAM retention detection voltage
Data Sheet U16792EJ1V0DS
31
µPD67B, 68B
7. POC CIRCUIT
The POC circuit monitors the power supply voltage and applies an internal reset to the microcontroller when the
battery is replaced.
Cautions 1. There are cases in which the POC circuit cannot detect a low power supply voltage of less
than 1 ms. Therefore, if the power supply voltage has become low for a period of less than
1 ms, the POC circuit may malfunction because it does not generate an internal reset signal.
2. Clock oscillation is stopped by the resonator due to low power supply voltage before the
POC circuit generates the internal reset signal. In this case, malfunction may result when
the power supply voltage is recovered after the oscillation is stopped. This type of
phenomenon takes place because the POC circuit does not generate an internal reset signal
(because the power supply voltage recovers before the low power supply voltage is
detected) even though the clock has stopped. If, by any chance, a malfunction has taken
place, remove the battery for a short time and put it back. In most cases, normal operation
will be resumed.
3. In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to
KI3 when POC is released due to supply voltage rising (Can be left open. When open, leave
the pull-down resistor connected).
Data Sheet U16792EJ1V0DS
32
µPD67B, 68B
7.1 Functions of POC Circuit
The POC circuit has the following functions.
• Generates an internal reset signal when VDD ≤ VPOC.
• Cancels an internal reset signal when VDD > VPOC.
Here, VDD: power supply voltage, VPOC: POC detection voltage.
VDD
Operating ambient temperature TA = –40 to +85°C
3.6 V
Clock frequency fX = 3.5 to 4.5 MHz
1.65 V
VPOC
←POC detection voltage VPOC = 1.5 V (TYP.)Note 3
Approx. 1.4 V
0 V
→ t
Internal reset signal
Operation mode
Reset
↑
↑ Reset
Note 2
Note 1
Notes 1. Actually, oscillation stabilization wait time must elapse before the circuit is switched to operation mode.
The oscillation stabilization wait time is about 534/fX to 918/fX (when about 134 to 230 µs; @ fX = 4 MHz).
2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen,
it is necessary for the power supply voltage to be kept less than the VPOC for the period of 1 ms or
more. Therefore, in reality, there is the time lag of up to 1 ms until the reset takes effect.
3. The POC detection voltage (VPOC) varies between approximately 1.4 to 1.65 V; thus, the reset may
be canceled at a power supply voltage smaller than the guaranteed range (VDD = 1.65 to 3.6 V).
However, as long as the conditions for operating the POC circuit are met, the actual lowest operating
power supply voltage becomes lower than the POC detection voltage. Therefore, there is no
malfunction occurring due to a shortage of power supply voltage. However, malfunction for such
reasons as the clock not oscillating due to low power supply voltage may occur (refer to Caution 2
in 7. POC CIRCUIT).
7.2 Oscillation Check at Low Power Supply Voltage
A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate
even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POC
detection voltage). Whether this condition is met or not can be checked by measuring the oscillation status in a
product that actually includes a POC circuit, as follows.
<1> Connect a storage oscilloscope to the XOUT pin so that the oscillation status can be measured.
<2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply
voltage VDD from 0 V (making sure to avoid VDD > 3.6 V).
At first (during VDD < approx. 1.4 V), the XOUT pin is 0 V regardless of the VDD. However, at the point that VDD
reaches the POC detection voltage (VPOC = 1.5 V (TYP.)), the voltage of the XOUT pin jumps to about 0.5VDD. Maintain
this power supply voltage for a while to measure the waveform of the XOUT pin. If by any chance the oscillation
start voltage of the resonator is lower than the POC detection voltage, the growing oscillation of the XOUT pin can
be confirmed within several ms after the VDD has reached the VPOC.
Data Sheet U16792EJ1V0DS
33
µPD67B, 68B
8. SYSTEM CLOCK OSCILLATOR
The system clock oscillator consists of oscillators for ceramic resonators (fX = 3.5 to 4.5 MHz).
Figure 8-1. System Clock
XOUT
XIN
GND
Ceramic resonator
The system clock oscillator stops oscillating when a reset is applied or in STOP mode.
Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figure to avoid an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as GND. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Data Sheet U16792EJ1V0DS
34
µPD67B, 68B
9. INSTRUCTION SET
9.1 Machine Language Output by Assembler
The bit length of the machine language of this product is 10 bits per word. However, the machine language that
is output by the assembler is extended to 16 bits per word. As shown in the example below, the extension is made
by inserting 3-bit extended bits (111) in two locations.
Figure 9-1. Example of Assembler Output (10 Bits Extended to 16 Bits)
<1> In the case of “ANL A, @R0H”
1
1 0 1 0
1
0 0 0 0
1 1 1
1 0 1 0
1 1 1
1
0 0 0 0 = FAF0
1
Extended bits
Extended bits
<2> In the case of “OUT P0, #data8”
0
0 1 1 0
1
1 0 0 0
1 1 1
0 1 1 0
1 1 1
1
1 0 0 0 = E6F8
0
Extended bits
Extended bits
Data Sheet U16792EJ1V0DS
35
µPD67B, 68B
9.2 Circuit Symbol Description
A:
Accumulator
ASR:
addr:
CY:
Address stack register
Program memory address
Carry flag
data4:
data8:
4-bit immediate data
8-bit immediate data
data10: 10-bit immediate data
F:
Status flag
M0:
Modulo register for setting the low-level period
Modulo register for setting the low-level period (lower 4 bits)
Modulo register for setting the low-level period (higher 4 bits)
Modulo register for setting the high-level period
Modulo register for setting the high-level period (lower 4 bits)
Modulo register for setting the high-level period (higher 4 bits)
Program counter
M00:
M01:
M1:
M10:
M11:
PC:
Pn:
Port register pair (n = 0, 1, 3, 4)
P0n:
P1n:
Port register (lower 4 bits)
Port register (higher 4 bits)
ROMn: Bit n of the program memory (n = 0 to 9)
Rn:
R0n:
R1n:
SP:
T:
Register pair
Data memory (General-purpose register; n = 0 to F)
Data memory (General-purpose register; n = 0 to F)
Stack pointer
Timer register
T0:
T1:
(×):
Timer register (lower 4 bits)
Timer register (higher 4 bits)
Content addressed with ×
Data Sheet U16792EJ1V0DS
36
µPD67B, 68B
9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table
Accumulator Manipulation Instructions
Mnemonic Operand
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
∨
ANL
ORL
XRL
INC
A, R0n
FBEn
FAEn
FAF0
(A) ← (A) (Rmn) m = 0, 1 n = 0 to F
CY ← A3 • Rmn3
1
1
A, R1n
∨
A, @R0H
(A) ← (A) ((P13), (R0))7-4
CY ← A3 • ROM7
∨
A, @R0L
FBF0
(A) ← (A) ((P13), (R0))3-0
CY ← A3 • ROM3
∨
A, #data4 FBF1
data4
data4
data4
(A) ← (A) data4
2
1
CY ← A3 • data43
(A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F
CY ← 0
A, R0n
FDEn
FCEn
FCF0
A, R1n
A, @R0H
(A) ← (A) ∨ ((P13), (R0))7-4
CY ← 0
A, @R0L
FDF0
(A) ← (A) ∨ ((P13), (R0))3-0
CY ← 0
A, #data4 FDF1
(A) ← (A) ∨ data4
CY ← 0
2
1
A, R0n
F5En
F4En
F4F0
(A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F
CY ← A3 • Rmn3
A, R1n
A, @R0H
(A) ← (A) ∨ ((P13), (R0))7-4
CY ← A3 • ROM7
A, @R0L
F5F0
(A) ← (A) ∨ ((P13), (R0))3-0
CY ← A3 • ROM3
A, #data4 F5F1
(A) ← (A) ∨ data4
CY ← A3 • data43
(A) ← (A) + 1
2
1
A
F4F3
if (A) = 0 CY ← 1
else CY ← 0
RL
A
A
FCF3
FEF3
(An+1) ← (An), (A0) ← (A3)
CY ← A3
RLZ
if A = 0 reset
else (An+1) ← (An), (A0) ← (A3)
CY ← A3
Data Sheet U16792EJ1V0DS
37
µPD67B, 68B
I/O Instructions
Mnemonic Operand
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
IN
A, P0n
A, P1n
P0n, A
P1n, A
A, P0n
A, P1n
A, P0n
A, P1n
A, P0n
A, P1n
FFF8 + n
FEF8 + n
E5F8 + n
E4F8 + n
FBF8 + n
FAF8 + n
FDF8 + n
FCF8 + n
F5F8 + n
F4F8 + n
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
1
1
OUT
ANL
ORL
XRL
(Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4
∨
(A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn3
(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn3
Mnemonic Operand
Instruction Code
1st Word 2nd Word 3rd Word
Pn, #data8 E6F8 + n data8
Operation
Instruction Instruction
Length Cycle
OUT
(Pn) ← data8
n = 0, 1, 3, 4
2
1
Remark Pn: P1n to P0n are handled in pairs.
Data Transfer Instructions
Mnemonic Operand
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
MOV
A, R0n
FFEn
FEEn
FEF0
(A) ← (Rmn)
CY ← 0
m = 0, 1 n = 0 to F
1
1
A, R1n
A, @R0H
(A) ← ((P13), (R0))7-4
CY ← 0
A, @R0L
FFF0
(A) ← ((P13), (R0))3-0
CY ← 0
A, #data4 FFF1
data4
(A) ← data4
CY ← 0
2
1
R0n, A
R1n, A
E5En
E4En
(Rmn) ← (A)
m = 0, 1 n = 0 to F
Mnemonic Operand
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
MOV
Rn, #data8 E6En
Rn, @R0 E7En
data8
—
—
(R1n to R0n) ← data8
n = 0 to F
2
1
1
—
(R1n to R0n) ← ((P13), (R0)) n = 1 to F
Remark Rn: R1n to R0n are handled in pairs.
Data Sheet U16792EJ1V0DS
38
µPD67B, 68B
Branch Instructions
Mnemonic Operand
Instruction Code
1st Word 2nd Word 3rd Word
addr
Operation
Instruction Instruction
Length
Cycle
JMP
JC
addr (Page 0) E8F1
addr (Page 1) E9F1
PC ← addr
2
1
addr
addr
addr
addr
addr
addr
addr
addr
addr
addr (Page 0) ECF1
addr (Page 1) EAF1
addr (Page 0) EDF1
addr (Page 1) EBF1
addr (Page 0) EEF1
addr (Page 1) F0F1
addr (Page 0) EFF1
addr (Page 1) F1F1
if CY = 1 PC ← addr
else PC ← PC + 2
if CY = 0 PC ← addr
else PC ← PC + 2
if F = 1 PC ← addr
else PC ← PC + 2
if F = 0 PC ← addr
else PC ← PC + 2
JNC
JF
JNF
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.
Subroutine Instructions
Mnemonic Operand
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
CALL
RET
addr (Page 0) E6F2
E8F1
E9F1
addr
addr
SP ← SP + 1, ASR ← PC, PC ← addr
PC ← ASR, SP ← SP – 1
3
2
addr (Page 1) E6F2
E8F2
1
1
Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.
Data Sheet U16792EJ1V0DS
39
µPD67B, 68B
Timer Manipulation Instructions
Mnemonic Operand
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
MOV
A, T0
FFFF
FEFF
FFF6
FEF6
FFF7
FEF7
E5FF
F4FF
E5F6
E4F6
E5F7
E4F7
(A) ← (Tn)
CY ← 0
n = 0, 1
n = 0, 1
n = 0, 1
n = 0, 1
n = 0, 1
n = 0, 1
1
1
A, T1
A, M00
A, M01
A, M10
A, M11
T0, A
(A) ← (M0n)
CY ← 0
(A) → (M1n)
CY → 0
(Tn) ← (A)
(T) n ← 0
(M0n) ← (A)
CY ← 0
T1, A
M00, A
M01, A
M10, A
M11, A
(M1n) ← (A)
CY ← 0
Mnemonic Operand
MOV
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
T, #data10 E6FF
data10
data10
data10
(T) ← data10
2
1
M0, #data10 E6F6
M1, #data10 E6F7
(M0) ← data10
(M1) ← data10
T, @R0
F4FF
E7F6
E7F7
(T) ← ((P13), (R0))
(M0) ← ((P13), (R0))
(M1) ← ((P13), (R0))
1
M0, @R0
M1, @R0
Other Instructions
Mnemonic Operand
Instruction Code
Operation
Instruction Instruction
Length Cycle
1st Word 2nd Word 3rd Word
HALT
STTS
#data4
#data4
E2F1
E3F1
data4
data4
Standby mode
2
1
if statuses match F ← 1
else F ← 0
R0n
E3En
FAF3
E0E0
if statuses match F ← 1
else F ← 0
1
n = 0 to F
SCAF
NOP
if A = 0FH CY ← 1
else CY ← 0
PC ← PC + 1
Data Sheet U16792EJ1V0DS
40
µPD67B, 68B
9.4 Accumulator Manipulation Instructions
ANL A, R0n
ANL A, R1n
<1> Instruction code:
<2> Cycle count:
<3> Function:
1
1
0
1 R
4
0 R
3
R
2
R
1
R
0
1
∨
(A) ← (A) (Rmn) m = 0, 1 n = 0 to F
CY ← A3 • Rmn3
The accumulator contents and the register Rmn contents are ANDed and the results are entered in the
accumulator.
ANL A, @R0H
ANL A, @R0L
<1> Instruction code:
1
1 0 1 0/1 1 0 0 0 0
<2> Cycle count:
<3> Function:
1
∨
(A) ← (A) ((P13), (R0))7-4 (in the case of ANL A, @R0H)
CY ← A3 • ROM7
∨
(A) ← (A) ((P13), (R0))3-0 (in the case of ANL A, @R0L)
CY ← A3 • ROM3
The accumulator contents and the program memory contents specified by the control register P13 and
register pair R10 to R00 are ANDed and the results are entered in the accumulator.
If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect.
• Program memory (ROM) configuration
b9
b7
b6
b5
b4
b8
b3
b2
b1
b0
H↓
L↓
Valid bits at the time of accumulator manipulation
ANL A, #data4
<1> Instruction code:
1
0
1
0
0
0
1
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
∨
(A) ← (A) data4
CY ← A3 • data43
The accumulator contents and the immediate data are ANDed and the results are entered in the
accumulator.
Data Sheet U16792EJ1V0DS
41
µPD67B, 68B
ORL A, R0n
ORL A, R1n
<1> Instruction code:
1
1
1
0 R
4
0 R
3
R2
R1
R0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F
CY ← 0
The accumulator contents and the register Rmn contents are ORed and the results are entered in the
accumulator.
ORL A, @R0H
ORL A, @R0L
<1> Instruction code:
1
1 1 0 0/1 1 0 0 0 0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ ((P13), (R0))7-4 (in the case of ORL A, @R0H)
(A) ← (A) ∨ ((P13), (R0))3-0 (in the case of ORL A, @R0L)
CY ← 0
The accumulator contents and the program memory contents specified by the control register P13 and
register pair R10 to R00 are ORed and the results are entered in the accumulator.
If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect.
ORL A, #data4
<1> Instruction code:
1
0
1
0
1
0
0
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ data4
CY ← 0
The accumulator contents and the immediate data are ORed and the results are entered in the
accumulator.
XRL A, R0n
XRL A, R1n
<1> Instruction code:
1
0
1
0 R
4
0 R
3
R2
R1
R0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ (Rmn) m = 0, 1 n = 0 to F
CY ← A3 • Rmn3
The accumulator contents and the register Rmn contents are exclusive-ORed and the results are
entered in the accumulator.
Data Sheet U16792EJ1V0DS
42
µPD67B, 68B
XRL A, @R0H
XRL A, @R0L
<1> Instruction code:
1
0 1 0 0/1 1 0 0 0 0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ ((P13), (R0))7-4 (in the case of XRL A, @R0H)
CY ← A3 • ROM7
(A) ← (A) ∨ ((P13), (R0))3-0 (in the case of XRL A, @R0L)
CY ← A3 • ROM3
The accumulator contents and the program memory contents specified by the control register P13 and
register pair R10 to R00 are exclusive-ORed and the results are entered in the accumulator.
If H is specified, b7, b6, b5, and b4 take effect. If L is specified, b3, b2, b1, and b0 take effect.
XRL A, #data4
<1> Instruction code:
1
0
0
0
1
0
0
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ data4
CY ← A3 • data43
The accumulator contents and the immediate data are exclusive-ORed and the results are entered in
the accumulator.
INC A
<1> Instruction code:
1
0 1 0 0 1 0 0 1 1
<2> Cycle count:
<3> Function:
1
(A) ← (A) + 1
if A = 0 CY ← 1
else CY ← 0
The accumulator contents are incremented (+1).
RL A
<1> Instruction code:
1
1 1 0 0 1 0 0 1 1
<2> Cycle count:
<3> Function:
1
(An + 1) ← (An), (A0) ← (A3)
CY ← A3
The accumulator contents are rotated anticlockwise bit by bit.
RLZ A
<1> Instruction code:
1
1 1 1 0 1 0 0 1 1
<2> Cycle count:
<3> Function:
1
if A = 0 reset
else (An + 1) ← (An), (A0) ← (A3)
CY ← A3
The accumulator contents are rotated anticlockwise bit by bit.
If A = 0H at the time of instruction execution, an internal reset takes effect.
Data Sheet U16792EJ1V0DS
43
µPD67B, 68B
9.5 I/O Instructions
IN A, P0n
IN A, P1n
<1> Instruction code:
<2> Cycle count:
<3> Function:
1
1
1
1 P
4
1
1 P
2
P
1
P
0
1
(A) ← (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
The port Pmn data is loaded (read) onto the accumulator.
OUT P0n, A
OUT P1n, A
<1> Instruction code:
0
0
1
0 P
4
1
1 P
2
P1
P0
<2> Cycle count:
<3> Function:
1
(Pmn) ← (A) m = 0, 1 n = 0, 1, 3, 4
The accumulator contents are transferred to port Pmn to be latched.
ANL A, P0n
ANL A, P1n
<1> Instruction code:
1
1
0
1 P
4
1
1 P
2
P1
P0
<2> Cycle count:
<3> Function:
1
∨
(A) ← (A) (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the
accumulator.
ORL A, P0n
ORL A, P1n
<1> Instruction code:
1
1
1
0 P
4
1
1 P
2
P1
P0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← 0
The accumulator contents and the port Pmn contents are ORed and the results are entered in the
accumulator.
XRL A, P0n
XRL A, P1n
<1> Instruction code:
1
0
1
0 P
4
1
1 P
2
P1
P0
<2> Cycle count:
<3> Function:
1
(A) ← (A) ∨ (Pmn) m = 0, 1 n = 0, 1, 3, 4
CY ← A3 • Pmn
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered
in the accumulator.
Data Sheet U16792EJ1V0DS
44
µPD67B, 68B
OUT Pn, #data8
<1> Instruction code:
0
0
0
1
1
0
1
1 P
2
P
1
P
0
d7
d6
d5
d4
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
(Pn) ← data8 n = 0, 1, 3, 4
The immediate data is transferred to port Pn. In this case, port Pn refers to P1n to P0n operating in pairs.
9.6 Data Transfer Instructions
MOV A, R0n
MOV A, R1n
<1> Instruction code:
1
1
1
1 R
4
0 R
3
R2
R1
R0
<2> Cycle count:
<3> Function:
1
(A) ← (Rmn) m = 0, 1 n = 0 to F
CY ← 0
The register Rmn contents are transferred to the accumulator.
MOV A, @R0H
<1> Instruction code:
1
1 1 1 0 1 0 0 0 0
<2> Cycle count:
<3> Function:
1
(A) ← ((P13), (R0))7-4
CY ← 0
The higher 4 bits (b7 b6 b5 b4) of the program memory specified by control register P13 and register pair
R10 to R00 are transferred to the accumulator. b9 is ignored.
MOV A, @R0L
<1> Instruction code:
1
1 1 1 1 1 0 0 0 0
<2> Cycle count:
<3> Function:
1
(A) ← ((P13), (R0))3-0
CY ← 0
The lower 4 bits (b3 b2 b1 b0) of the program memory specified by control register P13 and register pair
R10 to R00 are transferred to the accumulator. b8 is ignored.
• Program memory (ROM) contents
@R0 H
@R0 L
b9
b7 b6 b5 b4
b8
b3 b2 b1 b0
MOV A, #data4
<1> Instruction code:
1
0
1
0
1
0
1
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
(A) ← data4
CY ← 0
The immediate data is transferred to the accumulator.
Data Sheet U16792EJ1V0DS
45
µPD67B, 68B
MOV R0n, A
MOV R1n, A
<1> Instruction code:
0
0
1
0 R
4
0 R
3
R2
R1
R0
<2> Cycle count:
<3> Function:
1
(Rmn) ← (A) m = 0, 1 n = 0 to F
The accumulator contents are transferred to register Rmn.
MOV Rn, #data8
<1> Instruction code:
0
0
0
1
1
0
0 R
3
R
2
R
1
R
0
d7
d6
d5
d4
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
(R1n-R0n) ← data8 n = 0 to F
The immediate data is transferred to the register. Using this instruction, registers operate as register
pairs.
The pair combinations are as follows:
R0: R10 - R00
R1: R11 - R01
:
RE: R1E - R0E
RF: R1F - R0F
Lower column
Higher column
MOV Rn, @R0
<1> Instruction code:
0
0
1
1
1
0 R
3
R2
R1
R0
<2> Cycle count:
<3> Function:
1
(R1n-R0n) ← ((P13), (R0)) n = 1 to F
The program memory contents specified by control register P13 and register pair R10 to R00 are
transferred to register pair R1n to R0n. The program memory consists of 10 bits and has the following
state after the transfer to the register.
Program memory
b9
b7 b6 b5 b4
b8
b3 b2 b1 b0
→
b9
b7 b6 b5 b4
b8
b3 b2 b1 b0
@R0
R1n
R0n
The higher 2 to 4 bits of the program memory address are specified by the control register (P13).
Data Sheet U16792EJ1V0DS
46
µPD67B, 68B
9.7 Branch Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
µPD67B (ROM: 1K steps):
µPD68B (ROM: 2K steps):
Page 0
Pages 0, 1
JMP addr
<1> Instruction code: Page 0
0
1
0
0
0
1
0
0
0
1
; page 1 0 1 0 0 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count:
<3> Function:
1
PC ← addr
The 10 bits (PC9-0) of the program counter are replaced directly by the specified address addr (a9 to
a0).
JC addr
<1> Instruction code: Page 0
0
1
1
0
0
1
0
0
0
1
; page 1 0 1 0 1 0 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count:
<3> Function:
1
if CY = 1 PC ← addr
else PC ← PC + 2
If the carry flag CY is set (to 1), a jump is made to the address specified by addr (a9 to a0).
JNC addr
<1> Instruction code: Page 0
0
1
1
0
1
1
0
0
0
1
; page 1 0 1 0 1 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count:
<3> Function:
1
if CY = 0 PC ← addr
else PC ← PC + 2
If the carry flag CY is cleared (to 0), a jump is made to the address specified by addr (a9 to a0).
JF addr
<1> Instruction code: Page 0
0
1
1
1
0
1
0
0
0
1
; page 1 1 0 0 0 0 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count:
<3> Function:
1
if F = 1 PC ← addr
else PC ← PC + 2
If the status flag F is set (to 1), a jump is made to the address specified by addr (a9 to a0).
JNF addr
<1> Instruction code: Page 0
0
1
1
1
1
1
0
0
0
1
; page 1 1 0 0 0 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count:
<3> Function:
1
if F = 0 PC ← addr
else PC ← PC + 2
If the status flag F is cleared (to 0), a jump is made to the address specified by addr (a9 to a0).
Data Sheet U16792EJ1V0DS
47
µPD67B, 68B
9.8 Subroutine Instructions
The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically
performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as
follows.
µPD67B (ROM: 1K steps):
µPD68B (ROM: 2K steps):
Page 0
Pages 0, 1
CALL addr
<1> Instruction code:
0
0
1
1
0
0
1
1
0
0
0
0
1 0
Page 0
0
1
0
0
0
1
; page 1 0 1 0 0 1 1 0 0 0 1
a9
a7
a6
a5
a4
a8
a3
a2
a1
a0
<2> Cycle count:
<3> Function:
2
SP ← SP + 1
ASR ← PC
PC ← addr
Increments (+1) the stack pointer value and saves the program counter value in the address stack
register. Then, enters the address specified by the operand addr (a9 to a0) into the program counter.
If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect.
RET
<1> Instruction code:
<2> Cycle count:
<3> Function:
0
1 0 0 0 1 0 0 1 0
1
PC ← ASR
SP ← SP – 1
Restores the value saved in the address stack register to the program counter. Then, decrements
(–1) the stack pointer.
If a borrow is generated when the stack pointer value is decremented (–1), an internal reset takes effect.
Data Sheet U16792EJ1V0DS
48
µPD67B, 68B
9.9 Timer Manipulation Instructions
MOV A, T0
MOV A, T1
<1> Instruction code:
<2> Cycle count:
<3> Function:
1
1 1 1 0/1 1 1 1 1 1
1
(A) ← (Tn) n = 0, 1
CY ← 0
The timer register Tn contents are transferred to the accumulator. T1 corresponds to (t9, t8, t7, t6); T0
corresponds to (t5, t4, t3, t2).
T
t
9
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
0
T1
T0
Can be set with
↓
MOV T, #data10
MOV T, @R0
MOV A, M00
MOV A, M01
<1> Instruction code:
<2> Cycle count:
<3> Function:
1
1 1 1 0/1 1 0 1 1 0
1
(A) ← (M0n) n = 0, 1
CY ← 0
The modulo register M0n contents are transferred to the accumulator. M01 corresponds to (t9, t8, t7,
t6); M00 corresponds to (t5, t4, t3, t2).
M0
t
9
t
8
t
7
t
6
t5
t
4
t
3
t
2
t
1
t
0
M01
M00
Can be set with
↓
MOV M0, #data10
MOV M0, @R0
Data Sheet U16792EJ1V0DS
49
µPD67B, 68B
MOV A, M10
MOV A, M11
<1> Instruction code:
1
1 1 1 0/1 1 0 1 1 1
<2> Cycle count:
<3> Function:
1
(A) ← (M1n) n = 0, 1
CY ← 0
The modulo register M1n contents are transferred to the accumulator. M11 corresponds to (t9, t8, t7,
t6); M10 corresponds to (t5, t4, t3, t2).
M1
t
9
t
8
t
7
t
6
t
5
t
4
t
3
t
2
t
1
t
0
M11
M10
Can be set with
↓
MOV M1, #data10
MOV M1, @R0
MOV T0, A
MOV T1, A
<1> Instruction code:
<2> Cycle count:
<3> Function:
0
0 1 0 0/1 1 1 1 1 1
1
(Tn) ← (A) n = 0, 1
The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t9, t8, t7, t6); T0
corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to T1, t1 becomes
0; if data is transferred to T0, t0 becomes 0.
MOV M00, A
MOV M01, A
<1> Instruction code:
0
0 1 0 0/1 1 0 1 1 0
<2> Cycle count:
<3> Function:
1
(M0n) ← (A) n = 0, 1
(CY) ← 0
The accumulator contents are transferred to the modulo register M0n. M01 corresponds to (t9, t8, t7,
t6); M00 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M01,
t1 becomes 0; if data is transferred to M00, t0 becomes 0.
MOV M10, A
MOV M11, A
<1> Instruction code:
0
0 1 0 0/1 1 0 1 1 1
<2> Cycle count:
<3> Function:
1
(M1n) ← (A) n = 0, 1
(CY) ← 0
The accumulator contents are transferred to the modulo register M1n. M11 corresponds to (t9, t8, t7,
t6); M10 corresponds to (t5, t4, t3, t2). After executing this instruction, if data is transferred to M11,
t1 becomes 0; if data is transferred to M10, t0 becomes 0.
Data Sheet U16792EJ1V0DS
50
µPD67B, 68B
MOV T, #data10
<1> Instruction code:
0
0 1 1 0 1 1 1 1 1
t1
t9
t8
t7
t6
t0
t5
t4
t3
t2
<2> Cycle count:
<3> Function:
1
(T) ← data10
The immediate data is transferred to the timer register T (t9 to t0).
Remark The timer time is set as follows: (Set value + 1) × 64/fX – 4/fX
MOV M0, #data10
<1> Instruction code:
0
0 1 1 0 1 0 1 1 0
t1
t9
t8
t7
t6
t0
t5
t4
t3
t2
<2> Cycle count:
<3> Function:
1
(M0) ← data10
The immediate data is transferred to the modulo register M0 (t9 to t0).
MOV M1, #data10
<1> Instruction code:
0
0 1 1 0 1 0 1 1 1
t1
t9
t8
t7
t6
t0
t5
t4
t3
t2
<2> Cycle count:
<3> Function:
1
(M1) ← data10
The immediate data is transferred to the modulo register M1 (t9 to t0).
MOV T, @R0
<1> Instruction code:
0
0 1 1 1 1 1 1 1 1
<2> Cycle count:
<3> Function:
1
(T) ← ((P13), (R0))
Transfers the program memory contents specified by the control register P13 and the register pair R10
to R00 to the timer register T (t9 to t0).
The program memory, which consists of 10 bits, is placed in the following state after the transfer to the
register.
Timer
T
Program memory
t1
t
9
t8
t7
t6
t0
t5
t4
t3
t2
→
t9
t
8
t7
t6
t
5
t4
t3
t2
t1
t0
@R
0
T1
T0
The higher 2 to 4 bits of the program memory address are specified by the control register (P13).
Caution When setting a timer value in the program memory, be sure to use the DT
quasi-directive.
Data Sheet U16792EJ1V0DS
51
µPD67B, 68B
MOV M0, @R0
<1> Instruction code:
0
0 1 1 1 1 0 1 1 0
<2> Cycle count:
<3> Function:
1
(M0) ← ((P13), (R0))
Transfers the program memory contents specified by the control register P13 and the register pair R10
to R00 to the modulo register M0 (t9 to t0).
The program memory, which consists of 10 bits, is placed in the following state after the transfer to the
register.
Modulo register
Program memory
M0
t1
t9
t
8
t
7
t6
t
0
t5
t
4
t3
t2
→
t
9
t
8
t7
t
6
t5
t
4
t
3
t
2
t
1
t
0
@R
0
M01
M00
The higher 2 to 4 bits of the program memory address are specified by the control register (P13).
Caution When setting a register value in the program memory, be sure to use the DT
quasi-directive.
MOV M1, @R0
<1> Instruction code:
0
0 1 1 1 1 0 1 1 1
<2> Cycle count:
<3> Function:
1
(M1) ← ((P13), (R0))
Transfers the program memory contents specified by the control register P13 and the register pair R10
to R00 to the modulo register M1 (t9 to t0).
The program memory, which consists of 10 bits, is placed in the following state after the transfer to the
register.
Modulo register
Program memory
M1
t1
t9
t
8
t
7
t6
t
0
t5
t
4
t3
t2
→
t
9
t
8
t7
t
6
t5
t
4
t
3
t
2
t
1
t
0
@R
0
M11
M10
The higher 2 to 4 bits of the program memory address are specified by the control register (P13).
Caution When setting a register value in the program memory, be sure to use the DT
quasi-directive.
9.10 Other Instructions
HALT #data4
<1> Instruction code:
0
0
0
0
0
0
1
0
0
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
Standby mode
Places the CPU in standby mode.
The condition for having the standby mode (HALT/STOP mode) canceled is specified by the immediate
data.
Data Sheet U16792EJ1V0DS
52
µPD67B, 68B
STTS R0n
<1> Instruction code:
0
0
0
1
1
0 R
3
R2
R1
R0
<2> Cycle count:
<3> Function:
1
if statuses match F ← 1
else F ← 0 n = 0 to F
Compares the S0, S1, S2, KI/O, KI, and TIMER statuses with the register R0n contents. If at least one
of the statuses matches the bits that have been set, the status flag F is set (to 1).
If none of them match, the status flag F is cleared (to 0).
STTS #data4
<1> Instruction code:
0
0
0
0
0
0
1
0
1
0
1 0 0 0 1
0 d
3
d2
d1
d0
<2> Cycle count:
<3> Function:
1
if statuses match F ← 1
else F ← 0
Compares the S0, S1, S2, KI/O, KI, and TIMER statuses with the immediate data contents. If at least one
of the statuses matches the bits that have been set, the status flag F is set (to 1).
If none of them match, the status flag F is cleared (to 0).
SCAF (Set Carry if ACC = FH)
<1> Instruction code:
<2> Cycle count:
<3> Function:
1
1 0 1 0 1 0 0 1 1
1
if A = 0FH CY ← 1
else CY ← 0
Sets the carry flag CY (to 1) if the accumulator contents are FH.
The accumulator values after executing the SCAF instruction are as follows.
Accumulator Value
Before Execution After Execution
Carry Flag
×××0
××01
×011
0111
1111
0000
0001
0011
0111
1111
0 (clear)
0 (clear)
0 (clear)
0 (clear)
1 (set)
Remark ×: don’t care
NOP
<1> Instruction code:
0
0 0 0 0 0 0 0 0 0
<2> Cycle count:
<3> Function:
No operation
1
PC ← PC + 1
Data Sheet U16792EJ1V0DS
53
µPD67B, 68B
10. ASSEMBLER RESERVED WORDS
10.1 Mask Option Quasi-Directives
When creating a program in the µPD67B and 68B, it is necessary to use a mask option quasi-directive in the
assembler’s source program.
10.1.1 OPTION and ENDOP quasi-directives
The quasi-directives from the OPTION quasi-directive down to the ENDOP quasi-directive are called the mask
option definition block. The format of the mask option definition block is as follows.
Format
Symbol field
[Label:]
Mnemonic field
Operand field
Comment field
[; Comment]
OPTION
:
:
ENDOP
10.1.2 Mask option definition quasi-directive
The quasi-directive that can be used in the mask option definition block is shown in Table 10-1.
The mask option definition can only be specified as follows. Be sure to specify the following quasi-directive.
Example
Symbol field
Mnemonic field
OPTION
Operand field
Comment field
NOUSECAP
ENDOP
; Capacitor for oscillation
not incorporated
Table 10-1. Mask Option Definition Quasi-Directive
Name
Mask Option Definition Quasi-Directive
PRO File
Address Value
2043H
Data Value
00
CAP
NOUSECAP
(Capacitor for oscillation not incorporated)
Data Sheet U16792EJ1V0DS
54
µPD67B, 68B
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C)
Item
Symbol
VDD
Conditions
Ratings
Unit
V
Power supply voltage
Input voltage
–0.3 to +3.8
VI
KI/O, KI, S0, S1, S2
REM
–0.3 to VDD + 0.3
V
Output voltage
VO
–0.3 to VDD + 0.3
V
Note
Output current, high
IOH
Peak value
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
Peak value
rms value
–30
–20
–7.5
–5
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
LED
KI/O Per pin
–13.5
–9
Total for LED and KI/O pins
–18
–12
7.5
Note
Output current, low
IOL
REM
LED
5
7.5
5
Operating ambient
temperature
TA
–40 to +85
Storage temperature
Tstg
–65 to +150
°C
Note The rms value should be calculated as follows: [rms value] = [Peak value] × Duty.
√
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Power Supply Voltage Range (TA = –40 to +85°C)
Item
Symbol
Conditions
fX = 3.5 to 4.5 MHz
MIN.
1.65
TYP.
3.0
MAX.
3.6
Unit
V
Power supply voltage
VDD
Data Sheet U16792EJ1V0DS
55
µPD67B, 68B
DC Characteristics (TA = –40 to +85°C, VDD = 1.65 to 3.6 V)
Item
Symbol
VIH1
Conditions
MIN.
0.7VDD
0.65VDD
0
TYP.
MAX.
Unit
V
Input voltage, high
KI/O
VDD
VDD
VIH2
KI, S0, S1, S2
V
Input voltage, low
VIL1
KI/O
0.3VDD
0.15VDD
3
V
VIL2
KI, S0, S1, S2
KI
0
V
Input leakage current,
high
ILIH1
µA
VI = VDD, pull-down resistor not incorporated
ILIH2
S0, S1, S2
3
µA
VI = VDD, pull-down resistor not incorporated
Input leakage current,
low
ILIL1
ILIL2
ILIL3
VOH1
VOL1
VOL2
IOH1
IOH2
IOL1
KI
VI = 0 V
VI = 0 V
–3
–3
–3
µA
µA
µA
V
KI/O
S0, S1, S2 VI = 0 V
Output voltage, high
Output voltage, low
REM, LED, KI/O
IOH = –0.3 mA
0.8VDD
REM, LED
KI/O
IOL = 0.3 mA
0.3
0.4
V
IOL = 15 µA
V
Output current, high
Output current, low
REM
KI/O
VDD = 3.0 V, VOH = 1.0 V
VDD = 3.0 V, VOH = 2.2 V
VDD = 3.0 V, VOL = 0.4 V
VDD = 3.0 V, VOL = 2.2 V
–5
–2.5
47
–12
–7
mA
mA
µA
µA
kΩ
kΩ
V
KI/O
70
260
75
390
150
250
On-chip pull-down
resistance
R1
KI, S0, S1, S2
KI/O
300
500
3.6
R2
130
0.9
Data retention power
supply voltage
VDDDR
In STOP mode
RAM retention detection
voltage
VID
1.5
0.7
1.65
1.4
V
Supply current
IDD1
Operation
mode
fX = 4.0 MHz, VDD = 3 V 10%
mA
IDD2
IDD3
HALT mode
STOP mode
fX = 4.0 MHz, VDD = 3 V 10%
VDD = 3 V 10%
0.65
2.0
1.3
9.0
3.0
mA
µA
µA
VDD = 3 V 10%, TA = 25°C
1.8
Data Sheet U16792EJ1V0DS
56
µPD67B, 68B
AC Characteristics (TA = –40 to +85°C, VDD = 1.65 to 3.6 V)
Item
Symbol
Conditions
MIN.
14
TYP.
16
MAX.
18.5
Unit
µs
Instruction execution time tCY
VDD = 2.0 to 3.6 V
KI, S0, S1, S2 high-level
width
tH
10
µs
When releasing standby mode In STOP mode Note
µs
Note 10 + 284/fX + oscillation growth time
Remark tCY = 64/fX (fX: System clock oscillation frequency)
POC Circuit (TA = –40 to +85°C)
Item
Symbol
Conditions
MIN.
TYP.
1.5
MAX.
1.65
Unit
V
Note
POC detection voltage
VPOC
Note Refers to the voltage with which the POC circuit releases an internal reset. If VPOC < VDD, the internal
reset is released.
From the time of VPOC ≥ VDD until the internal reset takes effect, a delay of up to 1 ms occurs. When the
period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect.
System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.65 to 3.6 V)
Item
Symbol
Conditions
MIN.
3.5
TYP.
4.0
MAX.
4.5
Unit
Oscillation frequency
(ceramic resonator)
fX
MHz
Data Sheet U16792EJ1V0DS
57
µPD67B, 68B
Recommended Oscillator Constant
Ceramic resonator (TA = –40 to +85°C)
Manufacturer
Part Number
Frequency
(MHz)
4.0
Oscillator Constant (pF)
C1 C2
Unnecessary (on-chip C type)
Oscillation Voltage Range (VDD) Remark
MIN.
1.65
MAX.
3.6
Murata Mfg. CSTCR4M00G55-R0
–
Co., Ltd.
CSTLS4M00G56-B0
CSTCR4M19G55-R0
CSTLS4M19G56-B0
4.194
External circuit example
XIN
XOUT
C1
C2
Caution These oscillator constants are reference values based on evaluation by the manufacturer of
the resonator under a specific environment.
If optimization of the oscillator characteristics is required for the actual application, apply to
the resonator manufacturer for evaluation on the mounting circuit.
The oscillation voltage and oscillation frequency only indicate the oscillator characteristics;
the oscillator must be used within the ratings of the DC and AC characteristics specified under
the internal operation conditions of the µPD67B and 68B.
Data Sheet U16792EJ1V0DS
58
µPD67B, 68B
12. CHARACTERISTIC CURVES (REFERENCE VALUES)
IOL vs. VOL (REM, LED)
(TA = 25°C, VDD = 3.0 V)
IDD vs. VDD (fx = 4 MHz)
(TA = 25°C)
25
20
15
10
5
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
Operation mode
HALT mode
0.1
0
1.5
0
3
1
2
2
2.5
3
3.6
4
1.65
Low-level output voltage VOL [V]
Power supply voltage VDD [V]
IOL vs. VOL (KI/O)
IOH vs. VOH (REM, LED, KI/O)
(TA = 25°C, VDD = 3.0 V)
(TA = 25°C, VDD = 3.0 V)
500
450
400
350
300
250
200
150
100
50
− 20
− 18
− 16
− 14
− 12
− 10
− 8
µ
− 6
− 4
− 2
0
V
0
1
2
3
DD
V
DD − 1
V
DD − 2
VDD − 3
Low-level output voltage VOL [V]
High-level output voltage VOH [V]
Data Sheet U16792EJ1V0DS
59
µPD67B, 68B
13. APPLICATION CIRCUIT EXAMPLE
Example of Application in System
• Remote control transmitter (48 keys; mode selection switch supported)
K
K
S
S
I/O6
I/O7
0
K
K
K
K
K
K
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
+
1/LED
REM
V
X
X
DD
Note 1
Note 3
Note 3
Note 3
Note 3
OUT
KI3
KI2
KI1
KI0
Note 1
IN
GND
Note 2
S2
Mode selection
switch
Key matrix
8 × 6 = 48 keys
Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option.
2. S2: Set to enable for STOP mode release.
3. Set pins KI0 to KI3 to “with pull-down resistors”.
Data Sheet U16792EJ1V0DS
60
µPD67B, 68B
• Remote control transmitter (56 keys supported)
KI/O6
KI/O7
S0
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
+
S1/LED
REM
VDD
KI/O0
Note 1
Note 3
XOUT
KI3
Note 1
Note 3
Note 3
Note 3
XIN
KI2
KI1
KI0
GND
Note 2
S2
Key matrix
8 × 7 = 56 keys
Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option.
2. S2: Set to enable for STOP mode release.
3. Set pins KI0 to KI3 to “with pull-down resistors”.
Data Sheet U16792EJ1V0DS
61
µPD67B, 68B
• Remote control transmitter (56 keys supported, mode selection switch supported)
Data can be read from the KI/O0 to KI/O7 pins by connecting a pull-up resistor of 50 kΩ and a switch to these
pins (which then become high level when the switch is on and low level when off). Set the KI/O0 to KI/O7 pins
to input mode at this time. Reading data from these pins enables multiple output data to be obtained for the
same key input.
A pull-up resistor can be connected to any of pins KI/O0 to KI/O7 (the figure below shows an example of when
a pull-up resistor is connected to the KI/O5 pin).
The mode selection switch in the figure is used for switching the set for unified multiple ROM codes.
VDD
Mode selection switch
KI/O6
KI/O7
S0
KI/O5
KI/O4
KI/O3
KI/O2
KI/O1
+
S1/LED
REM
VDD
KI/O0
Note 1
Note 3
XOUT
KI3
KI2
KI1
KI0
Note 1
Note 3
Note 3
Note 3
XIN
GND
Note 2
S2
Key matrix
8 × 7 = 56 keys
Notes 1. When incorporation of a capacitor for oscillation has not been specified by a mask option.
2. S2: Set to enable for STOP mode release.
3. Set pins KI0 to KI3 to “with pull-down resistors”.
Caution For a switch used by the end user to switch the mode on the same set, the mode may not be
correctly read while a key is being pressed. In this case, either avoid placing a key on the switch
line, or read the mode while a key is not being pressed.
Data Sheet U16792EJ1V0DS
62
µPD67B, 68B
14. PACKAGE DRAWING
20-PIN PLASTIC SSOP (7.62 mm (300))
20
11
detail of lead end
F
G
T
P
L
U
E
1
10
A
H
I
J
S
N
S
K
C
B
M
D
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
6.65 0.15
0.475 MAX.
0.65 (T.P.)
+0.08
0.24
D
–0.07
E
F
G
H
I
0.1 0.05
1.3 0.1
1.2
8.1 0.2
6.1 0.2
1.0 0.2
0.17 0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6 0.15
S20MC-65-5A4-2
Remark The external dimensions and material of the ES version are the same as those of the mass produced
version.
Data Sheet U16792EJ1V0DS
63
µPD67B, 68B
15. RECOMMENDED SOLDERING CONDITIONS
The µPD67B and 68B should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 15-1. Surface Mounting Type Soldering Conditions
µPD67BMC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))
µPD68BMC-×××-5A4: 20-pin plastic SSOP (7.62 mm (300))
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),
IR35-00-3
VP15-00-3
WS60-00-1
—
Count: Three times or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),
Count: Three times or less
Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for partial heating).
Data Sheet U16792EJ1V0DS
64
µPD67B, 68B
APPENDIX A. DEVELOPMENT TOOLS
An emulator is provided as an emulation tool and a PROM programmer and program adapter are provided as
writing tools for the PROM product, the µPD6P9.
Hardware
• Emulator (EB-69, EB-69ANote 1
Tool to emulate the µPD67B, 68B, and 6P9.
)
• Emulation probe (NP-20GSNote 1
)
Probe for 20-pin SSOP to connect the emulator to the target system.
• Flexible board (EV-9500GS-20)
20-pin flexible board to facilitate the connection between the emulation probe and the target system.
• PROM programmer (AF-9706Note 2, AF-9708Note 2, AF-9709Note 2
PROM programmer supporting the µPD6P9.
)
The µPD6P9 can be programmed by connecting the program adapter.
• Program adapter (PA-61P34BMC)
Adapter to program the µPD6P9. Use in combination with the AF-9706, AF-9708, and AF-9709.
Notes 1. This is a product of Naito Densei Machida Mfg. Co., Ltd.
For details, contact Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-45-475-4191).
2. This is a product of Ando Electric Co., Ltd.
For details, contact Ando Electric Co., Ltd. (TEL: +81-3-3733-1151).
Software
• Assembler (AS6133 Ver. 2.22 or later)
Development tool for remote control transmitter software.
Part Number List of AS6133
Host Machine
PC-9800 series
OS
Supply Medium
3.5-inch 2HD
Part Number
MS-DOS (Ver. 5.0 to Ver. 6.2)
µS5A13AS6133
(CPU: 80,386 or more)
IBM PC/AT compatible
MS-DOS (Ver. 6.0 to Ver. 6.22)
3.5-inch 2HC
µS7B13AS6133
PC DOS (Ver. 6.1 to Ver. 6.3)
Caution Although Ver. 5.0 or later has a task swap function, this function cannot be used with this
software.
Data Sheet U16792EJ1V0DS
65
µPD67B, 68B
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN µPD67B, 68B, AND OTHER PRODUCTS
Item
µPD67A
1,002 × 10 bits
32 × 4 bits
µPD68A
µPD67B
µPD68B
ROM capacity
RAM capacity
Stack
2,026 × 10 bits
1,002 × 10 bits
2,026 × 10 bits
1 level (also used as RF of RAM)
8 × 7 = 56 keys
Key matrix
Key extended input
Clock frequency
S0, S1, S2
Ceramic oscillation
• fX = 3.5 to 4.5 MHz
Timer
Clock
64/fX
Count start
Output value
Frequency
Writing count value
(Set value + 1) × 64/fX – 4/fX
Carrier
Each high-/low-level width can be set from 250 ns to 64 µs (@ fX = 4 MHz operation) via
modulo registers (2 channels).
Output start
Synchronized with timer
16 µs (fX = 4 MHz)
n = 1 to F
Instruction execution time
“MOV Rn, @R0” instruction
Standby
mode
Reset
POC
Release condition
• HALT mode for timer only.
(HALT instruction) • STOP mode for only releasing KI (KI/O high-level output or KI/O0 high-level output)
Relation between HALT instruction HALT instruction not executed when F = 1
execution and status flag (F)
POC circuit
• Provided
• Generates internal reset signal on detection
• VPOC = 1.85 V (TYP.)
• Provided
• VPOC = 1.5 V (TYP.)
RAM retention detector
• VID = 1.4 V (TYP.)
VDD = 2.0 to 3.6 V
TA = –40 to +85°C
20-pin plastic SSOP (7.62 mm (300))
µPD6P9
• VID = 1.5 V (TYP.)
VDD = 1.65 to 3.6 V
Supply voltage
Operating ambient temperature
Package
One-time PROM
Data Sheet U16792EJ1V0DS
66
µPD67B, 68B
APPENDIX C. EXAMPLE OF REMOTE CONTROL TRANSMISSION FORMAT
(in the case of NEC transmission format in command one-shot transmission mode)
Caution When using the NEC transmission format, please apply to NEC Electronics for a custom code.
(1) REM output waveform (From <2> on, the output is made only when the key is held down)
REM output
58.5 to 76.5 ms
< 1 >
< 2 >
108 ms
108 ms
Remark If the key is held down, the power consumption of the infrared light-emitting diode (LED) can be reduced
by transmitting only the reader code and the stop bit from the second time.
(2) Enlarged waveform of <1>
< 3 >
REM output
9 ms
4.5 ms
Custom code
8 bits
Custom code'
8 bits
Data code
8 bits
Data code
8 bits
Stop bit
1 bit
13.5 ms
Leader code
18 to 36 ms
58.5 to 76.5 ms
27 ms
(3) Enlarged waveform of <3>
REM output
9 ms
4.5 ms
0.56 ms
13.5 ms
1.125 ms 2.25 ms
0
1
1
0
0
(4) Enlarged waveform of <2>
REM output
9 ms
2.25 ms
11.25 ms
Leader code
0.56 ms
Stop bit
Data Sheet U16792EJ1V0DS
67
µPD67B, 68B
(5) Carrier waveform (enlarged waveform of each code’s high period)
REM output
8.77 µs
26.3 µs
9 ms or 0.56 ms
Carrier frequency: 38 kHz
(6) Bit array of each code
C0
C1
C2
C3
C4
C5
C6
C7
C0
' C1
' C2
' C3
' C4
' C5
' C6
' C7
' D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
C
0
C
1
C
2
C
3
C
4
C
5
C
6
C
7
or or or or or or or or
C
o
C
1
C
2
C
3
C
4
C
5
C
6
C
7
Leader code
Custom code
Custom code'
Data code
Data code
Caution To prevent malfunction with other systems when receiving data in the NEC transmission
format, not only fully decode (make sure to check Data code as well) the total 32 bits of the
16-bit custom codes (Custom code, Custom code’) and the 16-bit data codes (Data code,
Data code), but also check to make sure that no signals are present.
Data Sheet U16792EJ1V0DS
68
µPD67B, 68B
[MEMO]
Data Sheet U16792EJ1V0DS
69
µPD67B, 68B
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Data Sheet U16792EJ1V0DS
70
µPD67B, 68B
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
800-366-9782
NEC Electronics Hong Kong Ltd.
Seoul Branch
• Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Seoul, Korea
Tel: 02-558-3737
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
• Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2445845
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
• Tyskland Filial
Taeby, Sweden
Tel: 08-63 80 820
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J03.4
Data Sheet U16792EJ1V0DS
71
µPD67B, 68B
MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of July, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
UPD68BMC-XXX-5A4-A
Microcontroller, 4-Bit, MROM, 4MHz, MOS, PDSO20, 7.62 MM, LEAD FREE, PLASTIC, SSOP-20
NEC
UPD68MC-XXX-5A4-A
Microcontroller, 4-Bit, OTPROM, 4.5MHz, MOS, PDSO20, 0.300 INCH, PLASTIC, SSOP-20
NEC
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