UPD4482363GF-A50 [NEC]
8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT; 8M - BIT的CMOS同步快速SRAM流水线操作双循环DESELECT
| 型号： | UPD4482363GF-A50 |
| 厂家： | 
NEC |
| 描述： | 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION DOUBLE CYCLE DESELECT |
| 文件： | 总28页 (文件大小：298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4482163, 4482183, 4482323, 4482363
8M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
DOUBLE CYCLE DESELECT
Description
The µPD4482163 is a 524,288-word by 16-bit, the µPD4482183 is a 524,288-word by 18-bit, µPD4482323 is a 262,144-
word by 32-bit and the µPD4482363 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The µPD4482163, µPD4482183, µPD4482323 and µPD4482363 integrates unique synchronous peripheral circuitry, 2-
bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD4482163, µPD4482183, µPD4482323 and µPD4482363 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD4482163, µPD4482183, µPD4482323 and µPD4482363 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
• Single 3.3 V power supply
• Synchronous operation
• Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60)
TA = −40 to +85 °C (-A44Y, -A50Y, -A60Y)
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs and outputs for pipelined operation
• Double-Cycle deselect timing
• All registers triggered off positive clock edge
• 3.3 V LVTTL Compatible : All inputs and outputs
• Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable : /BW1 to /BW4, /BWE (µPD4482323, µPD4482363)
/BW1, /BW2, /BWE (µPD4482163, µPD4482183)
Global write enable : /GW
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M14904EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark shows major revised points.
The mark # shows major revised points.
2000
µPD4482163, 4482183, 4482323, 4482363
Ordering Information
Part number
Access
Time
ns
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O Interface
3.3 V LVTTL
Operating
Temperature
°C
Package
µPD4482163GF-A44
µPD4482163GF-A50
µPD4482163GF-A60
µPD4482183GF-A44
µPD4482183GF-A50
µPD4482183GF-A60
µPD4482323GF-A44
µPD4482323GF-A50
µPD4482323GF-A60
µPD4482363GF-A44
µPD4482363GF-A50
µPD4482363GF-A60
µPD4482163GF-A44Y
µPD4482163GF-A50Y
µPD4482163GF-A60Y
µPD4482183GF-A44Y
µPD4482183GF-A50Y
µPD4482183GF-A60Y
µPD4482323GF-A44Y
µPD4482323GF-A50Y
µPD4482323GF-A60Y
µPD4482363GF-A44Y
µPD4482363GF-A50Y
µPD4482363GF-A60Y
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
2.8
3.1
3.5
225
200
167
225
200
167
225
200
167
225
200
167
225
200
167
225
200
167
225
200
167
225
200
167
3.3 ± 0.165
0 to 70
100-pin PLASTIC
LQFP (14 × 20)
−40 to +85
Data Sheet M14904EJ3V0DS
2
µPD4482163, 4482183, 4482323, 4482363
Pin Configurations
/××× indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[µPD4482163GF, µPD4482183GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
2
3
V
DDQ
4
V
V
DD
Q
V
SS
Q
5
SS
Q
NC
NC
6
NC
7
I/OP1, NC
I/O8
I/O9
8
I/O10
9
I/O7
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
Q
V
DD
DD
Q
I/O11
I/O12
NC
I/O6
I/O5
V
SS
V
DD
NC
NC
V
DD
V
SS
I/O13
I/O14
ZZ
I/O4
I/O3
V
DD
Q
Q
V
V
DD
Q
V
SS
SS
Q
I/O15
I/O16
I/O2
I/O1
NC
I/OP2, NC
NC
NC
V
SS
Q
Q
V
V
SS
Q
V
DD
DD
Q
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for the 1-pin index mark.
Data Sheet M14904EJ3V0DS
3
µPD4482163, 4482183, 4482323, 4482363
Pin Identification (µPD4482163GF, µPD4482183GF)
Symbol Pin No.
A0 to A18
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, Synchronous Address Input
49, 50, 43, 80
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23
Synchronous Data In,
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
I/OP1, NCNote
I/OP2, NCNote
/ADV
74
24
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
83
/AP
84
/AC
85
/CE,CE2, /CE2
98, 97, 92
/BW1, /BW2, /BWE 93, 94, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Power Supply
Output Buffer Ground
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 51, 52, 53, No Connection
56, 57, 66, 75, 78, 79, 95, 96
Note NC (No Connection) is used in the µPD4482163GF.
I/OP1 and I/OP2 are used in the µPD4482183GF.
Data Sheet M14904EJ3V0DS
4
µPD4482163, 4482183, 4482323, 4482363
100-pin PLASTIC LQFP (14 x 20)
[µPD4482323GF, µPD4482363GF]
Marking Side
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP2, NC
I/O16
I/OP3, NC
I/O17
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
I/O15
I/O18
3
V
V
DD
Q
V
DD
Q
Q
4
SS
Q
V
SS
5
I/O14
I/O13
I/O12
I/O11
I/O19
I/O20
I/O21
I/O22
6
7
8
9
V
V
SS
Q
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DD
Q
V
DD
I/O10
I/O9
I/O23
I/O24
NC
V
SS
NC
V
DD
V
DD
NC
ZZ
V
SS
I/O25
I/O26
I/O8
I/O7
V
V
DD
Q
V
DD
Q
Q
SS
Q
V
SS
I/O6
I/O5
I/O4
I/O3
I/O27
I/O28
I/O29
I/O30
V
V
SS
Q
V
SS
Q
Q
DD
Q
V
DD
I/O2
I/O31
I/O32
I/O1
I/OP1, NC
I/OP4, NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for the 1-pin index mark.
Data Sheet M14904EJ3V0DS
5
µPD4482163, 4482183, 4482323, 4482363
Pin Identification (µPD4482323GF, µPD4482363GF)
Symbol
A0 to A17
Pin No.
Description
Synchronous Address Input
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, Synchronous Data In,
75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23,
24, 25, 28, 29
Synchronous / Asynchronous Data Out
I/OP1, NCNote
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
/ADV
51
Synchronous Data In (Parity),
80
Synchronous / Asynchronous Data Out (Parity)
1
30
83
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
/AP
84
/AC
85
/CE, CE2, /CE2
98, 97, 92
/BWE1 to /BWE4, /BWE 93, 94, 95, 96, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
14, 16, 38, 39, 42, 66
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD4482323GF.
I/OP1 to I/OP4 are used in the µPD4482363GF.
Data Sheet M14904EJ3V0DS
6
µPD4482163, 4482183, 4482323, 4482363
Block Diagrams
[µPD4482163, µPD4482183]
19
17
19
Address
A0 to A18
Registers
A0, A1
A1’
MODE
/ADV
CLK
Q1
Binary
Counter
and Logic
A0’
/AC
/AP
Row and Column
Decoders
CLR
Q0
8/9
8/9
Byte 1
Byte 1
Memory cell array
1,024 rows
/BW1
/BW2
Write Register
Write Driver
Byte 2
Write Register
Byte 2
Write Driver
512 × 16 columns
(8,388,608 bits)
512 × 18 columns
(9,437,184 bits)
/BWE
16/18
/GW
/CE
16/18
Enable
Register
Output
Registers Buffers
Output
CE2
/CE2
/G
Input
Registers
2
16/18
I/O1 to I/O16
I/OP1 to I/OP2
Power Down Control
ZZ
Burst Sequence
[µPD4482163, µPD4482183]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 to A2, A1, A0
A18 to A2, A1, /A0
A18 to A2, /A1, A0
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
Data Sheet M14904EJ3V0DS
7
µPD4482163, 4482183, 4482323, 4482363
[µPD4482323, µPD4482363]
18
16
18
Address
A0 to A17
Registers
A0, A1
MODE
/ADV
CLK
A1’
Q1
Binary
Counter
and Logic
A0’
/AC
/AP
Row and Column
Decoders
CLR
Q0
8/9
8/9
8/9
8/9
Byte 1
Byte 1
Memory cell array
1,024 rows
/BW1
/BW2
/BW3
Write Register
Write Driver
Byte 2
Write Register
Byte 2
Write Driver
256 × 32 columns
(8,388,608 bits)
Byte 3
Write Register
Byte 3
Write Driver
256 × 36 columns
(9,437,184 bits)
Byte 4
Write Register
Byte 4
Write Driver
/BW4
/BWE
32/36
32/36
Output
Registers Buffers
Output
/GW
/CE
Enable
Register
CE2
/CE2
Input
Registers
/G
4
32/36
I/O1 to I/O32
I/OP1 to I/OP4
Power Down Control
ZZ
[µPD4482323, µPD4482363]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 to A2, A1, A0
A17 to A2, A1, /A0
A17 to A2, /A1, A0
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
Data Sheet M14904EJ3V0DS
8
µPD4482163, 4482183, 4482323, 4482363
Asynchronous Truth Table
Operation
Read Cycle
Read Cycle
Write Cycle
Deselected
/G
L
I/O
Dout
H
×
High-Z
High-Z, Din
High-Z
×
Remark × : don’t care
Synchronous Truth Table
Operation
/CE
H
L
CE2
/CE2
×
/AP
×
/AC
L
/ADV
×
/WRITE
CLK
Address
None
Deselected Note
×
L
×
L
×
H
H
×
×
×
×
H
×
×
×
×
×
×
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
Deselected Note
×
L
×
×
None
Deselected Note
L
H
×
L
×
×
×
None
Deselected Note
L
H
H
L
L
×
×
None
Deselected Note
L
H
L
L
×
×
None
Read Cycle / Begin Burst
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Suspend Burst
Read Cycle / Suspend Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Suspend Burst
Write Cycle / Suspend Burst
L
×
×
×
External
External
Next
L
L
H
H
×
L
×
H
H
H
H
H
L
L
L
L
L
×
×
H
H
H
H
L
L
H
×
×
L
Next
×
H
×
H
H
×
Current
Current
External
Next
H
L
×
L
H
H
×
×
×
H
H
H
H
L
H
×
×
L
Next
×
H
×
H
H
Current
Current
H
×
Note Deselect status is held until new “Begin Burst” entry.
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [µPD4482163, µPD4482183]
/BW1 to /BW4 and /GW are HIGH, and /BWE is LOW. [µPD4482323, µPD4482363]
Data Sheet M14904EJ3V0DS
9
µPD4482163, 4482183, 4482323, 4482363
Partial Truth Table for Write Enables
[µPD4482163, µPD4482183]
Operation
/GW
H
/BWE
/BW1
/BW2
Read Cycle
H
L
L
L
L
×
×
H
L
×
H
H
L
Read Cycle
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / All Bytes
Write Cycle / All Bytes
H
H
H
L
H
L
L
×
×
Remark × : don’t care
[µPD4482323, µPD4482363]
Operation
/GW
H
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
L
L
L
L
L
L
×
×
H
L
×
H
H
L
×
H
H
H
L
×
H
H
H
H
L
Read Cycle
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
Write Cycle / All Bytes
H
H
H
H
H
L
H
H
H
L
H
H
L
H
L
Write Cycle / All Bytes
L
×
×
×
×
Remark × : don’t care
Pass-Through Truth Table
Previous Cycle
Present Cycle
Next Cycle
Operation
Operation
Add /WRITE
Ak
I/O
Operation
Add /CEs /WRITE /G
I/O
Write Cycle
L
Dn(Ak) Read Cycle
(Begin Burst)
Am
L
H
L
Q1(Ak)
Read Q1(Am)
Deselected
-
H
×
×
High-Z
No Carry Over from
Previous Cycle
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [µPD4482163, µPD4482183]
/BW1 to /BW4 and /GW are HIGH, and /BWE is LOW. [µPD4482323, µPD4482363]
/CEs = L means /CE is LOW, /CE2 is LOW and CE2 is HIGH.
/CEs = H means /CE is HIGH or /CE2 is HIGH or CE2 is LOW.
ZZ (Sleep) Truth Table
ZZ
Chip Status
Active
≤ 0.2 V
Open
Active
≥ VDD − 0.2 V
Sleep
Data Sheet M14904EJ3V0DS
10
µPD4482163, 4482183, 4482323, 4482363
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
+4.0
Unit Notes
V
V
Output supply voltage
Input voltage
VDDQ
VIN
VDD
VDD + 0.5
VDDQ + 0.5
70
V
V
1, 2
1, 2
Input / Output voltage
Operating ambient temperature
VI/O
TA
-A44, -A50, -A60
°C
-A44Y, -A50Y, -A60Y
–40
–55
+85
Storage temperature
Tstg
+125
°C
Notes 1. –2.0 V (MIN.) (Pulse width : 2 ns)
2. VDDQ + 2.3 V (MAX.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
3.135
3.135
2.0
TYP.
3.3
MAX.
3.465
Unit
V
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
3.3
3.465
V
VDDQ + 0.3
+0.8
V
VIL
–0.3 Note
V
Note –0.8 V (MIN.) (Pulse Width : 2 ns)
Data Sheet M14904EJ3V0DS
11
µPD4482163, 4482183, 4482323, 4482363
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit
µA
Note
Input leakage current
I/O leakage current
Operating supply current
VIN (except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled
ILO
–2
+2
µA
IDD
Device selected, Cycle = MAX.
-A44
440
mA
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA
-A44Y
-A50
400
320
180
-A50Y
-A60
-A60Y
IDD1
Suspend cycle, Cycle = MAX.
/AC, /AP, /ADV, /GW, /BWEs ≥ VIH,
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA
Device deselected, Cycle = 0 MHz
Standby supply current
ISB
30
15
mA
VIN ≤ VIL or VIN ≥ VIH, All inputs are static
Device deselected, Cycle = 0 MHz
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V,
VI/O ≤ 0.2 V, All inputs are static
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
ISB1
ISB2
130
15
Power down supply current ISBZZ ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
mA
V
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
IOL = +8.0 mA
2.4
0.4
V
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Symbol
CIN
Test conditions
MIN.
TYP.
MAX.
Unit
pF
Input capacitance
VIN = 0 V
VI/O = 0 V
Vclk = 0 V
6.0
8.0
6.0
Input / Output capacitance
Clock Input capacitance
CI/O
pF
Cclk
pF
Remark These parameters are periodically sampled and not 100% tested.
Data Sheet M14904EJ3V0DS
12
µPD4482163, 4482183, 4482323, 4482363
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input waveform (Rise / Fall time = 1 ns (20 to 80%))
3.0 V
1.5 V
Test ponts
1.5 V
V
SS
Output waveform
1.5 V
Test points
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
VT = +1.5 V
50 Ω
ZO = 50 Ω
I/O (Output)
CL
Remark CL includes capacitance's of the probe and jig, and stray capacitances.
Data Sheet M14904EJ3V0DS
13
µPD4482163, 4482183, 4482323, 4482363
Read and Write Cycle
Parameter
Symbol
-A44
-A44Y
-A50
-A50Y
-A60
-A60Y
Unit
Note
(225 MHz)
(200 MHz)
(167 MHz)
Standard
Alias
TCYC
TCD
TOE
TDC1
TDC2
TOLZ
TOHZ
TCZ
TCH
TCL
TAS
TSS
TDS
TWS
–
MIN.
MAX.
–
MIN.
MAX.
–
MIN.
MAX.
Cycle time
TKHKH
TKHQV
TGLQV
TKHQX1
TKHQX2
TGLQX
TGHQZ
TKHQZ
TKHKL
4.4
–
5.0
–
6.0
–
–
3.5
3.5
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time
2.8
2.8
–
3.1
3.1
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
Output disable to output High-Z
Clock high to output High-Z
Clock high pulse width
Clock low pulse width
Setup times Address
Address status
–
–
–
0
0
0
1.5
0
–
1.5
0
–
1.5
0
–
–
–
–
0
2.8
2.8
–
0
3.1
3.1
–
0
3.5
3.5
–
1.5
1.8
1.8
1.4
1.5
2.0
2.0
1.5
1.5
2.0
2.0
1.5
TKLKH
–
–
–
TAVKH
TADSVKH
TDVKH
TWVKH
–
–
–
Data in
Write enable
Address advance TADVVKH
Chip enable
Address
TEVKH
TKHAX
–
Hold times
TAH
TSH
TDH
TWH
–
0.4
–
0.5
–
0.5
–
ns
Address status
Data in
TKHADSX
TKHDX
Write enable
TKHWX
Address advance TKHADVX
Chip enable
TKHEX
TZZE
–
Power down entry time
TZZE
TZZR
–
–
8.8
8.8
–
–
10.0
10.0
–
–
12.0
12.0
ns
ns
Power down recovery time
TZZR
Data Sheet M14904EJ3V0DS
14
READ CYCLE
TKHKH
CLK
/AP
/AC
TKHKL
TKLKH
TADSVKH
TKHADSX
TADSVKH
TKHADSX
TAVKH
TKHAX
A1
A2
A3
Address
/ADV
TADVVKH
TKHADVX
TWVKH
TKHWX
TKHWX
µ
/BWE
/BWs
Note3
Note3
TWVKH
/GW
TEVKH
TKHEX
/CEs Note1
/G
TGLQV
TGHQZ
High-Z
Data In
TKHQV
Q2(A2)
TKHQZ
TGLQX
TKHQX2
Note2
High-Z
High-Z
Q1(A1)
Q1(A2)
Q3(A2)
Q4(A2) Q1(A2) Q1(A3)
Data Out
Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Outputs are disabled within two clock cycles after deselect.
2.
3. If /GW is set to low level or /BWE is set to low level and one of /BW1 to /BW4 is set to low level,
Q1(A3) is not output.
Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
Remark
WRITE CYCLE
TKHKH
CLK
/AP
TADSVKH TKHADSX
TKHKL
TKLKH
TADSVKH TKHADSX
/AC
Address
/ADV
TAVKH
TKHAX
A1
A2
A3
TADVVKH
TKHADVX
µ
TWVKH
TKHWX
/BWENote1
/BWs
TWVKH
TKHWX
/GWNote1
TEVKH
TKHEX
/CEs Note2
/G
TDVKH
TKHDX
High-Z
D1(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
Data In
TGHQZ
High-Z
Data Out
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
TADSVKH
/AP
/AC
TKHADSX
TAVKH
TKHAX
A1
A2
A3
Address
/ADV
TADVVKH
TKHADVX
µ
TWVKH
TKHWX
/BWE Note1
/BWs
TKHWX
TWVKH
/GW Note1
TEVKH
TKHEX
/CEs Note2
/G
TDVKH
TKHDX
High-Z
High-Z
Data In
D1(A2)
TGHQZ
TKHQV
TKHQX1
TGLQX
Q1(A2)
High-Z
High-Z
High-Z
Data Out
Q1(A1)
Q1(A3) Q2(A3)
Q3(A3)
Q4(A3)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
2.
Notes
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
SINGLE READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
/AC
TAVKH TKHAX
A2
A5
A8
A3
A4
Address
A7
A9
A1
A6
TKHWX
TKHWX
TWVKH
/BWE Note1
/BWs
Note4
Note4
TWVKH
/GW Note1
µ
TEVKH
TKHEX
/CEs Note2
/G
TDVKH TKHDX
High-Z
TGLQV
High-Z
Data In
D1(A5) D1(A6)
D1(A7)
TKHQZ
Q1(A9)
TKHQV
Q1(A7)
TGHQZ
TGLQX
Q1(A1)
Note3
High-Z
High-Z
Data Out
Q1(A8)
Q1(A2) Q1(A3)
Q1(A4)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
2.
Notes
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
Outputs are disabled within two clock cycles after deselect.
3.
4.
If /GW is set to low level or /BWE is set to low level and one of /BW1 to /BW4 is set to low level,
Q1(A9) is not output.
/AP is HIGH and /ADV is don't care.
Remark
POWER DOWN (ZZ) CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
µ
/ADV
/BWE
/BWs
/GW
/CEs
/G
High-Z
High-Z
Q1(A1)
Q1(A2)
Data Out
TZZR
TZZE
ZZ
Power Down (ISBZZ) State
STOP CLOCK CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
µ
/ADV
/BWE
/BWs
/GW
/CEs
/G
High-Z
High-Z
High-Z
Data In
High-Z
Q1(A1)
Q1(A2)
Data Out
Note
Power Down State (ISB1
)
Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V
µPD4482163, 4482183, 4482323, 4482363
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
14.0 0.2
16.0 0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125 0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
Data Sheet M14904EJ3V0DS
21
µPD4482163, 4482183, 4482323, 4482363
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4482163, 4482183, 4482323 and 4482363.
Types of Surface Mount Devices
µPD4482163GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482183GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482323GF : 100-pin PLASTIC LQFP (14 x 20)
µPD4482363GF : 100-pin PLASTIC LQFP (14 x 20)
Data Sheet M14904EJ3V0DS
22
µPD4482163, 4482183, 4482323, 4482363
Revision History
Edition/
Page
Type of
revision
Location
Description
Date
This
edition
Previous
edition
(Previous edition → This edition)
3rd edition/ Throughout Throughout Modification
Dec. 2002 Addition
−
−
Preliminary Data Sheet → Data Sheet
Extended operating temperature products
(TA = −40 to +85 °C)
Data Sheet M14904EJ3V0DS
23
µPD4482163, 4482183, 4482323, 4482363
[MEMO]
Data Sheet M14904EJ3V0DS
24
µPD4482163, 4482183, 4482323, 4482363
[MEMO]
Data Sheet M14904EJ3V0DS
25
µPD4482163, 4482183, 4482323, 4482363
[MEMO]
Data Sheet M14904EJ3V0DS
26
µPD4482163, 4482183, 4482323, 4482363
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14904EJ3V0DS
27
µPD4482163, 4482183, 4482323, 4482363
•
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
UPD4483362
8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
NEC
UPD4483362GF-A75
8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
NEC
©2020 ICPDF网 联系我们和版权申明