UPD444001 [NEC]
4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT; 4M位CMOS快速SRAM 4M - WORD BY 1位![UPD444001](http://pdffile.icpdf.com/pdf1/p00062/img/icpdf/UPD444001_324321_icpdf.jpg)
型号: | UPD444001 |
厂家: | ![]() |
描述: | 4M-BIT CMOS FAST SRAM 4M-WORD BY 1-BIT |
文件: | 总16页 (文件大小:143K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD444001
4M-BIT CMOS FAST SRAM
4M-WORD BY 1-BIT
Description
The µPD444001 is a high speed, low power, 4,194,304 bits (4,194,304 words by 1 bit) CMOS static RAM.
Operating supply voltage is 5.0 V ± 0.5 V.
The µPD444001 is packaged in 32-pin PLASTIC SOJ.
Features
• 4,194,304 words by 1 bit organization
• Fast access time : 10, 11, 12 ns (MAX.)
• Output Enable input for easy application
• Single +5.0 V power supply
Ordering Information
Part number
Package
Access time
Supply current mA (MAX.)
At operating At standby
ns (MAX.)
µPD444001LE-10
µPD444001LE-11
µPD444001LE-12
32-pin PLASTIC SOJ
(10.16 mm (400))
10
11
12
170
10
160
150
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14947EJ4V0DS00 (4th edition)
Date Published May 2002 NS CP(K)
Printed in Japan
The mark shows major revised points.
2000
©
µPD444001
Pin Configuration (Marking Side)
/xxx indicates active low signal.
32-pin PLASTIC SOJ (10.16 mm (400))
A0
A1
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A21
A20
A19
A18
A17
A16
/OE
GND
2
A2
3
A3
4
A4
5
A5
6
/CS
7
V
CC
8
GND
9
VCC
DIN
10
11
12
13
14
15
16
DOUT
/WE
A6
A15
A14
A13
A12
A11
NC
A7
A8
A9
A10
A0 - A21 : Address Inputs
DIN
: Data Input
DOUT
/CS
/WE
/OE
VCC
: Data Output
: Chip Select
: Write Enable
: Output Enable
: Power supply
: Ground
GND
NC
: No connection
Remark Refer to Package Drawing for the 1-pin index mark.
2
Data Sheet M14947EJ4V0DS
µPD444001
Block Diagram
A0
|
A21
Memory cell array
4,194,304 bits
Input data
controller
Sense amplifier /
Switching circuit
Output data
controller
DIN
Column decoder
DOUT
Address buffer
/CS
/OE
/WE
V
CC
GND
Truth Table
/CS
H
/OE
×
/WE
×
Mode
Not selected
Read
I/O
High impedance
DOUT
Supply current
ISB
ICC
L
L
H
L
×
L
Write
DIN
L
H
H
Output disable
High impedance
Remark × : Don’t care
3
Data Sheet M14947EJ4V0DS
µPD444001
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
–0.5 Note to +7.0
–0.5 Note to VCC+0.5
0 to 70
Unit
V
Input / Output voltage
Operating ambient temperature
Storage temperature
V
TA
°C
°C
Tstg
–55 to +125
Note –2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
VIH
Condition
MIN.
4.5
TYP.
5.0
MAX.
5.5
Unit
V
High level input voltage
2.2
VCC + 0.5
+0.8
V
Low level input voltage
VIL
–0.5 Note
0
V
Operating ambient temperature
TA
70
°C
Note –2.0 V (MIN.) (pulse width : 2 ns)
4
Data Sheet M14947EJ4V0DS
µPD444001
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Input leakage current
Output leakage current
Symbol
ILI
Test condition
VIN = 0 V to VCC
MIN.
–2
TYP.
MAX.
+2
Unit
µA
ILO
VOUT = 0 V to VCC,
–2
+2
µA
/CS = VIH or /OE = VIH or /WE = VIL
Operating supply current
Standby supply current
ICC
/CS = VIL,
Cycle time : 10 ns
170
160
150
40
mA
mA
IOUT = 0 mA,
Cycle time : 11 ns
Cycle time : 12 ns
Minimum cycle time
ISB
/CS = VIH, VIN = VIH or VIL
/CS ≥ VCC – 0.2 V,
ISB1
10
VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V
IOH = –4.0 mA
High level output voltage
Low level output voltage
VOH
VOL
2.4
V
V
IOL = +8.0 mA
0.4
Remark
VIN : Input voltage
VOUT : Output voltage
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol
Input capacitance
Test condition
VIN = 0 V
MIN.
TYP.
MAX.
Unit
pF
CIN
6
8
Output capacitance
COUT
VOUT = 0 V
pF
Remarks 1. VIN : Input voltage
VOUT : Output voltage
2. These parameters are periodically sampled and not 100% tested.
5
Data Sheet M14947EJ4V0DS
µPD444001
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time ≤ 3 ns)
Output Waveform
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or
Figure 2.
Figure 1
Figure 2
(for tAA, tACS, tOE, tOH)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, tOW)
Ω
Ω
Ω
Ω
Remark CL includes capacitances of the probe and jig, and stray capacitances.
6
Data Sheet M14947EJ4V0DS
µPD444001
Read Cycle
Parameter
Symbol
-10
-11
-12
Unit Notes
MIN.
10
MAX.
MIN.
11
MAX.
MIN.
12
MAX.
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
10
10
5
11
11
5
12
12
6
1
/CS access time
tACS
tOE
/OE access time
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/CS to output in high impedance
/OE to output hold in high impedance
tOH
3
3
0
3
3
0
3
3
0
tCLZ
tOLZ
tCHZ
tOHZ
2, 3
5
5
6
5
6
6
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = VIL
7
Data Sheet M14947EJ4V0DS
µPD444001
Read Cycle Timing Chart 2 (/CS Access)
Caution Address valid prior to or coincident with /CS low level input.
Remark In read cycle, /WE should be fixed to high level.
8
Data Sheet M14947EJ4V0DS
µPD444001
Write Cycle
Parameter
Symbol
-10
-11
-12
Unit Notes
MIN.
10
7
MAX.
MIN.
11
7.5
7.5
8
MAX.
MIN.
12
8
MAX.
Write cycle time
tWC
tCW
tAW
tWP
tDW
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CS to end of write
Address valid to end of write
Write pulse width
7
8
7
8
Data valid to end of write
Data hold time
5
5
6
0
0
0
Address setup time
tAS
0
0
0
Write recovery time
tWR
tWHZ
tOW
1
1
1
/WE to output in high impedance
Output active from end of write
5
5
6
1, 2
3
3
3
Notes 1. Transition is measured at ± 200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
9
Data Sheet M14947EJ4V0DS
µPD444001
Write Cycle Timing Chart 1 (/WE Controlled)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to DOUT while DOUT is in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the DOUT pin is always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the DOUT pin high impedance.
10
Data Sheet M14947EJ4V0DS
µPD444001
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
Address (Input)
t
AS
t
CW
/CS (Input)
/WE (Input)
t
t
AW
WP
t
WR
t
DW
t
DH
Data in
DIN (Input)
High impedance
DOUT (Output)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to DOUT while DOUT is in the output state.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
11
Data Sheet M14947EJ4V0DS
µPD444001
Package Drawing
32-PIN PLASTIC SOJ (10.16mm (400))
B
32
17
C
D
1
16
G
J
E
F
U
T
S
P
M
M
N
Q
S
K
I
H
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
B
C
D
E
F
G
H
I
21.26±0.2
10.16
11.18±0.2
1.005±0.1
0.74
3.5±0.2
2.545±0.2
0.8 MIN.
2.6
J
K
M
N
P
Q
T
1.27(T.P.)
0.40±0.10
0.12
9.4±0.20
0.1
R0.85
+0.10
0.20
U
−0.05
P32LE-400A-1
12
Data Sheet M14947EJ4V0DS
µPD444001
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD444001.
Type of Surface Mount Device
µPD444001LE
: 32-pin PLASTIC SOJ (10.16 mm (400))
13
Data Sheet M14947EJ4V0DS
µPD444001
Revision History
Edition/
Page
Type of
revision
Location
Description
Date
This
edition
Previous
edition
(Previous edition → This edition)
4th edition/
May 2002
p.1, 2, 12, 13 p.1, 2, 13, 14 Deletion
Ordering Information,
Pin Configuration,
32-pin PLASTIC TSOP (II)
Package Drawing,
Type of Surface Mount Device
DC Characteristics
p.5
p.5
Deletion
Remark2
Remark2
Note3
Modification Capacitance
Modification Read Cycle, Write Cycle
Deletion
p.7, 9
p.7, 9
Remark
14
Data Sheet M14947EJ4V0DS
µPD444001
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Data Sheet M14947EJ4V0DS
µPD444001
•
The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
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patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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Customers must check the quality grade of each semiconductor product before using it in a particular
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
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M8E 00. 4
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