UPD44324184F5-E50-EQ2

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

µPD44324084, 44324094, 44324184, 44324364

36M-BIT DDRII SRAM

4-WORD BURST OPERATION

Description

The µPD44324084 is a 4,194,304-word by 8-bit, the µPD44324094 is a 4,194,304-word by 9-bit, the µPD44324184 is a

2,097,152-word by 18-bit and the µPD44324364 is a 1,048,576-word by 36-bit synchronous double data rate static RAM

fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The µPD44324084, µPD44324094, µPD44324184 and µPD44324364 integrate unique synchronous peripheral circuitry

and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K

and /K.

These products are suitable for application which require synchronous operation, high speed, low voltage, high density

and wide bit configuration.

These products are packaged in 165-pin PLASTIC FBGA.

Features

• 1.8 ± 0.1 V power supply and HSTL I/O

• DLL circuitry for wide output data valid window and future frequency scaling

• Pipelined double data rate operation

• Common data input/output bus

• Four-tick burst for reduced address frequency

• Two input clocks (K and /K) for precise DDR timing at clock rising edges only

• Two output clocks (C and /C) for precise flight time

and clock skew matching-clock and data delivered together to receiving device

• Internally self-timed write control

• Clock-stop capability with µs restart

• User programmable impedance output

• Fast clock cycle time : 3.3 ns (300 MHz), 4.0 ns (250 MHz), 5.0 ns (200 MHz)

• Simple control logic for easy depth expansion

• JTAG boundary scan

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

Document No. M16781EJ1V0DS00 (1st edition)

Date Published October 2004 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2003

µPD44324084, 44324094, 44324184, 44324364

Ordering Information

Part number

Cycle

Time

ns

Clock

Frequency

MHz

Organization Core Supply

I/O

Package

(word x bit)

Voltage

V

Interface

µPD44324084F5-E33-EQ2 ^Note

µPD44324084F5-E40-EQ2

µPD44324084F5-E50-EQ2

µPD44324094F5-E33-EQ2 ^Note

µPD44324094F5-E40-EQ2

µPD44324094F5-E50-EQ2

µPD44324184F5-E33-EQ2 ^Note

µPD44324184F5-E40-EQ2

µPD44324184F5-E50-EQ2

µPD44324364F5-E33-EQ2 ^Note

µPD44324364F5-E40-EQ2

µPD44324364F5-E50-EQ2

3.3

4.0

5.0

3.3

4.0

5.0

3.3

4.0

5.0

3.3

4.0

5.0

300

250

200

300

250

200

300

250

200

300

250

200

4 M x 8-bit

1.8 ± 0.1

HSTL

165-pin PLASTIC

FBGA (13 x 15)

4 M x 9-bit

2 M x 18-bit

1M x 36-bit

Note Under development

Preliminary Data Sheet M16781EJ1V0DS

2

µPD44324084, 44324094, 44324184, 44324364

Pin Configurations

/××× indicates active low signal.

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324084F5-EQ2]

1

2

3

A

4

5

/NW1

NC

A

6

7

NC

/NW0

A

8

9

A

10

A

11

CQ

DQ3

NC

DQ2

NC

ZQ

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

V^SS

NC

VREF

NC

DQ6

NC

TCK

R, /W

A

/K

/LD

A

NC

DQ4

NC

DQ5

VDDQ

NC

DQ7

A

K

NC

VDDQ

NC

A

NC

VREF

DQ1

NC

TMS

VSS

NC

VSS

A

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

VDDQ

VSS

VDDQ

VSS

G

H

J

NC

DQ0

NC

TDI

K

L

M

N

P

R

VSS

A

C

A

/C

A

: Address inputs

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

DQ0 to DQ7

/LD

R, /W

/NW0, /NW1

K, /K

C, /C

CQ, /CQ

ZQ

/DLL

: Data inputs / outputs

: Synchronous load

: Read Write input

: Nibble Write data select

: Input clock

: Output clock

: Echo clock

: Output impedance matching

: DLL disable

TCK

TDO

V^REF

V^DD

V^DDQ

VSS

NC

: No connection

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.

Preliminary Data Sheet M16781EJ1V0DS

3

µPD44324084, 44324094, 44324184, 44324364

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324094F5-EQ2]

1

2

3

A

4

5

6

7

NC

/BW0

A

8

9

A

10

A

11

CQ

DQ4

NC

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

V^SS

NC

VREF

NC

DQ7

NC

TCK

R, /W

A

NC

A

/K

/LD

A

NC

DQ5

NC

DQ6

VDDQ

NC

DQ8

A

K

NC

VDDQ

NC

A

NC

VREF

DQ2

NC

TMS

VSS

NC

VSS

A

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

DQ3

NC

G

H

J

NC

ZQ

NC

K

L

NC

DQ1

NC

M

N

P

R

VSS

NC

A

C

A

DQ0

TDI

A

/C

A

: Address inputs

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

DQ0 to DQ8

/LD

R, /W

/BW0

K, /K

C, /C

CQ, /CQ

ZQ

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

: Output clock

: Echo clock

: Output impedance matching

: DLL disable

TCK

TDO

V^REF

VDD

V^DDQ

V^SS

NC

: No connection

/DLL

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.

Preliminary Data Sheet M16781EJ1V0DS

4

µPD44324084, 44324094, 44324184, 44324364

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324184F5-EQ2]

1

2

V^SS

3

4

5

/BW1

NC

A

6

7

NC

/BW0

A1

8

9

A

10

A

11

CQ

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

A

R, /W

A

/K

/LD

A

DQ9

NC

K

NC

VDDQ

NC

A

NC

DQ8

NC

VSS

A0

VSS

A

VSS

DQ7

NC

DQ10

DQ11

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

NC

VDDQ

VSS

VDDQ

VSS

NC

DQ6

DQ5

NC

DQ12

NC

G

H

J

DQ13

VDDQ

NC

VREF

NC

VREF

DQ4

NC

ZQ

NC

K

L

NC

DQ14

NC

DQ3

DQ2

NC

DQ15

NC

M

N

P

R

NC

DQ1

NC

DQ16

DQ17

A

VSS

NC

A

C

A

NC

DQ0

TDI

TCK

A

/C

A

TMS

A0, A1, A

DQ0 to DQ17

/LD

R, /W

/BW0, /BW1

K, /K

C, /C

CQ, /CQ

ZQ

: Address inputs

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

: Output clock

: Echo clock

: Output impedance matching

: DLL disable

TCK

TDO

V^REF

VDD

V^DDQ

V^SS

NC

: No connection

/DLL

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 7A are expansion addresses: 2A for 72Mb and 7A for 144Mb.

Preliminary Data Sheet M16781EJ1V0DS

5

µPD44324084, 44324094, 44324184, 44324364

165-pin PLASTIC FBGA (13 x 15)

(Top View)

[µPD44324364F5-EQ2]

1

2

3

4

5

/BW2

/BW3

A

6

7

/BW1

/BW0

A1

8

9

A

10

VSS

11

CQ

A

B

C

D

E

F

/CQ

NC

/DLL

NC

TDO

V^SS

A

R, /W

A

/K

/LD

A

DQ27

NC

DQ18

DQ28

DQ19

DQ20

DQ21

DQ22

VDDQ

DQ32

DQ23

DQ24

DQ34

DQ25

DQ26

A

K

NC

VDDQ

NC

A

NC

DQ8

DQ7

DQ16

DQ6

DQ5

DQ14

ZQ

VSS

A0

VSS

A

VSS

DQ17

NC

DQ29

NC

VSS

VDD

VSS

A

VSS

VDD

VSS

A

VSS

VDDQ

VSS

VDDQ

VSS

DQ15

NC

DQ30

DQ31

VREF

NC

G

H

J

NC

VREF

DQ13

DQ12

NC

DQ4

DQ3

DQ2

DQ1

DQ10

DQ0

TDI

K

L

NC

DQ33

NC

M

N

P

R

DQ11

NC

DQ35

NC

VSS

A

C

A

DQ9

TMS

TCK

A

/C

A

A0, A1, A

DQ0 to DQ35

/LD

R, /W

/BW0 to /BW3

K, /K

C, /C

CQ, /CQ

ZQ

: Address inputs

TMS

TDI

: IEEE 1149.1 Test input

: IEEE 1149.1 Clock input

: IEEE 1149.1 Test output

: HSTL input reference input

: Power Supply

: Ground

: Data inputs / outputs

: Synchronous load

: Read Write input

: Byte Write data select

: Input clock

: Output clock

: Echo clock

: Output impedance matching

: DLL disable

TCK

TDO

V^REF

VDD

V^DDQ

V^SS

NC

: No connection

/DLL

Remarks 1. Refer to Package Drawing for the index mark.

2. 2A and 10A are expansion addresses: 10A for 72Mb and 2A for 144Mb.

Preliminary Data Sheet M16781EJ1V0DS

6

µPD44324084, 44324094, 44324184, 44324364

Pin Identification

Symbol

Description

A0

A1

A

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the

rising edge of K. All transactions operate on a burst of four words (two clock periods of bus activity). A0 and A1

are used as the lowest two address bits for BURST READ and BURST WRITE operations permitting a random

burst start address on x18 and x36 devices. These inputs are ignored when device is deselected or once

BURST operation is in progress.

DQ0 to DQxx Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and /K. Output

data is synchronized to the respective C and /C data clocks or to K and /K if C and /C are tied to HIGH.

x8 device uses DQ0 to DQ7.

x9 device uses DQ0 to DQ8.

x18 device uses DQ0 to DQ17.

x36 device uses DQ0 to DQ35.

/LD

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition

includes address and read/write direction. All transactions operate on a burst of 4 data (two clock periods of bus

activity).

R, /W

Synchronous Read/Write Input: When /LD is LOW, this input designates the access type (READ when R, /W is

HIGH, WRITE when R, /W is LOW) for the loaded address. R, /W must meet the setup and hold times around

the rising edge of K.

/BWx

/NWx

Synchronous Byte Writes (Nibble Writes on x8): When LOW these inputs cause their respective byte or nibble

to be registered and written during WRITE cycles. These signals must meet setup and hold times around the

rising edges of K and /K for each of the two rising edges comprising the WRITE cycle. See Pin Configurations

for signal to data relationships.

K, /K

C, /C

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data

on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous

inputs must meet setup and hold times around the clock rising edges.

Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of

/C is used as the output timing reference for first and third output data. The rising edge of C is used as the

output reference for second and fourth output data. Ideally, /C is 180 degrees out of phase with C. C and /C

may be tied HIGH to force the use of K and /K as the output reference clocks instead of having to provide C and

/C clocks. If tied HIGH, C and /C must remain HIGH and not be toggled during device operation.

Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q

tristates.

CQ, /CQ

ZQ

Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus

impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to

ground. This pin cannot be connected directly to GND or left unconnected.

/DLL

DLL Disable: When LOW, this input causes the DLL to be bypassed for stable low frequency operation.

TMS

TDI

IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left Not Connected if the JTAG function is not

used in the circuit.

TCK

IEEE 1149.1 Clock Input: 1.8V I/O levels. This pin must be tied to VSS if the JTAG function is not used in the

circuit.

TDO

VREF

VDD

IEEE 1149.1 Test Output: 1.8V I/O level.

HSTL Input Reference Voltage: Nominally V^DDQ/2. Provides a reference voltage for the input buffers.

Power Supply: 1.8V nominal. See DC Characteristics and Operating Conditions for range.

VDDQ

Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Characteristics

and Operating Conditions for range.

VSS

NC

Power Supply: Ground

No Connect: These signals are internally connected and appear in the JTAG scan chain as the logic level

applied to the ball sites. These signals may be connected to ground to improve package heat dissipation.

Preliminary Data Sheet M16781EJ1V0DS

7

µPD44324084, 44324094, 44324184, 44324364

Block Diagram

CLK

Burst

Logic

A1'

A0'

A1

D1

D0

Q1

Q0

A0

R

Address

Register

Address

/LD

/W

E

Compare

/C

C

A0''

A0'''

Output control

Logic

Write address

Register

K

E

A0'

Input

Register

/A0'

A0'

ZQ

0

2 :1

MUX

Memory

Array

CLK

/A0'

K

1

A0'

Output Buffer

E

DQ

0

1

/K

Input

Register

E

A0'''

Output Enable

Register

C

R, /W

Register

E

Preliminary Data Sheet M16781EJ1V0DS

8

µPD44324084, 44324094, 44324184, 44324364

Power-on Sequence

The following two timing charts show the recommended power-on sequence, i.e., when starting the clock after

V^DD/VDDQ stable and when starting the clock before VDD/VDDQ stable.

1. Clock starts after V^DD/VDDQ stable

V

DD/VDDQ

V

DD/VDDQ Stable (< 0.1 V DC per 50 ns)

Clock

Clock Start

1,024 cycles or more

Stable Clock

Start

Normal Operation

2. Clock starts before V^DD/VDDQ stable

V

DD/VDDQ

VDD/VDDQ Stable (< 0.1 V DC per 50 ns)

Clock

Clock Start

30 ns (MIN.)

1,024 cycles or more Start

DLL Reset or DLL Off

Stable Clock

Normal Operation

Preliminary Data Sheet M16781EJ1V0DS

9

µPD44324084, 44324094, 44324184, 44324364

Burst Sequence

Linear Burst Sequence Table

[µPD44324184, µPD44324364]

A1, A0

0, 0

A1, A0

0, 1

A1, A0

1, 0

A1, A0

1, 1

External Address

1st Internal Burst Address

2nd Internal Burst Address

3rd Internal Burst Address

0, 1

1, 0

1, 1

0, 0

1, 0

1, 1

0, 0

0, 1

1, 1

0, 0

0, 1

1, 0

Truth Table

Operation

/LD R, /W

CLK

DQ

WRITE cycle

L

L → H

Data in

Data out

High-Z

Load address, input write data on two

consecutive K and /K rising edge

READ cycle

Input data

Input clock

D(A1)

D(A2)

D(A3)

D(A4)

K(t+1) ↑

/K(t+1) ↑

K(t+2) ↑

/K(t+2) ↑

L

H

Load address, read data on two

consecutive C and /C rising edge

NOP (No operation)

Output data

Q(A1)

Q(A2)

Q(A3)

Q(A4)

Output clock /C(t+1) ↑

C(t+2) ↑ /C(t+2) ↑ C(t+3) ↑

H

X

STANDBY(Clock stopped)

Stopped Previous state

Remarks 1. H : High level, L : Low level, × : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C rising edges

except if C and /C are HIGH then Data outputs are delivered at K and /K rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. A1 refers to the address input during a WRITE or READ cycle. A2, A3 and A4 refer to the next internal

burst address in accordance with the linear burst sequence.

7. It is recommended that K = /K = C = /C when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.

Preliminary Data Sheet M16781EJ1V0DS

10

µPD44324084, 44324094, 44324184, 44324364

Byte Write Operation

[µPD44324084]

Operation

K

/K

–

/NW0

/NW1

Write DQ0 to DQ7

L → H

0

1

0

1

0

1

–

L → H

–

L → H

–

Write DQ0 to DQ3

Write DQ4 to DQ7

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44324094]

Operation

K

/K

–

/BW0

Write DQ0 to DQ8

L → H

0

1

–

L → H

–

L → H

–

Write nothing

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44324184]

Operation

K

L → H

–

/K

–

/BW0

/BW1

Write DQ0 to DQ17

0

1

0

1

0

1

L → H

–

Write DQ0 to DQ8

Write DQ9 to DQ17

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

[µPD44324364]

Operation

K

L → H

–

/K

–

/BW0

/BW1

/BW2

/BW3

Write DQ0 to DQ35

0

1

0

1

0

1

0

1

0

1

0

1

0

1

L → H

–

Write DQ0 to DQ8

Write DQ9 to DQ17

Write DQ18 to DQ26

Write DQ27 to DQ35

Write nothing

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

–

L → H

Remark H : High level, L : Low level, → : rising edge.

Preliminary Data Sheet M16781EJ1V0DS

11

µPD44324084, 44324094, 44324184, 44324364

Bus Cycle State Diagram

LOAD NEW

ADDRESS

Count = 0

Load, Count = 4

Write

Load, Count = 4

READ DOUBLE

Read

WRITE DOUBLE

Count = Count + 2

Always

Count = 2

Always

Count = 2

Load

NOP,

Count = 4

ADVANCE ADDRESS

BY TWO

ADVANCE ADDRESS

BY TWO

NOP

Supply voltage provided

Power UP

Remarks 1. A0 and A1 are internally advanced in accordance with the burst order table.

Bus cycle is terminated after burst count = 4.

2. State transitions: L = (/LD = LOW); /L = (/LD = HIGH); R = (/R, W = HIGH); W = (/R, W = LOW).

3. State machine control timing sequence is controlled by K.

Preliminary Data Sheet M16781EJ1V0DS

12

µPD44324084, 44324094, 44324184, 44324364

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol Conditions

MIN.

–0.5

0

TYP.

MAX.

Unit

V

Supply voltage

VDD

VDDQ

VIN

+2.5

Output supply voltage

Input voltage

VDD

VDD + 0.5 (2.5 V MAX.)

VDDQ + 0.5 (2.5 V MAX.)

70

V

Input / Output voltage

Operating ambient temperature

Storage temperature

VI/O

TA

V

°C

Tstg

–55

+125

Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause

permanent damage. The device is not meant to be operated under conditions outside the limits

described in the operational section of this specification. Exposure to Absolute Maximum Rating

conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (TA = 0 to 70 °C)

Parameter

Supply voltage

Symbol

Conditions

MIN.

1.7

TYP.

MAX.

1.9

Unit

V

Note

VDD

Output supply voltage

High level input voltage

Low level input voltage

Clock input voltage

VDDQ

VIH (DC)

VIL (DC)

VIN

1.4

VDD

V

1

VREF + 0.1

–0.3

VDDQ + 0.3

VREF – 0.1

VDDQ + 0.3

0.95

V

1, 2

V

–0.3

V

Reference voltage

VREF

0.68

V

Notes 1. During normal operation, VDDQ must not exceed VDD.

2. Power-up: V^IH≤ VDDQ + 0.3 V and VDD ≤ 1.7 V and VDDQ ≤ 1.4 V for t ≤ 200 ms

Recommended AC Operating Conditions (TA = 0 to 70 °C)

Parameter

High level input voltage

Low level input voltage

Symbol

VIH (AC)

VIL (AC)

Conditions

MIN.

VREF + 0.2

–

TYP.

MAX.

–

Unit

V

Note

1

VREF – 0.2

V

Note 1. Overshoot: VIH (AC) ≤ VDD + 0.7 V for t ≤ TKHKH/2

Undershoot: V^{IL (AC)}≥ – 0.5 V for t ≤ TKHKH/2

Control input signals may not have pulse widths less than TKHKL (MIN.) or operate at cycle rates less than

TKHKH (MIN.).

Preliminary Data Sheet M16781EJ1V0DS

13

µPD44324084, 44324094, 44324184, 44324364

DC Characteristics (TA = 0 to 70°C, VDD = 1.8 ± 0.1 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit Note

x8, x9 x18 x36

Input leakage current

I/O leakage current

Operating supply current

(Read Write cycle)

ILI

–2

–

+2

µA

ILO

IDD

VIN ≤ VIL or VIN ≥ VIH, –E33

750 1,050 1,200 mA

650 900 1,000

550 750 850

II/O = 0 mA

–E40

–E50

Cycle = MAX.

Standby supply current

(NOP)

ISB1

VIN ≤ VIL or VIN ≥ VIH, –E33

550

500

mA

II/O = 0 mA

–E40

–E50

Cycle = MAX.

400

High level output voltage

Low level output voltage

VOH(Low) |IOH| ≤ 0.1 mA

VOH Note1

VOL(Low) IOL ≤ 0.1 mA

VOL Note2

VDDQ – 0.2

VDDQ/2–0.12

VSS

–

VDDQ

V

3, 4

VDDQ/2+0.12

0.2

VDDQ/2–0.12

VDDQ/2+0.12

Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

2. Outputs are impedance-controlled. I^OL= (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.

3. AC load current is higher than the shown DC values.

4. HSTL outputs meet JEDEC HSTL Class I and Class II standards.

Capacitance (TA = 25 °C, f = 1MHz)

Parameter

Input capacitance

Symbol

CIN

Test conditions

VIN = 0 V

MIN.

TYP.

MAX.

Unit

pF

4

6

5

7

6

Input / Output capacitance

Clock Input capacitance

CI/O

VI/O = 0 V

Vclk = 0 V

pF

Cclk

pF

Remark These parameters are periodically sampled and not 100% tested.

Preliminary Data Sheet M16781EJ1V0DS

14

µPD44324084, 44324094, 44324184, 44324364

AC Characteristics (TA = 0 to 70 °C, VDD = 1.8 ± 0.1 V)

AC Test Conditions

Input waveform (Rise / Fall time ≤ 0.3 ns)

1.25 V

0.75 V

0.25 V

0.75 V

Test Points

Output waveform

V

DDQ / 2

Test Points

VDDQ / 2

Output load condition

Figure 1. External load at test

VDDQ / 2

0.75 V

50 Ω

V

REF

ZO = 50 Ω

SRAM

250 Ω

ZQ

Preliminary Data Sheet M16781EJ1V0DS

15

µPD44324084, 44324094, 44324184, 44324364

Read and Write Cycle

-E33

-E40

-E50

Parameter

Symbol

Unit Note

(300 MHz)

(250 MHz)

(200 MHz)

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Clock

Average Clock cycle time (K, /K, C, /C) TKHKH

ns

1

2

3.3

–

8.4

0.2

–

4.0

–

8.4

0.2

–

5.0

–

8.4

0.2

–

2.3

2.8

3.55

–

Clock phase jitter (K, /K, C, /C)

Clock HIGH time (K, /K, C, /C)

Clock LOW time (K, /K, C, /C)

Clock to /clock (K→/K., C→/C.)

Clock to /clock (/K→K., /C→C.)

Clock to data clock 250 to 300 MHz

TKC var

TKHKL

TKLKH

TKH /KH

T /KHKH

TKHCH

1.32

1.49

0

1.6

1.8

–

0

2.0

2.2

–

0

–

1.45

1.8

2.3

2.8

3.55

–

(K→C., /K→/C.)

200 to 250 MHz

167 to 200 MHz

133 to 167 MHz

< 133 MHz

1.8

2.3

2.8

3.55

–

DLL lock time (K, C)

K static to DLL reset

TKC lock

TKC reset

Cycle

ns

3

1,024

30

1,024

30

1,024

30

–

Output Times

C, /C HIGH to output valid

C, /C HIGH to output hold

C, /C HIGH to echo clock valid

C, /C HIGH to echo clock hold

CQ, /CQ HIGH to output valid

CQ, /CQ HIGH to output hold

C HIGH to output High-Z

TCHQV

TCHQX

ns

–

– 0.45

–

– 0.45

–

– 0.27

–

– 0.45

0.45

–

0.45

–

0.27

–

0.45

–

– 0.45

–

– 0.45

–

– 0.3

–

– 0.45

0.45

–

0.45

–

0.3

–

0.45

–

– 0.45

–

– 0.45

–

– 0.35

–

– 0.45

0.45

–

0.45

–

0.35

–

0.45

–

TCHCQV

TCHCQX

TCQHQV

TCQHQX

TCHQZ

4

C HIGH to output Low-Z

TCHQX1

Setup Times

Address valid to K rising edge

Synchronous load input (/LD),

read write input (R, /W) valid to

K rising edge

TAVKH

TIVKH

ns

5

0.4

–

0.5

–

0.6

–

Data inputs and write data select

inputs (/BWx, /NWx) valid to

K, /K rising edge

TDVKH

ns

5

0.3

–

0.35

–

0.4

–

Hold Times

K rising edge to address hold

K rising edge to

TKHAX

TKHIX

ns

5

0.4

–

0.5

–

0.6

–

synchronous load input (/LD),

read write input (R, /W) hold

K, /K rising edge to data inputs and

write data select inputs (/BWx, /NWx)

hold

TKHDX

ns

5

0.3

–

0.35

–

0.4

–

Preliminary Data Sheet M16781EJ1V0DS

16

µPD44324084, 44324094, 44324184, 44324364

Notes 1. The device will operate at clock frequencies slower than TKHKH(MAX.).

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.

3. V^DDslew rate must be less than 0.1 V DC per 50 ns for DLL lock retention.

DLL lock time begins once V^DDand input clock are stable.

It is recommended that the device is kept inactive during these cycles.

4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

5. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions

unless otherwise noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, /C are tied HIGH, K, /K become the references for C, /C timing parameters.

5. V^DDQ is 1.5 V DC.

Preliminary Data Sheet M16781EJ1V0DS

17

µPD44324084, 44324094, 44324184, 44324364

Read and Write Timing

NOP

READ

NOP

WRITE

READ

(burst of 4)

1

2

3

4

5

6

7

8

9

10

11

12

13

TKHKH

K

TKHKL TKLKH

TKLKH

TKH/KH

T/KHKH

/K

/LD

TIVKH

TKHIX

R, /W

TAVKH

TKHAX

Address

DQ

A2

A1

A3

A4

A0

TKHDX

TDVKH

D21

D22

D23

D24

D31 D32

D33

D34

Q41

Q01 Q02 Q03

TCHQX

Q04

Q11

Q12

Q13

Q14

Qx2

TCQHQX

TCHQX

TCQHQV

TCHQX1

TCHQV

TKHCH

TCHQV

TCHQZ

CQ

TCHCQX

TCHCQV

/CQ

C

TCHCQX

TCHCQV

TKHKL TKLKH TKHKH TKH/KH T/KHKH

/C

Remarks 1. Q01 refers to output from address A0.

Q02 refers to output from the next internal burst address following A0, etc.

2. Outputs are disable (high impedance) one clock cycle after a NOP.

3. The second NOP cycle is not necessary for correct device operation;

however, at high clock frequencies it may be required to prevent bus contention.

Preliminary Data Sheet M16781EJ1V0DS

18

µPD44324084, 44324094, 44324184, 44324364

JTAG Specification

These products support a limited set of JTAG functions as in IEEE standard 1149.1.

Test Access Port (TAP) Pins

Pin name

TCK

Pin assignments

2R

Description

Test Clock Input. All input are captured on the rising edge of TCK and all outputs

propagate from the falling edge of TCK.

Test Mode Select. This is the command input for the TAP controller state machine.

TMS

TDI

10R

11R

Test Data Input. This is the input side of the serial registers placed between TDI and

TDO. The register placed between TDI and TDO is determined by the state of the TAP

controller state machine and the instruction that is currently loaded in the TAP instruction.

TDO

1R

Test Data Output. Output changes in response to the falling edge of TCK. This is the

output side of the serial registers placed between TDI and TDO.

Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high

for five rising edges of TCK. The TAP controller state is also reset on the SRAM POWER-UP.

JTAG DC Characteristics (T^A= 0 to 70°C, VDD = 1.8 ± 0.1 V, unless otherwise noted)

Parameter

Symbol

ILI

Conditions

MIN.

–5.0

TYP.

MAX.

+5.0

Unit

µA

Note

JTAG Input leakage current

JTAG I/O leakage current

0 V ≤ VIN ≤ VDD

–

ILO

0 V ≤ VIN ≤ VDDQ,

µA

Outputs disabled

JTAG input high voltage

JTAG input low voltage

JTAG output high voltage

VIH

VIL

1.3

–0.3

1.6

1.4

–

VDD+0.3

V

+0.5

–

VOH1

VOH2

VOL1

VOL2

| IOHC | = 100 µA

| IOHT | = 2 mA

IOLC = 100 µA

IOLT = 2 mA

–

JTAG output low voltage

0.2

0.4

–

Preliminary Data Sheet M16781EJ1V0DS

19

µPD44324084, 44324094, 44324184, 44324364

JTAG AC Test Conditions

Input waveform (Rise / Fall time ≤ 1 ns)

1.8 V

0.9 V

0 V

0.9 V

Test Points

Output waveform

0.9 V

Test Points

0.9 V

Output load

Figure 2. External load at test

V

TT = 0.9 V

50 Ω

ZO = 50 Ω

TDO

20 pF

Preliminary Data Sheet M16781EJ1V0DS

20

µPD44324084, 44324094, 44324184, 44324364

JTAG AC Characteristics (TA = 0 to 70 °C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Note

Clock

Clock cycle time

Clock frequency

Clock high time

Clock low time

tTHTH

fTF

100

–

10

–

ns

MHz

ns

tTHTL

tTLTH

40

–

ns

Output time

TCK low to TDO unknown

TCK low to TDO valid

TDI valid to TCK high

TCK high to TDI invalid

tTLOX

tTLOV

tDVTH

tTHDX

0

–

20

–

ns

10

–

Setup time

TMS setup time

Capture setup time

tMVTH

tCS

10

–

ns

Hold time

TMS hold time

Capture hold time

tTHMX

tCH

10

–

ns

JTAG Timing Diagram

tTHTH

TCK

tMVTH

tTHTL

t

TLTH

TMS

TDI

tTHMX

tDVTH

tTHDX

tTLOV

tTLOX

TDO

Preliminary Data Sheet M16781EJ1V0DS

21

µPD44324084, 44324094, 44324184, 44324364

Scan Register Definition (1)

Register name

Description

Instruction register

The instruction register holds the instructions that are executed by the TAP controller when it is

moved into the run-test/idle or the various data register state. The register can be loaded when it is

placed between the TDI and TDO pins. The instruction register is automatically preloaded with the

IDCODE instruction at power-up whenever the controller is placed in test-logic-reset state.

Bypass register

ID register

The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial

test data to be passed through the RAMs TAP to another device in the scan chain with as little delay

as possible.

The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when

the controller is put in capture-DR state with the IDCODE command loaded in the instruction register.

The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR

state.

Boundary register

The boundary register, under the control of the TAP controller, is loaded with the contents of the

RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and

TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to

activate the boundary register.

The Scan Exit Order tables describe which device bump connects to each boundary register

location. The first column defines the bit’s position in the boundary register. The second column is

the name of the input or I/O at the bump and the third column is the bump number.

Scan Register Definition (2)

Register name

Instruction register

Bypass register

ID register

Bit size

Unit

bit

3

1

bit

32

109

bit

Boundary register

bit

ID Register Definition

Part number Organization ID [31:28] vendor revision no.

ID [27:12] part no.

0000 0000 0100 0001

0000 0000 0100 0010

0000 0000 0100 0011

0000 0000 0100 0100

ID [11:1] vendor ID no.

00000010000

ID [0] fix bit

µPD44324084

µPD44324094

µPD44324184

µPD44324364

4M x 8

4M x 9

XXXX

1

00000010000

2M x 18

1M x 36

00000010000

Preliminary Data Sheet M16781EJ1V0DS

22

µPD44324084, 44324094, 44324184, 44324364

SCAN Exit Order

Bit

Signal name

x9 x18 x36

Bump

ID

Bit

Signal name

Bump

ID

Bit

Signal name

x9 x18 x36

NC NC NC NC

Bump

ID

no.

x8

no.

x8

x9 x18 x36

no.

x8

1

2

/C

C

A

6R

6P

6N

7P

7N

7R

8R

8P

9R

37 NC NC NC NC 10D

38 NC NC NC NC 9E

73

2C

74 DQ4 DQ5 DQ11 DQ20 3E

3

39 NC NC DQ7 DQ17 10C

40 NC NC NC DQ16 11D

75

76

77

78

79

80

81

NC NC NC DQ29 2D

4

NC NC NC NC

2E

1E

5

41 NC NC NC NC

42 NC NC NC NC

9C

9D

6

NC NC DQ12 DQ30 2F

NC NC NC DQ21 3F

7

43 DQ3 DQ4 DQ8 DQ8 11B

44 NC NC NC DQ7 11C

8

NC NC NC NC

1G

1F

9

45 NC NC NC NC

9B

10

11

12

13

14

15

16

17

NC DQ0 DQ0 DQ0 11P

NC NC NC DQ9 10P

NC NC NC NC 10N

46 NC NC NC NC 10B

82 DQ5 DQ6 DQ13 DQ22 3G

47

48

49

50

51

CQ

11A

10A

9A

83

84

85

86

87

88

89

90

NC NC NC DQ31 2G

A

VSS

/DLL

1H

1J

2J

NC NC NC NC

9P

A

NC NC NC NC

NC NC DQ1 DQ11 10M

NC NC NC DQ10 11N

NC NC NC NC 9M

8B

A1

A0

7C

6C

8A

NC NC DQ14 DQ23 3K

NC NC NC DQ32 3J

52 NC NC A0

53 /LD

NC NC NC NC

9N

NC NC NC NC

2K

1K

18 DQ0 DQ1 DQ2 DQ2 11L

54 NC NC NC /BW1 7A

55 /NW0 /BW0 /BW0 /BW0 7B

19

20

21

22

23

24

25

NC NC NC DQ1 11M

NC NC NC NC 9L

91 DQ6 DQ7 DQ15 DQ33 2L

56

57

K

6B

6A

92

93

94

95

96

97

98

NC NC NC DQ24 3L

NC NC NC NC 1M

NC NC NC NC 10L

NC NC DQ3 DQ3 11K

NC NC NC DQ12 10K

/K

58 NC NC NC /BW3 5B

59 /NW1 NC /BW1 /BW2 5A

NC NC NC NC

1L

NC NC DQ16 DQ25 3N

NC NC NC DQ34 3M

NC NC NC NC

9J

60

61

62

63

64

65

R, /W

A

4A

5C

4B

3A

2A

1A

9K

NC NC NC NC

1N

26 DQ1 DQ2 DQ4 DQ13 10J

A

NC NC NC NC 2M

27

28

29

30

31

32

33

34

NC NC NC DQ4 11J

ZQ 11H

A

99 DQ7 DQ8 DQ17 DQ26 3P

100 NC NC NC DQ35 2N

VSS

/CQ

NC NC NC NC 10G

NC NC NC NC 9G

NC NC DQ5 DQ5 11F

NC NC NC DQ14 11G

101 NC NC NC NC

102 NC NC NC NC

2P

1P

66 NC NC DQ9 DQ27 2B

67 NC NC NC DQ18 3B

103

104

105

106

107

108

109

A

–

3R

68 NC NC NC NC

69 NC NC NC NC

1C

1B

4R

NC NC NC NC

9F

4P

NC NC NC NC 10F

70 NC NC DQ10DQ19 3D

71 NC NC NC DQ28 3C

5P

35 DQ2 DQ3 DQ6 DQ6 11E

36 NC NC NC DQ15 10E

5N

72 NC NC NC NC

1D

5R

Internal

Preliminary Data Sheet M16781EJ1V0DS

23

µPD44324084, 44324094, 44324184, 44324364

JTAG Instructions

Instructions

EXTEST

Description

The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-

scan register cells at output pins are used to apply test vectors, while those at input pins capture test

results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the

boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST,

the output drive is turned on and the PRELOAD data is driven onto the output pins.

IDCODE

BYPASS

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in

capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The

IDCODE instruction is the default instruction loaded in at power up and any time the controller is

placed in the test-logic-reset state.

The BYPASS instruction is loaded in the instruction register when the bypass register is placed

between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This

allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE /

PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-

DR state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the

RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to

capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state).

Although allowing the TAP to sample metastable input will not harm the device, repeatable results

cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input

data capture setup plus hold time (t^CSplus tCH). The RAMs clock inputs need not be paused for any

other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving

the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM DQ pins are forced to an

inactive drive state (high impedance) and the boundary register is connected between TDI and TDO

when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

0

IR1

0

IR0

0

Instruction

EXTEST

Note

1

0

1

IDCODE

0

1

0

SAMPLE-Z

0

1

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

1

0

1

0

1

0

1

Note 1. TRISTATE all DQ pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

Preliminary Data Sheet M16781EJ1V0DS

24

µPD44324084, 44324094, 44324184, 44324364

TAP Controller State Diagram

1

0

Test-Logic-Reset

0

1

Run-Test / Idle

Select-DR-Scan

0

Select-IR-Scan

0

1

Capture-DR

0

Capture-IR

0

Shift-DR

1

Shift-IR

1

Exit1-DR

0

Exit1-IR

0

Pause-DR

1

Pause-IR

1

0

Exit2-DR

1

Exit2-IR

1

Update-DR

Update-IR

1

0

1

0

Disabling the Test Access Port

It is possible to use this device without utilizing the TAP. To disable the TAP Controller without interfering with normal

operation of the device, TCK must be tied to VSS to preclude mid level inputs.

TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and

may be left unconnected. But they may also be tied to VDD through a 1 kΩ resistor.

TDO should be left unconnected.

Preliminary Data Sheet M16781EJ1V0DS

25

µPD44324084, 44324094, 44324184, 44324364

Package Drawing

165-PIN PLASTIC FBGA (13x15)

E

w S B

ZD

ZE

B

11

10

9

8

7

A

6

5

D

4

3

2

1

R P N M L K J H G F E D C B A

w S A

INDEX MARK

y1 S

A2

h

A

S

ITEM MILLIMETERS

A1

e

y

D

E

13.00

15.00

1.50

0.50

1.00

0.60

1.40

0.40

1.00

0.50

0.08

0.15

0.20

S

ZD

ZE

e

φ M

x

φ

b

S A B

h

A

A1

A2

b

y

x

w

y1

This package drawing is a preliminary version. It may be changed in the future.

Preliminary Data Sheet M16781EJ1V0DS

28

µPD44324084, 44324094, 44324184, 44324364

Recommended Soldering Condition

Please consult with our sales offices for soldering conditions of these products.

Types of Surface Mount Devices

µPD44324084F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

µPD44324094F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

µPD44324184F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

µPD44324364F5-EQ2: 165-pin PLASTIC FBGA (13 x 15)

Preliminary Data Sheet M16781EJ1V0DS

29

µPD44324084, 44324094, 44324184, 44324364

Revision History

Edition/

Page

Type of

revision

Location

Description

Date

This

edition

(Previous edition → This edition)

1st edition/

Oct. 2004

Modification



Preliminary Product Information

Throughout Throughout

→ Preliminary Data sheet

F5-EQ1 → F5-EQ2

Package Code

Deletion

Addition



−E60 (167MHz)

p.2

Ordering Information

"Note Under development" has been added to

−E33.

pp.3-6

p.9

pp.3-6



Pin Configurations

Remark 2 has been added

Power-on sequence has been added

Power-on Sequence

p.14

p.13

Modification DC Characteristics IDD (MAX.)

MAX.

Unit

x8, x9 x18 x36

−E33 620 650 730

−E40 540 560 620

−E50 450 470 520

x8, x9 x18 x36

mA

−E33 750 1,050 1,200

−E40 650 900 1,000

−E50 550 750 850

DC Characteristics ISB1 (MAX.)

MAX.

Unit

x8, x9 x18 x36

mA

−E33

−E40

−E50

290

250

210

−E33

−E40

−E50

550

500

400

Preliminary Data Sheet M16781EJ1V0DS

30

µPD44324084, 44324094, 44324184, 44324364

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

1

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

Preliminary Data Sheet M16781EJ1V0DS

31

µPD44324084, 44324094, 44324184, 44324364

•

The information in this document is current as of October, 2004. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1


型号：	UPD44324184F5-E50-EQ2
厂家：	NEC
描述：	36M-BIT DDRII SRAM 4-WORD BURST OPERAT 36M位DDRII SRAM 4字突发OPERAT 存储内存集成电路静态存储器双倍数据速率
文件：	总32页 (文件大小：344K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD44324184F5-E50-EQ2 [NEC]

相关型号：

UPD44324184F5-E50-EQ2-A

UPD44324184F5-E50-EQ2-A

UPD44324184F5-E50Y-EQ2

UPD44324184F5-E50Y-EQ2-A

UPD44324185BF5-E33-FQ1

UPD44324185BF5-E33-FQ1-A

UPD44324185BF5-E33Y-FQ1-A

UPD44324185BF5-E35Y-FQ1

UPD44324185BF5-E40Y-FQ1-A

UPD44324185BF5-E50-FQ1

UPD44324185BF5-E50-FQ1-A

UPD44324185BF5-E50Y-FQ1