UPD23C256112AGY-XXX-MKH-A [NEC]
MASK ROM, 32MX8, MOS, PDSO48, 12 X 18 MM, LEAD FREE, PLASTIC, REVERSE, TSOP1-48;
| 型号： | UPD23C256112AGY-XXX-MKH-A |
| 厂家： | 
NEC |
| 描述： | MASK ROM, 32MX8, MOS, PDSO48, 12 X 18 MM, LEAD FREE, PLASTIC, REVERSE, TSOP1-48 有原始数据的样本ROM ISM频段 光电二极管 内存集成电路 |
| 文件： | 总32页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD23C256112A
NAND INTERFACE
256M-BIT MASK-PROGRAMMABLE ROM
Description
The μPD23C256112A is a 256 Mbit NAND interface programmable mask read-only memory that operates with a
single power supply. The memory organization consists of (512 + 16 (Redundancy)) bytes x 32 pages x 2,048 blocks.
The μPD23C256112A is a serial type mask ROM in which addresses and commands are input and data output serially
via the I/O pins.
The μPD23C256112A is packed in 48-pin PLASTIC TSOP(I).
Features
• Word organization
(33,554,432 + 1,048,576Note) words by 8 bits
• Page size
(512 + 16Note) by 8 bits
• Block size
(16,384 + 512Note) by 8 bits
Note Underlined parts are redundancy.
Caution Redundancy is not programmable parts and is fixed to all FFH.
• Operation mode
READ mode (1), READ mode (2), READ mode (3), RESET, STATUS READ, ID READ
• Operating supply voltage : VCC = 3.3 ± 0.3 V
• Access Time
Memory cell array to starting address
Read cycle time
: 7 μs (MAX.)
: 50 ns (MIN.)
: 35 ns (MAX.)
/RE access time
• Operating supply current
During read
: 30 mA (MAX.) (50 ns cycle operation)
During standby (CMOS) : 100 μA (MAX.)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15902EJ3V0DS00 (3rd edition)
Date Published February 2006 NS CP (K)
Printed in Japan
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μPD23C256112A
Ordering Information
Part Number
Package
μPD23C256112AGY-xxx-MJH
μPD23C256112AGY-xxx-MKH
μPD23C256112AGY-xxx-MJH-A
μPD23C256112AGY-xxx-MKH-A
48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
<R>
<R>
Remarks 1. xxx : ROM code suffix No.
2. Products with -A at the end of the part number are lead-free products.
<R>
Data Sheet M15902EJ3V0DS
2
μPD23C256112A
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
[ μPD23C256112AGY-xxx-MJH ]
[ μPD23C256112AGY-xxx-MJH-A ]
<R>
Marking Side
NC
NC
NC
IC
IC
GND
R, /B
/RE
/CE
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
NC
V
CC
VCC
V
SS
V
SS
NC
NC
CLE
ALE
/WE
IC
IC
IC
NC
NC
NC
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
I/O0 to I/O7
: Address Inputs / Command Inputs / Data Outputs
: Command Latch Enable Input
: Address Latch Enable Input
: Write Enable Input
: Read Enable Input
: Chip Enable Input
CLE
ALE
/WE
/RE
/CE
R, /BNote1
: READY, /BUSY Output
: Supply voltage
VCC
Vss
: Ground
NC Note2
IC Note3
GND
: No connection
: Internal connection
: GND
Notes 1. This pin is an open-drain output pin. Therefore, a pull-up resistor is required when using this pin.
2. Some signals can be applied because this pin is not connected to the inside of the chip.
3. Leave this pin unconnected or connected to VSS.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15902EJ3V0DS
3
μPD23C256112A
48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
[ μPD23C256112AGY-xxx-MKH ]
[ μPD23C256112AGY-xxx-MKH-A ]
<R>
Marking Side
NC
NC
NC
NC
NC
NC
IC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
I/O7
I/O6
I/O5
I/O4
NC
IC
GND
R, /B
/RE
/CE
NC
NC
NC
NC
V
CC
V
V
CC
V
SS
SS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
CLE
ALE
/WE
IC
IC
IC
NC
NC
NC
NC
NC
NC
I/O0 to I/O7
CLE
: Address Inputs / Command Inputs / Data Outputs
: Command Latch Enable Input
: Address Latch Enable Input
: Write Enable Input
: Read Enable Input
: Chip Enable Input
ALE
/WE
/RE
/CE
R, /BNote1
: READY, /BUSY Output
: Supply voltage
VCC
Vss
: Ground
NC Note2
IC Note3
GND
: No connection
: Internal connection
: GND
Notes 1. This pin is an open-drain output pin. Therefore, a pull-up resistor is required when using this pin.
2. Some signals can be applied because this pin is not connected to the inside of the chip.
3. Leave this pin unconnected or connected to VSS.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15902EJ3V0DS
4
μPD23C256112A
Input / Output Pin Functions
Pin name
I/O0 to I/O7
Input / Output
Function
Input, Output I/O port for address input, command input, and data output. I/O pins.
(Address Inputs / Command
Inputs / Data Outputs)
Input pin for signal for controlling loading of commands to command register in
CLE
Input
device. By making this signal high level at the rising edge or falling edge of the /WE
(Command latch Enable
Input)
signal, the data of the I/O0 to I/O7 pins is loaded to the command register as
commands.
ALE
Input
Input pin for signal for controlling loading of address data to the address register in
the device. By making this signal high level at the rising edge or falling edge of the
/WE signal, the data of the I/O0 to I/O7 pins is loaded as address.
(Address latch Enable
Input)
/WE
Input
Input
Input pin for signal for loading the data from the I/O0 to I/O7 pins inside the device.
(Write Enable Input)
/RE
Input pin for signal for serially outputting data. The output data of I/O0 to I/O7 is
determined after tREA from the falling edge of the /RE signal, and the internal address
counter is incremented by +1 at the rising edge of the /RE signal.
Input pin for device selection signal. During read, the standby mode is entered by
making this signal high level.
(Read Enable Input)
/CE
Input
(Chip Enable Input)
R, /B
Output
Output pin for signal that notifies the internal operating status of the device to
external. This is an open-drain output signal. During read, Busy is output during
operation (R, /B = low level), and upon completion, Ready (R, /B = high level) is
automatically output.
(READY, /BUSY Output)
Data Sheet M15902EJ3V0DS
5
μPD23C256112A
Block Diagram
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
Dara Register Circuit
Sense Amplifier
Y-Selector
Status Register
ID Register
Address
Register
Command
Register
I/O6
I/O7
Memory Cell Matrix
/CE
CLE
ALE
/WE
/RE
READ Contorol Circuit
READY/BUSY
Control Circuit
Vcc
Vss
R, /B (Open-drain)
Data Sheet M15902EJ3V0DS
6
μPD23C256112A
Memory Area
1 Page = 528 Bytes
0
•
•
•
255256
•
•
•
511
• 527
0
1
2
•
1 Block
= 32 Pages
•
•
30
31
•
•
•
•
•
•
•
•
•
(A)
(B)
(C)
2,048 Blocks
= 65,536 Pages
65,533
65,534
65,535
512 Bytes
(Main memory)
16 Bytes
(Redundancy)
• The start address (SA) during read operation is specified divided into three areas using three types of read
commands.
In read mode (1), start address (SA) is set in area (A).
In read mode (2), start address (SA) is set in area (B).
In read mode (3), start address (SA) is set in area (C).
One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy).
One block consists of 32 pages.
Caution The data of area (C) is redundancy. Redundancy is not programmable parts and is fixed to all FFH.
Data Sheet M15902EJ3V0DS
7
μPD23C256112A
Operation Modes
Command input, address input, and serial read are all performed from I/O pins, and the respective statuses are
controlled by the CLE, ALE, /WE, /RE, and /CE signals.
Command
input cycle
Address input cycle
Serial read cycle
CLE
/CE
/WE
ALE
/RE
I/O0 to I/O7
R, /B
High-Z
High-Z
Busy
High-Z
Operation mode
Mode
CLE
H
ALE
L
/CE
L
/WE
H
/RE
H
Command input cycle
Address input cycle
Serial read cycle
L
H
L
H
L
L
L
Operation mode during serial read
Mode
Data output
CLE
ALE
L
/CE
L
/WE
H
/RE
L
I/O0 to I/O7
Data output
High-Z
L
L
L
Output High-Z
Standby
L
L
H
H
L
H
H
×
High-Z
Remark × : VIH or VIL
Data Sheet M15902EJ3V0DS
8
μPD23C256112A
Operation Commands
The following six operation settings are possible by inputting commands from I/O pins.
Command receivable
Command
HEX
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
during Busy
Read mode(1)
Read mode(2)
Read mode(3)Note1
Reset Note2
00H
01H
50H
FFH
70H
90H
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
H
H
H
L
L
H
H
H
H
H
L
H
H
L
H
L
Status read
ID read Note3
H
L
Notes 1. The data output in read mode (3) is all FFH.
2. The only command that can be executed when the device is Busy is the reset command. Do not set any
of the other commands while the device is Busy.
3. For ID read, input “00H” during the first address cycle after setting a command.
I/O Pin Correspondence Table during Address Input Cycle (Address Setting)
(1) When 00H or 01H command is set [Read mode (1), Read mode (2)]
Command
1st address cycle
2nd address cycle
3rd address cycle
I/O7
A7
I/O6
A6
I/O5
A5
I/O4
A4
I/O3
A3
I/O2
A2
I/O1
A1
I/O0
A0
A16
A24
A15
A23
A14
A22
A13
A21
A12
A20
A11
A19
A10
A18
A9
A17
(2) When 50H command is set [Read mode (3)]
Command
1st address cycle
2nd address cycle
3rd address cycle
I/O7
×
I/O6
×
I/O5
×
I/O4
×
I/O3
A3
I/O2
A2
I/O1
A1
I/O0
A0
A16
A24
A15
A23
A14
A22
A13
A21
A12
A20
A11
A19
A10
A18
A9
A17
Remarks 1. A0 to A24 are internal addresses.
2. Internal address A8 is set internally with command 00H or 01H.
3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address
cycle are VIH or VIL.
Data Sheet M15902EJ3V0DS
9
μPD23C256112A
Usage Cautions
(1) Rated operation
Operation using timing other than shown in the timing charts is not guaranteed.
(2) Commands that can be input
The only commands that can be input are 00H, 01H, 50H, 70H, 90H, and FFH. Do not input any other commands.
If other commands are input, the subsequent operation is not guaranteed.
(3) Command limitations during Busy period
Do not input commands other than the reset command (FFH) during the Busy period. If a command is input
during the Busy period, the subsequent operation is not guaranteed.
(4) Cautions regarding /RE clock
• Following the last /RE clock, do not input the /RE clock until the R, /B pin changes from Busy to Ready.
• Do not input the /RE clock other than during data output.
(5) Cautions upon power application
Since the state of the device is undetermined upon power on, input high level to the /CE pin and execute the reset
command following power on.
(6) Cautions during read mode
• Perform address input immediately following command input. If address input is done without performing
command input first, the correct data cannot be output because the operation mode is undetermined.
• To execute the read mode after the read mode has been stopped with the reset command (FFH) and /CE, input
again a command and address.
(7) Busy output following access of last address in page in read mode
After the access to the last address in a page, if the delay (tRHCH) from /RE to /CE is 30 ns or less, the Ready
status is maintained and Busy is not output by keeping /CE high level for a set period (tCEH).
t
CEH
/CE
/RE
t
RHCH
526
527
R, /B
Data Sheet M15902EJ3V0DS
10
μPD23C256112A
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VI
Condition
Rating
–0.5 to +4.6
Unit
V
Input voltage
–0.3 to VCC+0.3
–0.3 to VCC+0.3 ( ≤ 4.6)
0 to 70
V
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
TA
V
°C
°C
Tstg
–65 to +150
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25°C)
Parameter
Input capacitance
Output capacitance
Symbol
CI
Test condition
MIN.
TYP.
MAX.
10
Unit
pF
f = 1 MHz
CO
10
pF
DC Characteristics (TA = 0 to 70°C, VCC = 3.3 ± 0.3 V)
Parameter
High level input voltage
Low level input voltage
High level output voltage
Low level output voltage
Input leakage current
Symbol
VIH
Test conditions
MIN.
2.0
TYP.
MAX.
VCC + 0.3
+0.8
Unit
V
VIL
–0.3
2.4
V
VOH
VOL
ILI
IOH = –400 μA
V
IOL = 2.1 mA
0.4
±10
±10
V
VI = 0 V to VCC
VO = 0 V to VCC
μA
μA
Output leakage current
Power supply current in read
ILO
ICCO1
ICCO3
/CE = VIL, IOUT = 0 mA, tCYCLE = 50 ns
tCYCLE = 50 ns
30
30
mA
mA
Power supply current
in command input
Power supply current
in address input
ICCO5
tCYCLE = 50 ns
30
mA
Standby current (TTL)
Standby current (CMOS)
(R, /B) pin output current
ICCS1
ICCS2
/CE = VIH
1
mA
μA
/CE = VCC – 0.2 V
VOL = 0.4 V
100
IOL(R, /B)
8
mA
Data Sheet M15902EJ3V0DS
11
μPD23C256112A
AC Characteristics (TA = 0 to 70°C, VCC = 3.3 ± 0.3 V)
Parameter
CLE setup time
Symbol
tCLS
tCLH
tCS
MIN
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
μs
μs
CLE hold time
10
0
/CE setup time
/CE hold time
tCH
10
25
0
Write pulse width
tWP
ALE setup time
tALS
tALH
tDS
ALE hold time
10
20
10
50
15
20
35
50
Data setup time
Data hold time
tDH
Write cycle time
tWC
tWH
tRR
/WE high hold time
Ready to /RE falling edge
Read pulse width
tRP
Read cycle time
tRC
/RE access time (serial data access)
/CE high hold time for last address in serial read cycle
/RE access time (ID read )
/RE high to output High-Z
/CE high to output High-Z
/RE high hold time
tREA
tCEH
tREAID
tRHZ
tCHZ
tREH
tIR
35
100
10
35
30
20
15
0
Output High-Z to /RE falling edge
/RE access time (status read)
/CE access time (status read)
/WE high to /CE low
tRSTO
tCSTO
tWHC
tWHR
tAR1
tCR
35
45
30
30
/WE high to /RE low
ALE low to /RE low (ID read)
/CE low to /RE low (ID read)
Memory cell array to starting address
/WE high to Busy
100
100
tR
7
tWB
200
ALE low to /RE low (read cycle)
/RE last clock rising edge to Busy (in sequential read)
/CE high to Ready (when interrupted by /CE in read mode)
Device reset time
tAR2
tRB
50
200
1
Note
tCRY
tRST
6
Note tCRY (time from /CE high to Ready) depends on the pull-up resister of the R, /B output pin.
Data Sheet M15902EJ3V0DS
12
μPD23C256112A
AC Test Conditions
Input waveform (Rise / Fall Time ≤ 5 ns)
Test points
1.5 V
1.5 V
Output waveform
Test points
1.5 V
1.5 V
Output load
1 TTL + 100 pF
Data Sheet M15902EJ3V0DS
13
Read Cycle Timing Chart (1)
(In case of read mode (1))
CLE
tCLS
t
CLH
/CE
/WE
ALE
/RE
t
CEH
t
CS
t
CH
t
CS
t
WC
t
R
t
ALH
t
ALS
t
WP
t
WH
t
ALH
t
CRY
t
AR2
t
CHZ
t
RR
t
RC
t
RC
t
RP
t
REH
t
WB
t
RHZ
t
RHZ
t
DS
t
DH
t
DS
t
DS
t
DS
High-Z
High-Z
00H
A9 to A16
D
OUT
D
OUT
D
OUT
I/O0 to I/O7
A0 to A7
A17 to A24
N
N+1
527
t
REA
t
DH
t
DH
t
DH
t
RB
R, /B
Output page M data
Access
page M
Remarks 1. Start address (SA) specification when read is performed with command 00H. N: 0 to 255
2. Then time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R,/B output pin.
Read Cycle Timing Chart (2)
(In case of read mode (2))
CLE
tCLS
t
CLH
/CE
/WE
ALE
/RE
t
CEH
t
CS
t
CH
t
CS
t
WC
t
R
t
ALH
t
ALS
t
WP
t
WH
t
ALH
t
CRY
t
AR2
t
CHZ
t
RR
t
RC
t
RC
t
RP
t
REH
t
WB
t
RHZ
t
RHZ
t
DS
t
DH
t
DS
t
DS
t
DS
High-Z
High-Z
I/O0 to I/O7
01H
D
OUT
D
OUT
D
OUT
A0 to A7
A9 to A16
A17 to A24
256+N
256+N+1
527
t
REA
t
DH
t
DH
t
DH
t
RB
R, /B
Output page M data
Access
page M
Remarks 1. Start address (SA) specification when read is performed with command 01H. N: 0 to 255
2. Then time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R,/B output pin.
Read Cycle Timing Chart (3)
(In case of read mode (3))
CLE
t
CLS
t
CLH
/CE
/WE
ALE
/RE
t
CEH
tCS
t
CH
t
CS
t
WC
tR
t
ALH
t
ALS
tWP
tWH
tALH
tCRY
t
AR2
t
CHZ
tRR
t
RC
t
RC
t
RP
t
REH
tWB
t
RHZ
t
RHZ
tDS
tDH
t
DS
tDS
tDS
High-Z
High-Z
I/O0 to I/O7
50H
D
OUT
DOUT
A0 to A3
A9 to A16
A17 to A24
DOUT
512+N
512+N+1
527
tREA
tDH
tDH
tDH
tRB
R, /B
Output page M data
Access
page M
Remarks 1. Start address (SA) specification when read is performed with command 50H. N: 0 to 15
2. The start address of area C (redundancy data) is specified with A0 to A3 during the 1st address cycle. At this time, A4 to A7 are Don't Care.
3. The time (tCRY) from /CE high to Ready is cancelled depends on the pull-up register of the R, /B output pin.
4. The data that is output is FFH.
Read Cycle Timing Chart (4)
(When /CE is made high level in the read mode)
CLE
tCLS
tCLH
/CE
/WE
ALE
/RE
tR
tWC
t
tCS
t
CH
CS
t
ALH
t
ALH
tALS
tWP
tWH
t
AR2
t
CHZ
t
RR
tRC
t
RC
t
RHZ
tRP
tREH
tWB
t
RHZ
tDS
tDS
tDS
t
DS
tDH
High-Z
High-Z
Address
input
Address
input
Address
input
Command
input
DOUT
DOUT
DOUT
I/O0 to I/O7
N
N+1
N
+2
tREA
tDH
tDH
tDH
R, /B
Access
page M
If /CE is made high level during the read cycle, the read operation until that time is cancelled.
Therefore, to perform read again, execute a new command and new address input.
Remark
μPD23C256112A
Sequential Read
In read modes (1), (2), and (3), when a command (00H, 01H, 50H) is input and an address specified, if it is in the
block that includes the address that was specified first, the address is automatically incremented and the read
operation is continuously performed until the last address in the same block, by inputting the /RE clock. At this time, a
Busy period (tR) occurs after the last address is accessed in a page.
CommandNote
Command
input
Output of in last page
in block
input
00H
01H
50H
Address
input
Page M
data output
Page M+1
data output
Address
input
Data output
00H
01H
50H
Note
t
CRY
t
R
t
R
t
R
t
R
t
R
R, /B
Busy
Busy
Busy
Busy
Busy
Busy
In same block
(Maximum of 32 pages)
Note To perform read again after reading the 527th byte of data of the last page of block, stop the read operation once,
and then restart the read operation by inputting again the read command and an address.
Relationship Between Command and Start Address (SA) during Sequential Read
(A)
(B)
(C)
(A)
(B)
(C)
(A)
(B)
SA
(C)
0
256
512 527
0
256
512 527
0
256
512 527
SA
SA
1 block
= 32 pages
Sequential read mode (2)
(When "01H" command is input)
Sequential read mode (3)Note
(When "50H" command is input)
Sequential read mode (1)
(When "00H" command is input)
Note When the "50H" command is set, only the (C) area (redundancy data part) is continuously read.
• When the “00H” command is set, the start address (SA) is set to area (A).
• When the “01H” command is set, the start address (SA) is set to area (B).
• When the “50H” command is set, the start address (SA) is set to area (C).
Data Sheet M15902EJ3V0DS
18
Sequential Read Cycle Timing Chart (1)
(In case of read mode (1))
CLE
t
CLS
tCLH
tCH
/CE
/WE
ALE
/RE
tCS
tCS
tWC
tR
tALH
tALS
tWP
tWH
tALH
tAR2
tRR
tRC
tRC
tR
tRR
tRP
tREH
tWB
tRHZ
tDS
tDH
tDS
tDS
tDS
High-Z
High-Z
High-Z
I/O0 to I/O7
00H
DOUT
DOUT
DOUT
A0 to A7
A9 to A16
A17 to A24
tDH
DOUT
DOUT
N
tREA
N+1
527
0
1
tDH
tDH
tRB
R, /B
Access
page M+1
Access
page M
Output page
M+1 data
Output page M data
Remark Start address (SA) specification when read is performed with command 00H. N: 0 to 255
Sequential Read Cycle Timing Chart (2)
(In case of read mode (2))
CLE
t
CLS
t
CLH
/CE
/WE
ALE
/RE
tCS
t
CH
t
CS
t
WC
t
R
t
ALH
t
ALS
tWP
t
WH
t
ALH
tAR2
t
RR
t
RC
t
RC
t
R
t
RR
tRP
tREH
t
WB
t
RHZ
t
DS
t
DH
t
DS
t
DS
t
DS
High-Z
High-Z
High-Z
I/O0 to I/O7
01H
D
OUT
D
OUT
D
OUT
A0 to A7
A9 to A16
A17 to A24
D
OUT
D
OUT
256+N
256+N+1
527
0
1
t
REA
t
DH
tDH
tDH
t
RB
R, /B
Access
page M+1
Access
page M
Output page
M+1 data
Output page M data
Remark Start address (SA) specification when read is performed with command 01H. N: 0 to 255
Sequential Read Cycle Timing Chart (3)
(In case of read mode (3))
CLE
tCLS
t
CLH
/CE
/WE
ALE
/RE
t
CS
t
CH
t
CS
t
WC
t
R
t
ALH
t
ALS
t
WP
t
WH
t
ALH
t
AR2
t
RR
t
RC
t
RC
t
R
t
RR
t
RP
t
REH
t
WB
t
RHZ
t
DS
t
DH
t
DS
t
DS
t
DS
High-Z
High-Z
High-Z
I/O0 to I/O7
50H
D
OUT
D
OUT
D
OUT
A0 to A3
A9 to A16
A17 to A24
D
OUT
D
OUT
512+N
512+N+1
527
512
513
t
REA
t
DH
t
DH
t
DH
t
RB
R, /B
Access
page M+1
Access
page M
Output page
M+1 data
Output page M data
Remark Start address (SA) specification when read is performed with command 50H. N: 0 to 15
μPD23C256112A
Status Read
Status information can be output from the I/O pins with the /RE clock following input of the 70H command. Status
read is a function to recognize the status of the device from external.
tCLS
CLE
tCLS
tCLH
/CE
/WE
tCS
tCH
t
CSTO
tCHZ
tWP
tWHC
tRHZ
/RE
t
WHR
tDS
tDH
tIR
High-Z
High-Z
I/O0 to I/O7
Status
70H
tRSTO
R, /B
Ready
Status
Status output data Note
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Ready / Busy
Not used
0 / 1
0
0
Not used
Not used
0
Not used
0
Not used
0
Ready / Busy
Write protect
1 / 0
0
Note Use the status read command only during Ready.
Data Sheet M15902EJ3V0DS
22
μPD23C256112A
ID Read
To recognize the ID code (maker code / device code) of this device in a system, execute the ID read command.
The ID code can be read with the following timing.
t
CLS
CLE
/CE
/WE
ALE
/RE
t
CLS
t
CLH
t
CH
t
CR
t
CS
t
CH
t
CS
t
ALH
tALS
t
WP
t
ALH
t
AR1
t
RC
t
RP
t
REH
t
DH
t
DS
t
DH
t
DS
Maker code
10H
Device code
58H
High-Z
90H
00H
I/O0 to I/O7
t
REAID
t
REAID
I/O7
L
I/O6
L
I/O5
L
I/O4
H
I/O3
L
I/O2
L
I/O1
L
I/O0
L
HEX
10H
58H
Maker code
Device code
L
H
L
H
H
L
L
L
Cautions 1. If the /RE clock is input after the maker code and device code are output, the output data is not
guaranteed. Therefore, do not input the /RE clock following device code output.
2. Do not input an address other than 00H after setting the ID read command (90H). If an address other
than 00H is input, the data following /RE clock input is not guaranteed.
Data Sheet M15902EJ3V0DS
23
μPD23C256112A
Reset Cycle Timing Chart
CLE
t
CLS
tCLH
/CE
/WE
t
CS
t
CH
t
RST
t
ALS
t
WP
t
ALH
ALE
t
DS
t
DH
I/O0 to I/O7
FFH
t
WB
R, /B
Data Sheet M15902EJ3V0DS
24
μPD23C256112A
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
F
G
R
Q
L
S
24
25
E
P
I
A
J
C
S
B
M
M
D
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
12.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
0.1 0.05
1.2 MAX.
1.0 0.05
16.4 0.1
0.8 0.2
0.145 0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0 0.2
+5°
3°
Q
−3°
R
S
0.25
0.60 0.15
S48GY-50-MJH1-1
Data Sheet M15902EJ3V0DS
25
μPD23C256112A
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
E
S
L
Q
R
G
24
25
S
F
K
N
S
M
A
D
M
B
C
I
J
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
E
F
G
I
12.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
0.1 0.05
1.2 MAX.
1.0 0.05
16.4 0.1
0.8 0.2
0.145 0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0 0.2
+5°
3°
Q
−3°
R
S
0.25
0.60 0.15
S48GY-50-MKH1-1
Data Sheet M15902EJ3V0DS
26
μPD23C256112A
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD23C256112A.
Types of Surface Mount Device
μPD23C256112AGY-MJH : 48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
μPD23C256112AGY-MKH : 48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
μPD23C256112AGY-MJH-A : 48-pin PLASTIC TSOP(I) (12x18) (Normal bent)
μPD23C256112AGY-MKH-A : 48-pin PLASTIC TSOP(I) (12x18) (Reverse bent)
<R>
<R>
Data Sheet M15902EJ3V0DS
27
μPD23C256112A
Revision History
Edition/
Page
Previous
Type of
revision
Location
Description
Date
This
(Previous edition → This edition)
edition
p.2
edition
p.1
3rd edition/
Feb. 2006
Addition
Addition
Addition
Ordering Information
Pin Configuration
Recommended Soldering
Conditions
Lead-free products have been added
Lead-free products have been added
Lead-free products have been added
pp.3,4
p.27
pp.2,3
p.26
Data Sheet M15902EJ3V0DS
28
μPD23C256112A
[ MEMO ]
Data Sheet M15902EJ3V0DS
29
μPD23C256112A
[ MEMO ]
Data Sheet M15902EJ3V0DS
30
μPD23C256112A
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M15902EJ3V0DS
31
μPD23C256112A
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of February, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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