UPD23C16040BLGY-XXX-MJH-A [NEC]
MASK ROM, 1MX16, 90ns, MOS, PDSO48, 12 X 18 MM, PLASTIC, TSOP1-48;
| 型号： | UPD23C16040BLGY-XXX-MJH-A |
| 厂家： | 
NEC |
| 描述： | MASK ROM, 1MX16, 90ns, MOS, PDSO48, 12 X 18 MM, PLASTIC, TSOP1-48 有原始数据的样本ROM ISM频段 光电二极管 内存集成电路 |
| 文件： | 总24页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD23C16040BL, 23C16080BL
16M-BIT MASK-PROGRAMMABLE ROM
2M-WORD BY 8-BIT (BYTE MODE) / 1M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Description
The µPD23C16040BL and µPD23C16080BL are 16,777,216 bits mask-programmable ROM. The word organization is
selectable (BYTE mode : 2,097,152 words by 8 bits, WORD mode : 1,048,576 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The µPD23C16040BL and µPD23C16080BL are packed in 48-pin PLASTIC TSOP(I) and 44-pin PLASTIC SOP.
Features
• Word organization
2,097,152 words by 8 bits (BYTE mode)
1,048,576 words by 16 bits (WORD mode)
• Page access mode
BYTE mode : 8 byte random page access (µPD23C16040BL)
16 byte random page access (µPD23C16080BL)
WORD mode :4 word random page access (µPD23C16040BL)
8 word random page access (µPD23C16080BL)
• Operating supply voltage : VCC = 2.7 V to 3.6 V
Operating supply
voltage
Access time /
Page access time
ns (MAX.)
Power supply current (Active mode)
mA (MAX.)
Standby current
(CMOS level input)
µA (MAX.)
VCC
µPD23C16040BL
µPD23C16080BL
3.0 V 0.3 V
3.3 V 0.3 V
90 / 25
85 / 25
40
55
30
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15720EJ3V0DS00 (3rd edition)
Date Published March 2003 NS CP(K)
Printed in Japan
The mark
shows major revised points.
2001
µPD23C16040BL, 23C16080BL
Ordering Information
Part Number
Package
µPD23C16040BLGY-xxx-MJH
µPD23C16040BLGY-xxx-MKH
µPD23C16040BLGX-xxxNote
µPD23C16080BLGY-xxx-MJH
µPD23C16080BLGY-xxx-MKH
µPD23C16080BLGX-xxxNote
48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
44-pin PLASTIC SOP (15.24 mm (600))
48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
44-pin PLASTIC SOP (15.24 mm (600))
Note Under development
(xxx : ROM code suffix No.)
Data Sheet M15720EJ3V0DS
2
µPD23C16040BL, 23C16080BL
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
[ µPD23C16040BLGY-xxx-MJH ]
[ µPD23C16080BLGY-xxx-MJH ]
Marking Side
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
O15, A−1
O7
2
3
4
5
O14
O6
6
7
O13
O5
8
9
O12
O4
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A19
NC
V
CC
CC
V
NC
NC
A18
A17
A7
O11
O3
O10
A6
O2
A5
O9
A4
O1
A3
O8
A2
O0
A1
/OE or OE or DC
GND
A0
/CE
GND
A0 to A19
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE or OE
VCC
: Output Enable
: Supply voltage
: Ground
GND
NC Note
DC
: No Connection
: Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15720EJ3V0DS
3
µPD23C16040BL, 23C16080BL
48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
[ µPD23C16040BLGY-xxx-MKH ]
[ µPD23C16080BLGY-xxx-MKH ]
Marking Side
GND
GND
O15, A−1
O7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
3
4
O14
5
O6
6
O13
7
O5
8
O12
9
O4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A8
V
CC
CC
A19
NC
V
NC
NC
O11
A18
A17
A7
O3
O10
O2
A6
O9
A5
O1
A4
O8
A3
O0
/OE or OE or DC
GND
A2
A1
A0
GND
/CE
A0 to A19
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE or OE
VCC
: Output Enable
: Supply voltage
: Ground
GND
NC Note
DC
: No Connection
: Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15720EJ3V0DS
4
µPD23C16040BL, 23C16080BL
44-pin PLASTIC SOP (15.24 mm (600))
[ µPD23C16040BLGX-xxx ]
[ µPD23C16080BLGX-xxx ]
Marking Side
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A18
2
A19
A17
3
A8
A7
4
A9
A6
5
A10
A5
6
A11
A4
7
A12
A3
8
A13
A2
9
A14
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A15
A0
A16
/CE
WORD, /BYTE
GND
O15, A−1
O7
GND
/OE or OE or DC
O0
O8
O14
O6
O1
O9
O13
O5
O2
O10
O3
O12
O4
O11
V
CC
A0 to A19
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A–1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE or OE
VCC
: Output Enable
: Supply voltage
GND
: Ground
NC Note
DC
: No Connection
: Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M15720EJ3V0DS
5
µPD23C16040BL, 23C16080BL
Input / Output Pin Functions
Pin name
WORD, /BYTE
Input / Output
Function
Input
The pin for switching WORD mode and BYTE mode.
High level : WORD mode (1M-word by 16-bit)
Low level : BYTE mode (2M-word by 8-bit)
A0 to A19
Input
Address input pins.
(Address inputs)
A0 to A19 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
A0 to A19 are used as 20 bits address signals.
BYTE mode (2M-word by 8-bit)
A0 to A19 are used as the upper 20 bits of total 21 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
Data output pins.
O0 to O7, O8 to O14
(Data outputs)
Output
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (2M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1
Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (1M-word by 16-bit)
(Data output 15,
LSB Address input)
The most significant output data bus (O15).
BYTE mode (2M-word by 8-bit)
The least significant address bus (A−1).
/CE
Input
Input
Chip activating signal.
(Chip Enable)
When the OE is active, output states are following.
High level : High-Z
Low level : Data out
/OE or OE or DC
(Output Enable, Don't care)
VCC
Output enable signal. The active level of OE is mask option. The active level of OE
can be selected from high active, low active and Don’t care at order.
−
−
−
Supply voltage
GND
NC
Ground
Not internally connected. (The signal can be connected.)
Data Sheet M15720EJ3V0DS
6
µPD23C16040BL, 23C16080BL
Block Diagram
O8
O9
O10 O11 O12 O13 O14 O15, A 1
O2
O3 O4
O5 O6 O7
O0
O1
A0
A1
A2
A3
A4
A5
Output Buffer
Y-Selector
WORD, /BYTE
/OE or OE or DC
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
Memory Cell Matrix
1,048,576 words by 16 bits /
2,097,152 words by 8 bits
/CE
A18
A19
Data Sheet M15720EJ3V0DS
7
µPD23C16040BL, 23C16080BL
Mask Option
The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected
from among " 0 " " 1 " " x " shown in the table below.
Option
/OE or OE or DC
OE active level
0
1
x
/OE
OE
DC
L
H
Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE
L
/OE
L
Mode
Active
Output state
Data out
High-Z
H
H
H or L
Standby
High-Z
Operation mode (Option : 1)
/CE
L
OE
L
Mode
Active
Output state
High-Z
H
Data out
High-Z
H
H or L
Standby
Operation mode (Option : x)
/CE
L
DC
Mode
Active
Output state
Data out
High-Z
H or L
H or L
H
Standby
Remark L : Low level input
H : High level input
Data Sheet M15720EJ3V0DS
8
µPD23C16040BL, 23C16080BL
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VI
Condition
Rating
Unit
V
–0.3 to +4.6
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–10 to +70
Input voltage
V
Output voltage
VO
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +150
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25 °C)
Parameter
Input capacitance
Output capacitance
Symbol
CI
Test condition
MIN.
TYP.
MAX.
10
Unit
f = 1 MHz
pF
pF
CO
12
DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
Symbol
VIH
Test conditions
MIN.
2.0
TYP.
MAX.
VCC + 0.3
+0.5
Unit
V
High level input voltage
Low level input voltage
VIL
VCC = 3.0 V 0.3 V
VCC = 3.3 V 0.3 V
IOH = –100 µA
–0.3
–0.3
2.4
V
+0.8
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
Power supply current
VOH
VOL
ILI
V
V
IOL = 2.1 mA
0.4
+10
+10
40
VI = 0 V to VCC
–10
–10
µA
µA
mA
ILO
VO = 0 V to VCC, Chip deselected
ICC1
/CE = VIL (Active µPD23C16040BL VCC = 3.0 V 0.3 V
mode), IO = 0 mA
VCC = 3.3 V 0.3 V
µPD23C16080BL VCC = 3.0 V 0.3 V
VCC = 3.3 V 0.3 V
40
55
55
Standby current
ICC3
/CE = VCC – 0.2 V (Standby mode)
30
µA
Data Sheet M15720EJ3V0DS
9
µPD23C16040BL, 23C16080BL
AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
Symbol Test condition
VCC = 3.0 V 0.3 V
MIN. TYP. MAX.
VCC = 3.3 V 0.3 V
MIN. TYP. MAX.
Unit
Address access time
Page access time
tACC
tPAC
tSKEW
tCE
90
25
10
90
25
85
25
10
85
25
ns
ns
ns
ns
ns
ns
ns
ns
Address skew time
Note
Chip enable access time
Output enable access time
Output hold time
tOE
tOH
tDF
0
0
0
0
Output disable time
25
90
25
85
WORD, /BYTE access time
tWB
Note tSKEW indicates the following three types of time depending on the condition.
1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the
next address is determined.
2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the
/CE high level input point.
3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is
determined.
Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is switched
from high level to low level following address determination, or when the address is changed after /CE is switched
from low level to high level.
Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
AC Test Conditions
Input waveform (Rise / Fall time ≤ 5 ns)
1.4 V
Test points
1.4 V
Output waveform
1.4 V
Test points
1.4 V
Output load
1TTL + 100 pF
Data Sheet M15720EJ3V0DS
10
µPD23C16040BL, 23C16080BL
Cautions on power application
To ensure normal operation, always apply power using /CE following the procedure shown below.
1) Input a high level to /CE during and after power application.
2) Hold the high level input to /CE for 200 ns or longer (wait time).
3) Start normal operation after the wait time has elapsed.
Power Application Timing Chart 1 (When /CE is made high at power application)
Wait time
Normal operation
/CE (Input)
200 ns or longer
V
CC
Power Application Timing Chart 2 (When /CE is made high after power application)
Wait time
Normal operation
/CE (Input)
200 ns or longer
V
CC
Caution Other signals can be either high or low during the wait time.
Data Sheet M15720EJ3V0DS
11
µPD23C16040BL, 23C16080BL
Read Cycle Timing Chart 1
t
SKEW
t
SKEW
tSKEW
A0 to A19,
(Input)
A−1 Note1
t
ACC
t
ACC
tACC
/CE (Input)
Note2
Note2
tDF
t
CE
t
DF
/OE or OE (Input)
t
OE
t
OH
t
OH
tOH
High-Z
High-Z
O0 to O7,
O8 to O15 Note3
(Input)
Data out
Data out
Data out
Notes 1. During WORD mode, A–1 is O15.
2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
Data Sheet M15720EJ3V0DS
12
µPD23C16040BL, 23C16080BL
Read Cycle Timing Chart 2 (Page Access Mode)
Upper address Note 1
(Input)
A2 to A19
A3 to A19
tACC
/CE (Input)
t
CE
/OE or OE (Input)
tOE
Page address Note 1
A–1 Note 2, A0, A1
(Input)
A–1 Note 2, A0, A1, A2
Note 5
Note 5
PAC
Note 3
DF
tPAC
t
t
tOH
tOH
tOH
High-Z
High-Z
O0 to O7,
(Output)
Data Out
Data Out
Data Out
O8 to O15 Note 4
Notes 1. The address differs depending on the product as follows.
Part Number
Upper address
A2 to A19
Page address
µPD23C16040BL
µPD23C16080BL
A–1, A0, A1
A3 to A19
A–1, A0, A1, A2
2. During WORD mode, A–1 is O15.
3. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1.
5. The definition of page access time is as follows.
[ µPD23C16040BL ]
Page access time
Upper address (A2 to A19)
inputs condition
/CE input condition
/OE or OE input condition
t
PAC
Before tACC – tPAC
Before tCE – tPAC
Before stabilizing of page
address (A–1, A0, A1)
[ µPD23C16080BL ]
Page access time
Upper address (A3 to A19)
inputs condition
/CE input condition
Before tCE – tPAC
/OE or OE input condition
t
PAC
Before tACC – tPAC
Before stabilizing of page
address (A–1, A0, A1, A2)
Data Sheet M15720EJ3V0DS
13
µPD23C16040BL, 23C16080BL
WORD, /BYTE Switch Timing Chart
High-Z
High-Z
A–1 (Input)
(Input)
WORD, /BYTE
t
OH
t
ACC
t
OH
t
WB
O0 to O7 (Output)
O8 to O15 (Output)
Data Out
Data Out
High-Z
Data Out
Data Out
t
DF
Data Out
Remark Chip Enable (/CE) and Output Enable (/OE or OE) : Active.
Data Sheet M15720EJ3V0DS
14
µPD23C16040BL, 23C16080BL
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
F
G
R
Q
L
24
25
S
E
P
I
A
J
C
S
B
M
M
D
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
12.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
0.1 0.05
1.2 MAX.
1.0 0.05
16.4 0.1
0.8 0.2
0.145 0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0 0.2
+5°
3°
Q
−3°
R
S
0.25
0.60 0.15
S48GY-50-MJH1-1
Data Sheet M15720EJ3V0DS
15
µPD23C16040BL, 23C16080BL
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
E
S
L
Q
R
G
F
24
25
K
N
S
M
A
D
M
B
S
C
I
J
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
E
F
G
I
12.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
0.1 0.05
1.2 MAX.
1.0 0.05
16.4 0.1
0.8 0.2
0.145 0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0 0.2
+5°
3°
Q
−3°
R
S
0.25
0.60 0.15
S48GY-50-MKH1-1
Data Sheet M15720EJ3V0DS
16
µPD23C16040BL, 23C16080BL
44-PIN PLASTIC SOP (15.24 mm (600))
44
23
detail of lead end
P
1
22
A
H
F
I
J
G
S
B
C
N
S
L
K
D
M
M
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.4
27.83
A
−0.05
B
C
0.78 MAX.
1.27 (T.P.)
+0.08
0.42
D
−0.07
E
F
G
H
I
0.15 0.1
3.0 MAX.
2.7 0.05
16.04 0.3
13.24 0.1
1.4 0.2
J
+0.08
0.22
K
−0.07
L
M
N
0.8 0.2
0.12
0.10
+7°
3°
P
−3°
P44GX-50-600A-4
Data Sheet M15720EJ3V0DS
17
µPD23C16040BL, 23C16080BL
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD23C16040BL and µPD23C16080BL.
Types of Surface Mount Device
µPD23C16040BLGY-MJH : 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µPD23C16040BLGY-MKH : 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µPD23C16040BLGX
: 44-pin PLASTIC SOP (15.24 mm (600))
µPD23C16080BLGY-MJH : 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent)
µPD23C16080BLGY-MKH : 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent)
µPD23C16080BLGX
: 44-pin PLASTIC SOP (15.24 mm (600))
Data Sheet M15720EJ3V0DS
18
µPD23C16040BL, 23C16080BL
Revision History
Edition/
Page
Previous
edition
3rd edition/ Throughout Throughout Modification
Type of
Location
Description
Date
This
edition
revision
(Previous edition → This edition)
Preliminary Data Sheet → Data Sheet
Under development (44-pin PLASTIC SOP)
Address skew time (tSKEW)
Note
Mar. 2003
p.2
p.2
Addition
Addition
Ordering Information
AC Characteristics
p.10
p.10
p.11
p.12
–
Addition
Cautions on power application
Read Cycle Timing Chart 1
p.11
Modification
Data Sheet M15720EJ3V0DS
19
µPD23C16040BL, 23C16080BL
[MEMO]
Data Sheet M15720EJ3V0DS
20
µPD23C16040BL, 23C16080BL
[MEMO]
Data Sheet M15720EJ3V0DS
21
µPD23C16040BL, 23C16080BL
[MEMO]
Data Sheet M15720EJ3V0DS
22
µPD23C16040BL, 23C16080BL
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS
FOR CMOS
Note:
Input levels of CMOS devices must be fixed. CMOS devices behave differently than Bipolar or
NMOS devices. If the input of a CMOS device stays in an area that is between VIL (MAX.) and
V
IH (MIN.) due to the effects of noise or some other irregularity, malfunction may result.
Therefore, not only the input waveform is fixed, but also the waveform changes, it is important
to use the CMOS device under AC test conditions. For unused input pins in particular, CMOS
devices should not be operated in a state where nothing is connected, so input levels of CMOS
devices must be fixed to high or low by using pull-up or pull-down circuitry. Each unused pin
should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device
and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M15720EJ3V0DS
23
µPD23C16040BL, 23C16080BL
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
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•
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M8E 02. 11-1
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