UPD17P012GC-8BT-A [NEC]
IC,MICROCONTROLLER,4-BIT,UPD17K CPU,CMOS,QFP,80PIN,PLASTIC;
| 型号： | UPD17P012GC-8BT-A |
| 厂家： | 
NEC |
| 描述： | IC,MICROCONTROLLER,4-BIT,UPD17K CPU,CMOS,QFP,80PIN,PLASTIC 可编程只读存储器 微控制器 光电二极管 |
| 文件： | 总318页 (文件大小：2087K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17012, 17P012
4-BIT SINGLE-CHIP MICROCONTROLLERS WITH
DIGITAL TUNING SYSTEM HARDWARE
DESCRIPTION
The µPD17012 is a 4-bit single-chip CMOS microcontroller equipped with hardware for digital tuning systems.
The µPD17P012 is a version of the µPD17012 with one-time PROM instead of mask ROM.
The user can write programs to the µPD17P012 once, and it is ideal for experimental production of the µPD17012
during system design or small-scale production.
This series employs a 17K architecture CPU that can directly manipulate the data memory, execute various
operations, and control the peripheral hardware with a single instruction. All the instructions are one-word 16-bit
instructions. Besides various I/O ports, an LCD controller/driver, A/D converter, D/A converter (PWM output), and
BEEP output, this microcontroller has a prescaler that can operate at up to 250 MHz, a PLL frequency synthesizer,
and frequency counter for digital tuning systems. This series therefore ideal for configuring a high-performance, multi-
functional digital tuning system on a single chip.
FEATURES
•
•
17K architecture: General-purpose register method
Program memory (ROM)
•
Various peripheral hardware
General-purposeI/Oports,LCDcontroller/driver,serial
interface, A/D converter, D/A converter (PWM output),
BEEP output, frequency counter
Interrupts
µPD17012: Mask ROM
8 KB (4,096 × 16 bits)
µPD17P012: One-time PROM
8 KB (4,096 × 16 bits)
•
•
External: 1
•
•
General-purpose data memory (RAM)
316 × 4 bits
Instruction execution time
Internal:
3
Power-on-reset, reset by CE pin, and power failure
detector
4.44 µs (with 4.5 MHz crystal resonator)
Decimal operation
•
•
Power-saving CMOS
•
•
•
Supply voltage: VDD = 5 V 10%
Table reference
Hardware for PLL frequency synthesizer
Dualmodulusprescaler(250MHzmax.),programmable
divider, phase comparator, charge pump
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark
shows major revised points.
Document No. U10101EJ4V0DS00 (4th edition)
Date Published August 2001 N CP(K)
Printed in Japan
1994, 2000
©
µPD17012, 17P012
ORDERING INFORMATION
Part Number
Package
µPD17012GF-×××-3BE
µPD17012GC-×××-8BT
µPD17P012GF-3BE
µPD17P012GC-8BT
64-pin plastic QFP (14 × 20)
80-pin plastic QFP (14 × 14)
64-pin plastic QFP (14 × 20)
80-pin plastic QFP (14 × 14)
Remark ××× indicates the ROM code suffix.
OVERVIEW OF FUNCTIONS
Item
µPD17012
µPD17P012
Program memory (ROM)
8 KB (4,096 × 16 bits) (mask ROM)
Table reference area: 4,096 × 16 bits
316 × 4 bits
8 KB (4,096 × 16 bits) (one-time PROM)
General-purpose data memory (RAM)
Register file
33 × 4 bits (control register)
Port register
12 × 4 bits (functions alternately as LCD segment register)
4.44 µs (with 4.5 MHz crystal resonator)
Instruction execution time
Stack levels
•
•
Address stack: 5 levels (stack operation enabled)
Interrupt stack: 2 levels (stack operation disabled)
General-purpose ports
•
•
•
I/O ports: 14 pins
Input ports: 8 pins
Output ports: 8 pins (+20: LCD segment pin)
BEEP output
2 pins (frequency can be set individually)
Selectable frequency (200 Hz, 1 kHz, 3 kHz, 9 kHz)
LCD controller/driver
20 segments, 3 commons
1/3 duty, 1/2 bias, frame frequency: 167 Hz, drive voltage: VDD,
segment pins also used as key source pins: 16
All 20 pins can be used as output port pins
(4 pins can be set in output mode individually and the rest are set at once)
Serial interface
1 channel
3-wire (serial I/O)
D/A converter
A/D converter
Interrupts
8 bits × 2 channels (PWM output)
6 bits × 2 channels (successive approximation method by software)
4 (maskable)
External: 1 (INT pin)
Internal: 3 (timer × 2, serial interface)
Timer
Reset
3 channels
12-bit timer (10, 50 µs)
Basic timer 0 (1, 5, 100, 250 ms)
Basic timer 1 (1, 5, 100, 250 ms)
•
•
•
Power-on reset (on power application)
Reset by CE pin (CE pin low level → high level)
Power failure detection function
2
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Item
Division mode
µPD17012
µPD17P012
PLL frequency
synthesizer
Two types
Direct division mode
Pulse swallow mode
(VCOL pin: 20 MHz MAX.)
(VCOL pin: 30 MHz MAX.)
(VCOH pin: 250 MHz MAX.)
Reference
frequency
12 programmable frequencies
1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50, 100 kHz
Charge pump
Error-out outputs: 1
Phase comparator Unlock detection by program
Frequency counter
•
Frequency measurement
P1B3/FMIFC pin: In FMIF mode 5 to 15 MHz
In AMIF mode 0.3 to 1 MHz
P1B2/AMIFC pin: 0.3 to 1 MHz
External gate width measurement
P0B3/FCG1, P0B2/FCG0 pins
•
Supply voltage
Package
VDD = 5 V 10%
64-pin plastic QFP (14 × 20)
80-pin plastic QFP (14 × 14)
3
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
PIN CONFIGURATION (TOP VIEW)
(1) µPD17012
64-pin plastic QFP (14 × 20)
µPD17012GF-×××-3BE
64 63 62 61 60 59 58 57 56 55 54 53 52
1
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1A
1
0
LCD
LCD
LCD
LCD
6
7
8
9
/KS
/KS
/KS
/KS
6
7
8
9
/PYA
/PYA
/PYA
/PYA
6
7
8
9
2
P1A
3
EO
4
V
DD1
VCOL
VCOH
CE
5
LCD10/KS10/PYA10
LCD11/KS11/PYA11
LCD12/KS12/PYA12
LCD13/KS13/PYA13
LCD14/KS14/PYA14
LCD15/KS15/PYA15
6
7
8
V
DD2
9
P0A
P0A
P0A
2
/SCK
/SO
/SI
1
1
1
10
11
12
13
14
15
16
17
18
19
1
0
LCD16/P2E
LCD17/P2F
LCD18/P2G
LCD19/P2H
0
P1B
3
/FMIFC
0
P1B
2
/AMIFC
0
P1B
P1B
P0B
P0B
1
0
3
2
/ADC
/ADC
/FCG
/FCG
1
0
1
0
1
0
0
COM
COM
COM
0
1
2
P0B
1
/BEEP
/BEEP
P1D
0
P0B
0
P1D
1
20 21 22 23 24 25 26 27 28 29 30 31 32
4
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
80-pin plastic QFP (14 × 14)
µPD17012GC-×××-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
LCD7/KS7/PYA7
LCD8/KS8/PYA8
LCD9/KS9/PYA9
LCD10/KS10/PYA10
LCD11/KS11/PYA11
LCD12/KS12/PYA12
NC
P1A0
EO
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
2
VDD1
3
NC
4
VCOL
5
VCOH
6
CE
7
LCD13/KS13/PYA13
LCD14/KS14/PYA14
NC
VDD2
8
VDD2
9
P0A2/SCK1
P0A1/SO1
P0A0/SI1
P1B3/FMIFC
P1B2/AMIFC
NC
10
11
12
13
14
15
16
17
18
19
20
LCD15/KS15/PYA15
LCD16/P2E0
LCD17/P2F0
LCD18/P2G0
LCD19/P2H0
COM0
P1B1/ADC1
P1B0/ADC0
P0B3/FCG1
P0B2/FCG0
P0B1/BEEP1
COM1
NC
COM2
P1D0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Caution Pin 4 can also be used as the VDD1 pin.
Use pin 4 as the VDD1 pin when using the µPD17012 and µPD17P012 on the same board.
5
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) µPD17P012
64-pin plastic QFP (14 × 20)
µPD17P012GF-3BE
(a) Normal operation mode
64 63 62 61 60 59 58 57 56 55 54 53 52
1
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1A
1
0
LCD
LCD
LCD
LCD
6
7
8
9
/KS
/KS
/KS
/KS
6
7
8
9
/PYA
/PYA
/PYA
/PYA
6
7
8
9
2
P1A
3
EO
4
V
DD1
VCOL
VCOH
CE
5
LCD10/KS10/PYA10
LCD11/KS11/PYA11
LCD12/KS12/PYA12
LCD13/KS13/PYA13
LCD14/KS14/PYA14
LCD15/KS15/PYA15
6
7
8
VDD2
9
P0A
P0A
P0A
2
/SCK
/SO
/SI
1
1
1
10
11
12
13
14
15
16
17
18
19
1
0
LCD16/P2E
LCD17/P2F
LCD18/P2G
LCD19/P2H
0
P1B
3
/FMIFC
0
P1B
2
/AMIFC
0
P1B
P1B
P0B
P0B
1
0
3
2
/ADC
/ADC
/FCG
/FCG
1
0
1
0
1
0
0
COM
COM
COM
0
1
2
P0B
1
/BEEP
/BEEP
P1D
0
P0B
0
P1D
1
20 21 22 23 24 25 26 27 28 29 30 31 32
6
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(b) PROM programming mode
64 63 62 61 60 59 58 57 56 55 54 53 52
1
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
(L)
3
4
VDD1
5
6
(L)
7
8
VDD2
9
(OPEN)
10
11
12
13
14
15
16
17
18
19
(L)
D4
D5
D6
D7
(L)
(L)
20 21 22 23 24 25 26 27 28 29 30 31 32
Caution The items in parentheses indicates the processing of pins not used in the PROM programming
mode.
L:
Independently connect to GND via a resistor
OPEN: Leave open.
7
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
80-pin plastic QFP (14 x 14)
µPD17P012GC-8BT
(a) Normal operation mode
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
LCD
LCD
LCD
7
8
9
/KS
/KS
/KS
7
8
9
/PYA
/PYA
/PYA
7
8
9
P1A
0
1
EO
2
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
DD1
DD1
3
LCD10/KS10/PYA10
LCD11/KS11/PYA11
LCD12/KS12/PYA12
NC
V
4
VCOL
VCOH
CE
5
6
7
LCD13/KS13/PYA13
LCD14/KS14/PYA14
NC
VDD2
8
VDD2
9
P0A
P0A
P0A
2
/SCK
/SO
/SI
1
1
1
10
11
12
13
14
15
16
17
18
19
20
LCD15/KS15/PYA15
1
LCD16/P2E
LCD17/P2F
LCD18/P2G
LCD19/P2H
0
0
0
P1B
3
/FMIFC
/AMIFC
NC
0
P1B
2
0
COM
COM
NC
0
P1B
P1B
P0B
P0B
1
0
3
2
/ADC
/ADC
/FCG
/FCG
1
0
1
0
1
1
COM
2
P1D
0
P0B /BEEP
1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
8
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(b) PROM programming mode
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
(L)
2
3
V
DD1
DD1
(OPEN)
4
V
5
6
(L)
7
NC
(OPEN)
NC
V
DD2
DD2
8
V
9
10
11
12
13
14
15
16
17
18
19
20
(L)
D
4
5
D
(OPEN)
NC
D
6
D
7
NC
(OPEN)
(L)
(L)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Caution The items in parentheses indicates the processing of pins not used in the PROM programming
mode.
L:
Independently connect to GND via a resistor
OPEN: Leave open.
9
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
PIN IDENTIFICATION
ADC0, ADC1:
AMIFC:
A/D converter input
P0B0 to P0B3: Port 0B
P0C0 to P0C3: Port 0C
P0D0 to P0D3: Port 0D
P1A0 to P1A2: Port 1A
P1B0 to P1B3: Port 1B
P1C0 to P1C3: Port 1C
AM intermediate frequency
counter input
BEEP0, BEEP1: BEEP output
CE:
Chip enable input
Address update clock input
CLK:
COM0 to COM2: LCD common signal output
P2E0:
P2F0:
P2G0:
P2H0:
Port 2E
Port 2F
Port 2G
Port 2H
D0 to D7:
EO:
Data I/O
Error out output
FCG0, FCG1:
FMIFC:
External gate counter input
FM intermediate frequency
counter input
PWM0, PWM1: D/A converter output
PYA0 to PYA15: Port YA
GND:
Ground
SCK1:
SI1:
Serial clock I/O
INT:
External interrupt input
Key source signal input
Key source signal output
Serial data input
K0 to K3:
KS0 to KS15:
SO1:
Serial data output
VCOH:
VCOL:
VDD1, VDD2:
VPP:
Local oscillation high input
Local oscillation low input
Power supply
LCD0 to LCD19: LCD segment signal output
NC:
No connection
MD0 to MD3:
Operation mode selection
Program voltage application
Crystal resonator connection
P0A0 to P0A2: Port 0A
XIN, XOUT:
10
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
BLOCK DIAGRAM
(1) µPD17012
COM0
P0A0 to P0A2
P0B0 to P0B3
P0C0 to P0C3
3
4
COM1
COM2
RF
LCD0/PYA0/KS0
LCD
controller/
driver
to
LCD15/PYA15/KS15
RAM
16 × 4 bits
LCD16/P2E0
LCD17/P2F0
LCD18/P2G0
LCD19/P2H0
4
System register
P0D0/K0 to
P0D3/K3
4
PYA0 to PYA15
P1A0 to P1A2
P1B0 to P1B3
P1C0 to P1C3
P1D0 to P1D3
16
3
FCG0/P0B2
FCG1/P0B3
AMIFC/P1B2
FMIFC/P1B3
Frequency
counter
ALU
4
Port
ADC1/P1B1
ADC0/P1B0
A/D
converter
4
PWM1/P0C1
PWM0/P0C0
D/A
converter
Instruction
decoder
4
P2E0
P2F0
P2G0
P2H0
12-bit
timer
Mask ROM
4,096 × 16 bits
Basic
timer 0
Basic
timer 1
Program counter
BEEP1/P0B1
BEEP0/P0B0
VCOH
VCOL
EO
BEEP
PLL
Stack
5 × 12 bits
SCK1/P0A2
Serial
interface
SO1/P0A1
SI1/P0A0
XIN
CPU
OSC
XOUT
Peripheral
Interrupt
control
INT
VDD1
Reset
VDD2
CE
GND
11
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) µPD17P012
COM
COM
COM
0
1
2
P0A
0
to P0A
2
3
4
RF
LCD /PYA
to0
0
/KS
0
P0B
0
to P0B
to P0C
to P0D
3
3
LCD
controller/
driver
LCD15/PYA15/KS15
RAM
16 × 4 bits
LCD16/P2E
LCD17/P2F
LCD18/P2G
LCD19/P2H
0
P0C
0
4
0
0
System registers
P0D
0
3
4
0
(MD
0
to MD
3
)
PYA
0
to PYA15
16
3
FCG
FCG
0
/P0B
/P0B
2
1
3
Frequency
counter
AMIFC/P1B
FMIFC/P1B
2
P1A
P1B
0
to P1A
to P1B
2
ALU
3
0
3
4
Port
ADC
ADC
1
0
/P1B
/P1B
1
0
A/D
converter
(D
7
to
D4
)
P1C
0
to P1C
to
3
4
(D
3
D
0
)
PWM
PWM
1
0
/P0C
/P0C
1
D/A
converter
Instruction
decoder
P1D
0
to P1D
3
4
0
P2E
P2F
P2G
P2H
0
0
0
0
12-bit
timer
One-time PROM
4096 × 16 bits
Basic
timer 0
Basic
timer 1
Program counter
BEEP
BEEP
1
0
/P0B
/P0B
1
0
VCOH
VCOL
EO
BEEP
PLL
Stack
5 × 12 bits
SCK
SO /P0A
SI /P0A
1/P0A
2
Serial
interface
1
1
X
IN
CPU
(CLK)
1
0
OSC
Peripheral
XOUT
Interrupt
control
INT (VPP
)
V
V
DD1
DD2
Reset
CE
GND
Remark The items in parentheses indicate the pins when used in the PROM programming mode.
12
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
CONTENTS
1. PIN FUNCTIONS............................................................................................................................ 18
1.1
1.2
1.3
1.4
Pin Function List................................................................................................................ 18
Pin Equivalent Circuits ...................................................................................................... 21
Recommended Connection of Unused Pins ................................................................... 25
Notes on Using CE and INT Pins...................................................................................... 26
2. PROGRAM MEMORY (ROM) ........................................................................................................ 27
2.1
2.2
2.3
2.4
Outline of Program Memory.............................................................................................. 27
Program Memory ............................................................................................................... 28
Program Counter ............................................................................................................... 28
Program Flow ..................................................................................................................... 29
3. ADDRESS STACK (ASK) .............................................................................................................. 31
3.1
3.2
3.3
3.4
3.5
Outline of Address Stack .................................................................................................. 31
Address Stack Registers (ASR)........................................................................................ 31
Stack Pointer (SP) .............................................................................................................. 32
Operation of Address Stack.............................................................................................. 33
Notes on Using Address Stack......................................................................................... 33
4. DATA MEMORY (RAM) .................................................................................................................. 34
4.1
4.2
4.3
4.4
Outline of Data Memory .................................................................................................... 34
Configuration and Function of Data Memory.................................................................. 35
Addressing of Data Memory ............................................................................................. 37
Notes on Using Data Memory ........................................................................................... 38
5. SYSTEM REGISTER (SYSREG) ................................................................................................... 39
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Outline of System Register ............................................................................................... 39
System Register List ......................................................................................................... 40
Address Register (AR)....................................................................................................... 41
Window Register (WR) ...................................................................................................... 43
Bank Register (BANK) ....................................................................................................... 44
Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer) ... 45
General Register Pointer (RP) .......................................................................................... 47
Program Status Word (PSWORD) ..................................................................................... 49
Notes on Using System Register ..................................................................................... 50
6. GENERAL REGISTER (GR) .......................................................................................................... 51
6.1
6.2
6.3
6.4
Outline of General Register .............................................................................................. 51
General Register Body ...................................................................................................... 51
Address Generation of General Register by Instructions.............................................. 52
Notes on Using General Register..................................................................................... 53
7. ALU (Arithmetic Logic Unit) BLOCK........................................................................................... 54
7.1 Outline of ALU Block ......................................................................................................... 54
13
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
7.2
7.3
7.4
Configuration and Function of Each Block ..................................................................... 55
ALU Processing Instruction List ...................................................................................... 55
Notes on Using ALU .......................................................................................................... 59
8. REGISTER FILE (RF) .................................................................................................................... 60
8.1
8.2
8.3
8.4
8.5
Outline of Register File ..................................................................................................... 60
Configuration and Function of Register File................................................................... 61
Register File Manipulation Instructions (“PEEK WR, rf” and “POKE rf, WR”).............. 62
Control Registers ............................................................................................................... 62
Notes on Using Register File ............................................................................................ 68
9. DATA BUFFER (DBF) .................................................................................................................... 69
9.1
9.2
9.3
9.4
Outline of Data Buffer........................................................................................................ 69
Data Buffer ......................................................................................................................... 70
Peripheral Hardware and Data Buffer List ....................................................................... 71
Notes on Using Data Buffer .............................................................................................. 73
10. GENERAL-PURPOSE PORTS ...................................................................................................... 74
10.1 Configuration and Classification of General-Purpose Ports ......................................... 74
10.2 Functional Outline of General-Purpose Ports ................................................................. 75
10.3 General-Purpose I/O Ports (P0A, P0B, P1A, and P1D).................................................... 80
10.4 General-Purpose Input Ports (P0D and P1B) .................................................................. 86
10.5 General-Purpose Output Ports (P0C and P1C) ............................................................... 88
10.6 General-Purpose Output Ports (P2E to P2H and PYA) ................................................... 90
11. INTERRUPTS ................................................................................................................................ 97
11.1 Outline of Interrupt Block.................................................................................................. 97
11.2 Interrupt Control Block...................................................................................................... 99
11.3 Interrupt Stack Register .................................................................................................... 103
11.4 Stack Pointer, Address Stack Register, Program Counter ............................................. 104
11.5 Interrupt Enable Flip-Flop (INTE)...................................................................................... 104
11.6 Acknowledging Interrupts................................................................................................. 105
11.7 Operations After Acknowledging Interrupt ..................................................................... 110
11.8 Restoring from Interrupt Servicing Routine.................................................................... 110
11.9 External (INT Pin) Interrupt ............................................................................................... 111
11.10 Internal Interrupt ................................................................................................................ 113
12. TIMER ............................................................................................................................................ 114
12.1 General ............................................................................................................................... 114
12.2 Basic Timer 0 ...................................................................................................................... 115
12.3 Basic Timer 1 ...................................................................................................................... 128
12.4 12-Bit Timer ........................................................................................................................ 136
13. A/D CONVERTER (ADC) ............................................................................................................... 144
13.1 General ............................................................................................................................... 144
13.2 Input Selector Block .......................................................................................................... 145
13.3 Compare Voltage Generator Block and Compare Block ................................................ 146
13.4 Comparison Timing Chart ................................................................................................. 150
13.5 Performance of A/D Converter.......................................................................................... 150
14
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13.6 Using A/D Converter .......................................................................................................... 151
13.7 Status on Reset.................................................................................................................. 156
14. D/A CONVERTER (DAC)............................................................................................................... 157
14.1 Configuration of D/A Converter ........................................................................................ 157
14.2 Functional Outline of D/A Converter ................................................................................ 157
14.3 Output Select Blocks......................................................................................................... 158
14.4 Duty Setting Blocks and Clock Generation Block .......................................................... 160
14.5 Cautions on Using D/A Converter .................................................................................... 163
14.6 Status on Reset.................................................................................................................. 164
15. SERIAL INTERFACE ..................................................................................................................... 165
15.1 Configuration of Serial Interface ...................................................................................... 166
15.2 Functional Outline of Serial Interface .............................................................................. 167
15.3 Shift Clock and Serial Data I/O Pin Control Blocks ........................................................ 168
15.4 Clock Generation Block .................................................................................................... 170
15.5 Clock Counter .................................................................................................................... 172
15.6 Presettable Shift Register (SIO1SFR) .............................................................................. 173
15.7 Wait Control Block ............................................................................................................. 175
15.8 Outline of Serial Interface Operation ............................................................................... 177
15.9 Status of Serial Interface on Reset .................................................................................. 178
16. PLL FREQUENCY SYNTHESIZER ............................................................................................... 179
16.1 Configuration of PLL Frequency Synthesizer................................................................. 179
16.2 Functional Outline of PLL Frequency Synthesizer......................................................... 180
16.3 Input Select Block and Programmable Divider ............................................................... 181
16.4 Reference Frequency Generator ...................................................................................... 186
16.5 Phase Comparator (φ-DET), Charge Pump, and Unlock Detection Block..................... 188
16.6 PLL Disabled Status .......................................................................................................... 191
16.7 Using PLL Frequency Synthesizer................................................................................... 191
16.8 Status on Reset.................................................................................................................. 195
17. FREQUENCY COUNTER .............................................................................................................. 196
17.1 Outline of Frequency Counter .......................................................................................... 196
17.2 Input/Output Select Block and Gate Time Control Block ............................................... 197
17.3 Start/Stop Control Block and IF Counter......................................................................... 200
17.4 Using IF Counter Function................................................................................................ 206
17.5 Error of External Gate Counter......................................................................................... 208
17.6 Status on Reset.................................................................................................................. 208
18. BEEP .............................................................................................................................................. 209
18.1 General ............................................................................................................................... 209
18.2 I/O Select Block and Output Select Block ....................................................................... 210
18.3 Clock Select Block and Clock Generator Block .............................................................. 212
18.4 Output Waveform of BEEP ................................................................................................ 213
18.5 Status on Reset.................................................................................................................. 213
15
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19. LCD CONTROLLER/DRIVER ....................................................................................................... 214
19.1 Configuration of LCD Controller/Driver ........................................................................... 214
19.2 Functional Outline of LCD Controller/Driver ................................................................... 215
19.3 LCD Segment Register ...................................................................................................... 217
19.4 Segment Signal/General-Purpose Output Port Select Block......................................... 220
19.5 Common Signal Output Timing Control Block and
Segment Signal/Key Source Signal Output Timing Control Block................................ 222
19.6 Output Waveforms of Common and Segment Signals ................................................... 224
19.7 Using LCD Controller/Driver ............................................................................................. 228
19.8 Status on Reset.................................................................................................................. 230
20. KEY SOURCE CONTROLLER/DECODER................................................................................... 231
20.1 Configuration of Key Source Controller/Decoder........................................................... 231
20.2 Functional Outline of Key Source Controller/Decoder................................................... 232
20.3 Key Source Data Setting Block......................................................................................... 233
20.4 Output Timing Control Blocks and Segment/Port Select Block .................................... 235
20.5 Key Input Control Block .................................................................................................... 239
20.6 Using Key Source Controller/Decoder............................................................................. 242
20.7 Status on Reset.................................................................................................................. 250
21. STANDBY ...................................................................................................................................... 251
21.1 Configuration of Standby Block ....................................................................................... 251
21.2 Standby Function............................................................................................................... 252
21.3 Selecting Device Operation Mode with CE Pin ............................................................... 252
21.4 Halt Function ...................................................................................................................... 254
21.5 Clock Stop Function .......................................................................................................... 262
21.6 Device Operations in Halt and Clock Stop Status .......................................................... 265
21.7 Notes on Processing Each Pin in Halt and Clock Stop Status ...................................... 266
22. RESET............................................................................................................................................ 269
22.1 Configuration of Reset Block ........................................................................................... 269
22.2 Reset Function ................................................................................................................... 270
22.3 CE Reset ............................................................................................................................. 271
22.4 Power-on Reset .................................................................................................................. 275
22.5 Relationship Between CE Reset and Power-on Reset ................................................... 278
22.6 Power Failure Detection .................................................................................................... 282
23. INSTRUCTION SET ....................................................................................................................... 290
23.1 Outline of Instruction Set .................................................................................................. 290
23.2 Legend ................................................................................................................................ 291
23.3 Instruction Set List ............................................................................................................ 292
23.4 Assembler (RA17K) Embedded Macro Instructions ....................................................... 294
24. RESERVED SYMBOLS ................................................................................................................. 295
24.1 Data Buffer (DBF)............................................................................................................... 295
24.2 System Register (SYSREG) .............................................................................................. 295
24.3 LCD Segment Register ...................................................................................................... 296
24.4 Port Register ...................................................................................................................... 297
16
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
24.5 Register File (Control Register) ........................................................................................ 298
24.6 Peripheral Hardware Register........................................................................................... 300
24.7 Others ................................................................................................................................. 300
25. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY (µPD17P012 ONLY) ............... 301
25.1 Operation Modes for Program Memory Write/Verify....................................................... 301
25.2 Program Memory Write Procedure ................................................................................... 302
25.3 Program Memory Read Procedure ................................................................................... 303
26. ELECTRICAL SPECIFICATIONS .................................................................................................. 304
27. PACKAGE DRAWINGS.................................................................................................................. 310
28. RECOMMENDED SOLDERING CONDITIONS............................................................................. 312
APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR ................................................ 313
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................. 314
17
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
1. PIN FUNCTIONS
1.1 Pin Function List
(1) Normal operation mode
Pin No.
Symbol
Function
Output Format
After Power-on
Reset
64-Pin 80-Pin
63
1
77
80
1
P1A2
3-bit I/O port (port 1A). Input/output can be specified
in 1-bit units.
CMOS
Input
P1A1
P1A0
push-pull
2
3
2
EO
Output from PLL frequency synthesizer charge pump.
The division value of the local oscillation frequency
and the phase of the reference frequency are
compared at this pin, and the result is output.
CMOS
3-state
High impedance
4
8
3 (4) VDD1
Positive power-supply pins. 5 V 10% is supplied to
these pins. When only the CPU is operating, 3.5 to
5.5 V is supplied to these pins. 2.3 to 5.5 V is supplied
when the clock is stopped. The same potential voltage
is supplied to VDD1 and VDD2.
−
−
8, 9
VDD2
5
6
5
6
VCOL
VCOH
PLL local oscillation frequency is input.
−
−
Input
7
7
CE
Device selection and reset signal input.
Input
Input
9
10
11
12
P0A2/SCK1
P0A1/SO1
P0A0/SI1
Port 0A and serial interface I/O pins.
CMOS
10
11
• P0A2 to P0A0
• 3-bit I/O port
push-pull
• Input/output can be specified in 1-bit units.
• SCK1
• Serial clock I/O
• SO1
• Serial data output
• SI1
• Serial data input
12
13
14
15
13
14
16
17
P1B3/FMIFC Port 1B. Frequency counter input and analog input to
P1B2/AMIFC A/D converter pins.
−
Input
P1B1/ADC1
P1B0/ADC0
• P1B3 to P1B0
• 4-bit input port
• FMIFC, AMIFC
• Frequency counter inputs
• ADC1, ADC0
• Analog inputs to A/D converter
Remark The parenthesized value applies to the µPD17P012.
18
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Pin No.
Symbol
Function
Output Format
After Power-on
Reset
64-Pin 80-Pin
16
17
18
19
18
19
20
21
P0B3/FCG1
P0B2/FCG0
P0B1/BEEP1
P0B0/BEEP0
Port 0B. External gate counter input and BEEP output
CMOS
Input
pins.
push-pull
• P0B3 to P0B0
• 4-bit I/O port
• Input/output can be specified in 1-bit units.
• FCG1, FCG0
• External gate counter inputs
• BEEP1, BEEP0
• BEEP outputs
20
21
22
23
22
24
25
26
P1C3
P1C2
P1C1
P1C0
4-bit output port (port 1C)
CMOS
Low-level output
push-pull
24
25
27
28
XOUT
XIN
Pins for connecting crystal resonator for system clock
oscillation.
CMOS push-pull
−
−
−
26 30, 69 GND
58 31, 71
Ground pins. These pins must be connected to the
same potential.
−
27
28
29
30
33
34
35
37
P0C3
Port 0C. D/A converter output pins.
• P0C3 to P0C0
N-ch
open-drain
(+12 V withstand
voltage)
Low-level output
P0C2
P0C1/PWM1
P0C0/PWM0
• 4-bit output port
• PWM1, PWM0
• D/A converter outputs
31
32
33
34
38
39
40
41
P1D3
P1D2
P1D1
P1D0
4-bit I/O port (port 1D). Input/output can be specified
in 4-bit units.
CMOS
Input
push-pull
35
36
37
42
44
45
COM2
COM1
COM0
These pins output the common signals of the LCD
controller/driver.
CMOS
Low-level output
Low-level output
ternary output
38
39
40
41
46
47
48
49
LCD19/P2H0
LCD18/P2G0
LCD17/P2F0
LCD16/P2E0
Port 2H, 2G, 2F, and 2E. LCD controller/driver
segment signal output pins.
CMOS
push-pull
• P2H0, P2G0, P2F0, P2E0
• 1-bit output ports
• LCD19 to LCD16
• LCD controller/driver segment signal outputs
19
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Pin No.
Symbol
Function
Output Format
After Power-on
Reset
64-Pin 80-Pin
42 to
57
50
52
53
55
to
LCD15/KS15/PYA15 Port YA. Segment signal output of LCD controller/
CMOS
Low-level output
to
driver and key source signal output of key matrix.
• PYA15 to PYA0
push-pull
LCD
0
/KS
0/PYA
0
• 16-bit output port
• LCD15 to LCD0
67
• LCD controller/driver segment signal outputs
• KS15 to KS0
• Key matrix key source signal outputs
59 to
62
73
to
P0D3/K3 to
P0D0/K0
Port 0D. Key source signal return input of LCD
segment.
−
−
Input with pull-
down resistor
76
• P0D3 to P0D0
• 4-bit input port
• K3 to K0
• Key source signal return inputs
64
78
INT
Vector interrupt pin for edge detection.
Rising or falling edge can be selected.
Input
(2) PROM programming mode (µPD17P012 only)
Pin No.
Symbol
Function
Output Format
−
64-Pin 80-Pin
4
8
3, 4
8, 9
VDD1
VDD2
Positive power supply. Supply +6 V to these pins when writing, reading,
or verifying the program memory.
12 to 13, 14,
15 16, 17
20 to 22, 24
D4 to D7
8-bit data I/O when writing, reading, or verifying the program memory.
CMOS push-pull
D0 to D3
CLK
23
to 26
25
28
Clock input to update addresses when writing, reading, or verifying the
program memory.
−
−
−
−
26, 58 30, 69,
31, 71
GND
Ground.
59 to 73 to MD3 to MD0
62 76
64 78
Input to select the operation mode when writing, reading, or verifying the
program memory.
VPP
Pin to apply the program voltage when writing, reading, or verifying the
program memory. Apply +12.5 V.
Remark Pins not listed above are not used in the PROM programming mode. For the processing of unused pins,
refer to (2) µPD17P012 (b) PROM programming mode.
20
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
1.2 Pin Equivalent Circuits
(1) P0A (P0A2/SCK1, P0A1/SO1, P0A0/SI1)
P0B (P0B3/FCG1, P0B2/FCG0, P0B1/BEEP1, P0B0/BEEP0)
P1A (P1A2, P1A1, P1A0)
(I/O)
P1D (P1D3, P1D2, P1D1, P1D0)
VDD
RESET (other than P1D)
Read instruction (P1D only)
VDD
(2) P1C (P1C3, P1C2, P1C1, P1C0)
LCD15/KS15/PYA15 to LCD0/KS0/PYA0
(Output)
LCD19/P2H0, LCD18/P2G0, LCD17/P2F0, LCD16/P2E0,
VDD
(3) P0C (P0C3, P0C2, P0C1/PWM1, P0C0/PWM0) (output)
21
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(4) P0D (P0D3/K3, P0D2/K2, P0D1/K1, P0D0/K0) (input)
V
DD
High on resistance
(5) P1B (P1B1/ADC1, P1B0/ADC0) (input)
V
DD
A/D converter
(6) P1B (P1B3/FMIFC, P1B2/AMIFC) (input)
V
DD
General-purpose port
High-on resistance
V
DD
V
DD
Frequency counter
22
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(7) CE
INT
(Schmitt trigger input)
VDD
(8) XOUT (output), XIN (input)
V
DD
High-on resistance
V
DD
XIN
Internal clock
High on
resistance
X
OUT
(9) EO (output)
V
DD
23
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(10) COM2
COM1
(Output)
COM0
V
DD
V
DD
High-on resistance
High-on resistance
(11) VCOH
VCOL
(Input)
VDD
High-on resistance
VDD
High-on
resistance
24
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
1.3 Recommended Connection of Unused Pins
The following connections are recommended for unused pins.
Table 1-1. Recommended Connection of Unused Pins
Pin Name
I/O Mode
Recommended Connection of Unused Pins
Independently connect to GND via a resistorNote 1
Independently connect to VDD or GND via a resistorNote 1
P0D0/K0 to P0D3/K3
P1B0/ADC0
Input
.
.
P1B1/ADC1
P1B2/AMIFCNotes 2, 3
P1B3/FMIFCNotes 2, 3
P1C0/P1C3
Set to P1B2 and connect to VDD or GND via a resistorNote 1
Set to P1B3 and connect to VDD or GND via a resistorNote 1
Leave open.
.
.
CMOS push-pull output
P2E0/LCD16
P2F0/LCD17
P2G0/LCD18
P2H0/LCD19
PYA0/LCD0/KS0 to
PYA15/LCD15/KS15
P0C0/PWM0
P0C1/PWM1
P0C2, P0C3
N-ch open-drain output
Set to low-level output by software, and leave open.
Set to general-purpose input port by software, and
P0A0/SI1
I/ONote 4
P0A1/SO1
independently connect to VDD or GND via a resistorNote 1
.
P0A2/SCK1
P0B0/BEEP0
P0B1/BEEP1
Notes 2, 3
P0B2/FCG0
Notes 2, 3
P0B3/FCG1
P1A0 to P1A2
P1D0 to P1D3
CE
Input
Connect to VDD via a resistorNote 1
Connect to GND via a resistorNote 1
.
INTNote 5
.
VCOH, VCOL
COM0 to COM2
EO
Disable by software, and leave open.
Leave open.
Output
Notes 1. Note that when pulling up (connecting to VDD via a resistor) or pulling down (connecting to GND via a resistor)
a pin externally using a high resistance value, the current consumption (through current) of the port
increases because the pin approaches the high-impedance state. Generally, a resistance value of several
tens of kΩ suffices for pull up and pull down, although this value depends on each application circuit.
2. This general-purpose input port has a circuit designed so that the current consumption does not increase
even in the high-impedance state.
3. Do not set this pin to AMIFC, FMIFC, FCG0 or FCG1, or the current consumption will increase.
4. These input/output ports become general-purpose input ports at power-on, clock stop, and CE reset.
5. In the µPD17P012, the INT pin functions alternately as the VPP pin for writing or verifying the program
memory. If the INT pin is not used, directly connect to GND.
25
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
1.4 Notes on Using CE and INT Pins
The CE and INT pins have a function to set a test mode (for IC test) in which the internal operations of the
µPD17012 and 17P012 are tested, in addition to the functions listed in 1.1 Pin Function List.
In the µPD17P012, the INT pin functions alternately as the VPP pin for writing or verifying the program memory.
If a voltage higher than VDD is applied to either of these pins, the test mode is set. Therefore, if noise exceeding
VDD is applied to these pins even during normal operation, the test mode may be set by mistake, affecting normal
operation.
Noise may be superimposed on these pins if the length of the wiring of these pins is too long.
Therefore, keep the wiring length as short as possible. If noise is inevitable, take noise suppression measures
by using an external component as illustrated below.
•
Connect a diode with low VF
between CE or INT and VDD
•
Connect a capacitor between CE or INT and VDD
VDD
VDD
Diode with
low V
V
DD
V
DD
F
CE, INT
CE, INT
26
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
2. PROGRAM MEMORY (ROM)
2.1 Outline of Program Memory
Figure 2-1 illustrates the program memory.
As shown in this figure, the program memory consists of program memory and a program counter.
The addresses of the program memory are specified by the program counter.
The program memory has the following two major functions.
(1) Storing programs
(2) Storing constant data
Figure 2-1. Outline of Program Memory
Program counter
Program memory
Instruction
Address
specification
Constant data
27
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
2.2 Program Memory
Figure 2-2 shows the configuration of the program memory.
As shown in this figure, the program memory has a configuration of 4,096 steps × 16 bits.
Therefore, program memory addresses are addresses 0000H to 0FFFH.
All instructions are 1-word instructions, 16 bits long, so that one instruction can be stored in one address of
the program memory.
The constant data in the program memory contents is read to the data buffer by using a table reference
instruction.
Figure 2-2. Configuration of Program Memory
0 0 0 0 H
16 bits
Page 0
0 7 F F H
0 8 0 0 H
4 K
2 K
Page 1
0 F F F H
2.3 Program Counter
Figure 2-3 shows the configuration of the program counter.
As shown in this figure, the program counter is configured as a 12-bit binary counter. The most significant
bit, b11, indicates a page.
The program counter specifies an address of the program memory.
Figure 2-3. Configuration of Program Counter
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Page
PC
28
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
2.4 Program Flow
The execution flow of the program is controlled by the program counter, which specifies an address of the
program memory.
Figure 2-4 shows the value set to the program counter when each instruction is executed.
Table 2-1 shows the vector address when an interrupt is acknowledged.
2.4.1 Branch instructions
(1) Direct branch (“BR addr”)
The branch destination address of the direct branch instruction is in the area of addresses 0000H to
0FFFH, i.e. all the addresses of the program memory.
(2) Indirect branch (“BR @AR”)
The branch destination address of the indirect branch instruction is in the area of addresses 0000H to
0FFFH, i.e. all the addresses of the program memory.
Also refer to 5.3 Address Register (AR).
2.4.2 Subroutine
(1) Direct subroutine call (“CALL addr”)
The top address of the subroutine that can be called by the direct subroutine call instruction is within page
0 (addresses 0000H to 07FFH) in the program memory.
(2) Indirect subroutine call (“CALL @AR”)
The top address of the subroutine that can be called by the indirect subroutine call instruction is in the
area of addresses 0000H to 0FFFH, i.e. all the addresses of the program memory.
Also refer to 5.3 Address Register (AR).
2.4.3 Table referencing
Addresses that can be referenced by the table reference instruction (“MOVT DBF, @AR”) are in the area of
addresses 0000H to 0FFFH, i.e. all the addresses of the program memory.
Also refer to 5.3 Address Register (AR) and 9.2.2 Table reference instruction (“MOVT DBF, @AR”).
29
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 2-4. Specification of Program Counter on Instruction Execution
Program counter
Contents of program counter (PC)
Instruction
BR addr
b
11
b10
b9
b
8
b
7
b
6
b
5
b
4
b
3
b2
b1
b
0
Page 0
Page 1
0
Instruction operand (addr)
Instruction operand (addr)
1
0
CALL addr
BR @AR
CALL @AR
Address register contents
MOVT DBF, @AR
RET
Contents of address stack register (ASR) specified
by stack pointer (SP)
RETSK
(Return address)
RETI
When interrupt is acknowledged
Vector address of each interrupt
Power-on reset, CE reset
0
0
0
0
0
0
0
0
0
0
0
0
Table 2-1. Interrupt Vector Address
Priority Internal/External
Interrupt Source
INT pin
Vector address
0004H
1
2
3
4
External
Internal
Internal
Internal
12-bit timer
0003H
0002H
0001H
Basic timer 1
Serial interface
30
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
3. ADDRESS STACK (ASK)
3.1 Outline of Address Stack
Figure 3-1 illustrates the address stack.
The address stack consists of a stack pointer and address stack registers.
The addresses of the address stack registers are specified by the stack pointer.
The address stack saves a return address when a subroutine call instruction is executed or when an interrupt
is acknowledged.
The address stack is also used when a table reference instruction is executed.
Figure 3-1. Outline of Address Stack
Stack pointer
Address stack register
Return address
Address specification
3.2 Address Stack Registers (ASR)
Figure 3-2 shows the configuration of the address stack registers.
Although there are six 12-bit address stack registers: ASR0 to ASR5, no register is assigned to ASR5, and
five 12-bit registers, ASR0 to ASR4, are used.
The address stack saves a return address when a subroutine call instruction or table reference instruction
is executed, or when an interrupt is acknowledged.
Figure 3-2. Configuration of Address Stack Registers
Stack pointer
Address stack registers (ASR)
(SP)
Bit
Address
0H
Bit
b
3
b2
b
1
b0
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0
SP2 SP1 SP0
ASR0
ASR1
ASR2
ASR3
ASR4
1H
2H
3H
4H
5H
←Cannot be used
ASR5 (undefined)
31
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
3.3 Stack Pointer (SP)
Figure 3-3 shows the configuration and function of the stack pointer.
The stack pointer is a 4-bit binary counter.
It specifies the address of an address stack register.
The value of the stack pointer can be directly read or written by using a register manipulation instruction.
Figure 3-3. Configuration and Function of Stack Pointer
Name
Flag symbol
Address
01H
Read/
write
R/W
b
3
b2
b
1
b
0
Stack pointer
SP
0
S
P
2
S
P
1
S
P
0
Specifies address of address stack register (ASR)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Address 0 (ASR0)
Address 1 (ASR1)
Address 2 (ASR2)
Address 3 (ASR3)
Address 4 (ASR4)
Address 5 (ASR5)
Fixed to “0”
Power-on
Clock stop
CE
0
1
1
1
0
0
0
1
1
1
32
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
3.4 Operation of Address Stack
3.4.1 On execution of subroutine call (“CALL addr”, “CALL @AR”) or return (“RET”, “RETSK”) instruction
When a subroutine call instruction is executed, the value of the stack pointer is decremented by one and a
return address is saved to the address stack register specified by the stack pointer.
When a return instruction is executed, the contents (return address) of the address stack register specified
by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by
one.
3.4.2 On execution of table reference instruction (“MOVT DBF, @AR”)
When a table reference instruction is executed, the value of the stack pointer is decremented by one, and
a return address is saved to the address stack register specified by the stack pointer.
Next, the contents of the program memory specified by the address register are read to the data buffer, the
contents (return address) of the address stack register specified by the stack pointer are restored to the program
counter, and then the value of the stack pointer is incremented by one.
3.4.3 On acknowledgement of interrupt and execution of return instruction (“RETI”)
When an interrupt is acknowledged, the value of the stack pointer is decremented by one, and the return
address is saved to the address stack register specified by the stack pointer.
When a return instruction is executed, the contents (return address) of the address stack register specified
by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by
one.
3.4.4 On execution of address stack manipulation instruction (“PUSH AR”, “POP AR”)
When the “PUSH” instruction is executed, the value of the stack pointer is decremented by one, and the
contents of the address register are transferred to the address stack register specified by the stack pointer.
When the “POP” instruction is executed, the contents of the address stack register specified by the stack
pointer are transferred to the address register, and the value of the stack pointer is incremented by one.
3.5 Notes on Using Address Stack
The nesting level of the address stack is 5 and the value of the address stack register (ASR5) is “undefined”
when the value of the stack pointer is 05H.
Do not use a subroutine call or interrupt exceeding level 5 without manipulating the stack; otherwise,
execution returns to an undefined address.
33
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
4. DATA MEMORY (RAM)
4.1 Outline of Data Memory
Figure 4-1 illustrates the data memory.
As shown in this figure, the data memory consists of a general-purpose data memory, system register, data
buffer, LCD segment register, and port registers.
The data memory stores data, transfers data with the peripheral hardware units, sets display data, transfers
data with the ports, and controls the CPU.
Figure 4-1. Outline of Data Memory
Peripheral hardware
Data transfer
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Data buffer
Data memory
BANK0
Port register
Port register
BANK1
BANK2
LCD segment register
Port register
System register
Data transfer
Port
Data transfer
LCD
34
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
4.2 Configuration and Function of Data Memory
Figure 4-2 shows the configuration of the data memory.
As shown in the figure, the data memory consists of banks.
Each bank consists of 128 nibbles with 7H row addresses and 0FH column addresses.
The data memory can be divided by classification of function into the blocks explained in 4.2.1 through 4.2.6
below.
The contents of the data memory can be operated, compared, judged, and transferred in 4-bit units by using
a data memory manipulation instruction.
Table 4-1 lists the available data memory manipulation instructions.
4.2.1 System register (SYSREG)
The system register is allocated to addresses 74H to 7FH.
Because the system register is allocated to every bank, the identical system register exists at addresses 74H
to 7FH of any bank.
For details, refer to 5. SYSTEM REGISTER (SYSREG).
4.2.2 Data buffer (DBF)
The data buffer is allocated to addresses 0CH to 0FH of BANK0.
For details, refer to 9. DATA BUFFER (DBF).
4.2.3 LCD segment register
The LCD segment register is allocated to addresses 5CH to 6FH of BANK2.
For details, refer to 19. LCD CONTROLLER/DRIVER.
4.2.4 Port registers
The port registers are allocated to addresses 70H to 73H of each bank.
For details, refer to 10. GENERAL-PURPOSE PORTS.
4.2.5 General-purpose data memory
The general-purpose data memory is allocated to the addresses of the data memory excluding those of the
system register, LCD segment register, and port registers.
The general-purpose data memory of the µPD17012 consists of a total of 316 nibbles (316 × 4 bits): 112
nibbles for each of BANK0 and BANK1, and 92 nibbles for BANK2.
4.2.6 Unallocated data memory
Data memory areas to which nothing is actually allocated exist in part of the port registers.
For details of these data memory areas, refer to 4.4.2 Notes on unallocated data memory and 10.
GENERAL-PURPOSE PORTS.
35
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 4-2. Configuration of Data Memory
Column address
1 2 3 4 5 6 7 8 9 A B C D E F
0
0
1
2
3
4
5
6
7
Data memory
BANK0
BANK1
BANK2
System register
Column address
0
1
2
3
4
4
4
5
5
5
6
7
8
9
A
B
C
D
E
F
0
Data buffer (DBF)
1
2
3
4
5
6
7
Example
Address 1AH
of BANK0
General register
BANK0
b3
b
2
b
1
b
0
Port register
System register (SYSREG)
0
1
2
3
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
BANK1
Port register
Same system
register exists.
System register (SYSREG)
0
1
2
3
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
BANK2
LCD segment register
Port register
System register (SYSREG)
36
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 4-1. Data Memory Manipulation Instructions
Function
Addition
Instruction
Operation
ADD
ADDC
Subtraction
Logical
SUB
SUBC
AND
OR
XOR
Compare
SKE
SKGE
SKLT
SKNE
Transfer
MOV
LD
ST
Judgement
SKT
SKF
4.3 Addressing of Data Memory
Figure 4-3 shows addressing of the data memory.
An address of the data memory is specified by a bank, a row address, and a column address.
The row and column addresses are directly specified by using a data memory manipulation instruction. The
bank is specified by the contents of the bank register.
For details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG).
Figure 4-3. Addressing of Data Memory
Bank
Row Address Column Address
b3
b2
b
1
b0
b2
b1
b
0
b
3
b2
b
1
b0
Bank
Data memory address
M
register
Instruction operand
37
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
4.4 Notes on Using Data Memory
4.4.1 On power-on reset
The contents of the general-purpose data memory are undefined on power-on reset.
Initialize the general-purpose data memory as necessary.
4.4.2 Notes on unallocated data memory
If a data memory manipulation instruction is executed to a data memory address to which nothing has been
allocated, the following operations are performed.
(1) Device operation
If a read instruction is executed, 0 is read.
Nothing is affected even if a write instruction is executed.
(2) Assembler (RA17K) operation
Assembly is performed normally.
An error does not occur.
(3) In-circuit emulator (IE-17K) operation
If a read instruction is executed, 0 is read.
Nothing is affected even if a write instruction is executed.
An error does not occur.
38
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5. SYSTEM REGISTER (SYSREG)
5.1 Outline of System Register
Figure 5-1 shows the location in the data memory and outline of the system register.
As shown in this figure, the system register is allocated to addresses 74H to 7FH of each bank of the data
memory. Therefore, an identical system register exists at addresses 74H to 7FH of any bank.
Because the system register is located in the data memory, it can be manipulated by any data memory
manipulation instruction.
The system register consists of seven registers.
Figure 5-1. Location on Data Memory and Outline of System Register
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Data memory
BANK0
BANK1
BANK2
System register
Address
Name
74H
75H
76H
77H
78H
79H
Address register
(AR)
Window register Bank register
(WR)
(BANK)
Controls program memory address.
Transfers data
Specifies bank of
Function
with register file. data memory.
Address
Name
7AH
7BH
7CH
7DH
7EH
7FH
Index register
(IX)
General register
pointer (RP)
Program status
word
Data memory row
address pointer (MP)
(PSWORD)
Function Modifies address of data memory.
Specifies address of general
register
Controls operation.
39
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.2 System Register List
Figure 5-2 shows the configuration of the system register.
Figure 5-2. Configuration of System Register
Address
Name
74H
75H
76H
77H
78H
79H
System register
Address register
(AR)
Window
register
(WR)
Bank
register
(BANK)
BANK
Symbol
AR3
AR2
AR1
AR0
WR
Bit
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
Data
0
0
0
0
0
0
Address
Name
7AH
7BH
7CH
7DH
7EH
7FH
System register
Index register (IX)
General register
pointer (RP)
Program status
word
Data memory row
(PSWORD)
PSW
address pointer (MP)
Symbol
IXH
MPH
IXM
IXL
RPH
RPL
MPL
Bit
b3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
Data
M
P
E
B
C
D
C
M
P
C
Y
Z
I
(IX)
(RP)
X
E
0
0
0
0
(MP)
40
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.3 Address Register (AR)
5.3.1 Configuration of address register
Figure 5-3 shows the configuration of the address register.
As shown in this figure, the address register consists of 16 bits, or 74H to 77H (AR3 to AR0) of the system
register. However, since the higher 4 bits are always fixed to 0, this register actually operates as a 12-bit register.
Figure 5-3. Configuration of Address Register
Address
Name
Symbol
Bit
74H
75H
76H
77H
AR0
Address register (AR)
AR3
AR2
AR1
b3
b
2
b
1
b0
b3
b
2
b
1
b0
b3
b
2
b
1
b0
b3
b2
b
1
b0
DataNote
M
S
B
L
S
B
0
0
0
0
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Clock stop
CE
Remark Power-on: Power-on reset
Clock stop: Execution of clock stop instruction
CE: CE reset
Note Bits marked as “0” are fixed to 0.
41
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.3.2 Function of address register
The address register specifies a program memory address when a table reference (“MOVT DBF, @AR”),
stack manipulation (“PUSH AR”, “POP AR”), indirect branch (“BR @AR”) or indirect subroutine call (“CALL
@AR”) instruction is executed.
A dedicated instruction (“INC AR”) that can increment the value of the address register by one is also
available.
The following paragraphs (1) through (5) explain the operations to be performed when the respective
instructions are executed.
(1) Table reference instruction (“MOVT DBF, @AR”)
This instruction reads the constant data (16-bit) of the program memory address specified by the contents
of the address register to the data buffer.
The addresses for storing constant data specified by the address register are 0000H to 0FFFH.
(2) Stack manipulation instructions (“PUSH AR”, “POP AR”)
When the “PUSH AR” instruction is executed, the value of the stack pointer is decremented by one, and
the contents of the address register (AR) are stored to the address stack register specified by the value
of the decremented stack pointer.
When the “POP AR” instruction is executed, the contents of the address stack register specified by the
stack pointer are transferred to the address register, and the value of the stack pointer is incremented
by one.
(3) Indirect branch instruction (“BR @AR”)
This instruction branches execution to the program memory address specified by the contents of the
address register.
The branch addresses specified by the address register are 0000H to 0FFFH.
(4) Indirect subroutine call instruction (“CALL @AR”)
This instruction calls the subroutine at the program memory address specified by the contents of the
address register.
The top address of the subroutine specified by the address register are 0000H to 0FFFH.
(5) Address register increment instruction (“INC AR”)
This instruction increments the contents of the address register by one.
Because the address register of the µPD17012 consists of 12 bits, its contents are cleared to 0000H if
the “INC AR” instruction is executed when the contents of the address register are 0FFFH.
5.3.3 Address register and data buffer
The address register can transfer data via the data buffer as part of the peripheral hardware.
For details, refer to 9. DATA BUFFER (DBF).
42
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.4 Window Register (WR)
5.4.1 Configuration of window register
Figure 5-4 shows the configuration of the window register.
As shown in the figure, the window register consists of 4 bits at address 78H of the system register.
Figure 5-4. Configuration of Window Register
Address
Name
78H
Window register
(WR)
Symbol
Bit
WR
b
3
b
2
b
1
b0
Data
M
S
B
L
S
B
Power-on
Undefined
Clock stop
CE
Holds previous
status
5.4.2 Function of window register
The window register is used to transfer data with the register file (RF) which is explained later.
To transfer data between the window register and register file, the dedicated instructions “PEEK WR, rf” and
“POKE rf, WR” are used (rf: address of register file).
The following paragraphs (1) and (2) explain the operations to be performed when each of these instructions
is executed.
Also refer to 8. REGISTER FILE (RF).
(1) “PEEK WR, rf” instruction
When this instruction is executed, the contents of the register file addressed by “rf” are transferred to
the window register.
(2) “POKE rf, WR” instruction
When this instruction is executed, the contents of the window register are transferred to the register file
addressed by “rf”.
43
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.5 Bank Register (BANK)
5.5.1 Configuration of bank register
Figure 5-5 shows the configuration of the bank register.
As shown in the figure, the bank register consists of 4 bits at address 79H (BANK) of the system register.
Actually, however, this register is a 2-bit register because the higher 2 bits are always fixed to 0.
Figure 5-5. Configuration of Bank Register
Address
Name
79H
Bank register
(BANK)
Symbol
Bit
BANK
b
3
b
2
b
1
b0
Data
0
0
M
S
B
L
S
B
Power-on
0
0
0
Clock stop
CE
5.5.2 Function of bank register
The bank register specifies a bank of the data memory.
Table 5-1 shows the relationship between the value of the bank register and the bank of the data memory
specified by each value of the bank register.
Because the bank register exists on the system register, its contents can be rewritten no matter which bank
may be currently specified.
In other words, the bank register can be manipulated independently of the current status of the bank.
Table 5-1. Specifying Bank of Data Memory
Bank Register
(BANK)
Data Memory
Bank
b3
b
2
b
1
b
0
0
0
0
0
BANK0
0
0
0
0
0
0
0
1
1
1
0
1
BANK1
BANK2
Setting prohibited
44
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer)
5.6.1 Configuration of index register and data memory row address pointer
Figure 5-6 shows the configuration of the index register and data memory row address pointer.
As shown in the figure, the index register consists of an index register (IX) and an index enable flag (IXE).
IX is an 11-bit register consisting of the lower 3 bits (IXH) of system register address 7AH, and addresses 7BH
and 7CH (IXM and IXL). IXE is the least significant bit of address 7FH (PSW).
The data memory row address pointer (memory pointer) consists of a data memory row address pointer, which
consists of 7 bits with the lower 3 bits of address 7AH (MPH) and address 7BH (MPL), and a data memory row
address pointer enable flag (memory pointer enable flag: MPE), which is the most significant bit of address 7AH
(MPH).
In other words, the higher 7 bits of the index register are shared with the data memory row address pointer.
Note, however, that the higher 2 bits of the index register and data memory row address pointer (bits b2 and
b1 of address 7AH) are always fixed to 0.
Figure 5-6. Configuration of Index Register and Data Memory Row Address Pointer
Address
Name
7AH
7BH
7CH
7EH
7FH
Program status word
(PSWORD)
Index register (IX)
Memory pointer (MP)
IXH
MPH
IXM
MPL
IXL
PSW
Symbol
b3 b2 b1 b0
b3 b2 b1 b0
b3 b2 b1 b0
b3 b2 b1 b0
b3 b2 b1 b0
Bit
Data
0
0
M
P
E
M
S
B
L
S
B
I
X
E
IX
M
S
B
L
S
B
MP
Power-on
0
0
0
0
0
0
0
0
0
0
0
0
Clock stop
CE
45
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.6.2 Functions of index register and data memory row address pointer
The index register and data memory row address pointer modify the addresses of the data memory.
The following paragraphs (1) and (2) explain the functions of the index register and data memory row address
pointer, respectively.
A dedicated instruction (“INC IX”) that can increment the value of the address register by one is also available.
For details on address modification, refer to 7. ALU (Arithmetic Logic Unit) BLOCK.
(1) Index register
The index register modifies a specified data memory address according to the contents of the index
register when a data memory manipulation instruction is executed.
This modification, however, is valid only when the IXE flag is set to 1.
To modify an address, the bank, row address, and column address of the data memory are ORed with
the contents of the index register, and the instruction is executed to the data memory whose address
(called an actual address) is specified by the result of this OR operation.
All the data memory manipulation instructions are subject to address modification by the index register.
The following instructions are not subject to modification by the index register.
INC
AR
RORC r
CALL addr
CALL @AR
RET
INC
IX
MOVT
PUSH
POP
PEEK
POKE
GET
PUT
BR
DBF, @AR
AR
AR
RETSK
RETI
WR, rf
rf, WR
DBF, p
p, DBF
addr
EI
DI
STOP s
HALT h
NOP
BR
@AR
(2) Data memory row address pointer
The data memory row address pointer modifies the address at the indirect transfer destination when a
general register indirect transfer instruction (“MOV @r, m” or “MOV m, @r”) is executed.
However, this modification is valid only when the MPE flag is set to 1.
To modify the address, the bank and row address at the transfer destination are replaced with the
contents of the data memory row address pointer.
Instructions other than general register indirect transfer instructions are not subject to address
modification.
(3) Index register increment instruction (“INC IX”)
This instruction increments the contents of the index register by one.
Because the index register is configured from 9 bits, the contents of the index register are cleared to 000H
if the INC IX instruction is executed when the contents of the index register are 1FFH.
46
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.7 General Register Pointer (RP)
5.7.1 Configuration of general register pointer
Figure 5-7 shows the configuration of the general register pointer.
As shown in this figure, the general register pointer consists of 7 bits: 4 bits of address 7DH (RPH) of the
system register and the higher 3 bits of address 7EH (RPL). However, because the higher 2 bits of address
7DH are always fixed to 0, actually the lower 5 bits of this register (the lower 2 bits of address 7DH and the higher
3 bits of address 7EH) are valid.
Figure 5-7. Configuration of General Register Pointer
Address
Name
7DH
7EH
General register pointer
(RP)
Symbol
Bit
RPH
RPL
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
Data
M
S
B
L
S
B
B
C
D
0
0
Power-on
0
0
0
0
0
0
Clock stop
CE
47
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.7.2 Function of general register pointer
The general register pointer specifies a general register in the data memory.
Figure 5-8 shows the address of the general register specified by the general register pointer.
As shown in the figure, the higher 4 bits of the general register pointer (RPH: address 7DH) specify a bank,
and the lower 3 bits (RPL: address 7EH) specify a row address.
Because the valid number of bits of the general register pointer is 5, the row addresses (0H to 7H) of BANK0
and BANK1 can be specified as general registers.
For details on the operations of the general registers, refer to 6. GENERAL REGISTER (GR).
Figure 5-8. Address of General Register Specified by General Register Pointer
General register pointer
(RP)
RPH
RPL
b3
b2
b
1
b
0
b
3
b
2
b
1
b
0
0
0
M
S
B
L
S
B
B
C
D
Specifies row address of each bank
Specifies bank
Bank
Row address
0H
1H
2H
0
0
0
0
0
0
0
0
0
1
0
BANK0
0
0
0
0
0
1
3H
4H
5H
0
0
0
1
1
1
0
1
1
1
0
0
1
0
1
BANK1
BANK2
6H
7H
1
1
0
0
1
1
1
1
0
1
5.7.3 Notes on using general register pointer
The least significant bit of address 7EH (RPL) to which the general register pointer is allocated is used as
the BCD flag of the program status word.
When rewriting the value of RPL, therefore, pay attention to the value of the BCD flag.
48
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.8 Program Status Word (PSWORD)
5.8.1 Configuration of program status word
Figure 5-9 shows the configuration of the program status word.
As shown in the figure, the program status word consists of 5 bits: the least significant bit of address 7EH
(RPL) of the system register and the 4 bits of the address 7FH (PSW).
The program status word consists of five flags, each of which functions independently: BCD (BCD), compare
(CMP), carry (CY), zero (Z), and index enable (IXE) flags.
Figure 5-9. Configuration of Program Status Word
Address
Name
7EH
(RP)
7FH
Program status word
(PSWORD)
Symbol
Bit
RPL
PSW
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
Data
B
C
D
C
M
P
C
Y
Z
I
X
E
Power-on
0
0
0
0
0
0
Clock stop
CE
49
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
5.8.2 Function of program status word
The program status word is a register that sets the condition of an operation or transfer instruction of the ALU
(Arithmetic Logic Unit) or indicates the result of an executed operation.
Table 5-2 outlines the function of each flag of the program status word.
For details, refer to 7. ALU (Arithmetic Logic Unit) BLOCK.
Table 5-2. Functional Outline of Program Status Word
(RP)
Program status word
(PSWORD)
PSW
RPL
b3
b2
b1
b0
b3
b
2
b
1
b0
B
C
D
C
M
P
C
Y
Z
I
X
E
Flag Name
Function
Index enable flag
(IXE)
This flag modifies the address of the data memory when a data
memory manipulation instruction is executed.
0: No modification
1: Modification
Zero flag
(Z)
This flag indicates that the result of an arithmetic operation
executed is 0.
Note that the status of 0 or 1 differs depending on the contents of the
compare flag.
Carry flag
(CY)
This flag indicates the occurrence of a carry or borrow as a result of
execution of an addition or subtraction instruction.
It is reset to 0 if a carry/borrow does not occur; it is set to 1 if a
carry/borrow occurs.
This flag is also used as the shift bit of the “RORC r” instruction.
This flag is used avoid storing the result of an arithmetic operation to
the data memory or general register.
Compare flag
(CMP)
0: Result stored
1: Result not stored
BCD flag
(BCD)
This flag is used to execute an arithmetic operation in decimal.
0: Binary operation executed
1: Decimal operation executed
5.8.3 Notes on using program status word
If an arithmetic operation (addition or subtraction) instruction is executed for the program status word, the
result of the arithmetic operation is stored in the program status word.
For example, even if an operation that causes a carry to occur is executed, if the result of the operation is
0000B, 0000B is stored in the PSW.
5.9 Notes on Using System Register
The data of the system register fixed to 0 is not affected even if a write instruction is executed to it.
This data is always 0 when it is read.
50
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
6. GENERAL REGISTER (GR)
6.1 Outline of General Register
Figure 6-1 illustrates the general register.
As shown in the figure, the general register consists of a general register pointer and general register body.
The bank and row address of the general register body are specified by the general register pointer.
The general register body is used to transfer data and execute operations between data memory addresses.
Figure 6-1. Outline of General Register
Column address
Data memory
General register
General register
pointer
Transfer, operation
BANK0
BANK1
BANK2
System register
6.2 General Register Body
The general register body consists of 16 nibbles (16 × 4 bits) at the same row addresses in the data memory.
For the range of the banks and row addresses that can be specified by the general register pointer and general
register, refer to 5.7 General Register Pointer (RP).
The 16 nibbles of the same row address specified as a general register executes operations and transfers
data with the data memory using a single instruction.
In other words, operations or transfer between data memory addresses can be executed with a single
instruction.
The general register can be controlled by a data memory manipulation instruction like the other data memory
areas.
51
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
6.3 Address Generation of General Register by Instructions
The following subsections 6.3.1 and 6.3.2 explain how the addresses of the general register are generated
when each instruction is executed.
For details of the operation of each instruction, refer to 7. ALU (Arithmetic Logic Unit) BLOCK.
6.3.1 Addition (“ADD r, m”, “ADDC r, m”),
subtraction (“SUB r, m”, “SUBC r, m”),
logical operation (“AND r, m”, “OR r, m”, “XOR r, m”),
direct transfer (“LD r, m”, “ST m, r”),
and rotation processing (“RORC r”) instructions
Table 6-1 shows the address of general register “R” specified by operand “r” of an instruction. Only the column
address is specified as operand “r”.
Table 6-1. Address Generation of General Register
Bank
Row Address Column Address
b3
b2
b
1
b0
b2
b1
b
0
b
3
b2
b
1
b0
Contents of general
register pointer
General register address
R
r
6.3.2 Indirect transfer (“MOV @r,m”, “MOV m, @r”) instructions
Table 6-2 shows the address of the general register “R” specified by operand “r” of an instruction and an
indirect transfer address specified by “@R”.
Table 6-2. Address Generation of General Register
Bank
Row Address Column Address
b3
b2
b
1
b0
b2
b1
b
0
b
3
b2
b
1
b0
Contents of general
register pointer
General register address
Indirect transfer address
R
r
@R
Same as data memory
Contents of R
52
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
6.4 Notes on Using General Register
6.4.1 Row address of general register
Note that because the row address of the general register is specified by the general register pointer, the
bank currently specified may differ from the bank of the general register.
6.4.2 Operation between general register and immediate data
No instruction that executes an operation between the general register and immediate data is provided.
To execute an operation between the general register and immediate data, the general register must be
treated as a data memory area.
53
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
7. ALU (Arithmetic Logic Unit) BLOCK
7.1 Outline of ALU Block
Figure 7-1 outlines the ALU block.
As shown in the figure, the ALU block consists of an ALU, temporary registers A and B, a program status
word, decimal adjuster, and data memory address controller.
The ALU operates, judges, compares, rotates, and transfers 4-bit data in the data memory.
Figure 7-1. Outline of ALU Block
Data bus
Address
control
Temporary
register A
Temporary
register B
Program status word
Carry/borrow/
zero detection/decimal/
storage specification
Index modification
memory pointer
ALU
• Arithmetic operation
• Logical operation
• Bit judgment
• Comparison
• Rotation processing
• Transfer
Data memory
Decimal adjustment
54
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
7.2 Configuration and Function of Each Block
7.2.1 ALU
The ALU executes arithmetic or logical operations, bit judgment, comparison, rotation processing, and
transfer of 4-bit data according to an instruction specified by the program.
7.2.2 Temporary registers A and B
Temporary registers A and B temporarily store 4-bit data.
These registers are automatically used when an instruction is executed and are not controlled by the program.
7.2.3 Program status word
The program status word controls the operation of the ALU and stores the status of the ALU.
For details of the program status word, refer to 5.8 Program Status Word (PSWORD).
7.2.4 Decimal adjuster
If the BCD flag of the program status word is set to 1 as a result of an executed arithmetic operation, the
arithmetic operation result is converted into a decimal number by the decimal adjuster.
7.2.5 Address controller
The address controller specifies an address of the data memory.
At this time, address modification by the index register and data memory row address pointer is also
controlled.
7.3 ALU Processing Instruction List
Table 7-1 lists the ALU operations when each instruction is executed.
Table 7-2 shows modification of data memory addresses by the index register and data memory row address
pointer.
Table 7-3 shows the decimal adjustment data when a decimal operation is executed.
55
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 7-1. List of ALU Processing Instruction Operations
ALU
Instruction
Difference in Operation Based on Program Status Word (PSWORD)
Address Modification
Function
Value of Value of
BCD Flag CMP Flag
Arithmetic
Operation
Operation of
CY Flag
Operation of Z Flag
Index
Memory
Pointer
Addition
ADD
r, m
0
0
Stores result of Set if carry or
binary operation. borrow occurs;
Set if result of operation
Executed
Not
m, #n4
r, m
is 0000B; otherwise, reset.
executed
ADDC
0
1
Does not store
otherwise, reset. Holds status if result of
m, #n4
result of binary
operation.
operation is 0000B;
otherwise, reset.
Subtrac-
tion
SUB
r, m
1
1
0
1
Stores result of
decimal operation.
Set if result of operation is
0000B; otherwise, reset.
m, #n4
r, m
SUBC
Does not store
result of decimal
operation.
Holds status if result of
operation is 0000B; otherwise,
reset.
m, #n4
Logical
OR
r, m
Any
Any
Not affected
Holds previous
status.
Holds previous status.
Executed
Not
operation
m, #n4
r, m
(held)
(held)
executed
AND
XOR
m, #n4
r, m
m, #n4
m, #n
m, #n
m, #n4
m, #n4
m, #n4
m, #n4
r, m
Judgment SKT
SKF
Any
Any
Not affected
Not affected
Holds previous
status.
Holds previous status.
Holds previous status.
Executed
Executed
Not
(held) (reset)
executed
Not
Compare SKE
Any
Any
Holds previous
status.
SKNE
(held)
(held)
executed
SKGE
SKLT
LD
Transfer
Any
Any
Not affected
Holds previous
status
Holds previous status
Executed
Not
ST
m, r
(held)
(held)
executed
MOV
m, #n4
@r, m
Executed
Not
m, @r
r
Rotation RORC
Any
Any
Not affected
Value of general Holds previous value
register b0
Not
(held) (held)
executed executed
56
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 7-2. Modification of Data Memory Address and Modification of Indirect Transfer
Address by Index Register and Data Memory Row Address Pointer
IXE MPE General Register Address Specified by r Data Memory Address Specified by m Indirect Transfer Address Specified by @r
Bank
Row
Column
Address
Bank
Row
Column
Address
Bank
Row
Column
Address
Address
Address
Address
b
3
b
2
b
1
b
0
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
2
b
1
b
0
b
3
b
2
b
1
b
0
0
0
1
1
0
1
0
1
RP
r
BANK
m
BANK
m
R
(r)
ditto
ditto
ditto
MP
(r)
BANK
m
BANK
m
R
Logical
OR
Logical
OR
IX
IXH, IXM
(r)
(r)
ditto
ditto
MP
BANK:
IX:
Bank register
Index register
Index enable flag
IXE:
IXH:
IXM:
IXL:
m:
Bits 10 through 8 of index register
Bits 7 through 4 of index register
Bits 3 through 0 of index register
Data memory address indicated by mR, mC
Data memory row address (higher)
Data memory column address (lower)
Data memory row address pointer
mR:
mC:
MP:
MPE: Memory pointer enable flag
General register column address
r:
RP:
(x):
x:
General register pointer
Contents addressed by x
Direct address such as m and r
57
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 7-3. Decimal Adjustment Data
Operation Result
Hexadecimal Addition
Decimal Addition
Operation Result
Hexadecimal Subtraction Decimal Subtraction
CY Operation Result CY Operation Result
CY Operation Result CY Operation Result
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000B
0001B
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000B
0001B
1
2
0010B
2
0010B
3
0011B
3
0011B
4
0100B
4
0100B
5
0101B
5
0101B
6
0110B
6
0110B
7
0111B
7
0111B
8
1000B
8
1000B
9
1001B
9
1001B
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0000B
10
11
12
13
14
15
–16
–15
–14
–13
–12
–11
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
1100BNote
1101BNote
1110BNote
1111BNote
1100BNote
1101BNote
1110BNote
1111BNote
1100BNote
1101BNote
1110BNote
1111BNote
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1110BNote
1111BNote
1100BNote
1101BNote
1110BNote
1111BNote
1100BNote
1101BNote
1010BNote
1011BNote
1100BNote
1101BNote
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
Note The operation results are not correctly adjusted by the decimal adjustment circuit.
58
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
7.4 Notes on Using ALU
7.4.1 Notes on using operations for program status word
If an arithmetic operation is executed for the program status word, the result of the arithmetic operation is
stored in the program status word.
The CY and Z flags of the program status word are set or reset depending on the result of the arithmetic
operation. If an arithmetic operation is executed on the program status word itself, the result of the operation
is stored in the program status word, which makes it impossible to judge occurrence of a carry or a borrow, or
whether the result of the operation is zero.
If the CMP flag is set, however, the result of the operation is not stored in the program status word, and the
CY and Z flags are set or reset normally.
7.4.2 Notes on using decimal operations
A decimal operation can be executed only if the result falls within the following range:
(1) Result of addition:
0 to 19 in decimal
(2) Result of subtraction: 0 to 9 or –10 to –1 in decimal
If a decimal operation is executed exceeding this range, the CY flag is set, and the result is a value greater
than 1010B (0AH).
59
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
8. REGISTER FILE (RF)
8.1 Outline of Register File
Figure 8-1 illustrates the register file.
As shown in the figure, the register file consists of control registers existing on a space different from that
of the data memory, and a portion overlapping the data memory.
The control registers set the conditions of the peripheral hardware units.
Data is read from or written to the register file via the window register.
Figure 8-1. Outline of Register File
Register file
0
1
2
3
4
5
6
7
Peripheral hardware
Control registers
(separate space from data memory)
(Space same as data memory)
Data is manipulated via window register
System register
Window register
60
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
8.2 Configuration and Function of Register File
Figure 8-2 shows the configuration of the register file and its relationship with the data memory.
Addresses are allocated to the register file in 4-bit units, like the data memory, and the register file has a total
of 128 nibbles with row addresses 0H to 7H and column addresses 0H to 0FH.
Control registers that set the conditions of the peripheral hardware units are allocated to addresses 00H to
3FH.
Addresses 40H to 7FH overlap the data memory.
To put it another way, the addresses 40H to 7FH of the register file are the memory addresses of the data
memory bank currently selected.
These addresses, 40H to 7FH, can be treated in the same manner as the normal data memory areas, except
that they can be manipulated by a register file manipulation instruction (“PEEK WR, rf” or “POKE rf, WR”),
because they overlap the data memory.
Figure 8-2. Configuration of Register File and Its Relationship with Data Memory
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Data memory
BANK0
BANK1
BANK2
System register
0
1
2
3
Control register
Register file
61
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
8.3 Register File Manipulation Instructions (“PEEK WR, rf” and “POKE rf, WR”)
Data is read from or written to the register file via the window register in the system register by using a register
file manipulation instruction (“PEEK WR, rf” or “POKE rf, WR”). The operation of each instruction is explained
below.
(1) “PEEK WR, rf”
This instruction reads the data of the register file addressed by “rf” to the window register.
(2) “POKE rf, WR”
This instruction writes the data of the window register to the register file addressed by “rf”.
8.4 Control Registers
Figure 8-3 shows the configuration of the control registers.
As shown in this figure, a total of 64 nibbles (64 words × 4 bits) at addresses 00H to 3FH of the register file
can be used as control registers.
Of these nibbles, however, 33 nibbles are actually used. The remaining 31 nibbles are unused registers that
are prohibited from being read or written.
Each control register has an attribute of 1 nibble, and is classified into four types: read/write (R/W), read-
only (R), write-only (W), and read-and-reset (R & Reset).
Nothing is changed even if data is written to a read-only (R and R & Reset) register.
An undefined value is read if a write-only (W) register is read.
Of the 4-bit data in 1 nibble, the bit fixed to 0 is always 0 when it is read or written.
The 31 nibbles of unused registers are undefined when they are read, and nothing is changed when data is
written to them.
62
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 8-3. Configuration of Control Registers (1/2)
Column Address
Row
Item
0
1
2
3
4
5
6
7
Address
0
Name
Stack
pointer
(SP)
Serial I/O
mode select
register
I/F count
gate judge
register
PLL unlock A/D converter
CE pin
FF judge
register
compare
level judge
(8)Note
judge register register
Symbol
0
S
I
S
I
S
I
S
I
0
0
0
I
0
0
0
P
L
0
0
0
A
D
C
C
M
P
0
0
0
C
E
S
P
2
S
P
1
S
P
0
F
C
G
O
1
T
S
O
1
H
I
O
1
C
K
1
O
1
C
K
0
L
U
L
Z
Read/
write
R/W
R/W
R
R & Reset
R
R
1
Name
LCD mode
select
LCD port
select
IF counter
mode select select
register register
PWM mode A/D converter
BEEP
select
register
Key input
judge
Basic timer
0 carry FF
channel
(9)Note
register
register
select register
register
judge register
Symbol
0
K
S
E
N
L
C
D
E
N
P
Y
A
S
E
L
P
2
P
2
P
2
P
2
I
I
I
I
0
0
P
P
0
0
A
D
C
C
H
1
A
D
C
C
H
0
0
0
B
E
E
P
1
B
E
E
P
0
0
0
0
K
E
Y
J
0
0
0
B
T
F
C
F
C
M
D
0
F
C
C
K
1
F
C
C
K
0
W W
H
S
E
L
G
S
E
L
F
S
E
L
E
M
1
M
0
M
0
S M
E
L
D
1
S
E
L
S
E
L
C
Y
S
E
L
S
E
L
Read/
write
R/W
R/W
R/W
R/W
R/W
R/W
R & Reset
R & Reset
2
Name
PLL mode
select
IF counter FCG channel BEEP clock
Port 1D
control
select
select
group I/O
(A)
register
register
register
register
select register
Symbol
0
0
P
L
P
L
0
0
I
I
0
0
F
C
G
C
H
1
F
C
G
C
H
0
B
E
E
P
1
B
E
E
P
1
B
E
E
P
0
B
E
E
P
0
0
0
0
P
1
F
C
S
T
R
T
F
C
R
E
S
L
L
D
G
I
M
D
1
M
D
0
C
K
1
C
K
0
C
K
1
C
K
0
O
Read/
write
R/W
W
R/W
R/W
R/W
3
Name
PLL reference
clock select
register
Port 1A bit
I/O select
register
Port 0B bit
I/O select
register
Port 0A bit
I/O select
register
(B)Note
Symbol
P
L
P
L
P
L
P
L
0
P
1
A
B
I
P
1
A
B
I
P
1
A
B
I
P
0
B
B
I
P
0
B
B
I
P
0
B
B
I
P
0
B
B
I
0
P
0
A
B
I
P
0
A
B
I
P
0
A
B
I
L
L
L
L
R
F
C
K
3
R
F
C
K
2
R
F
C
K
1
R
F
C
K
0
O
2
O
1
O
0
O
3
O
2
O
1
O
0
O
2
O
1
O
0
Read/
write
R/W
R/W
R/W
R/W
Note Addresses in parentheses are for when an assembler (RA17K) is used.
63
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 8-3. Configuration of Control Registers (2/2)
8
9
A
B
C
D
E
F
Basic timer
clock select
register
12-bit timer 12-bit timer 12-bit timer
clock select overflow
register register
control
register
B
T
M
1
B
T
M
1
B
T
M
0
B
T
M
0
0
0
0
T
M
C
K
0
0
0
T
M
O
V
F
0
T
M
R
P
T
T
T
M
E
M
R
E
S
N
C
K
1
C
K
0
C
K
1
C
K
0
R/W
R/W
R
R/W
Interrupt
edge select
register
0
0
0
I
E
G
R/W
Interrupt
enable
register
I
P
S
I
I
I
I
P
B
T
M
1
P
T
M
P
O
1
R/W
Interrupt
request
Interrupt
request
Interrupt
request
Interrupt
request
register 4
register 3
register 2
register 1
0
0
0
I
0
0
0
I
0
0
0
I
I
0
0
I
R
Q
S
I
R
Q
B
T
R
Q
T
N
T
R
Q
M
O
1
M
1
R/W
R/W
R/W
R
R/W
64
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 8-1. Peripheral Hardware Control Functions of Control Registers (1/4)
Control Register
Peripheral Hardware Control Function
After Reset
b
b
b
b
3
2
1
0
S
T
C
E
Set Value
Read/
Address
Name
Functional Outline
Write
O
P
0
1
0
Port 1D
group I/O
select
– – – – – – – – –
0
Fixed to 0
– – – – – – – – –
27H
35H
36H
37H
1FH
2FH
3CH
3DH
3EH
R/W
0
0
0
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
register
P1DGIO
I/O setting of port 1D (Group I/O)
Input
Output
0
Fixed to 0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Port 1A
bit I/O
P1ABIO2
R/W – – – – – – – – –
select
P1ABIO1
– – – – – – – – –
P1A
P1A
P1A
P0B
P0B
P0B
P0B
2
1
0
3
2
1
0
pin
pin
pin
pin
pin
pin
pin
register
P1ABIO0
P0BBIO3
– – – – – – – – –
I/O setting (bit I/O)
Input
Output
0
0
0
Port 0B
bit I/O
P0BBIO2
– – – – – – – – –
R/W
select
P0BBIO1
– – – – – – – – –
register
P0BBIO0
0
Fixed to 0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Port 0A
bit I/O
P0ABIO2
R/W – – – – – – – – – P0A
2
1
0
pin
pin
pin
select
P0ABIO1
– – – – – – – – –
P0A
P0A
I/O setting (bit I/O)
Input
Output
0
0
0
0
0
0
register
P0ABIO0
0
– – – – – – – – –
Interrupt
edge select
register
0
Fixed to 0
R/W – – – – – – – – –
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IEG
Sets interrupt issuance edge (INT)
Rising edge
Falling edge
IPSIO1
– – – – – – – – –
Serial interface
Basic timer 1
R/W – – – – – – – – – 12-bit timer
Interrupt
enable
IPBTM1
Disables
interrupt
Enables
Interrupt
Enables interrupt
0
0
0
0
0
0
0
0
0
0
0
0
IPTM
– – – – – – – – –
INT pin
register
IP
0
– – – – – – – – –
Interrupt
request
0
Fixed to 0
– – – – – – – – –
R/W
R/W
R/W
0
register 4
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IRQSIO1
Detects interrupt request (serial interface)
Not requested
Requested
0
– – – – – – – – –
Interrupt
request
0
Fixed to 0
– – – – – – – – –
0
register 3
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IRQBTM1
Detects interrupt request (basic timer 1)
Not requested
Requested
0
– – – – – – – – –
Interrupt
request
0
Fixed to 0
– – – – – – – – –
0
register 2
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IRQTM
Detects interrupt request (12-bit timer)
Not requested
Requested
65
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 8-1. Peripheral Hardware Control Functions of Control Registers (2/4)
Control Register
Peripheral Hardware Control Function
After Reset
b
b
b
b
3
2
1
0
S
T
C
E
Set Value
Read/
Address
Name
Functional Outline
Write
O
P
0
1
R
INT
Detects status of INT pin
Low level
High level
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Interrupt
request
0
– – – – – – – – –
3FH
09H
0CH
0DH
0EH
17H
06H
14H
13H
Fixed to 0
0
0
0
0
0
0
0
0
0
0
0
1
0
R/W
0
register 1
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IRQ
Detects interrupt request (INT pin)
Not requested
Requested
BTM1CK1
– – – – – – – – –
0
0
1
0
1
1 ms
Sets clock of basic timer 1
100 ms 250 ms
5 ms
Basic timer
clock select
register
BTM1CK0
0
1
1
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
R/W
BTM0CK1
– – – – – – – – –
0
0
1
1
1 ms
Sets clock of basic timer 0
100 ms 250 ms
5 ms
BTM0CK0
0
1
0
1
0
– – – – – – – – –
12-bit timer
clock select
register
0
Fixed to 0
– – – – – – – – –
R/W
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
TMCK
Sets clock of 12-bit timer
50 µs
10 µs
0
– – – – – – – – –
12-bit timer
overflow
register
0
Fixed to 0
– – – – – – – – –
0
R
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
TMOVF
Detects overflow of timer/counter
No overflow
Overflow
0
Fixed to 0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
12-bit timer
control
TMRPT
R/W – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
TMRES Resets timer/counter Does not reset Resets
Selects operation mode of 12-bit timer
Free-run count mode
Modulo count mode
register
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
TMEN
Sets operation of timer/counter
Does not operate
Operates
0
Basic timer 0
carry FF
judge
– – – – – – – – –
0
– – – – – – – – –
0
R&
Reset
Fixed to 0
1
register
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
BTM0CY
Detects status of carry FF
Reset
Set
0
A/D
– – – – – – – – –
0
– – – – – – – – –
0
converter
compare
judge
Fixed to 0
R
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
ADCCMP
register
Detects comparison result
V
ADCIN < VREF
VADCIN > VREF
0
A/D
– – – – – – – – –
0
Fixed to 0
converter
channel
select
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
R/W
R/W
3
0
3
0
3
ADCCH1
– – – – – – – – –
0
ADC
0
0
ADC
1
1
1
Selects pins to be used for A/D converter
0
1
Not used Not used
register
ADCCH0
0
1
0
– – – – – – – – –
Fixed to 0
PWM mode
select
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
PWM1SEL
– – – – – – – – –
PWM
1
pin
General-
purpose
register
Set for D/A converter
D/A converter
PWM0SEL
PWM
0
pin
output port
66
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 8-1. Peripheral Hardware Control Functions of Control Registers (3/4)
Control Register
Peripheral Hardware Control Function
After Reset
b
b
b
b
3
2
1
0
S
T
C
E
Set Value
Read/
Address
Name
Functional Outline
Write
O
P
0
1
SIO1TS
Starts/stops operation
Stops operation Starts operation
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
General-purpose
Serial I/O
mode select
register
SIO1HIZ
Sets SO
1
pin as serial output pin
Serial output
I/O port
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
02H
R/W
0
0
0
0
0
1
1
SIO1CK1
External 37.5 kHz
clock
75 kHz
450 kHz
– – – – – – – – –
Sets clock of serial interface
SIO1CK0
0
1
0
1
0
– – – – – – – – –
PLL unlock
FF judge
register
0
Fixed to 0
– – – – – – – – –
05H R&Reset
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
PLLUL
Detects status of unlock FF
Lock status
Unlock status
0
– – – – – – – – –
Fixed to 0
0
PLL mode
select
21H
31H
04H
12H
23H
24H
15H
R/W – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
0
F
0
0
0
3
0
0
F
0
0
0
3
0
PLLMD1
– – – – – – – – –
0
0
1
1
register
Sets division method of PLL
Disable
MF
VHF
HF
PLLMD0
0
1
0
1
PLLRFCK3
– – – – – – – – –
0: 1.25 kHz, 1: 2.5 kHz, 2: 5 kHz,
3: 10 kHz, 4: 6.25 kHz,
5: 12.5 kHz, 6: 25 kHz, 7: 50
kHz, 8: 3 kHz, 9, A, B: Setting
prohibited, C:1kHz, D:9kHz, E:
100 kHz, F: Off
PLL
PLLRFCK2
– – – – – – – – –
PLLRFCK1
– – – – – – – – –
PLLRFCK0
reference
clock select
register
R/W
Sets reference frequency of PLL
0
– – – – – – – – –
IF counter
gate judge
register
0
Fixed to 0
– – – – – – – – –
R
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IFCG
Detects opening/closing of gate of frequency counter
Close
Open
0
FCG
0
1
1
IFCMD1
AMIFC pin
AMIF mode
FMIFC pin
FMIFC pin
– – – – – – – – – Sets mode of frequency counter
FMIF mode AMIF mode
IF counter
mode select
register
IFCMD0
0
1
0
1
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
R/W
0
0
1
1
IFCCK1
– – – – – – – – –
IFCCK0
1 ms
4 ms
8 ms
Open
Sets gate time of frequency counter
1 kHz 100 kHz 900 kHz
0
1
0
1
0
– – – – – – – – – Fixed to 0
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IF counter
control
W
IFCSTRT
Starts counting of IF counter
Does not start
Starts
register
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
IFCRES
Resets IF counter
Does not reset
Resets
0
FCG
– – – – – – – – –
0
Fixed to 0
channel
select
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
R/W
R/W
0
0
1
1
FCGCH1
– – – – – – – – –
FCG
0
FCG
1
Not
Not
Sets pin to be used as FCG
register
used used
1
FCGCH0
0
1
0
0
– – – – – – – – –
Fixed to 0
0
BEEP select
register
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
0
BEEP1SEL BEEP
– – – – – – – – –
1
pin
General-
purpose
I/O port
Set as BEEP
BEEP
BEEP0SEL BEEP
0
pin
67
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 8-1. Peripheral Hardware Control Functions of Control Registers (4/4)
Control Register
Peripheral Hardware Control Function
After Reset
b
b
b
b
3
2
1
0
S
T
C
E
Set Value
Read/
Address
Name
Functional Outline
Write
O
P
0
1
0
0
0
1
1
BEEP1CK1
– – – – – – – – –
BEEP1CK0
1 kHz 3 kHz 200 Hz 9 kHz
Sets output frequency of BEEP
1
BEEP clock
select
1
0
1
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
25H
10H
11H
R/W
0
0
0
0
1
1
BEEP0CK1
register
– – – – – – – – –
1 kHz 3 kHz 200 Hz 9 kHz
Sets output frequency of BEEP
0
0
1
0
1
BEEP0CK0
0
Fixed to 0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Key source off Key source on
R/W – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
LCD mode
select
KSEN
Sets key source output signal
LCDEN
Sets LCD display output
Display off
Display on
register
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
PYASEL
0
0
P2HSEL
– – – – – – – – –
PYA
0
-PYA15 pins
P2H
0
pin
pin
pin
pin
Set as general-
purpose output
port
General-
purpose
output port
LCD port
select
P2GSEL
– – – – – – – – –
P2G
0
LCD segment
R/W
P2F
P2E
0
P2FSEL
– – – – – – – – –
0
register
P2ESEL
0
– – – – – – – – –
Key input
judge
0
Fixed to 0
– – – – – – – – –
16H R&Reset
0
0
0
register
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
KEYJ
Detects if key input latch is valid
Latch invalid
Latch valid
0
– – – – – – – – –
CE pin level
judge
0
Fixed to 0
– – – – – – – – –
07H
R
–
–
–
register
0
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
CE
Detects status of CE pin
Low level
High level
Remark –: Determined according to the status of the pin.
8.5 Notes on Using Register File
Note the following points (1) through (3) when manipulating the write-only registers (W), read-only registers
(R), and unused registers of the control registers (addresses 00H to 3FH of the register file).
(1) When a write-only register is read, an undefined value is read.
(2) Nothing is changed even if data is written to a read-only register.
(3) An undefined value is read if an unused register is read. Nothing is changed even if data is written to an unused
register.
68
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
9. DATA BUFFER (DBF)
9.1 Outline of Data Buffer
Figure 9-1 illustrates the data buffer.
The data buffer is located in the data memory and has the following two functions:
(1) Reads constant data from program memory (table reference)
(2) Transfers data with peripheral hardware unit
Figure 9-1. Outline of Data Buffer
Data buffer
Data write (PUT)
Table reference
(MOVT)
Data read (GET)
Peripheral hardware
Constant data
Program memory
69
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
9.2 Data Buffer
9.2.1 Configuration of data buffer
Figure 9-2 shows the configuration of the data buffer.
As shown in the figure, the data buffer consists of a total of 16 bits at addresses 0CH to 0FH of BANK 0 on
the data memory.
The 16-bit data consists of bit b3 at address 0CH as the MSB and bit b0 at address 0FH as the LSB.
Because the data buffer is located in the data memory, it can be manipulated by all data memory manipulation
instructions.
Figure 9-2. Configuration of Data Buffer
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
Data buffer
(DBF)
Data memory
BANK0
BANK1
BANK2
7
7
System register
Address
0CH
0DH
0EH
0FH
Data memory
Bit
Bit
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Signal
DBF3
DBF2
DBF1
DBF0
M
S
B
L
S
B
Data buffer
Data
Data
70
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
9.2.2 Table reference instruction (“MOVT DBF, @AR”)
The operation of the “MOVT DBF, @AR” instruction is indicated below.
MOVT DBF, @AR
This instruction reads the contents of the program memory addressed by the contents of the address register
to the data buffer.
One stack level is used when the table reference instruction is used.
The program memory addresses that can be referenced by the table are all the addresses from 0000H to
0FFFH of the program memory.
9.2.3 Peripheral hardware control instructions (“PUT”, “GET”)
The operations of the “PUT” and “GET” instructions are as follows:
(1) GET DBF, p
This instruction reads the data of the peripheral register addressed by p to the data buffer.
(2) PUT p, DBF
This instruction sets the data of the data buffer to the peripheral register addressed by p.
9.3 Peripheral Hardware and Data Buffer List
Table 9-1 lists the peripheral hardware units and the functions of the data buffer.
71
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 9-1. Relationship Between Peripheral Hardware and Data Buffer (1/2)
Peripheral Hardware
Peripheral Register That Transfers Data with Data Buffer
Name
Symbol
Peripheral
Address
Execution of
PUT/GET
Instruction
A/D converter
A/D converter data register
ADCR
02H
PUT/GET
Serial interface
Presettable shift register
PWM data register 0
SIO1SFR
PWMR0
03H
04H
PUT/GET
PUT/GET
D/A converter
(PWM output)
PWM0 pin
-----------------------------------------------------------------------------------------------------
PWM1 pin
PWM data register 1
PWMR1
05H
Address register (AR)
PLL frequency synthesizer
Key source controller/decoder
Port YA
Address register
AR
40H
41H
42H
42H
43H
46H
47H
PUT/GET
PUT/GET
PUT/GET
PUT/GET
GET
PLL data register
PLLR
KSR
PYA
IFC
Key source data register
Port YA group register
IF counter data register
Timer modulo register
Timer counter
Frequency counter
12-bit timer
Timer modulo
Timer counter
TMM
TMC
PUT/GET
GET
Table 9-1. Relationship Between Peripheral Hardware and Data Buffer (2/2)
Peripheral Hardware
Function
Number of I/O
Bits of
Number of Bits
Outline
Data Buffer
A/D converter
Serial interface
8
6
Sets compare voltage VREF data of
A/D converter
x – 0.5
VREF =
× VDD, 1 ≤ x ≤ 63
64
8
8
8
8
Sets serial out data and reads serial in
data.
D/A converter
(PWM output)
Sets compare voltage VREF data of
A/D converter
x + 0.25
Duty D =
× 100%, 0 ≤ x ≤ 255
256
Frequency f = 4.3945 kHz
Address register (AR)
PLL frequency synthesizer
Key source controller/decoder
Port YA
16
16
16
16
13
16
16
16
Transfers data with address register.
Sets division ratio (N value) of PLL.
Sets output data of key source signal.
Sets output data of port YA 0: low level
1: high level
Frequency counter
16
16
16
16
12
12
Reads count value of frequency counter.
Sets reference data of timer modulo.
Read data of up-counter
12-bit timer
Timer modulo
Timer counter
72
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
9.4 Notes on Using Data Buffer
Note the following points (1) through (3) concerning unused peripheral address and write-only peripheral
registers (PUT only) and read-only peripheral registers (GET only) when transferring data with the peripheral
hardware units via the data buffer.
(1) When a write-only register is read, an undefined value is read.
(2) Nothing is changed even if data is written to a read-only register.
(3) An undefined value is read if an unused register is read. Nothing is changed even if data is written to an unused
register.
73
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10. GENERAL-PURPOSE PORTS
The general-purpose ports output a high-level, low-level, or floating signal to an external circuit, and read
a high-level or low-level signal from the external circuit.
10.1 Configuration and Classification of General-Purpose Ports
Figure 10-1 shows the block diagram of the general-purpose ports.
Table 10-1 classifies the general-purpose ports.
As shown in Figure 10-1, the general-purpose ports include ports 0A (P0A) to 1D (P1D) to which are set by
addresses 70H to 73H (port registers) of each bank of the data memory, ports 2E (P2E) to 2H (P2H) to which
data are set by addresses 5CH to 5FH of bank 2 of the data memory, and port YA (PYA) to which data is set
via a data buffer (DBF).
Each port consists of general-purpose port pins (e.g., port 0A consists of the P0A2 to P0A0 pins).
As shown in Table 10-1, the general-purpose ports are classified into input/output ports (I/O ports), input-
only ports (input ports), and output-only ports (output ports).
The I/O ports are further subdivided into bit I/O ports that can be set in the input or output mode in 1-bit units
(1-pin units) and group I/O ports that can be set in the input or output mode in 4-bit units (4-pin units).
Figure 10-1. Block Diagram of General-Purpose Port
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Peripheral address 42H
DBF
0
1
2
3
4
5
6
7
Data memory
BANK0
Port register
BANK1
5C 5D 5E 5F
BANK2
System register
Data
setting
Bit Bit
Bit
Group
I/O I/O Out In
I/O In Out I/O
Out Out Out Out
Out
P
0
A
P
2
E
P
2
F
P
2
G
P
2
H
P
Y
A
P
0
B
P
0
C
P
0
D
P
1
A
P
1
B
P
1
C
P
1
D
−
−
−
−
Control register
I/O setting
P
0
A
2
P
0
A
1
P
0
A
0
Pin configuration
example of P0A
−
pin pin pin
74
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 10-1. Classification of General-Purpose Ports
Classification of General-Purpose Ports
Port
Data Set by:
General-purpose ports
I/O dedicated Bit I/O
ports
Port 0A
Port 0B
Port 1A
Port register
Group I/O
Port 1D
Port register
Port register
Input dedicated port
Port 0D
Port 1B
Output dedicated port
Port 0C
Port 1C
Port register
Port 2E
Port 2F
Port 2G
Port 2H
Port register
(multiplexed with LCD segment register)
Peripheral register
Port YA
10.2 Functional Outline of General-Purpose Ports
The general-purpose output ports and the general-purpose I/O ports set in the output mode output a high
or low level from the corresponding pins when data is set to the corresponding port register or port group register.
The general-purpose input ports and the general-purpose I/O ports set in the input mode detect the level of
the signals input to the corresponding pins by reading the contents of the corresponding port register.
The general-purpose I/O ports are set in the input or output mode by the corresponding control register.
In other words, these ports can be set in the input or output mode by program.
P0A to P0D and P1A to P1D are set in the general-purpose port mode on power-on reset.
P2E to P2H and PYA are used as LCD segment signal output pins on power-on reset. To use these ports
as general-purpose output ports, the corresponding control registers must be set independently.
The following subsections 10.2.1 to 10.2.4 explain the port registers, the function of the port group register,
and the functional outline of each port.
75
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.2.1 General-purpose port data register (port register)
A port register sets the output data and reads the input data of the corresponding general-purpose port.
Because the port registers are mapped in the data memory, they can be manipulated by any data memory
manipulation instruction.
Figure 10-2 shows the relationship between a port register and the corresponding port pins.
By setting data to the port register corresponding to the port pins set in the general-purpose output port mode,
the output of each pin is set.
By reading the contents of the port register corresponding to the port pins set in the general-purpose input
port mode, the input status of each pin is detected.
Table 10-2 shows the relationship between each port (each pin) and port register.
Figure 10-2. Relationship Between Port Register and Pins
Port register
Bank
Address
Bit
n
m
b3
b2
b1
b0
P
P
P
P
3
2
1
0
Bit significance of port register
Address of port register (e.g., 70H = A, 71H = B, 72H = C, 73H = D)
Bank of port register
“ P ” of Port
Reserved words are defined for the port registers by the assembler.
Because these reserved words are defined in flag (bit) units, the assembler-embedded macro instructions
can be used.
Note that data memory type reserved words are not defined for the port registers.
P2E to P2H are multiplexed with LCD segment signal output pins. The port registers of P2E to P2H are also
multiplexed with LCD segment registers.
Because the LCD segment registers are also mapped in the data memory, they can be treated in the same
manner as the port registers.
10.2.2 Port YA (PYA) group register
The port YA (PYA) group register sets the output data of PYA. Port YA functions alternately as the key source
signal output pin. Therefore, the PYA group register is also used as the key source data register and is allocated
to address 42H of the peripheral addresses. For details, refer to 10.6.7.
10.2.3 General-purpose I/O ports (P0A, P0B, P1A, and P1D)
P0A, P0B, P1A, and P1D can be set in the input or output mode by the port 0A bit I/O select register (RF
address 37H), port 0B bit I/O select register (RF address 36H), port 1A bit I/O select register (RF address 35H),
and port 1D group I/O select register (RF address 27H), respectively.
The input/output data of the P0A, P0B, P1A, and P1D are set by port registers P0A (address 70H of BANK0),
P0B (address 71H of BANK0), P1A (address 70H of BANK1), and P1D (address 73H of BANK1), respectively.
Refer to Table 10-2.
For details, refer to 10.3.
76
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.2.4 General-purpose input ports (P0D and P1B)
The input data of P0D and P1B is read by port registers P0D (address 73H of BANK0) and P1B (address 71H
of BANK1), respectively.
Refer to Table 10-2.
For details, refer to 10.4.
10.2.5 General-purpose output ports (P0C, P1C, P2E, P2F, P2G, P2H, and PYA)
(1) P0C, P1C
The output data of P0C and P1C is set by port registers P0C (address 72H of BANK0) and P1C (address 72H
of BANK1).
Refer to Table 10-2.
For details, refer to 10.5.
(2) P2E, P2F, P2G, P2H, and PYA
P2E, P2F, P2G, P2H, and PYA usually operate as LCD segment signal output pins. To use these ports as
the output ports select the port using the P2ESEL to P2HSEL and PYASEL flags of the LCD port select register
and LCD mode select register.
The port to be used can be selected individually using P2E to P2H and PYA.
The output data of P2E, P2F, P2G, and P2H can be set by the P2E register (also used as LCDD16 of the
LCD segment register, address 5FH of BANK2), P2F register (also used as LCDD17, address 5EH of BANK2),
P2G register (also used as LCDD18, address 5DH of BANK2), and P2H register (also used as LCDD19,
address 5CH of BANK2).
Refer to Table 10-2.
For details, refer to 10.6.
77
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 10-2. Relationship Between Each Port (Pin) and Port Register (1/2)
Pin
Data Setting Method
Port Register (Data Memory)
Bit Symbol
Port
No.
Symbol
I/O
Remarks
Bank Address Symbol
(Reserved Word)
No pin
9 (10)
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
P0A3
P0A2
P0A1
P0A0
P0B3
P0B2
P0B1
P0B0
P0C3
P0C2
P0C1
P0C0
P0D3
P0D2
P0D1
P0D0
P1A3
P1A2
P1A1
P1A0
P1B3
P1B2
P1B1
P1B0
P1C3
P1C2
P1C1
P1C0
P1D3
P1D2
P1D1
P1D0
Fixed to 0”
P0A
P0A
P0A
P0B
P0B
P0B
P0B
P0C
P0C
P0C
P0C
P0D
P0D
P0D
P0D
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Port 0A
70H
71H
72H
73H
70H
71H
72H
73H
P0A
P0B
P0C
P0D
P1A
P1B
P1C
P1D
10 (11)
11 (12)
16 (18)
17 (19)
18 (20)
19 (21)
27 (33)
28 (34)
29 (35)
30 (37)
59 (73)
60 (74)
61 (75)
62 (76)
No pin
63 (77)
1 (80)
I/O (bit I/O)
I/O (bit I/O)
Port 0B
Port 0C
Port 0D
Port 1A
Port 1B
Port 1C
Port 1D
BANK0
Output
Input
Fixed to 0
P1A
P1A
P1A
P1B
P1B
P1B
P1B
P1C
P1C
P1C
P1C
P1D
P1D
P1D
P1D
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
I/O (bit I/O)
2 (1)
12 (13)
13 (14)
14 (16)
15 (17)
20 (22)
21 (24)
22 (25)
23 (26)
31 (38)
32 (39)
33 (40)
34 (41)
Input
BANK1
Output
I/O (group I/O)
Remark Numbers in parentheses are pin numbers for 80-pin package.
78
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 10-2. Relationship Between Each Port (Pin) and Port Register (2/2)
Pin
Data Setting Method
Port Register (Data Memory) Port Group Register (Peripheral Register)
Bit Symbol
Port
No.
Symbol
I/O
Peripheral
Address
Symbol
(Reserved Word)
Bank Address Symbol
Bit
(Reserved Word)
b
3
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
70H
71H
72H
– – –
– – –
– – –
– – –
– – –
– – –
– – –
BANK2
Fixed to 0
73H
5FH
– – –
P2E
P2E3
P2E2
P2E1
P2E0
P2F3
P2F2
P2F1
P2F0
P2G3
P2G2
P2G1
P2G0
P2H3
P2H2
P2H1
P2H0
No pin
41 (49)
No pin
Can be used as data memory
Can be used as data memory
Can be used as data memory
Can be used as data memory
Port 2E
Port 2F
Port 2G
Port 2H
(multiplexed
with LCDD16)
P2E
P2F
0
Output
Output
Output
Output
Output
5EH
P2F
(multiplexed
with LCDD17)
40 (48)
No pin
0
BANK2
5DH
P2G
(multiplexed
with LCDD18)
39 (47) P2G
No pin
0
5CH
(multiplexed
with LCDD19)
P2H
38 (46)
P2H
0
42 (50) PYA15
43 (52) PYA14
44 (53) PYA13
b
b
b
15
14
13
Port YA
|
|
42H
PYAR
|
(multiplexed with KSR)
55 (65) PYA
56 (66) PYA
57 (67) PYA
2
1
0
b
2
1
0
b
b
Remark Numbers in parentheses are pin numbers for 80-pin package.
79
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.3 General-Purpose I/O Ports (P0A, P0B, P1A, and P1D)
10.3.1 Configuration of I/O ports
The following paragraphs (1) through (3) indicate the configuration of the I/O ports.
(1) P0A (P0A2, P0A1, and P0A0 pins),
P0B (P0B3, P0B2, P0B1, and P0B0 pins),
P1A (P1A2, P1A1, and P1A0 pins)
I/O select flag
V
DD
Output latch
Write instruction
Port register
(1 bit)
V
DD
1
0
Read instruction
RESET
(2) P1D (P1D3, P1D2, P1D1, and P1D0 pins)
I/O select flag
V
DD
Write instruction
Output latch
Port register
(1 bit)
V
DD
1
0
Read instruction
80
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.3.2 Using I/O ports
The I/O ports are set in the input or output mode by I/O select registers P0A P0B, P1A, and P1D of the control
registers.
The bit I/O ports (P0A, P0B, and P1A) can be set in the input or output mode in 1-bit units, and group I/O
port (P1D) can be set in the input or output mode in 4-bit units.
Output data can be set to a port by writing the data to the corresponding port register, and the input data of
the port can be read by executing an instruction that reads the port register.
10.3.3 explains the I/O select register of each port.
10.3.4 and 10.3.5 explain how to use the input and output ports.
10.3.3 I/O port control register
The port 0A bit I/O, port 0B bit I/O, port 1A bit I/O, and port 1D group I/O select registers set each pin of the
P0A, P0B, P1A, and P1D in the input or output mode.
The configuration and functions of these registers are shown below.
(1) Port 0A bit I/O select register
Name
Flag symbol
Address
37H
Read/
Write
b3
0
b2
b1
b0
P
0
A
B
I
P
0
A
B
I
P
0
A
B
I
Port 0A bit I/O select
register
R/W
O
2
O
1
O
0
Sets input or output mode of port
0
1
Sets P0A0/SI1 pin in input mode.
Sets P0A0/SI1 pin in output mode.
Sets input or output mode of port
0
1
Sets P0A1/SO1 pin in input mode.
Sets P0A1/SO1 pin in output mode.
Sets input or output mode of port
0
1
Sets P0A2/SCK1 pin in input mode.
Sets P0A2/SCK1 pin in output mode.
Fixed to "0"
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
81
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) Port 0B bit I/O select register
Name
Flag symbol
Address
36H
Read/
Write
b
3
b2
b1
b
0
P
0
B
B
I
P
0
B
B
I
P
0
B
B
I
P
0
B
B
I
Port 0B bit I/O select
register
R/W
O
3
O
2
O
1
O
0
Sets input or output mode of port
0
1
Sets P0B
0
/BEEP
0
0
pin in input mode.
pin in output mode.
Sets P0B
0
/BEEP
Sets input or output mode of port
pin in input mode.
0
1
Sets P0B
1
/BEEP
1
1
Sets P0B
1
/BEEP
pin in output mode.
Sets input or output mode of port
0
1
Sets P0B
2
/FCG
0
0
pin in input mode.
pin in output mode.
Sets P0B
2
/FCG
Sets input or output mode of port
pin in input mode.
0
1
Sets P0B
3
/FCG
1
1
Sets P0B
3
/FCG
pin in output mode.
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
0
0
82
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(3) Port 1A bit I/O select register
Name
Flag symbol
Address
35H
Read/
Write
b3
0
b2
b1
b0
P
1
A
B
I
P
1
A
B
I
P
1
A
B
I
Port 1A bit I/O select
register
R/W
O
2
O
1
O
0
Sets input or output mode of port
0
1
Sets P1A0 pin in input mode.
Sets P1A0 pin in output mode.
Sets input or output mode of port
0
1
Sets P1A1 pin in input mode.
Sets P1A1 pin in output mode.
Sets input or output mode of port
0
1
Sets P1A2 pin in input mode.
Sets P1A2 pin in output mode.
Fixed to "0"
0
1
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
83
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(4) Port 1D group I/O select register
Name
Flag symbol
Address
27H
Read/
write
b
3
b2
b
1
b
0
Port 1D group I/O
select register
0
0
0
R/W
P
1
D
G
I
O
Sets input or output mode of port
0
1
Sets the P1D
3
3
to P1D
0
0
pins in input mode.
pins in output mode.
Sets the P1D
to P1D
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
84
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.3.4 Using I/O ports (P0A, P0B, P1A, and P1D) as input ports
Select the pin to be used as an input port pin by the I/O select register corresponding to each port.
Note that P1D can be set in the input or output mode in 4-bit units only.
The pin specified as an input port pin is floated (Hi-Z), and waits for input of an external signal.
The input data can be read by executing an instruction that reads the contents of the port register
corresponding to each port, such as the SKT instruction.
When a high level is input to each pin, 1 is read to the corresponding port register; when a low level is input,
0 is read.
If a write instruction, such as MOV, is executed to the port register corresponding to the port pin specified
as an input port pin, the contents of the output latch are rewritten.
10.3.5 Using I/O ports (P0A, P0B, P1A, and P1D) as output ports
Select the pin to be used as an output port pin by the I/O select register corresponding to each port.
Note that P1D can be set in the input or output mode in 4-bit units only.
The pin specified as an output port pin outputs the contents of the output latch.
The output data can be set by executing an instruction that writes the contents of the corresponding port
register to each pin, such as the MOV instruction.
To output a high level to each pin, write 1 to the corresponding port register; to output a low level, write 0.
The port pin can also be floated when it is specified as an input port pin.
When an instruction, such as SKT, that reads the contents of the port register corresponding to a port
specified as an output port is executed, the contents of the output latch are read.
10.3.6 Status of I/O ports (P0A, P0B, P1A, and P1D) on reset
(1) On power-on reset
All the I/O ports are set in the input mode.
Because the contents of the output latch are undefined, the output latch must be initialized by program, as
necessary, before setting the corresponding port in the output mode.
(2) On CE reset
All the I/O ports are set in the input mode.
The contents of the output latch are retained.
(3) On execution of clock stop instruction
All the I/O ports are set in the input mode.
The contents of the output latch are retained.
I/O ports other than P1D prevent an increase in the current consumption due to the noise of the input buffer
by using the RESET signal when the clock stop instruction is executed, as explained in 10.3.1.
If P1D is floated on execution of the clock stop instruction, the current consumption may increase due to
external noise. Externally pull this port down or up as necessary.
(4) In halt status
The previous status is retained.
85
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.4 General-Purpose Input Ports (P0D and P1B)
10.4.1 Configuration of input ports
The following paragraphs (1) and (2) indicate the configuration of the input ports.
(1) P0D (P0D3, P0D2, P0D1, and P0D0 pins)
Write instruction
VDD
Port register
(1 bit)
Input
latch
Read instruction
Key source signal timing output
RESET
High on resistance
(2) P1B (P1B3, P1B2, P1B1, and P1B0 pins)
To frequency counter or A/D converter
Write instruction
VDD
Port register
(1 bit)
Read instruction
RESET
86
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.4.2 Using input ports (P0D and P1D)
The input data is read by executing an instruction, such as SKT, that reads the contents of the port register
corresponding to each port pin.
When a high level is input to each pin, 1 is read to the corresponding port register; when a low level is input,
0 is read.
Nothing is changed even if a write instruction, such as MOV, is executed to the port register.
10.4.3 Notes on using input port (P0D)
The P0D is internally pulled down when it is used as a general-purpose port.
10.4.4 Status of input ports (P0D and P1B) on reset
(1) On power-on reset
All the input ports are specified as general-purpose input ports.
(2) On CE reset
All the input ports are specified as general-purpose input ports.
(3) On execution of clock stop instruction
All the input ports are specified as general-purpose input ports.
Because the RESET signal is output when the clock stop instruction is executed, P1B prevents an increase
in the current dissipation due to the noise of the input buffer as described in 10.4.1.
P0D is internally pulled down.
(4) In halt status
The previous status is retained.
87
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.5 General-Purpose Output Ports (P0C and P1C)
10.5.1 Configuration of output ports (P0C and P1C)
The following paragraphs (1) and (2) indicate the configuration of the output ports.
(1) P0C (P0C3, P0C2, P0C1, and P0C0 pins)
Output
latch
Write instruction
Port register
(1 bit)
Read instruction
(2) P1C (P1C3, P1C2, P1C1, and P1C0 pins)
VDD
Output
latch
Write instruction
Port register
(1 bit)
Read instruction
88
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.5.2 Use of output ports (P0C and P1C)
The output ports output the contents of the output latches.
The output data is set by executing an instruction, such as MOV, that writes the data to the port register
corresponding to the output port.
Write 1 to the port register to output a high level to the corresponding port; write 0 to output a low level.
Note, however, that the P0C3, P0C2, P0C1, and P0C0 pins are N-ch open-drain output pins and are floated
when a high level is output.
When an instruction, such as SKT, that reads the contents of the port register is read, the contents of the
output latch are read.
10.5.3 Status of output ports (P0C and P1C) on reset
(1) On power-on reset
The contents of the output latch are output.
Because the contents of the output latch are undefined, an undefined value is output for a fixed period (until
the output latch is initialized by program).
(2) On CE reset
The contents of the output latch are output.
The contents of the output latch are retained and the output data is not changed on CE reset.
(3) On execution of clock stop instruction
The contents of the output latch are output.
The contents of the output latch are retained and the output data is not changed on execution of the clock
stop instruction.
Therefore, initialize the output latch in the program as necessary.
(4) In halt status
The contents of the output latch are output.
The contents of the output latch are retained and the output data is not changed in the halt status.
89
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.6 General-Purpose Output Ports (P2E to P2H and PYA)
10.6.1 Configuration of output ports (P2E to P2H and PYA)
The configuration of the output ports is shown below.
(1) P2E (P2E0 pin)
P2F (P2F0 pin)
P2G (P2G0 pin)
P2H (P2H0 pin)
LCD/port
select flag
V
DD
Output
latch
Write instruction
1
0
Segment signal
timing control
Port register
(1 bit)
Also used as LCD
segment register
Read instruction
(2) PYA (PYA15 to PYA0)
LCD/port
select flag
VDD
Output
latch
Write instruction
(PUT)
1
0
Segment signal
key source
timing control
PYA group
register
(1 bit),
Also used as
key source data
register
Read instruction
(GET)
LCD segment register
90
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.6.2 Example of using output ports (P2E to P2H and PYA)
Each pin of P0E and P0F are used as an LCD segment signal output pin on power-on reset.
To use it as an output port pin, select the port to be used by the P2ESEL to P2HSEL and PYASEL flags of
the LCD port select register and LCD mode select register.
The port to be used can be selected by P2E to P2H and PYA independently.
The pins not set in the output port mode by the LCD port select register and LCD mode select register can
be used as LCD segment signal output pins.
The setting of P2E to P2H and PYA output data is described in 10.6.3 and 10.6.4.
The configuration and functions of the LCD port select register, LCD mode select register, and port YA (PYA)
group register are described in 10.6.5 to 10.6.7.
10.6.3 Setting data to P2E to P2H
Output data is set to P2E to P2H by executing an instruction, such as MOV, that writes data to the port
registers corresponding to the ports.
To output a high level to each port pin, write 1 to the corresponding port register; to output a low level, write
0.
The contents of the output latch are read when an instruction, such as SKT, that reads the contents of the
port register is executed.
Figure 10-3 shows the relationship between the P2E to P2H port registers and LCD segment register.
As shown in this figure, the LCD segment register’s higher 3 bits, LCDD16 to LCDD19, can be used as a
general-purpose data memory area when P2E to P2H are used.
Refer to Figure 19-5 Relationship Between LCD Display Dots, Output of Each Pin, and Data Setting
Registers in 14. LCD CONTROLLER/DRIVER.
Figure 10-3. Relationship Between Port Registers P2E to P2H and LCD Segment Register
P2ESEL flag
P2HSEL flag
1
0
LCD16/P2E
LCD19/P2H
0
to
0
b
b
b
b
0
Segment signal
timing control
LCDD16/P2E to
LCDD19/P2H
(5FH to 5CH)
1
2
3
91
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.6.4 PYA data setting
To set output data to PYA, execute the write the instruction “PUT PYA, DBF” to the port YA (PYA) group register
corresponding to each pin.
When the instruction “GET DBF, PYA”, which reads the contents of a PYA group register, is executed, the contents
of the output latch are read.
To output a high level to each pin, write 1 to the corresponding port register; to output a low level, write 0.
Figure 10-4. Relationship Between PYA Group Register and LCD Segment Register
PYASEL flag
1
0
LCD15/KS15/PYA15
Segment/key
source timing
control
b
b
b
0
b
b
15
14
LCDD15
(60H)
1
2
1
0
LCD14/KS14/PYA14
Segment/key
source timing
control
b
b
b
0
LCDD14
(61H)
1
2
KSR
PYA
1
0
LCD
LCD
1
/KS
/KS
1
/PYA
/PYA
1
0
Segment/key
source timing
control
b
b
b
0
LCDD1
(6EH)
1
2
1
0
b
b
1
0
0
0
Segment/key
source timing
control
b
b
b
0
LCDD0
(6FH)
1
2
92
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.6.5 Configuration and functions of LCD port select register
The LCD port select register specifies whether P2E, P2F, P2G, and P2H are used as LCD segment signal output
pins or as general-purpose output port pins.
The configuration and function of this register are illustrated below.
Name
Flag symbol
Address
11H
Read/
Write
b
3
b2
b1
b
0
LCD port select
register
P
2
P
2
P
2
P
2
R/W
H
S
E
L
G
S
E
L
F
S
E
L
E
S
E
L
Selects LCD segment signal output pin or general-purpose output port
0
1
LCD16/P2E
0
0
is used as LCD segment pin
LCD16/P2E
is used as general-purpose output pin
Selects LCD segment signal output pin or general-purpose output port
0
1
LCD17/P2F
0
0
is used as LCD segment pin
LCD17/P2F
is used as general-purpose output pin
Selects LCD segment signal output pin or general-purpose output port
0
1
LCD18/P2G
0
0
is used as LCD segment pin
LCD18/P2G
is used as general-purpose output pin
Selects LCD segment signal output pin or general-purpose output port
0
1
LCD19/P2H
0
0
is used as LCD segment pin
LCD19/P2H
is used as general-purpose output pin
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
Retained
Ports 2E, 2F, 2G, and 2H can be independently set as general-purpose output ports.
The pins not specified as general-purpose output port pins operate as LCD segment signal output pins.
93
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.6.6 Configuration and function of LCD mode select register
The LCD mode select register specifies whether the PYA pins are used as LCD segment signal output pins or as
general-purpose port pins. This register also turns ON/OFF all the LCD displays, and outputs key source signals.
The configuration and function of this register are illustrated below.
Name
Flag symbol
Address
10H
Read/
Write
b
3
b2
b1
b
0
LCD mode select
register
R/W
0
K
S
E
N
L
P
C
D
E
N
Y
A
S
E
L
Selects LCD segment output pin or general-purpose output pin
0
1
Uses LCD
0
/KS
0
/PYA
0
0
to LCD15/KS15/PYA15 pins as LCD segment pins
Uses LCD
0
/KS
0
/PYA
to LCD15/KS15/PYA15 pins as general-purpose output port pins
Turns on/off all LCD displays
0
1
Display off (all segment output and common output pins go low)
Display on
Sets output of key source signal
0
1
Key source off
Key source on
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
0
Retained
The 16 pins, LCD0/KS0/PYA0 to LCD15/KS15/PYA15, function alternately as LCD segment signal outputs and key
source signal outputs. When any of these pins is set as a general-purpose output port pin, however, neither the LCD
segment signal nor key source signal is output.
94
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.6.7 Port YA (PYA) group register
The PYA group register sets the output data of the PYA pins (PYA0 through PYA15).
The PYA pins can set 16-bit output data all at once.
The function of the PYA group register is illustrated below.
Data buffer
DBF3
DBF2
DBF1
DBF0
Transfer data
GET can be executed
PUT can be executed
16
Peripheral register
Peripheral
address
Name
b15
b14
b13
b12
b11
b10
b9
b
8
b
7
b6
b5
b4
b3
b2
b1
b0
Symbol
PYA
Port YA
group
42H
Valid data
register
Sets output data of port YA
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
0
1
2
3
4
5
6
7
8
9
/KS
/KS
/KS
/KS
/KS
/KS
/KS
/KS
/KS
/KS
0
1
2
3
4
5
6
7
8
9
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
0
1
2
3
4
5
6
7
8
9
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
LCD10/KS10/PYA10 pin
LCD11/KS11/PYA11 pin
LCD12/KS12/PYA12 pin
LCD13/KS13/PYA13 pin
LCD14/KS14/PYA14 pin
LCD15/KS15/PYA15 pin
Low-level output
0
1
High-level output
Port YA is alternately used with key source signal output pins.
Therefore, the PYA group register (peripheral address: 42H) is alternately used with the key source data register
(peripheral address: 42H), which is to be described later.
Consequently, the PYA group register is used to set the output data of port YA when the LCD0/KS0/PYA0 to LCD15/
KS15/PYA15 pins are specified as output port pins, and key source signal output data when these pins are specified
as key source signal output pins.
95
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
10.6.8 Status of output ports (P2E to P2H and PYA) on reset
(1) On power-on reset
P0E and P0F are set as LCD segment signal output pins and output a low level.
Because the contents of the output latch are undefined, undefined data is output if these ports are set in the
output mode as is. Initialize the ports in the program as necessary.
(2) On CE reset
P0E and P0F are set as LCD segment signal output pins and output a low level.
Because the contents of the output latch are retained, the previous values are retained if these ports are set
in the output mode as is.
(3) On execution of clock stop instruction
P0E and P0F are set as LCD segment signal output pins and output a low level.
Because the contents of the output latch are retained, the previous values are retained if these ports are set
in the output mode as is.
(4) In halt status
The contents of the output latch are output.
Because the contents of the output latch are retained, the output data is not changed in the halt status.
96
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11. INTERRUPTS
11.1 Outline of Interrupt Block
Figure 11-1 illustrates the interrupt block.
As shown in the figure, the interrupt block temporarily stops the program currently being executed in response
to an interrupt request output from any peripheral hardware unit and branches execution to an interrupt vector
address.
The interrupt block consists of an interrupt control block for each peripheral hardware unit, interrupt enable
flip-flop that enables all the interrupts, stack pointer that is controlled when an interrupt is acknowledged,
address stack register, program counter, and interrupt stack.
The interrupt control block of each peripheral hardware unit consists of an interrupt request flag (IRQxxx) that
detects each interrupt request, interrupt enable flag (IPxxx) that enables each interrupt, and vector address
generator (VAG) that specifies a vector address when an interrupt is acknowledged.
The peripheral hardware units that have an interrupt function are as follows:
•
•
•
•
INT pin (rising-edge detection)
12-bit timer
Basic timer 1
Serial interface
97
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-1. Outline of Interrupt Block
Interrupt control block
IPSIO1 flag
Program counter
Vector address
generator 01H
Serial
interface
IRQSIO1 flag
Address stack
register
Stack pointer
IPBTM1 flag
IRQBTM1 flag
System register
Vector address
generator 02H
Basic
timer 1
Interrupt stack
register
IPTM flag
Vector address
generator 03H
12-bit
timer
IRQTM flag
IP flag
Vector address
generator 04H
INT pin
IRQ flag
Interrupt enable
flip-flop
DI, EI instruction
98
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.2 Interrupt Control Block
The interrupt control block is provided for each peripheral hardware unit and detects an interrupt request,
enables the interrupt, and generates a vector address when the interrupt is acknowledged.
11.2.1 Configuration and function of interrupt request flag (IRQ×××)
Each interrupt request flag (IRQ×××) is set to 1 when an interrupt request is issued from the corresponding
peripheral hardware unit, and is reset to 0 when the interrupt is acknowledged. It cannot be set by software.
The issued state of each interrupt request can be detected by the detection of these interrupt request flags
when interrupts are not enabled.
Also, when 1 is directly written to the interrupt request flag via a window register, it means that the interrupt
request has been issued.
Once this flag has been set to 1, it is not reset until the corresponding interrupt is acknowledged or 0 is written
via a window register.
If more than one interrupt request is issued at the same time, the interrupt request flag corresponding to the
interrupt that has not been acknowledged is not reset.
The interrupt request flag is assigned to the register file’s interrupt request register.
The configuration and function of the interrupt request register are shown in Figures 11-2 to 11-5.
Figure 11-2. Configuration of Interrupt Request Register 1
Name
Flag symbol
Address
3FH
Read/
write
b
3
b2
b1
b
0
Interrupt request register 1
I
0
0
I
Bit 3: R
N
T
R
Q
Bit 0: R/W
Sets interrupt request issuing status of INT pin
0
1
Interrupt request not issued
Interrupt request issued
Fixed to 0
Detects status of INT pin
0
1
Low level is input
High level is input
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
99
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-3. Configuration of Interrupt Request Register 2
Name
Flag symbol
Address
3EH
Read/
write
b
3
b2
b1
b
0
0
0
0
I
Interrupt request register 2
R/W
R
Q
T
M
Sets interrupt request issuing status of 12-bit timer
0
1
Interrupt request not issued
Interrupt request issued
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
Figure 11-4. Configuration of Interrupt Request Register 3
Name
Flag symbol
Address
3DH
Read/
write
b
3
b2
b1
b
0
Interrupt request register 3
0
0
I
0
R/W
R
Q
B
T
M
1
Sets interrupt request issuing status of basic timer 1
0
1
Interrupt request not issued
Interrupt request issued
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
100
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-5. Configuration of Interrupt Request Register 4
Name
Flag symbol
Address
3CH
Read/
write
b
3
b2
b1
b
0
Interrupt request register 4
0
0
0
I
R/W
R
Q
S
I
O
1
Sets interrupt request issuing status of serial interface
Interrupt request not issued
0
1
Interrupt request issued
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
11.2.2 Configuration and function of interrupt enable flag (IP×××)
Each interrupt enable flag enables the interrupt of the corresponding peripheral hardware unit.
So that an interrupt is acknowledged, all the following three conditions must be satisfied.
• The interrupt must be enabled by the corresponding interrupt enable flag.
• An interrupt request must be issued by the corresponding interrupt request flag.
• The “EI” instruction (that enables all the interrupts) must be executed.
The interrupt enable flag is assigned to the register file’s interrupt enable register.
Figure 11-6 shows the configuration and function of the interrupt enable register.
101
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-6. Configuration of Interrupt Enable Register
Name
Flag symbol
Address
2FH
Read/
write
b
3
b2
b1
b
0
Interrupt enable register
I
P
S
I
I
I
P
T
I
P
R/W
P
B
T
M
O
1
M
1
Sets interrupt enable status of INT pin
0
1
Interrupt disabled
Interrupt enabled
Sets interrupt enable status of 12-bit timer
0
1
Interrupt disabled
Interrupt enabled
Sets interrupt enable status of basic timer 1
0
1
Interrupt disabled
Interrupt enabled
Sets interrupt enable status of serial interface
0
1
Interrupt disabled
Interrupt enabled
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
0
0
11.2.3 Vector address generator (VAG)
The vector address generator generates a branch address (vector address) of the program memory for the
interrupt source acknowledged when a peripheral hardware interrupt has been acknowledged.
Table 11-1 shows the vector address of each interrupt source.
Table 11-1. Vector Address of Each Interrupt Source
Interrupt Source
INT pin
Vector Address
04H
12-bit timer
03H
02H
01H
Basic timer 1
Serial interface
102
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.3 Interrupt Stack Register
11.3.1 Configuration and function of interrupt stack register
Figure 11-7 shows the configuration of the interrupt stack register and the system register whose contents
are saved to the interrupt stack register.
The interrupt stack register saves the contents of the following system registers when an interrupt is
acknowledged.
•
•
•
Bank register (BANK)
General register pointer (RP)
Program status word (PSWORD)
When an interrupt is acknowledged and the contents of the above system registers are saved to the interrupt
stack register, the contents of the above system registers are reset to 0.
The interrupt stack can save up to 2 levels of the contents of the above system registers.
Therefore, up to 2 levels of multiple interrupts can be executed.
The contents of the interrupt stack register are restored to the system registers when an interrupt return
instruction (“RETI”) is executed.
Figure 11-7. Configuration of Interrupt Stack Register
Interrupt stack register (INTSK)
Name
Bit
Bank stack
Register pointer stack high Register pointer stack low
Status stack
b3
b
2
b
1
b0
b3
b
2
b
1
b0
b
3
b2
b1
b0
b3
b2
b1
b0
–
–
–
–
0H
–
–
–
–
1H
Remark –: Bit not saved
103
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.3.2 Interrupt stack register operation
Figure 11-8 illustrates the operation of the interrupt stack register.
If multiple interrupts exceeding 2 levels are acknowledged, the first saved contents are discarded and
therefore must be saved by program.
Figure 11-8. Operation of Interrupt Stack Register
(a) If interrupt does not exceed 2 levels
Undefined
Undefined
A
Undefined
Undefined
Undefined
VDD application Interrupt A
RETI
(b) If interrupt exceeds 2 levels
A
B
A
C
B
B
B
B
B
Undefined
Interrupt A Interrupt B Interrupt C
RETI
RETI
11.4 Stack Pointer, Address Stack Register, Program Counter
The address stack register saves the return address to which execution is to be returned from an interrupt
processing routine.
The stack pointer specifies the address of the address stack register.
When an interrupt is acknowledged, therefore, the value of the stack pointer is decremented by one and the
value of the program counter at that time is saved to the address stack register specified by the stack pointer.
When the dedicated return instruction RETI is executed after the processing of the interrupt servicing routine
has been executed, the contents of the address stack register specified by the stack pointer are restored to the
program counter, and the value of the stack pointer is incremented by one.
For further information, also refer to 3. ADDRESS STACK (ASK).
11.5 Interrupt Enable Flip-Flop (INTE)
The interrupt enable flip-flop enables all the interrupts.
When this flip-flop is set, all the interrupts are enabled. When it is reset, all the interrupts are disabled.
This flip-flop is set or reset by using dedicated instructions EI (to set) and DI (to reset).
The EI instruction sets this flip-flop when the instruction next to the EI instruction is executed, and the DI
instruction resets the flip-flop while the DI instruction is executed.
When an interrupt is acknowledged, this flip-flop is automatically reset.
Nothing is affected even if the DI instruction is executed in the DI state, or if the EI instruction is executed
in the EI state.
This flip-flop is reset on power-on reset, CE reset, and on execution of the clock stop instruction.
104
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.6 Acknowledging Interrupts
11.6.1 Acknowledging interrupts and priority
An interrupt is acknowledged in the following procedure:
(1) Each peripheral hardware unit outputs an interrupt request signal to the corresponding interrupt control block
if a given interrupt condition is satisfied (e.g., if a rising signal is input to the INT pin).
(2) When the interrupt control block has received the interrupt request signal from the peripheral hardware unit,
it sets the corresponding interrupt request flag (e.g., IRQ flag if the peripheral unit is the INT pin) to 1.
(3) If the interrupt enable flag corresponding to the interrupt request flag (e.g., IP flag for IRQ flag) is set to 1 when
the interrupt request flag is set to 1, the interrupt control block outputs 1.
(4) The signal output by the interrupt control block is ORed with the output of the interrupt enable flip-flop, and
an interrupt acknowledge signal is output.
This interrupt enable flip-flop is set to 1 by the EI instruction and reset to 0 by the DI instruction.
If the interrupt control block outputs 1 while the interrupt enable flip-flop is 1, the interrupt is acknowledged.
As shown in Figure 11-1, the interrupt acknowledge signal is input to each interrupt control block when the
interrupt has been acknowledged.
The interrupt request flag is reset to 0 by the signal input to the interrupt control block, and a vector address
corresponding to the interrupt is output.
If more than one interrupt block outputs 1 at this time, the interrupt acknowledge signal is not transferred to
the next stage. If more than one interrupt request is issued at the same time, therefore, the interrupts are
acknowledged in the following priority order.
INT pin > 12-bit timer > basic timer 1 > serial interface
The interrupt of an interrupt source is not acknowledged unless the corresponding interrupt enable flag is
set to 1.
If the interrupt enable flag is reset to 0, therefore, an interrupt with a high hardware priority can be disabled.
105
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.6.2 Timing chart for acknowledging interrupt
Figure 11-9 shows the timing chart illustrating acknowledging interrupts.
(1) in this figure illustrates how one interrupt is acknowledged.
(a) in (1) shows the case where the interrupt request flag is the last to be set to 1, and (b) in (1) shows the
case where the interrupt enable flag is the last to be set to 1.
In either case, the interrupt is acknowledged when each of the interrupt request flag, interrupt enable flip-
flop, and interrupt enable flag are set to 1.
If the last flag or flip-flop that was set to 1 satisfies the first instruction cycle of the MOVT DBF, @AR instruction
or a given skip condition, the interrupt is acknowledged after the second instruction cycle of the MOVT DBF,
@AR instruction or the instruction that is skipped (NOP) has been executed.
The interrupt enable flip-flop is set in the instruction cycle next to the one in which the EI instruction is
executed.
(2) in Figure 11-9 illustrates how more than one interrupt is used.
In this case, the interrupts are sequentially acknowledged according to the hardware priority if all the interrupt
enable flags are set. The hardware priority can be changed by manipulating the interrupt enable flag by
program.
“Interrupt cycle” shown in Figure 11-9 is a special cycle in which the interrupt request flag is reset, a vector
address is specified, and the contents of the program counter are saved after an interrupt has been acknowledged,
and lasts for 4.44 µs, which is equivalent to the execution time of one instruction.
For details, refer to 11.7 Operations After Acknowledging Interrupt.
106
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-9. Timing Chart of Acknowledging Interrupt (1/3)
(1) When one interrupt (e.g., rising of INT pin) is used
(a) If interrupt is not masked by interrupt enable flag (IP×××)
<1> If the MOVT instruction or a normal instruction that does not satisfies the skip condition is executed
when an interrupt is acknowledged
MOV
POKE
Normal
instruction
Interrupt
cycle
EI
Instruction
WR, #0001B INTPM1, WR
INTE
INT pin
IRQ flag
IP flag
Interrupt acknowledged
Interrupt enable period
Instruction cycle:
4.44 µs
Interrupt servicing routine
<2> If the MOVT instruction or an instruction that satisfies the skip condition is executed when an
interrupt is acknowledged
MOVT DBF,@AR
Skip instruction
MOV
POKE
Interrupt
cycle
Instruction
EI
WR, #0001B INTPM, WR
INTE
INT pin
IRQ flag
IP flag
Interrupt acknowledged
Interrupt enable period
Interrupt servicing routine
107
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-9. Timing Chart of Acknowledging Interrupt (2/3)
(b) If interrupt is kept pending by interrupt enable flag
Interrupt
cycle
MOV
POKE
Instruction
EI
WR, #0001B INTPM1, WR
INTE
INT pin
IRQ flag
IP flag
Interrupt acknowledged
Interrupt pending period
Interrupt servicing routine
108
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-9. Timing Chart of Acknowledging Interrupt (3/3)
(2) When two or more interrupts are used (e.g. INT pin and 12-bit timer)
(a) Hardware priority
MOV
POKE
Interrupt
cycle
Interrupt
cycle
Instruction
EI
EI
WR, #0011B INTPM1, WR
INTE
INT pin
IRQ flag
12-bit timer
IRQTM flag
IP flag
IPTM flag
12-bit timer
interrupt
INT pin interrupt pending period
INT pin interrupt servicing
servicing
12-bit timer interrupt pending period
INT pin interrupt acknowledged
12-bit timer interrupt
acknowledged
(b) Software priority
Interrupt
cycle
Interrupt
cycle
MOV
POKE
MOV
POKE
EI
EI
Instruction
WR, #0011B INTPM1, WR
WR, #0011B INTPM1, WR
INTE
INT pin
IRQ flag
12-bit timer
IRQTM flag
IP flag
IPTM flag
INT pin interrupt pending period
12-bit timer interrupt pending period
12-bit timer interrupt servicing
INT pin interrupt
servicing
12-bit timer interrupt acknowledged
INT pin interrupt
acknowledged
109
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.7 Operations After Acknowledging Interrupt
When an interrupt has been acknowledged, the following processing is sequentially executed.
(1) The interrupt enable flip-flop and the interrupt request flag corresponding to the acknowledged interrupt are
reset to 0, disabling the interrupts.
(2) The contents of the stack pointer are decremented by one.
(3) The contents of the program counter are saved to the address stack register specified by the stack pointer.
The contents saved at this time are the next program memory address that is used after the interrupt has been
acknowledged. For example, if a branch instruction is executed, the contents saved are the branch destination
address; if a subroutine call instruction is executed, they are the called address. Because the interrupt is
acknowledged after the next instruction is executed as a NOP instruction if a skip condition is satisfied by a
skip instruction, the saved contents are the skipped address.
(4) The lower 2 bits of the bank register (BANK), lower 5 bits of the general register pointer (RP), and 5 bits of
the program status word (PSWORD) are saved to the interrupt stack.
(5) The contents of the vector address generator corresponding to the acknowledged interrupt are transferred
to the program counter. In other words, execution branches to an interrupt servicing routine.
The processing (1) through (5) above is executed in one special instruction cycle (4.44 µs) in which the normal
instruction is not executed. This instruction cycle is called an interrupt cycle.
In other words, one instruction cycle time is necessary since an interrupt has been acknowledged until
execution branches to the corresponding vector address.
11.8 Restoring from Interrupt Servicing Routine
To restore execution from an interrupt servicing routine to the processing that was being performed when
the interrupt occurred, a dedicated instruction, “RETI”, is used.
When the RETI instruction is executed, the following processing is sequentially executed.
(1) The contents of the address stack register specified by the stack pointer are saved to the program counter.
(2) The contents of the interrupt stack are restored to the lower 2 bits of the bank register (BANK), lower 5 bits
of the general register pointer (RP), and 5 bits of the program status word (PSWORD).
(3) The contents of the stack pointer are incremented by one.
The processing (1) through (3) above is executed in one instruction cycle in which the RETI instruction is
executed.
The difference between the RETI instruction and subroutine return instructions “RET” and “RETSK” is only
the restoring operation of the system register in (2) above.
110
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.9 External (INT Pin) Interrupt
11.9.1 Outline of external interrupt
Figure 11-10 illustrates the external interrupt.
As shown in the figure, the external interrupt issues an interrupt request at the rising edge of the signal input
to the INT pin.
The INT pin is a Schmitt-trigger input pin to prevent malfunctioning due to noise, and does not accept a pulse
less than 1 µs wide.
Figure 11-10. Outline of External Interrupt
Interrupt control block
INT flag
IEG flag
Edge
detection
block
INT pin
IRQ flag
Schmitt trigger
Remark INT: Detects pin status
IEG: Selects interrupt edge
11.9.2 Edge detection block
The edge detection block sets and detects the input signal edge (rising or falling edge) and that issues the
interrupt request of the INT pin.
The edge setting is made by the IEG flag.
Figure 11-11 shows the configuration and function of the interrupt edge select register.
111
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 11-11. Configuration of Interrupt Edge Select Register
Name
Flag symbol
Address
1FH
Read/
write
b
3
b2
b1
b
0
Interrupt edge select
register
0
0
0
I
E
G
R/W
Sets input edge issuing interrupt request of INT pin
0
1
Rising edge
Falling edge
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
Note that as soon as the interrupt request issuing edge is changed by the IEG flag, the interrupt request signal
may be issued.
Suppose that the IEG flag is set to 1 (specifying the falling edge) and that a high level is input to the INT pin, as
shown in Table 11-2. If the IEG flag is reset to 0 at this time, the edge detector judges that a rising edge has been
input, and issues an interrupt request.
Table 11-2. Issuing Interrupt Request by Changing IEG Flag
Changes in IEG Flag
IRQ Flag Status
INT Pin Status
Interrupt Request
1 → 0
Low level
High level
Low level
High level
Not issued
Issued
Retains previous status
Set to 1
(falling)
0 → 1
(rising)
(rising)
(falling)
Issued
Set to 1
Not issued
Retains previous status
112
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
11.9.3 Interrupt control block
The level of a signal input to the INT pin can be detected by using the INT flag.
This flag is set or reset independently of interrupts; therefore, it can be used as a 1-bit general-purpose input port
when the interrupt function is not used.
The INT flag can also be used as a general-purpose port that can detect the rising or falling edge by reading an
interrupt request flag if the interrupt corresponding to the flag is not enabled.
In this case, however, the interrupt request flag is not automatically reset and must be reset by program.
Also refer to 11.2.1 Configuration and function of Interrupt request flag (IRQxxx).
11.10 Internal Interrupt
Three internal interrupt sources, 12-bit timer, basic timer 1, and serial interface, are available.
11.10.1 Interrupt by 12-bit timer
This interrupt request is issued at fixed time intervals.
For details, refer to 12. TIMER.
11.10.2 Interrupt by basic timer 1
This interrupt request is issued at fixed time intervals.
For details, refer to 12. TIMER.
11.10.3 Interrupt by serial interface
This interrupt request is issued when a serial output or serial input operation has been completed.
For details, refer to 15. SERIAL INTERFACE.
113
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12. TIMER
The timers are used to control the program execution time.
12.1 General
Figure 12-1 illustrates the timers of the µPD17012.
As shown in this figure, the µPD17012 is provided with the following three timers:
• Basic timer 0
• Basic timer 1
• 12-bit timer (modulo timer)
Basic timer 0 is used to detect the status of a flip-flop that is set at fixed time intervals.
Basic timer 1 is used to issue an interrupt request at fixed time intervals.
The 12-bit timer is a modulo timer that issues an interrupt request at fixed time intervals.
Basic timer 0 can also be used to detect a power failure. The clock of each timer is generated by dividing the system
clock (4.5 MHz).
Figure 12-1. Outline of Timer
(a) Basic timer 0
Clock select
block
4.5 MHz
FF
BTM0CY flag
(b) Basic timer 1
Clock select
block
4.5 MHz
Interrupt request
(c) 12-bit timer
Start/stop
12-bit counter
Match detection
Modulo register
4.5 MHz
Clock select
block
Interrupt request
114
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.2 Basic Timer 0
12.2.1 Outline of basic timer 0
Figure 12-2 illustrates basic timer 0.
Basic timer 0 is used as a timer by detecting the status of a flip-flop that is set at fixed intervals (100, 250,
5, or 1 ms), using the BTM0CY flag (RF: address 17H, bit 0).
The contents of the flip-flop correspond to the BTM0CY flag.
If the BTM0CY flag is read first after power-on reset, 0 is always read. After that, the flag is set to 1 at fixed
intervals.
If the CE pin goes high from low, CE reset is effected in synchronization with the timing at which the BTM0CY
flag is set next.
Therefore, a power failure can be detected by reading the contents of the BTM0CY flag at system reset
(power-on reset or CE reset).
For details of power failure detection, refer to 22. RESET.
Figure 12-2. Outline of Basic Timer 0
Clock select block
BTM0CK0 flag
BTM0CK1 flag
4.5 MHz
Divider
Selector
Flip-flop
BTM0CY flag
Remarks 1. BTM0CK1 and BTM0CK0 (bits 1 and 0 of the basic timer clock select register: refer to Figure
12-3) set the time intervals at which the BTM0CY flag is set.
2. BTM0CY (bit 0 of the basic timer 0 carry FF judge register: refer to Figure 12-4) detects the
status of the flip-flop.
115
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.2.2 Clock select block
The clock select block divides the system clock (4.5 MHz) and sets the time interval at which the BTM0CY
flag is to be set, by using the basic timer clock select register.
Figure 12-3 shows the configuration of the basic timer clock select register.
Figure 12-3. Configuration of Basic Timer Clock Select Register
Name
Flag symbol
Address
09H
Read/
write
b
3
b
2
b
1
b
0
R/W
B
T
M
1
B
T
M
1
B
T
M
0
B
T
M
0
Basic timer clock select
register
C
K
1
C
K
0
C
K
1
C
K
0
Sets time interval at which BTM0CY flag is set
0
0
1
1
0
1
0
1
100 ms (10 Hz)
250 ms (4 Hz)
5 ms (200 Hz)
1 ms (1 kHz)
Sets time interval at which IRQBTM1 flag is setNote
100 ms (10 Hz)
0
0
1
1
0
1
0
1
250 ms (4 Hz)
5 ms (200 Hz)
1 ms (1 kHz)
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
Retained
Note
For Basic timer 1, refer to 12.3.
116
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.2.3 Flip-flop and BTM0CY flag
The flip-flop is set at fixed intervals and its status is detected by the BTM0CY flag of the basic timer 0 carry
FF judge register.
When the BTM0CY flag reads out its contents to the window register by PEEK instruction execution, it is reset
to 0 (Read & Reset).
The BTM0CY flag is 0 at power-on reset, and is 1 at CE reset and on execution of the clock stop instruction.
Therefore, this flag can be used to detect a power failure.
The BTM0CY flag is not set after power application until an instruction that reads it is executed. Once the
read instruction has been executed, the flag is set at fixed intervals.
Figure 12-4 shows the configuration of the basic timer 0 carry FF judge register.
Figure 12-4. Configuration of Basic Timer 0 Carry FF Judge Register
Name
Flag symbol
Address
17H
Read/
write
b
3
b2
b
1
b
0
0
0
0
B
T
Basic timer 0 carry FF judge
register
R & Reset
M
0
C
Y
Detects status of flip-flop
0
1
Flip-flop is not set
Flip-flop is set
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
1
1
117
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.2.4 Example of using basic timer 0
An example of a program using basic timer 0 is shown below.
This program executes processing A every 1 second.
Example
CLR2 BTM0CK1, BTM0CK0 ; Sets BTM0CY flag setting pulse to 10 Hz (100 ms)
MOV M1, #0
LOOP:
SKT1 BTM0CY
; Branches to NEXT if BTM0CY flag is “0”
BR
NEXT
ADD
SKE
BR
M1, #1
M1, #0AH
NEXT
; Adds 1 to M1
Executes processing A if M1 is “10” (1 second has elapsed)
;
MOV M1, #0
Processing A
NEXT:
Processing B
BR LOOP
; Executes processing B and branches to LOOP
118
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.2.5 Errors of basic timer 0
Errors of basic timer 0 include an error due to the detection time of the BTM0CY flag, and an error that occurs
when the time interval at which the BTM0CY flag is to be set is changed.
The following paragraphs (1) and (2) describe each error.
(1) Error due to detection time of BTM0CY flag
The time to detect the BTM0CY flag must be shorter than the time at which the BTM0CY flag is set (refer
to 12.2.6 Notes on using basic timer 0).
Where the time interval at which the BTM0CY flag is detected is tCHECK and the time interval at which the
flag is set is tSET (250, 10, 5, or 1 ms), tCHECK and tSET must relate as follows.
tCHECK < tSET
At this time, the error of the timer when the BTM0CY flag is detected is as follows, as shown in Figure
12-5.
0 < Error < tSET
Figure 12-5. Error of Basic Timer 0 due to Detection Time of BTM0CY Flag
H
BTM0CY flag
setting pulse
L
tSET
1
0
BTM0CY flag
tCHECK1
tCHECK2
t
CHECK3
SKT1
BTM0CY
<1>
SKT1
BTM0CY
<2>
SKT1
BTM0CY
<3>
SKT1
BTM0CY
<4>
As shown in Figure 12-5, the timer is updated because BTM0CY flag is 1 when it is detected in step <2>.
When the flag is detected next in step <3>, it is 0. Therefore, the timer is not updated until the flag is
detected again in <4>.
This means that the timer is extended by the time of tCHECK3.
119
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) Error when time interval to set BTM0CY flag is changed
The BTM0CK1 and BTM0CK0 flags set the time of the BTM0CY flag.
As described in 12.2.2, four types of timer time-setting pulses can be selected: 1 kHz, 200 Hz, 10 Hz,
and 4 Hz.
At this time, these four pulses operate independently. If the timer time-setting pulse is changed by using
the BTM0CK1 and BTM0CK0 flags, an error occurs as described in the example below.
Example
; <1>
INTIFLG BTM0CK1, NOT BTM0CK0
;
;
Sets BTM0CY flag setting pulse to 200 Hz (5 ms)
Sets BTM0CY flag setting pulse to 1 kHz (1 ms)
Processing A
; <2>
INITFLG BTM0CK1, BTM0CK0
Processing A
; <3>
INITFLG BTM0CK1, NOT BTM0CK0
;
Sets BTM0CY flag setting pulse to 200 Hz (5 ms)
At this time, the BTM0CY flag setting pulse is changed as shown in Figure 12-6.
Figure 12-6. Changing BTM0CY Flag Setting Pulse
H
Internal pulse
200 Hz
L
H
Internal pulse
1 kHz
L
H
BTM0CY flag
setting pulse
L
1
0
<1>
<2>
<3>
BTM0CY flag
SKT1 BTM0CY
As shown in Figure 12-6, if the BTM0CY flag setting time is changed and the new pulse falls, the BTM0CY
flag retains the previous status (<2> in the figure). If the new pulse rises, however, the BTM0CY flag
is set to 1 (<3> in the figure).
Although changing the pulse setting between 200 Hz (5 ms) and 1 kHz (1 ms) is described in this example,
the same applies to changing the pulse in respect to 4 Hz (250 ms) and 10 Hz (100 ms).
120
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Therefore, as shown in Figure 12-7, the error of the time until the BTM0CY flag is first set after the
BTM0CY flag setting time has been changed is as follows:
–tSET < Error < tCHECK
tSET:
New setting time of BTM0CY flag
tCHECK: Time to detect BTM0CY flag
Phase differences are provided among the internal pules of 4, 10, 200 Hz, and 1 kHz. Because these
phase differences are shorter than the newly set pulse time, they are included in the above error.
For the phase difference of each pulse, refer to 12.3.5 Notes on using basic timer 1.
Figure 12-7. Timer Error When BTM0CY Flag Setting Time Is Changed from A to B
(a) −tSET difference
(b) tCHECK difference
H
L
Internal pulse A
Internal pulse B
H
L
t
SET
t
SET
H
L
BTM0CY flag
setting pulse
H
L
BTM0CY flag
.
.
a = 0
a
a = 0
a
.
.
t
CHECK
SKT1 BTM0CY
Intrinsic timer time
Actual timer time
Time changed
Intrinsic timer time
Actual timer time
Time changed
An error of -tSET occurs if the BTM0CY flag
is detected immediately after the timer time
has been changed because the flag then
becomes “1”.
An error of tCHECK occurs if the timer time is
changed immediately after the BTM0CY
flag has been detected because the flag is
then reset once.
121
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.2.6 Cautions on using basic timer 0
(1) BTM0CY flag detection time interval
Keep the time to detect the BTM0CY flag shorter than the time at which the BTM0CY flag is set.
This is because if the time of processing B is longer than the time interval at which the BTM0CY flag is
set as shown in Figure 12-8, setting of the BTM0CY flag is overlooked.
Figure 12-8. BTM0CY Flag Detection and BTM0CY Flag
H
BTM0CY flag
setting pulse
L
t
SET
<1>
<2>
<3>
<4>
<5>
1
0
BTM0CY flag
SKT1 BTM0CY SKT1 BTM0CY
Processing A
SKT1 BTM0CY
Processing B
Because execution time of processing B takes too long
after detection of BTM0CY flag that has been set to 1 in
<2>, the BTM0CY flag that is set to 1 in <3> cannot be
detected.
(2) Timer updating processing time and BTM0CY flag detection time interval
As described in (1) above, time interval tSET at which the BTM0CY flag is detected must be shorter than
the time for which to set the BTM0CY flag.
At this time, even if the time interval at which the BTM0CY flag is detected is short, if the updating
processing time of the timer is long the processing of the timer may not be executed normally at CE reset.
Therefore, the following condition must be satisfied.
tCHECK + tTIMER < tSET
tCHECK: Time to detect BTM0CY flag
tTIMER: Timer updating processing time
tSET:
Time to set BTM0CY flag
An example is given below.
122
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example
Example of timer updating processing and BTM0CY flag detection time interval
START:
CLR2
BTIMER:
; <1>
BTM0CK1, BTM0CK0 ; Sets BTM0CY flag setting pulse to 10 Hz (100 ms)
SKT1
BR
BTM0CY
AAA
; Updates timer if BTM0CY flag is “1”
; Branches to AAA if BTM0CY flag is “0”
Timer updating
BR
BTIMER
AAA:
Processing A
BR
BTIMER
The timing chart of the above program is shown below.
H
CE pin
L
H
BTM0CY flag
setting pulse
L
t
SET
1
0
BTM0CY flag
BTM0CY detection interval
Timer updating processing
t
CHECK
tTIMER
If this timer updating processing
time is too long, CE reset is effected
during processing.
<1> SKT1
BTM0CY
<2> SKT1
BTM0CY
CE reset
(3) Correcting basic timer 0 carry at CE reset
Next, an example of correcting the timer at CE reset is described below.
As shown in the example below, the timer must be corrected at CE reset if the BTM0CY flag is used for
power failure detection and if the BTM0CY flag is used for a watch timer.
The BTM0CY flag is reset (to 0) first on power application (power-on reset), and is disabled from being
set until it is read once by the PEEK instruction.
If the CE pin goes high from low, a CE reset is effected in synchronization with the rising edge of the
BTM0CY flag setting pulse. At this time, the BTM0CY flag is set (to 1) and the timer is started.
By detecting the status of the BTM0CY flag at system reset (power-on reset or CE reset), therefore, it
can be identified whether a power-on reset or CE reset has been effected (power failure detection). That
is, a power-on reset has been effected if the flag is 0, and a CE reset has been effected if it is 1.
At this time, the watch timer must continue operating even if a CE reset has been effected.
However, because the BTM0CY flag is reset to 0 when it is read to detect a power failure, the set status
(1) of the BTM0CY flag is overlooked once.
Consequently, the watch timer must be updated if a CE reset is identified by means of power failure
detection.
For details of power failure detection, refer to 22. RESET.
123
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example
Example of correcting timer at CE reset (to detect power failure and update watch timer using
BTM0CY flag)
START:
; Program address 0000H
Processing A
; <1>
SKT1 BTM0CY
; Embedded macro
; Tests BTM0CY flag
BR
INITIAL
; if “0”, branches to INITIAL (power failure detection)
BACKUP:
; <2>
100 ms watch updating
; Corrects watch timer because of backup (CE reset)
LOOP:
; <3>
Processing B
SKF1 BTM0CY
: While performing processing B,
; tests BTM0CY flag and updates watch timer
BR
BR
BACKUP
LOOP
INITIAL:
CLR2 BTM0CK1, BTM0CK0
; Embedded macro
; Because power failure (power-on reset) occurs,
; sets setting time of BTM0CY flag to 100 ms, and
; executes processing C
Processing C
BR LOOP
Figure 12-9 shows the timing chart of the above program.
124
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 12-9. Timing Chart
5 V
0 V
H
V
DD
CE
L
BTM0CY flag setting
pulse (10 Hz)
H
L
1
0
BTM0CY flag
A
C
B
B
B
B
B
B
B
B
A
B
B
Program processing
Program instruction
<1>
<3>
<3>
<3> <3>
<3> <3>
<3> <3>
<1> <3> <3>
Power-on reset
Start from address 0
CE reset
Watch UP
Start from address 0
Watch UP
Watch UP
Watch UP
Application of
supply voltage
BTM0CY flag detected
Updates watch timer because
setting of BTM0CY flag (to 1)
is detected
Point A
Point B
Point C
Point D
Point E
As shown in Figure 12-9, the program is started from address 0000H because the internal 10-Hz pulse
rises when supply voltage VDD is first applied.
When the BTM0CY flag is detected at point A, it is judged that the BTM0CY flag is reset (to 0) and that
a power failure (power-on reset) has occurred because the power has just been applied.
Therefore, “processing C” is executed, and the BTM0CY flag setting pulse is set to 100 ms.
Because the content of the BTM0CY flag is read once at point A, the BTM0CY flag will be set to 1 every
100 ms.
Next, even if the CE pin goes low at point B and high at point C, the program counts up the watch timer
while executing “processing B”, unless the clock stop instruction is executed.
At point C, because the CE pin goes high from low, CE reset is effected at point D at which the BTM0CY
flag setting pulse rises next time, and the program is started from address 0000H.
When the BTM0CY flag is detected at point E at this time, it is set to 1. Therefore, this is judged to be
a back up (CE reset).
As is evident from the above figure, unless the watch is updated by 100 ms at point E, the watch is delayed
by 100 ms each time CE reset is effected.
If processing A takes longer than 100 ms when a power failure is detected at point E, the setting of the
BTM0CY flag is overlooked two times. Therefore, processing A must be completed within 100 ms.
The above description also applies when the BTM0CY flag setting pulse is set to 250, 5, or 1 ms.
Therefore, the BTM0CY flag must be detected for power failure detection within the BTM0CY flag setting
time after the program has been started from address 0000H.
125
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(4) If BTM0CY flag is detected at the same time as CE reset
As described in (3) above, CE reset is effected as soon as the BTM0CY flag is set to 1.
If the instruction that reads the BTM0CY flag happens to be executed at the same time as CE reset at
this time, the BTM0CY flag reading instruction takes precedence.
Therefore, if the next setting the BTM0CY flag (rising of BTM0CY flag setting pulse) after the CE pin has
gone high coincides with execution of the BTM0CY flag reading instruction, CE reset is effected at the
next timing at which the BTM0CY flag is set.
This operation is illustrated in Figure 12-10.
Figure 12-10. Operation When CE Reset Coincides with BTM0CY Flag Reading Instruction
H
CE pin
L
H
BTM0CY flag
setting pulse
L
1
0
BTM0CY flag
SKT1
SKT1
CE reset
BTM0CY
BTM0CY
H
L
1
0
BTM0CY flag
setting pulse
BTM0CY flag
Instruction
SKT1 BTM0CY
(PEEK ···)
(SKT ···)
Embedded macro
PEEK WR, . MF. BTM0CY SHR 4
SKT WR, #. DF. BTM0CY AND 000FH
4.44 µs
If BTM0CY flag is read at this time, CE reset is
effected delayed once.
Originally, program is started from address 0000H here.
However, CE reset is not effected because it happens to
coincide with program that reads BTM0CY flag.
Consequently, if the BTM0CY flag detection time interval coincides with the BTM0CY flag setting time
in a program that cyclically detects the BTM0CY flag, CE reset is never effected.
Therefore, the following point must be noted.
Because one instruction cycle is 4.44 µs (1/225 kHz), a program that detects the BTM0CY flag once, for
example, every 225 instructions, reads the BTM0CY flag every 4.44 µs × 225 = 1 ms.
Even if any of 1 ms, 5 ms, 100ms, or 250 ms is selected as the timer time setting pulse, if setting and
detection of the BTM0CY flag coincide once, CE reset is never effected.
126
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Therefore, do not create a cyclic program that satisfies the following condition.
tSET × 225
= n (n: natural number)
X
tSET: BTM0CY flag setting time
X: Cycle X step of instruction that reads BTM0CY flag
An example of a program that satisfies the above condition is shown below. Do not create such a
program.
Example
Processing A
SET
BTM0CK1, BTM0CK0 ; Embedded macro
; Sets BTM0CY flag setting pulse to 1 ms
LOOP:
AAA:
; <1>
SKT1 BTM0CY
; Embedded macro
BR
BR
BR
BBB
221 steps
LOOP
BBB:
221 steps
LOOP
Because the BTM0CY flag reading instruction in <1> is repeatedly executed every 225 instructions in
this example, CE reset is not effected if the BTM0CY flag happens to be set at the timing of the instruction
in <1>.
127
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.3 Basic Timer 1
12.3.1 General
Figure 12-11 illustrates basic timer 1.
Basic timer 1 issues an interrupt request at a fixed time interval and sets the IRQBTM1 flag to 1.
The interrupt generated by basic timer 1 is acknowledged when the IRQBTM1 flag is set, if the EI instruction has
been issued and the IPBTM1 flag has been set (refer to 11. INTERRUPTS).
Figure 12-11. Outline of Basic Timer 1
Clock select block
BTM1CK1 flag
BTM1CK0 flag
4.5 MHz
Divider
Selector
IRQBTM1 set signal
Remark BTM1CK1 and BTM1CK0 (bits 3 and 2 of the basic timer clock select register, refer to Figure 12-3) set
the time interval at which the IRQBTM1 flag is set.
12.3.2 Clock select block
The clock select block divides the system clock (4.5 MHz) and sets the time interval at which the IRQBTM1 flag
is to be set, by using the basic timer clock select register.
For the configuration and function of the basic timer clock select register, refer to Figure 12-3.
128
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.3.3 Application example of basic timer 1
A program example is shown below.
Example
M1
MEM
0.10H
; 80 ms counter
BTIMER1 DAT
0002H
; Symbol definition of basic timer 1 interrupt vector address
BR
START
; Branches to START
ORG
BTIMER1
; Program address (0002H)
ADD
SKT1
BR
M1, #0001B ; Adds 1 to M1
CY
; Tests CY flag
EI_RETI
; Returns if no carry
Processing A
EI_RETI:
START:
EI
RETI
INITFLG BTM1CK1, NOT BTM1CK0
; Embedded macro
; Sets basic timer 1 interrupt pulse to 5 ms
M1, #0000B ; Clears contents of M1 to 0
MOV
SET1
EI
IPBTM1
; Enables basic timer 1 interrupt
; Enables all interrupts
LOOP:
Processing B
BR
LOOP
This program executes processing A every 80 ms.
The points to be noted in this case are that the DI status is automatically set when an interrupt has been
acknowledged, and that the IRQBTM1 flag is set to 1 even in the DI status.
This means that the interrupt is acknowledged even if execution exits from an interrupt routine by execution of the
RETI instruction, if processing A takes longer than 5 ms.
Consequently, processing B is not executed.
129
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.3.4 Error of basic timer 1
As described in 12.3.3, the interrupt generated by basic timer 1 is acknowledged each time the basic timer 1
interrupt pulse falls, if the EI instruction has been executed, and if the interrupt has been enabled.
Therefore, an error of basic timer 1 occurs only when any of the following operations (1) to (3) is performed:
(1) When the first interrupt after the basic timer 1 interrupt has been enabled has been acknowledged
(2) When the time interval at which the IRQBTM1 flag is to be set is changed, i.e., when the first interrupt is
acknowledged after the interrupt pulse has been changed
(3) When data has been written to the IRQBTM1 flag
Figure 12-12 shows an error in each of the above operations.
Figure 12-12. Error of Basic Timer 1 (1/2)
(a) When interrupt by basic timer 1 is enabled
H
L
Basic timer 1
interrupt pulse
t
SET
1
IRQBTM1 flag
IPBTM1 flag
INTE FF
0
1
0
EI
DI
EI
EI
EI
Interrupt pending
<1><2>
<3>
SET1 IPBTM1
interrupt
Interrupt
acknowledged
Interrupt
acknowledged
acknowledged
At point <1> in the above figure, the interrupt by basic timer 1 is acknowledged as soon as the interrupt
is enabled.
At this time, the error is –tSET.
If an interrupt is enabled by the “EI” instruction at the next point <2>, the interrupt occurs at the falling edge
of the basic timer 1 interrupt pulse.
At this time, the error is:
–tSET < error < 0
130
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 12-12. Error of Basic Timer 1 (2/2)
(b) When basic timer 1 interrupt pulse is changed
H
L
Internal
pulse A
H
L
Internal
pulse B
H
L
1
Basic timer 1
interrupt pulse
IRQBTM1 flag
IPBTM1 flag
INTE FF
0
1
0
EI
DI
<1> Basic timer 1 interrupt
pulse changed
<3> Basic timer 1 interrupt
EI
EI
EI
EI
pulse changed
Interrupt acknowledged
<2> Interrupt acknowledged
Interrupt acknowledged
Even if the basic timer 1 interrupt pulse is changed to B at point <1> in the above figure, the interrupt is
acknowledged at the next point <2> because the basic timer 1 interrupt pulse does not fall.
If the basic timer 1 interrupt pulse is changed to A at <3>, the interrupt is immediately acknowledged
because the basic timer 1 interrupt pulse falls.
(c) When IRQBTM1 flag is manipulated
H
L
Basic timer 1
interrupt pulse
1
IRQBTM1 flag
IPBTM1 flag
INTE FF
0
1
0
EI
DI
EI
EI
EI
Interrupt acknowledged <1> SET1 IRQBTM1 <2> CLR1 IRQBTM1
Interrupt acknowledged
interrupt
interrupt not
acknowledged
acknowledged
The interrupt is immediately acknowledged if the IRQBTM1 flag is set to 1 at <1>.
If clearing the IRQBTM1 flag to 0 overlaps with the falling of the basic timer 1 interrupt pulse at <2>, the
interrupt is not acknowledged.
131
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.3.5 Notes on using basic timer 1
When creating a program, such as a watch program, in which processing is always performed at fixed time intervals
using basic timer 1 after the supply voltage has been applied (power-on reset), the basic timer 1 interrupt servicing
must be completed in a fixed time.
Let’s take the following example:
Example
M1
MEM
0.10H
; 1 ms counter
BTIMER1 DAT
0002H
; Symbol definition of interrupt vector address of basic timer 1
BR
START
; Branches to START
ORG
BTIMER1
; Program address (0002H)
ADD
SKT1
BR
M1, #0100B ; Adds 0100B to M1
CY
; Watch processing if carry occurs
; Returns if no carry occurs
EI_RETI
; <1>
Watch processing
EI_RETI:
START:
EI
RETI
INITFLG NOT BTM1CK1, BTM1CK0, NOT BTM0CK1, NOT BTM0CK0
; Embedded macro
; Sets time of interrupt by basic timer 1 to 250 ms
; and set time of BTM0CY flag to 100 ms
SET1
EI
IPBTM1
LOOP
; Embedded macro
; Enables interrupt by basic timer 1
; Enables all interrupts
LOOP:
Processing A
BR
In this example, watch processing <1> is executed every 1 second while processing A is executed.
If the CE pin goes high as shown in Figure 12-13 (a), CE reset is effected in synchronization with the rising of the
BTM0CY flag setting pulse.
If issuance of an interrupt request by the basic timer 1 happens to overlap with the setting of the BTM0CY flag
at this time, CE reset takes precedence.
When CE reset is effected, the basic timer 1 interrupt request (IRQBTM1) flag is cleared. Consequently, the timer
processing is skipped once.
132
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
To prevent this, a delay is actually provided to the rising of the BTM0CY flag setting pulse and falling of the basic
timer 1 interrupt pulse as shown in Figure 12-13 (b).
In the above example, therefore, skipping of the basic timer 1 interrupt is prevented, even if a CE reset is effected,
by performing the watch processing within 10 ms.
Because the BTM0CY flag setting pulse and basic timer 1 interrupt time setting pulse can be independently set
to 4 Hz (250 ms), 10 Hz (100 ms), 200 Hz (5 ms), or 1 kHz (1 ms), a time difference is provided as shown in Figure
12-14 and Table 12-1.
Consequently, if the basic timer 1 interrupt must be enabled even when a CE reset is effected, the servicing of
the basic timer 1 interrupt must be completed within the delay time of the pulse shown in Figure 12-14.
Figure 12-13. Timing Chart
(a)
H
CE pin
L
H
BTM0CY flag
setting pulse
L
H
Basic timer 1
interrupt pulse
L
Basic timer 1 interrupt
Because the BTM0CY flag setting pulse rises, a CE
reset is effected here. As a result, the basic timer 1
interrupt is skipped once.
(b)
H
CE pin
L
H
BTM0CY flag
setting pulse
L
H
Basic timer 1
interrupt pulse
L
Delay time: 10 ms in this case
Basic timer 1 interrupt
Basic timer 1 interrupt
CE reset
Because there is a delay of 10 ms between the
falling of the basic timer 1 interrupt pulse and the
rising of the BTM0CY flag setting pulse, if basic
timer 1 interrupt servicing is completed within 10
ms, the timer processing is executed normally,
even if a CE reset is effected.
133
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 12-14. Time Difference Between BTM0CY Flag Setting Pulse and Basic Timer 1 Interrupt Pulse
1 ms
BTM0CY
2 : 1 : 1
1 ms
INT
5 ms
1 ms
BTM0CY
5 ms
INT
Dummy
10 ms
100 ms
BTM0CY
100 ms
INT
250 ms
BTM0CY
250 ms
INT
134
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 12-1. Time Difference Between Rising Edge of BTM0CY Flag Setting Pulse
and Falling Edge of Basic Timer 1 Interrupt Pulse
Internal Pulse
BTM0CY Flag Setting Pulse Basic Timer 1 Interrupt Pulse
Minimum Value of Time Difference (Refer to Figure Below.)
t1
t2
1 ms
1 ms
1 ms
5 ms
666 µs
333 µs
333 µs
333 µs
333 µs
3 ms
333 µs
666 µs
666 µs
666 µs
666 µs
2 ms
1 ms
100 ms
250 ms
1 ms
1 ms
5 ms
5 ms
5 ms
5 ms
100 ms
250 ms
1 ms
2 ms
3 ms
5 ms
2 ms
3 ms
100 ms
100 ms
100 ms
100 ms
250 ms
250 ms
250 ms
250 ms
333 µs
1 ms
666 µs
4 ms
5 ms
100 ms
250 ms
1 ms
50 ms
10 ms
333 µs
1 ms
50 ms
40 ms
666 µs
4 ms
5 ms
100 ms
250 ms
40 ms
100 ms
10 ms
150 ms
H
BTM0CY flag
setting pulse
L
H
Basic timer 1
interrupt pulse
L
t1
t2
135
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.4 12-Bit Timer
12.4.1 General
Figure 12-15 illustrates the 12-bit timer.
The 12-bit timer operates as a timer by counting the basic clock (100 kHz or 20 kHz) by using a 12-bit counter,
and comparing its count value with a value set in advance.
Figure 12-15. Outline of 12-Bit Timer
Clock select block
Count block
TMOVF flag
Set
TMRES flag
TMRPT flag
TMCK flag
Selector
TMEN flag
DBF
12
Overflow
Timer/counter
(TMC)
4.5 MHz
Divider
Match
IRQTM
set signal
Match detector
Timer modulo
register (TMM)
12
DBF
Remarks 1. TMCK (bit 0 of 12-bit timer clock select register; refer to Figure 12-16) sets the basic clock frequency.
2. TMEN (bit 0 of 12-bit timer control register; refer to Figure 12-17) starts/stops the 12-bit timer.
3. TMRES (bit 1 of 12-bit timer control register; refer to Figure 12-17) controls resetting the timer/counter.
4. TMRPT (bit 2 of 12-bit timer control register; refer to Figure 12-17) selects the modulo count mode/free-
run count mode.
5. TMOVF (bit 0 of 12-bit timer overflow register; refer to Figure 12-18) detects an overflow in the timer/
counter.
136
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.4.2 Clock select block
The clock select block selects the basic clock that is used for the operation of the timer/counter.
Two basic clocks can be selected by using the TMCK flag.
Figure 12-16 shows the configuration and function of the 12-bit timer clock select register.
Figure 12-16. Configuration of 12-Bit Timer Clock Select Register
Clock select block
Count block
TMOVF flag
Set
TMRES flag
TMRPT flag
TMCK flag
Selector
TMEN flag
DBF
12
Overflow
Timer/counter
(TMC)
4.5 MHz
Divider
Match
IRQTM
set signal
Match detector
Timer modulo
register (TMM)
12
DBF
Remark R: retained
137
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.4.3 Count block
The count block counts the basic clock by using a 12-bit timer/counter. When the count value matches the value
of the timer modulo register, the count block issues an interrupt request.
The value of the timer/counter can be written or read via the data buffer.
The basic clock that is input to the timer/counter can be started or stopped by the TMEN flag.
The timer/counter can be reset by the TMRES flag.
The timer/counter is not automatically reset even when its count value matches the value of the timer modulo
register.
Either the modulo count mode or free-run count mode can be set by the TMRPT flag.
In the free-run count mode, the contents of the timer/counter are not reset even after a match between the value
of the timer/counter and the contents of the timer modulo register has been detected; therefore, the timer/counter
continues counting up.
In the modulo counter mode, the contents of the timer/counter are reset and then the timer/counter continues
counting when a match between the count value of the timer/counter and the contents of the timer modulo register
has been detected.
An overflow in the counter, if any, can be detected by the TMOVF flag. If an overflow has been detected, the
counting operation is stopped.
Figure 12-17 shows the configuration and function of the 12-bit timer control register.
Figure 12-18 shows the configuration and function of the 12-bit timer overflow register.
Figures 12-19 and 12-20 show the configurations of the timer/counter and timer modulo register respectively.
Figure 12-17. Configuration of 12-Bit Timer Control Register
Name
Flag symbol
Address
0EH
Read/
write
b
3
b2
b1
b
0
12-bit timer control
register
0
T
M
R
P
T
T
M
R
E
S
T
M
E
R/W
N
Starts/stops timer/counter
Restarts timer/counterNote
Sets mode of 12-bit timer
0
1
Stops
Starts
0
1
Does not reset
Resets
0
1
Free-run count mode
Modulo count mode
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
0
Retained
Note The TMRES flag is always 0 when it is read.
138
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 12-18. Configuration of 12-Bit Timer Overflow Register
Name
Flag symbol
Address
0DH
Read/
write
b
3
b
2
b
1
b
0
12-bit timer overflow
register
0
0
0
T
M
O
V
F
R
Detects overflow in timer/counter
0
1
Overflow does not occur
Overflow occurs
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
R
Remark R: retained
139
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 12-19. Configuration of Timer/Counter
Name
Symbol
Address
Bit
Data buffer
DBF3
0CH
DBF2
0DH
DBF1
0EH
DBF0
0FH
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
Data
Transfer data
GET
16
Peripheral register
Peripheral
Name
Timer/
counter
b
15
b
14
b
13
b
12
b
11
b
10
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Symbol
TMC
address
L
S
B
M
S
B
47H
Valid data
Measured value of timer/counter
0
|
• In free-run count mode, counts up to
FFFH and stops counting at the next
clock.
• In modulo count mode, counts up to
the data value set in the timer modulo
register, is cleared to 000H at the next
clock, then continues counting.
x
|
212 −1 (FFFH)
Fixed to 0
140
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 12-20. Configuration of Timer Modulo Register
Name
Symbol
Address
Bit
Data buffer
DBF3
0CH
DBF2
0DH
DBF1
0EH
DBF0
0FH
b3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
Data
Transfer data
GET
PUT
16
Name
Peripheral register
Peripheral
address
b
15
b
14
b
13
b
12
b
11
b
10
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Symbol
TMM
M
S
B
Timer
L
S
B
46H
modulo
register
Valid data
Set value of timer modulo
Setting prohibited
Modulo data
0
1
|
x
|
212 −1 (FFFH)
Fixed to 0
141
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.4.4 Application example of 12-bit timer
Example 1. Modulo count mode
TMINT
ORG
DAT
BR
0003H
; Symbol definition of 12-bit timer interrupt vector address
START
TMINT
; Program address (0003H)
Processing A
EI
RETI
START:
INITFLG TMCK
; Sets count clock to 100 kHz (10 µs)
MOV
MOV
MOV
PUT
SET1
EI
DBF2, #50 SHR 8 AND 0FH
DBF1, #50 SHR 4 AND 0FH
DBF0, #50 AND 0FH
TMM, DBF
IPTM
SET3
TMRPT, TMRES, TMEN
LOOP
LOOP:
Main processing
BR
This program executes processing A every 500 µs.
However, processing A must be completed within 500 µs.
Example 2. Free-run count mode
BR
Start
Start:
INITFLG TMCK
; Sets count clock to 100 kHz (10 µs)
INITFLG NOT TMRPT, TMRES, TMEN
Processing A
SKF1
BR
TMOVF
Overflow occurs
DBF, TMC
GET
Overflow occurs
This program is to measure the time required for processing A. The measurable time range is from 10 µs to 40,950
µs (the software in Example 2 cannot measure time exceeding 40,950 µs and therefore, execution must branch to
another routine to measure the time longer than 40,950 µs).
This program is used to measure the pulse width of a remote controller signal.
The modulo count mode is useful for issuing an interrupt request at fixed time intervals, but the free-run count mode
is better to measure total time.
142
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
12.4.5 Error of 12-bit timer
The 12-bit timer produces an error of a maximum of 1 basic clock in the following cases:
(1) When TMEN flag is manipulated
When the TMEN flag is set, an error of 0 to +1 clock occurs.
When the TMEN flag is cleared, an error of 0 to –1 clock occurs.
(2) When counter in operation is reset
When the counter is reset, an error of 0 to +1 clock occurs.
(3) When basic clock is changed during counter operation
An error of 0 to +1 clock of the new clock occurs.
12.4.6 Notes on using 12-bit timer
The interrupt by the 12-bit timer may be generated at the same time as the interrupt by basic timer 1 and CE reset.
If the timer must be updated even at CE reset, do not use the 12-bit timer. Instead, use basic timer 1.
143
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13. A/D CONVERTER (ADC)
13.1 General
Figure 13-1 illustrates the A/D converter.
The A/D converter compares an analog voltage input to the ADC0 or ADC1 pins with the internal compare voltage,
judges the comparison result via software, and converts the analog signal into a 6-bit digital signal.
The comparison result can be detected by the ADCCMP flag.
As the comparison method, successive approximation is employed.
Figure 13-1. Outline of A/D Converter
ADCCH1 flag
ADCCH0 flag
P1B
0
1
/ADC
0
1
Set/reset
Input select
block
Compare block
ADCCMP flag
P1B
/ADC
DBF
6
Compare voltage
generator block
(R-string D/A
converter)
Remarks 1. ADCCH0 and ADCCH1 (bits 0 and 1 of the A/D converter channel select register; refer to Figure
13-3) select the pin used for the A/D converter.
2. ADCCMP (bit 0 of the A/D converter compare judge register; refer to Figure 13-5) detects the result
of comparison.
144
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13.2 Input Selector Block
Figure 13-2 shows the configuration of the input selector block.
The input selector block selects the pin to be used via the A/D converter channel select register.
Two or more pins cannot be used at the same time with the A/D converter.
Figure 13-3 shows the configuration and function of the A/D converter channel select register.
Figure 13-2. Configuration of Input Selector Block
ADCCH1 flag
ADCCH0 flag
Selector
P1B
P1B
0
/ADC
/ADC
0
1
Compare block
V
ADCIN
1
Each I/O port
Figure 13-3. Configuration of A/D Converter Channel Select Register
Name
Flag symbol
Address
14H
Read/
write
b3
0
b2
0
b1
b0
A/D converter channel
select register
R/W
A
D
C
C
H
1
A
D
C
C
H
0
Sets pin used for A/D converter
0
0
1
1
0
1
0
1
P1B
0
/ADC
0
1
pin
pin
P1B
1
/ADC
A/D converter is not used (general-purpose input port)
A/D converter is not used (general-purpose input port)
Fixed to 0
Power-on
Clock stop
CE
0
0
1
1
1
1
1
1
145
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13.3 Compare Voltage Generator Block and Compare Block
Figure 13-4 shows the configuration of the compare voltage generator block and compare block.
The compare voltage generator block switches over the tap decoder by using 6-bit data set to the A/D converter
data register to generate 64 steps of compare voltage VREF.
In other words, this block is an R-string D/A converter.
The power source of the R string is the same as the VDD supplied to the device.
The voltage applied to the resistor of the R string is only supplied when the ADCCMP flag is read by using the PEEK
instruction.
The compare block judges which of the voltage VADCIN input from a pin and compare voltage VREF is greater.
Comparison is made by a comparator when the ADCCMP flag is read. Therefore, one compare time of the A/D
converter is equal to one instruction execution time (4.44 µs).
Figures 13-5 and 13-6 show the configuration and function of the A/D converter compare judge register and A/
D converter data register. Table 13-1 lists the compare voltages.
Figure 13-4. Configuration of Compare Voltage Generator Block and Compare Block
1/2 VDD
−
V
ADCIN
ADCCMP
flag
Comparator
2 pF
DBF
V
REF
+
A/D converter data
register (ADCR)
Tap decoder
V
DD
0
1
2
62
63
1
2
3
2
R
R
R
R
Reading ADCCMP flag
by PEEK instruction
146
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 13-5. Configuration of A/D Converter Compare Judge Register
Name
Flag symbol
Address
06H
Read/
write
b
3
b2
b1
b
0
A/D converter compare
judge register
0
0
0
A
D
C
C
M
P
R
Detects result of comparison by A/D converter
0
1
V
ADCIN < VREF
ADCIN > VREF
V
Fixed to 0
Power-on
Clock stop
CE
0
0
0
U
R
R
Remark U: Undefined
R: Retained
147
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 13-6. Configuration of A/D Converter Data Register
Data buffer
DBF3
DBF2
DBF1
DBF0
Transfer data
Don't care
Don't care
GET
PUT
Peripheral register
8
Peripheral
Name
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
Symbol
ADCR
address
A/D converter data register
0
0
02H
Valid data
Sets compare voltage of A/D converter
0
V
REF = 0 V
1
|
x − 0.5
64
VREF
=
× VDD (V)
x
|
FFH
Fixed to 0
148
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 13-1. Set Values of A/D Converter Data Register and Compare Voltages
Set Data of ADCR
Compare Voltage
Set Data of ADCR
Compare Voltage
Decimal
Hexadecimal
(HEX)
Logic Voltage
At VDD = 5 V
Unit: V
Decimal
Hexadecimal
(HEX)
Logic Voltage
At VDD = 5 V
Unit: V
(DEC)
Unit: × VDD V
(DEC)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Unit: × VDD V
31.5/64
32.5/64
33.5/64
34.5/64
35.5/64
36.5/64
37.5/64
38.5/64
39.5/64
40.5/64
41.5/64
42.5/64
43.5/64
44.5/64
45.5/64
46.5/64
47.5/64
48.5/64
49.5/64
50.5/64
51.5/64
52.5/64
53.5/64
54.5/64
55.5/64
56.5/64
57.5/64
58.5/64
59.5/64
60.5/64
61.5/64
62.5/64
0
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
0
0
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
2.461
2.539
2.617
2.695
2.773
2.852
2.930
3.008
3.086
3.164
3.242
3.320
3.398
3.477
3.555
3.633
3.711
3.789
3.867
3.945
4.023
4.102
4.180
4.258
4.336
4.414
4.492
4.570
4.648
4.727
4.805
4.883
1
0.5/64
0.039
0.117
0.195
0.273
0.352
0.430
0.508
0.586
0.664
0.742
0.820
0.898
0.977
1.055
1.133
1.211
1.289
1.367
1.445
1.523
1.602
1.680
1.758
1.836
1.914
1.992
2.070
2.148
2.227
2.305
2.383
2
1.5/64
3
2.5/64
4
3.5/64
5
4.5/64
6
5.5/64
7
6.5/64
8
7.5/64
9
8.5/64
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
9.5/64
10.5/64
11.5/64
12.5/64
13.5/64
14.5/64
15.5/64
16.5/64
17.5/64
18.5/64
19.5/64
20.5/64
21.5/64
22.5/64
23.5/64
24.5/64
25.5/64
26.5/64
27.5/64
28.5/64
29.5/64
30.5/64
149
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13.4 Comparison Timing Chart
The ADCEN flag is automatically cleared to 0 when the comparison operation has been completed.
Therefore, because the ADCEN flag is detected after it has been set, and the comparison result (ADCCMP flag)
is read when the ADCEN flag has been cleared, one compare time is equal to three instruction execution times (6
µs).
Figure 13-7 shows the timing chart.
Figure 13-7. Timing Chart of A/D Converter’s Compare Operation
Instruction cycle
Sample & hold
ADCEN flag
Comparison result
ADCCMP flag
13.5 Performance of A/D Converter
The performance of the A/D converter is as follows.
Parameter
Resolution
Performance
6 bits
Input voltage range
Quantization error
0-VDD
1
LSB
2
Over range
62.5
×
VDD
64
Offset, gain, and
3
2
Note
LSB
non linearity errors
Note Including quantization error.
150
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13.6 Using A/D Converter
13.6.1 Comparing one compare voltage
Here is a program example.
Example To compare input voltage VADCIN of the ADC0 pin with compare voltage VREF (31.5/64 VDD) and branch
to AAA if VADCIN > VREF or to BBB if VADCIN < VREF
INIT:
ADCR7
ADCR6
ADCR5
ADCR4
ADCR3
ADCR2
ADCR1
ADCR0
FLG 0.0EH.3
FLG 0.0EH.2
FLG 0.0EH.1
FLG 0.0EH.0
FLG 0.0FH.3
FLG 0.0FH.2
FLG 0.0FH.1
FLG 0.0FH.0
; Dummy
; Dummy
; Defines each bit of data buffer as ADCR data setting
; flag
CLR2
ADCCH1, ADCCH0
; Sets P1B0/ADC0 pin for the A/D converter
START:
INITFLG NOT ADCR3, NOT ADCR2, NOT ADCR1, NOT ADCR0
INITFLG NOT ADCR7, NOT ADCR6, ADCR5, NOT ADCR4
PUT
SKT1
BR
ADCR, DBF
ADCCMP
AAA
; Sets compare voltage VREF to 31.5/64 VDD
; Detects ADCCMP flag, and
; branches to AAA if False (0)
; branches to BBB if True (1)
BR
BBB
151
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13.6.2 Successive approximation by binary search method
The A/D converter can compare only one voltage at one time.
To convert an input voltage into a digital signal, therefore, successive approximation must be executed by
program.
If the processing time of the successive approximation program differs depending on the input voltage, the
relationship with the other processing programs may be undesirable.
Therefore, use of the binary search method as explained in (1) through (3) below is recommended.
(1) Concept of binary search
The concept of binary search is explained below.
First, the compare voltage is set to 1/2 VDD. If the result of comparison is True (a high level is input), a voltage
of 1/4 VDD is added to the result; if the result of comparison is False (a low level is input), a voltage of 1/4 VDD
is subtracted from the result and compared.
Subsequently, the compare voltage is sequentially compared with 1/8 VDD and 1/16 VDD to 1/64 VDD. If the
result of comparison is False after comparison has been executed six times, 1/64 VDD is subtracted from the
result and comparison is completed.
1
1/2
0
1
H
L
15/16
13/16
H
L
63/64
61/64
63/64
62/64
61/64
60/64
L
L
H
7/8
H
31/32
H
3/4
1/4
15/16
13/16
H
L
11/16
9/16
7/16
5/16
H
L
59/64
57/64
55/64
53/64
59/64
58/64
57/64
56/64
55/64
54/64
L
L
L
L
L
5/8
3/8
L
29/32
27/32
Compare
voltage
H
L
H
L
(×VDD
)
H
H
53/64
52/64
L
H
L
3/16
1/16
H
L
51/64
49/64
51/64
50/64
49/64
48/64
L
L
25/32
L
1/8
L
Subtracts 1/64
if False
First
time
Second
time
Third
time
Fourth
time
Fifth
time
Sixth
time
152
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) Flowchart of binary search method
START
Initialization
: Sets pin to be used
ADCR ← 100000B
: Sets compare voltage to 1/2 VDD
: Detects result of comparison
Y
ADCCMP = 1?
N
Resets b5 of ADCR
: If result is “0”, subtracts 1/2 VDD
: Adds 1/4 VDD to result to set compare voltage regardless of
whether result is “0” or “1”
Sets b4 of ADCR
Y
ADCCMP = 1?
: Detects result of comparison
: If result is “0”, subtracts 1/4 VDD
N
Resets b4 of ADCR
: Adds 1/8 VDD to result to set compare voltage regardless of
whether result is “0” or “1”
Sets b3 of ADCR
Y
ADCCMP = 1?
: Detects result of comparison
: Subtracts 1/8 VDD if result is “0”
N
Resets b3 of ADCR
: Adds 1/16 VDD to result to set compare voltage regardless of
whether result is “0” or “1”
Sets b2 of ADCR
Y
ADCCMP = 1?
: Detects result of comparison
N
Resets b2 of ADCR
: Subtracts 1/16 VDD if result is “0”
: Adds 1/32 VDD to result to set compare voltage regardless of
whether result is “0” or “1”
Sets b1 of ADCR
Y
ADCCMP = 1?
: Detects result of comparison
N
Resets b1 of ADCR
: Subtracts 1/32 VDD if result is “0”
: Adds 1/64 VDD to result to set compare voltage regardless of
whether result is “0” or “1”
Sets b0 of ADCR
Y
ADCCMP = 1?
: Detects result of comparison
N
Resets b0 of ADCR
: Subtracts 1/64 VDD if result is “0”
Detects contents of ADCR
END
: Completes conversion with current value if result is “1”
153
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(3) Program example of binary search method
(a) Method with short conversion time
INIT:
ADCR7
ADCR6
ADCR5
ADCR4
ADCR3
ADCR2
ADCR1
ADCR0
FLG 0.0EH.3
FLG 0.0EH.2
FLG 0.0EH.1
FLG 0.0EH.0
FLG 0.0FH.3
FLG 0.0FH.2
FLG 0.0FH.1
FLG 0.0FH.0
; Dummy
; Dummy
; Defines each bit of data buffer as ADCR data setting flag
CLR2
ADCCH1, ADCCH0
; Sets P1B0/ADC0 pin for the A/D converter
START:
INITFLG NOT ADCR3, NOT ADCR2, NOT ADCR1, NOT ADCR0
INITFLG NOT ADCR7, NOT ADCR6, ADCR5, NOT ADCR4
PUT
ADCR, DBF
ADCCMP
ADCR5
; Sets compare voltage to 31.5/64 VDD
; Detects ADCCMP and subtracts
; 32/64 VDD if “0” and adds
; 16/64 VDD
SKT1
CLR1
SET1
PUT
ADCR4
ADCR, DBF
ADCCMP
ADCR4
SKT1
CLR1
SET1
PUT
; Detects ADCCMP and subtracts
; 16/64 VDD if “0” and adds
; 8/64 VDD
ADCR3
ADCR, DBF
ADCCMP
ADCR3
SKT1
CLR1
SET1
PUT
; Detects ADCCMP and subtracts
; 8/64 VDD if “0” and adds
; 4/64 VDD
A/D conversion
ADCR2
ADCR, DBF
ADCCMP
ADCR2
SKT1
CLR1
SET1
PUT
; Detects ADCCMP and subtracts
; 4/64 VDD if “0” and adds
; 2/64 VDD
ADCR1
ADCR, DBF
ADCCMP
ADCR1
SKT1
CLR1
SET1
PUT
; Detects ADCCMP and subtracts
; 2/64 VDD if “0” and adds
; 1/64 VDD
ADCR0
ADCR, DBF
ADCCMP
ADCR0
SKT1
CLR1
; Detects ADCCMP and subtracts
; 1/64 VDD if “0”
END:
Number of program steps: 31 steps
Number of execution steps: 31 steps
A/D conversion time:
137.8 µs
154
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(b) Method with fewer program steps
ADWORK1 MEM
ADWORK0 MEM
0.00H
0.01H
; Work area for changing compare voltage
INITFLG NOT ADCCH1, NOT ADCCH0
; Sets P1B0/ADC0 pin for the A/D converter
START:
MOV
MOV
MOV
MOV
DBF1, #0010B
; Sets compare voltage to initial value of 31.5/64 VDD
DBF0, #0000B
ADWORK1, #0001B
ADWORK0, #0000B
AD_CHECK:
PUT
SKT1
BR
ADCR, DBF
ADCCMP
; Sets compare voltage VREF
; Detects ADCCMP flag
ADIN_L
ADD
ADDC
BR
DBF0, ADWORK0
DBF1, ADWORK1
NEXT_AD
; Increases compare voltage if “1”
A/D
ADIN_L:
conversion
SUB
DBF0, ADWORK0
DBF1, ADWORK1
; Decreases compare voltage if “0”
SUBC
NOP
;
; Described to keep A/D conversion time constant
NEXT_AD:
RORC
RORC
SKT1
BR
ADWORK1
ADWORK0
CY
; 6 bits completed?
AD_CHECK
ADCR, DBF
ADCCMP
PUT
SKT1
AND
DBF0, #1110B
.
.
.
Number of program steps: 22 steps
Number of execution steps: 58 to 63 steps
A/D conversion time:
257.8 to 280 µs
Where the A/D conversion time is held constant
Number of program steps: 23 steps
Number of execution steps: 63 steps
A/D conversion time:
280 µs
155
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
13.7 Status on Reset
13.7.1 On power-on reset
All the P1B1/ADC1 and P1B0/ADC0 pins are set in the general-purpose input port mode.
13.7.2 On execution of clock stop instruction
All the P1B1/ADC1 and P1B0/ADC0 pins are set in the general-purpose input port mode.
13.7.3 On CE reset
All the P1B1/ADC1 and P1B0/ADC0 pins are set in the general-purpose input port mode.
156
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
14. D/A CONVERTER (DAC)
The D/A converter (DAC) outputs its signal by means of PWM (Pulse Width Modulation), which varies the
duty factor.
By connecting an external lowpass filter to the D/A converter, digital signals can be converted into analog
signals.
14.1 Configuration of D/A Converter
Figure 14-1 shows the block diagram of the D/A converter.
As shown in the figure, the D/A converter consists of an output select block and a duty setting block for each
pin, and a clock generation block.
Figure 14-1. Block Diagram of D/A Converter
Control register
Data buffer
Output select
block
Duty setting
block
P0C
1
0
/PWM
1
0
f
PWM1
Clock
generation
block
Output select
block
Duty setting
block
P0C
/PWM
fPWM0
14.2 Functional Outline of D/A Converter
The D/A converter outputs a variable-duty signal to each output pin.
The output frequency is 4.4 kHz, and the duty factor can be changed in 256 steps.
The following subsections 14.2.1 through 14.2.3 outline the function of each block of the D/A converter.
14.2.1 Output select blocks
The output select blocks specify whether each pin is used as a general-purpose output port pin or a D/A
converter pin.
The mode of each pin is selected by PWM1SEL and PWM0SEL of the PWM mode select register (refer to
14.3).
14.2.2 Duty setting blocks
The duty setting blocks output a signal whose duty factor can be changed in 256 steps.
The duty factor of each output pin is independently set by the PWM data register (PWMR0 or PWMR1:
peripheral address 04H or 05H) via the data buffer (refer to 14.4).
14.2.3 Clock generation block
The clock generation block generates a basic clock that is used to set the duty factor of the output signal.
The generated clock frequency fPWM is 1.125 MHz (refer to 14.4).
157
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
14.3 Output Select Blocks
14.3.1 Configuration of output select blocks
Figure 14-2 shows the configuration of the output select blocks.
Figure 14-2. Configuration of Output Select Blocks
PWM1SEL flag
PWM0SEL flag
P0C
1
/PWM
1
Duty setting block
1
0
Output latch
P0C
0
/PWM
0
Duty setting block
1
0
Output latch
14.3.2 Function of output select blocks
The output select blocks select whether the P1B2/PWM1 and P1B1/PWM0 pins are used as general-purpose
output port pins or D/A converter pins.
This selection can be made by the PWM1SEL and PWM0SEL flags of the PWM mode select register. Each
pin can be set in the port mode or D/A converter mode independently.
The P0C1/PWM1 and P0C0/PWM0 pins are N-ch open-drain output pins and must be connected with an
external pull-up resistor.
The configuration and function of the PWM mode select register is shown in Figure 14-3.
158
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 14-3. Configuration of PWM Mode Select Register
Name
Flag symbol
Address
13H
Read/
write
b3
0
b2
0
b1
b0
PWM mode select
register
P
W
M
1
P
W
M
0
R/W
S
E
L
S
E
L
Sets function of P0C
0
/PWM
0
pin
pin
0
1
General-purpose output port
D/A converter
Sets function of P0C
1
/PWM
1
0
1
General-purpose output port
D/A converter
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
Retained
159
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
14.4 Duty Setting Blocks and Clock Generation Block
14.4.1 Configuration of duty setting blocks and clock generation block
Figure 14-4 shows the configuration of the duty setting blocks and clock generation block.
Figure 14-4. Configuration of Duty Setting Blocks and Clock Generation Block
Data buffer (DBF)
Address
Symbol
Data
0CH
0DH
0EH
0FH
DBF3
DBF2
DBF1
DBF0
M
S
B
L
S
B
Don't care Don't care
Peripheral address 05H
8
PWM1 data register
(PWMR1)
To output block
Comparator
f
PWM1
Counter (8 bits)
1.125 MHz
Peripheral address 04H
8
Clock
generation
block
PWM0 data register
(PWMR0)
To output block
Comparator
f
PWM0
Counter (8 bits)
1.125 MHz
14.4.2 Function and configuration of clock generation blocks
The clock generation block outputs the basic clocks (fPWM1 and fPWM0) that set the duty factor of each output
signal (of PWM1 and PWM0 pins).
The output frequency is 1.125 MHz (0.89 µs) for both fPWM1 and fPWM0.
However, fPWM1 and fPWM0 have the following phase difference.
f
f
PWM1
PWM0
222 ns
222 ns
888 ns
160
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
14.4.3 Function and operation of duty setting blocks
The duty setting blocks compare the value set to each PWM data register (PWM1 and PWM0) with the value
of each basic clock (fPWM1 and fPWM0) counted by an 8-bit counter, and output a high level if the value of the PWM
data register is greater, and a low level if the value of PWM data register is less.
Where the value set to the PWM data register is “x”, the duty factor is as follows.
x + 0.25
Duty factor: D =
× 100%
256
0.25 is an offset. A high level is output even when x = 0.
Because the basic clock is 1.125 MHz, the frequency and cycle of the output signal are as follows.
1.125 MHz
Frequency: f =
= 4.3945 kHz
256
256
Cycle:
T =
= 227.6 µs
1.125 MHz
An independent value can be set to each PWM data register via the data buffer.
In other words, each pin can output a signal with an independent duty factor.
The following subsections 14.4.4 and 14.4.5 explain the configuration and function of each PWM data
register, and the relationship between the output waveform and duty factor of each pin.
161
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
14.4.4 Configuration and function of each PWM data register
The function of each PWM data register is illustrated below.
The PWM data register sets the duty factor of a D/A converter (PWM output) output signal.
Name
Symbol
Address
Bit
Data buffer
DBF3
0CH
DBF2
0DH
DBF1
0EH
DBF0
0FH
b
3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
Data
Don't care
Don't care
Transfer data
8
GET can be executed
PUT can be executed
Peripheral register
Peripheral
Peripheral
hardware
Name
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
address
PWM0 data register
PWMR0
04H
PWM
0
pin
Valid data
PWM1 data register
PWMR1
05H
PWM
1
pin
Sets PWM output duty of each pin
x + 0.25
0
Duty: D =
× 100%
256
1.125 MHz
256
Frequency: f =
x
= 4.3945 kHz
255
162
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
14.4.5 Relationship of output waveform and each pin of D/A converter
(1) shows the relationship between the output waveform and duty factor. (2) shows the relationship of the
output waveform of each pin.
(1) Duty factor and output waveform
x = 0
x = 1
x = 2
888 ns
888 ns
222 ns
x = 255
666 ns
227.6 µs
(2) Output waveform of each pin
PWM
1
(x = 0)
PWM
0
(x = 0)
222 ns
227.6 µs
14.5 Cautions on Using D/A Converter
(1) The initial PWM output setting following the power on application is made in the following procedure. This
is because the PWM data register is undefined so that data should be set beforehand.
<1> Set the value of PWM data register
<2> Set the PWMnSEL flag
(2) Do not overwrite the data of PWM data register during PWM operation. The output of the correct duty for one
cycle (227.6 µs) cannot be obtained.
163
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
14.6 Status on Reset
14.6.1 On power-on reset
The P0C1/PWM1 and P0C0/PWM0 pins are set in the general-purpose output port mode.
The output value is undefined.
The value of each PWM data register is undefined.
14.6.2 On execution of clock stop instruction
The P0C1/PWM1 and P0C0/PWM0 pins are set in the general-purpose output port mode.
The output value is the previous contents of the output latch.
Each PWM data register retains the previous value.
14.6.3 On CE reset
The P0C1/PWM1 and P0C0/PWM0 pins retain the previous output status.
Therefore, the pin used for the D/A converter retains the current PWM output.
14.6.4 In halt status
The P0C1/PWM1 and P0C0/PWM0 pins retain the previous output status.
Therefore, the pin used for the D/A converter retains the current PWM output.
164
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15. SERIAL INTERFACE
The serial interface is used to transfer 8-bit serial data with an external device.
Figure 15-1. Block Diagram of Serial Interface
Control register
Data buffer
Peripheral address 03H
Presettable shift register
P0A
P0A
P0A
2
/SCK
/SO
/SI
1
1
1
1
I/O
con-
trol
0
Clock generation
Clock control
Serial interface
165
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.1 Configuration of Serial Interface
Figure 15-2 shows the configuration of the serial interface.
As shown in the figure, the shift clock control block of the serial interface consists of a clock I/O pin control
block, clock generation block, wait control block, and clock count block.
The serial data control block consists of a serial data I/O pin control block and a presettable shift register.
These blocks are controlled by the corresponding flags of the control registers.
Data is written to or read from the presettable shift register via the data buffer.
The following section 15.2 outlines each block.
Figure 15-2. Configuration of Serial Interface
Control register
Address
Flag
02H
S
I
O
1
T
S
S
S
I
S
I
O
1
C
K
0
I
O
1
H
I
symbol
O
1
C
K
1
Z
Shift clock I/O pin control block
WAIT
P0A
output control
2
/SCK
1
Output
latch
WRITE
port
register
READ
P0A
2
/SCK
1
Shift clock output
CLKOUT
SF8
SF8
clock
Clock
counter
control
Wait control
P0ABIO2 flag
Serial clock input
Serial data I/O pin control block
Data buffer (DBF)
Address 0CH 0DH 0EH
DBF3 DBF2 DBF1 DBF0
0FH
Symbol
Data
P0A
output control
1
/SO
1
Output
latch
WRITE
port
register
READ
P0A
1
/SO
1
M
S
B
L
S
B
03H
P0ABIO1 flag
CLKIN
Serial out data
DATAOUT
Output
latch
DATAIN
WRITE
port
P0A
0
/SI1
Presettable shift register
register
READ
P0ABIO0 flag
Serial in data
166
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.2 Functional Outline of Serial Interface
The serial interface uses the P0A2/SCK1, P0A1/SO1, and P0A0/SI1 pins.
The serial interface can select the internal clock or an external clock, and can execute receive and transmit
The following subsections 15.2.1 to 15.2.6 outline the functions of the respective blocks of the serial
interface.
For details of each block, refer to 15.3 to 15.7.
15.2.1 Shift clock I/O pin control block
This block selects the shift clock I/O pin.
The shift clock I/O pin is selected by the serial I/O mode select register.
Refer to 15.3.
15.2.2 Serial data I/O pin control block
This block selects the serial data I/O pin.
The serial data I/O pin is selected by the serial I/O mode select register.
Refer to 15.3.
15.2.3 Clock generation block
This block selects the clock frequency of the shift clock and controls the shift clock output timing.
The shift clock frequency is selected by the serial I/O mode select register.
Refer to 15.4.
15.2.4 Clock counter
The clock counter counts the number of rising edges of the clock output by the shift clock output pin and
outputs a signal at the eighth clock (SF8 signal).
The SF8 signal is used to make serial communication wait (pause).
Refer to 15.5.
15.2.5 Presettable shift register (SIO1SFR)
This shift register sets serial out data and stores serial in data.
It performs a shift operation by using the clock of the shift clock I/O pin and inputs/outputs data.
The output data is set and the input data is read via the data buffer.
Refer to 15.6.
15.2.6 Wait control block
This block places or releases serial communication in or from the wait status.
Serial communication is placed in or released from the wait status by the serial I/O mode select register.
Refer to 15.7.
167
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.3 Shift Clock and Serial Data I/O Pin Control Blocks
The shift clock and serial data I/O pin control blocks set the pins of the serial interface and control the
transmit/receive operations.
These control operations are specified by the serial I/O mode select register.
15.3.1 shows the configuration and function of the serial I/O mode select register.
15.3.2 indicates the status of each pin set by the serial I/O mode select register.
15.3.1 Configuration and function of serial I/O mode select register
The configuration and function of the serial I/O mode select register are illustrated below.
The SIO1CK1 and SIO1CK0 flags are used to select the internal clock or an external clock and to set the
frequency of the internal clock.
For details of the clock, refer to 15.4.
The SIO1TS flag places or releases the serial interface in or from the wait status.
For the wait operation, refer to 15.7.
Name
Flag symbol
Address
02H
Read/
write
b
3
b2
b1
b
0
Serial I/O mode select
register
S
I
O
1
T
S
S
I
S
I
O
1
C
K
1
S
I
O
1
C
K
0
R/W
O
1
H
I
Z
Sets I/O clock frequency of serial interface
0
0
1
1
0
1
0
1
External clock (slave)
37.5 kHz (master)
75 kHz (master)
450 kHz (master)
Sets P0A
1
/SO pin as serial out pin
1
0
1
General-purpose I/O port
Serial out
Starts serial communication of serial interface
0
1
Does not start serial communication (wait)
Starts serial communication (wait release)
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
0
0
168
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.3.2 Pin status setting by serial I/O mode select register
Table 15-1 shows the status of each pin set by the serial I/O mode select register.
As shown in this table, the I/O select flag of each pin must also be manipulated to set each pin.
For details of the I/O select flag, refer to 10. GENERAL-PURPOSE PORTS.
Table 15-1. Pin Status Setting by Serial I/O Mode Select Register
SIO1MODE
Pin
Communication
mode
Setting of
serial output
Clock
direction
Pin symbol
I/O select
flag of each
pin
Pin setting status
b
2
b1
b0
S
I
S
I
O
1
C
K
1
S
I
O
1
C
K
0
P
0
A
B
I
O
2
P
0
A
B
I
O
1
P
0
A
B
I
O
0
O
1
H
I
Z
0
0
0
External clock P0A
2
/SCK
1
3-wire
Wait : General-purpose input port
serial I/O
Wait released : External clock input
Wait : General-purpose output port
1
0
1
Wait released : External clock input
Wait : General-purpose input port
Wait released : Internal clock output
Wait : General-purpose output port
Wait released : General-purpose input port
General-purpose input port
General-purpose output port
General-purpose input port
Serial output
Internal clock
0
1
1
1
0
1
0
1
General-
purpose port
P0A
1
/SO
1
0
1
0
1
Serial output
P0A0/SI1
0
1
Serial input
General-purpose output port
169
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.4 Clock Generation Block
The clock generation block generates the clock when the internal clock is used (i.e., when a master operation
is performed) and controls the clock output timing.
The frequency fSC of the internal clock is set by using the SIO1CK1 and SIO1CK0 flags of the serial I/O mode
select register.
The shift clock is successively output until the value of the clock counter, which is explained in 15.5, reaches
“8”.
The following subsection 15.4.1 explains the clock output waveform and clock generation timing.
15.4.1 Internal shift clock generation timing
(1) On releasing wait status from initial status
The initial status is the status in which the internal clock is selected and the P0A2/SCK1 pin is set in the output
mode.
A high level is output to the P0A2/SCK1 pin in the wait status.
Wait release and clock selection can be made simultaneously.
Shift clock
1 : 1
Wait status
1/fSC
Initialization
Wait release
170
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) When wait operation is performed
For details of the wait operation, refer to 15.7.
(a) Wait status with value of clock counter reaching “8” (normal operation)
H
Shift
clock pin
Contents of output latch
L
Wait released status
Wait status
Wait release
1/fsc
Wait
(b) If forced wait is executed in wait status
H
Shift
clock pin
Contents of
output latch
Wait period
Contents of output latch
Wait period
L
Forced wait
by SIO1TS
(c) If forced wait is executed when wait status is released
At this time, the clock counter is reset.
H
Shift
clock pin
Contents of output latch
Wait status
L
Wait release status
1/fsc
Forced wait by SIO1TS
Contents of output latch
Wait release
H
L
Shift
clock pin
1/fsc
Wait release status
Wait status
Forced wait by SIO1TS
Wait release
(d) If wait status is released in wait release status
The clock output waveform is not changed at this time.
The clock counter is not reset. However, do not change the clock frequency during wait release.
171
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.5 Clock Counter
The clock counter is a wrap-around counter that counts the number of the shift clocks output from or input
to the shift clock (P0A2/SCK1) pin.
The clock counter directly reads the status of the shift clock pin. At this time, whether the clock is the internal
clock or an external clock is not identified.
The clock counter does not operate in the wait status of serial communication.
When the value of the clock counter is 8, serial communication is placed in the wait status at the rising edge
of the shift clock.
The contents of the clock counter cannot be directly read by program.
The following subsections 15.5.1 and 15.5.2 explain the operation of the clock counter and the conditions
under which the clock counter is reset.
15.5.1 Operation of clock counter
Figure 15-3 shows the operation of the clock counter.
The initial value of the clock counter is 0. The value of the clock counter is incremented by one each time
the falling of the shift clock pin is detected. When the value of the clock counter has been incremented to 8,
the clock counter is reset to 0 at the next rising edge of the shift clock pin.
Serial communication is placed in the wait status when the clock counter has been reset to 0.
Figure 15-3. Operation of Clock Counter
H
Shift
1
2
3
7
8
clock pin
L
H
L
Serial
data pin
D7
D6
D5
3
D1
D0
Clock
counter
0
1
2
7
8
0
Resets clock
counter
Releases wait
Wait
15.5.2 Clock counter reset condition
The clock counter is reset to 0 when any of the following conditions (1) through (5) is satisfied.
(1) On power-on reset
(2) On execution of the clock stop instruction
(3) When 0 is written to the SIO1TS flag (forced wait)
(4) When the shift clock rises while the value of the clock counter is “8” with the wait status released
(5) On CE reset
172
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.6 Presettable Shift Register (SIO1SFR)
The presettable shift register is an 8-bit shift register that writes serial out data and reads serial in data.
Data is written to or read from the presettable shift register via the data buffer by using the PUT or GET
instruction.
15.6.1 shows the configuration of the presettable shift register and its relationship with the data buffer.
The presettable shift register performs its shift operation in synchronization with the clock applied to the shift
clock (P0A2/SCK1) pin.
At this time, the contents of the most significant bit (MSB) of the presettable shift register are output to the
serial data output pin in synchronization with the fall of the shift clock, and the least significant bit (LSB) of the
presettable shift register is read in synchronization with the rise of the clock.
15.6.2 explains the points to be noted when writing or reading data to or from the presettable shift register.
The presettable shift register does not shift data in the wait status.
For details of the operation in each serial communication mode, refer to 15.8.
15.6.1 Configuration of presettable shift register and its relationship with data buffer
The configuration of the presettable shift register and its relationship with the data buffer are shown below.
Name
Symbol
Address
Bit
Data buffer
DBF3
0CH
DBF2
0DH
DBF1
0EH
DBF0
0FH
b
3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
Data
Don't care
Don't care
Transfer data
8
GET can be executedNote
PUT can be executedNote
Peripheral register
Peripheral
Symbol
Peripheral
hardware
Name
Presettable shift register
b
7
b6
b5
b
4
b
3
b2
b1
b
0
address
M
S
B
L
SIO1SFR
03H
Serial
S
B
interface
Valid data
Sets serial out data and reads serial
in data
D7 D6 D5 D4 D3 D2 D1 D0
D7←D6←D5←D4←D3←D2←D1←D0
Serial in
Serial out
Note If PUT or GET is executed in serial communication mode, data may be corrupted. For details, refer to 15.6.2
Notes on setting and reading data.
173
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.6.2 Notes on setting and reading data
Data is written to the presettable shift register by the PUT SIO1SFR, DBF instruction.
Data is read from the register by the GET DBF, SIO1SFR instruction.
Set or read data to or from the register in the wait status. While the wait status is released, the data may
not be correctly set or read depending on the status of the shift clock pin.
Table 15-2 indicates the timing of setting and reading data and points to be noted.
Table 15-2. Reading (GET) and Writing (PUT) Data from/to Presettable Shift Register and Notes
Status on Execution
of PUT/GET
Status of Shift Clock Pin
Operation of Presettable Shift Register (SIO1SFR)
Wait
Read (GET)
With external clock:
Floated
Normally read.
status
Write (PUT)
Normally written.
With internal clock:
Normally the output
latch value is used at
high level.
Content of MSB is output at falling edge of shift clock when wait
status is released next time (during transfer operation).
Clock
Data
MSB
PUT SIO1SFR, DBF
Wait released
Wait
Read (GET)
Write (PUT)
Low level
High level
Normally read.
released
status
Cannot be read normally.
Contents of SIO1SFR are destroyed.
Low level
Normally written.
Contents of MSB are output when PUT instruction is executed.
Clock counter is not reset.
Clock
Data
MSB
PUT SIO1SFR, DBF
High level
Cannot be written normally.
Contents of SIO1SFR are destroyed.
174
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.7 Wait Control Block
The wait control block controls communication of the serial interface by placing or releasing communication
in or from the wait status.
The wait control block is controlled by the SIO1TS flag of the serial I/O mode select register.
The following subsection 15.7.1 explains the wait operation and points to be noted.
15.7.1 Wait operation and notes
In the wait status, the clock generation block and presettable shift register stop operation, and serial
communication pauses.
Therefore, serial communication can be started when the wait status is released.
The wait status is released when 1 is written to the SIO1TS flag.
When 1 is written to this flag, the internal clock is output to the shift clock output pin (during master operation),
and presettable shift register and clock counter start operating.
If the shift clock rises when the value of the clock counter is 8, the wait status is set. At this time, the SIO1TS
flag is automatically reset to 0.
The operating status of serial communication can be checked by detecting the content of the SIO1TS flag
while the wait status is released.
Therefore, data is read or set after 1 has been written to the SIO1TS flag, serial communication has been
started, and then clearing of the SIO1TS flag to 0 has been detected.
If data is written to (by PUT instruction) or read from (by GET instruction) the presettable shift register while
the wait status is released, the correct data may not be written or read.
For details, refer to 15.6.2 Notes on setting and reading data.
If 0 is written to the SIO1TS flag while the wait status is released, the wait status is set. This is called forced
wait. When forced wait is executed, the clock counter is reset to 0.
Figure 15-4 shows an example of the wait operation.
175
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 15-4. Example of Wait Operation
H
L
Shift
clock pin
1
2
3
7
8
H
L
Serial data
input pin
d7
d6
d5
d1
d0
D0
H
L
Serial data
output pin
Previous value
D7
D6
D5
D1
Clock
counter
0
1
2
3
7
8
0
1
0
SIO1TS
Wait status
Wait released status
Wait status
Wait released
Wait
When the wait is released, the serial data is output at the next falling edge of the clock, and the status becomes
the wait released status.
When the shift clock has been input eight times, the shift clock pin outputs a high level, and the clock counter
and presettable shift register stop operation.
If data is written to or read from the presettable shift register while the wait status is released and the shift
clock pin is high, the correct data may not be set or read.
If data is written to the presettable shift register while the wait status is released and the shift clock pin is
low, the contents of the MSB are output to the serial data output pin as soon as the PUT instruction has been
executed.
If a forced wait is executed while the wait status is released, the wait status is set and the clock counter is
reset to 0 as soon as “0” has been written to the SIO1TS flag.
176
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.8 Outline of Serial Interface Operation
Table 15-3 shows an outline of the serial interface operation in each mode.
Table 15-3. Outline of Serial Interface Operation in Each Mode
Operation
Mode
3-Wire Serial I/O Mode
Slave Operation
Master Operation
SIO1CK1 = SIO1CK0 = other than 0
Item
SIO1CK1 = SIO1CK0 = 0
P0A
2
/SCK
1
Wait
Wait released
Wait
Wait released
Regardless of
When P0ABIO2 = 0
Floating
Regardless of
P0ABIO2
When P0ABIO2 = 0
Floating
Setting
P0ABIO2
status of
each pin
General-purpose
input port
Floating
General-purpose
input port
Outputs internal clock
Wait external clock
input
When P0ABIO2 = 1
General-purpose
output port
When P0ABIO2 = 1
General-purpose
output port
Outputs contents of
output latch
Outputs contents of
output latch
When SIO1HIZ = 0
When SIO1HIZ = 1
When SIO1HIZ = 0
P0A1/SO
1
When SIO1HIZ = 1
When P0ABIO1 = 0
General-purpose
input port
When P0ABIO1 = 0
General-purpose
input port
When P0ABIO1 = 0
General-purpose
input port
When P0ABIO1 = 0
General-purpose
input port
Floating
Floating
Floating
Floating
When P0ABIO1 = 1
Outputs serial data
When P0ABIO1 = 1
General-purpose
output port
When P0ABIO1 = 1
General-purpose
output port
When P0ABIO1 = 1
Outputs serial data
Outputs contents of
output latch
Outputs contents of
output latch
P0A0/SI
1
When P0ABIO0 = 0
Floating
Waits for external data
When P0ABIO0 = 1
General-purpose output port.
Outputs contents of output latch
Operation of clock
counter
Incremented at falling edge of SCK1 pin
Operation of
Output
presettable shift
When SIO1HIZ = 1
register (SIO1SFR)
Shifts data from MSB and outputs it to SO1 pin at falling edge of SCK1 pin
When SIO1HIZ = 0
Does not output data
Input
Shifts data of SI1 pin from LSB and inputs it at rising edge of SCK1 pin regardless of P0ABIO0
However, the contents of output latch are output to SI1 pin when P0ABIO0 = 1
Wait operation
Serial communication is started when 1 is written to SIO1TS.
SIO1TS is reset to 0 at rising edge of shift clock when value of clock counter is 8.
For the operation of each pin, refer to above.
177
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
15.9 Status of Serial Interface on Reset
15.9.1 On power-on reset
Each pin is set in the general-purpose input port mode (floating output).
The value of the presettable shift register is undefined.
15.9.2 On execution of clock stop instruction
Each pin is set in the general-purpose input port mode (floating output).
The presettable shift register retains the previous value.
15.9.3 On CE reset
Each pin is set in the general-purpose input port mode (floating output).
The presettable shift register retains the previous value.
15.9.4 In halt status
Each pin retains the current status.
If the internal clock is used (master operation) at this time, the clock is not output after the HALT instruction
has been executed.
To use the internal clock, therefore, the HALT instruction must be executed after communication has been
completed.
If an external clock is forcibly input, the serial interface functions even when the internal clock is used.
If the external clock is used (slave operation), the operation continues even when the HALT instruction has
been executed.
178
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16. PLL FREQUENCY SYNTHESIZER
The PLL (Phase Locked Loop) frequency synthesizer is used to lock the frequency in the MF (Medium
Frequency), HF (High Frequency), and VHF (Very High Frequency) bands to a specific frequency by comparing
phase differences.
16.1 Configuration of PLL Frequency Synthesizer
Figure 16-1 shows the block diagram of the PLL frequency synthesizer.
As shown in the figure, the PLL frequency synthesizer consists of an input select block, programmable divider
(PD), phase comparator (φ-DET), reference frequency generator (RFG), and charge pump.
By connecting these blocks with an external lowpass filter (LPF) and voltage-controlled oscillator (VCO), a
PLL frequency synthesizer is organized.
Figure 16-1. Block Diagram of PLL Frequency Synthesizer
Control register
Data buffer
Unlock detection
block
Programmable
divider
Phase
comparator
Input select
block
Charge
pump
φ
(
-DET)
(PD)
Reference
frequency generator
(RFG)
VCOH
VCOL
EO
Note
Note
Voltage-controlled
oscillator
Lowpass filter
(LPF)
(VCO)
Note External circuit
179
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.2 Functional Outline of PLL Frequency Synthesizer
The PLL frequency synthesizer divides a signal input from the VCOH or VCOL pin by using the programmable
divider and outputs a phase difference from the reference frequency from the EO pin.
The PLL frequency synthesizer operates only when the CE pin is high, and is disabled when the CE pin is
low.
For details of the disabled status of the PLL frequency synthesizer, refer to 16.6.
The following subsections 16.2.1 through 16.2.6 outline the function of each block of the PLL frequency
synthesizer.
16.2.1 Input select block
This block selects the pin from which a signal output from an external voltage-controlled oscillator is input.
As the input pin, the VCOH or VCOL pin is selected by the PLL mode select register (RF address 21H).
For details, refer to 16.3.
16.2.2 Programmable divider
The programmable divider divides the signal input from the VCOH or VCOL pin at the division ratio set by
the program.
Two types of division modes can be selected: direct division and pulse swallow modes.
The division mode is selected by the PLL mode select register.
The division ratio is set by the PLL data register (PLLR: peripheral address 41H) via the data buffer.
For details, refer to 16.3.
16.2.3 Reference frequency generator
This generator generates a reference frequency to be compared by the phase comparator.
Twelve types of reference frequencies can be selected by using the PLL reference clock select register (RF
address 31H).
For details, refer to 16.4.
16.2.4 Phase comparator and unlock detection block
The phase comparator compares the division signal output by the programmable divider with the signal from
the reference frequency generator, and outputs a phase difference.
The unlock detection block detects the unlock status of the PLL.
The unlock status of the PLL is detected by the PLL unlock FF judge register (RF address 05H).
For details, refer to 16.5.
16.2.5 Charge pump
The charge pump outputs the signal output by the phase comparator to the EO pin as a high-level, low-level,
or floating signal.
For details, refer to 16.5.
180
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.3 Input Select Block and Programmable Divider
16.3.1 Configuration of input select block and programmable divider
Figure 16-2 shows the configuration of the input select block and programmable divider.
As shown in the figure, the input select block consists of the VCOH and VCOL pins, and the amplifiers of the
respective pins.
The programmable divider consists of a 2-modulus prescaler, swallow counter, programmable counter, and
division mode select switch.
Figure 16-2. Configuration of Input Select Block and Programmable Divider
Control register
Address
Data buffer (DBF)
Address
Symbol
Data
21H
0CH
0DH
0EH
DBF1
0FH
Bit
b3
b2
b
1
b
0
DBF3
DBF2
DBF0
0
0
P
L
L
P
L
L
Flag
M
S
B
L
S
B
symbol
M
D
1
M
D
0
16
Peripheral address 41H
PLL data register
12 bits
2-4 decoder
4 bits
12
4
PSC
MF
VHF
2-modulus
prescaler
1/16, 1/17
Swallow
counter 4 bits
VCOH
VHF
VHF
HF
HF
f
N
Programmable
counter 12 bits
φ
To -DET
MF
VCOL
MF
HF
PLL disable signal
181
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.3.2 Functions of input select block and programmable divider
The input select block and programmable divider select the input pin and division mode of the PLL frequency
synthesizer.
As the input pin, the VCOH or VCOL pin can be selected.
The selected pin goes into an intermediate-potential state (approx. 1/2 VDD). The pin not selected is internally
pulled down.
These pins input signals via an AC amplifier, and the DC component of the input signal must be cut off by
connecting a capacitor to the pin in series.
Either the direct division mode or pulse swallow mode can be selected as the division mode.
The programmable counter divides the signal input from the VCOH or VCOL pin in a specified division mode
according to the values set to the swallow counter and programmable counter.
Table 16-1 show the input pins (VCOH and VCOL) and division modes.
The input pin and division mode to be used are selected by the PLL mode select register.
16.3.3 explains the configuration and function of the PLL mode select register.
The division ratio is set to the programmable divider by the PLL data register via the data buffer.
16.3.4 explains the programmable divider and PLL data register.
Table 16-1. Input Pins and Division Modes
Division Mode
Pin
VCOL
VCOL
VCOH
Input Frequency
(MHz)
Input Amplitude
Settable Division
Ratio
Division Ratio Settable in
Data Buffer
(Vp-p)
12
Direct division
(MF)
0.5 to 20
0.3
0.3
0.3
16 to 2 – 1
010×H to FFF×H
(×: lower 4 bits are arbitrary)
16
Pulse swallow
(HF)
5 to 30
256 to 2 – 1
0100H to FFFFH
0100H to FFFFH
16
Pulse swallow
(VHF)
50 to 150
30 to 250
256 to 2 – 1
182
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.3.3 Configuration and function of PLL mode select register
The PLL mode select register specifies the division mode of the PLL frequency synthesizer and the pin to
be used.
The configuration and function of the PLL mode select register are shown below.
The paragraphs (1) through (4) below outline the respective division modes.
Name
Flag symbol
Address
21H
Read/
write
b
3
b
2
b
1
b
0
PLL mode select register
0
0
P
L
P
L
R/W
L
L
M
D
1
M
D
0
Sets division mode of PLL frequency synthesizer
0
0
1
1
0
1
0
1
Disables VCOL and VCOH pins
Direct division mode (VCOL pin, MF mode)
Pulse swallow (VCOH pin, VHF mode)
Pulse swallow (VCOL pin, HF mode)
Fixed to “0”
Power-on
Clock stop
CE
0
0
0
0
0
0
Retained
(1) Direct division mode (MF)
In this mode, the VCOL pin is used.
The VCOH pin is pulled down.
In the direct division mode, the frequency of the input signal is divided only by the programmable counter.
(2) Pulse swallow mode (HF)
The VOL pin is used in this mode.
The VCOH pin is pulled down.
In this mode, the frequency of the input signal is divided by the swallow counter and programmable counter.
(3) Pulse swallow mode (VHF)
The VCOH pin is used in this mode.
The VCOL pin is pulled down.
In this mode, the frequency of the input signal is divided by the swallow counter and programmable counter.
(4) Disabling VCOL and VCOH pins
The VCOH and VCOL pins are internally pulled down.
However, the phase comparator, reference frequency generator, and charge pump operate.
Therefore, the operation is different from that in the PLL disable status to be explained later.
183
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.3.4 Programmable divider and PLL data register
The programmable divider divides the signal input from the VCOH or VCOL pin by the value set to the swallow
counter and programmable counter.
The swallow counter and programmable counter are 4-bit binary down counters.
The division ratio is set to the swallow counter and programmable counter by the PLL data register (PLLR:
peripheral address 41H) via data buffer.
Data is set to or read from the PLL data register by using the PUT PLLR, DBF or GET DBF, PLLR instruction.
The value to be divided is called N value.
For how to set the N value in each division mode, refer to 16.7.
(1) PLL data register and data buffer
The relationship between the PLL data register and data buffer is explained next.
In the direct division mode, the higher 12 bits are valid, and all 16 bits are valid in the pulse swallow mode.
In the direct division mode, all the higher 12 bits are set to the programmable counter.
In the pulse swallow mode, the higher 12 bits are set to the programmable counter, and the lower 4 bits are
set to the swallow counter.
(2) Relationship between division value N and divided output frequency
The relationship between the value “N” set to the PLL data register and the frequency “fN” of the signal divided
and output by the programmable divider is as follows.
For details, refer to 16.7.
(a) In direct division mode (MF)
fIN
fN =
N: 12 bits
N
(b) In pulse swallow mode (HF and VHF)
fIN
fN =
N: 16 bits
N
184
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Name
Symbol
Address
Bit
Data buffer
DBF3
0CH
DBF2
0DH
DBF1
0EH
DBF0
0FH
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
Data
Transfer data
GET can be executed
16
PUT can be executed
Peripheral
Peripheral register
Name
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
address
Peripheral address
PLL
data
register
PLLR
41H
PLL frequency
synthesizer
Valid data
Sets division value of PLL frequency synthesizer
Direct
division
mode
0
Don't care
Setting prohibited
15 (00FH)
16 (010H)
Don't care
Don't care
Division value N: N = x
x
Don't care
Don't care
212 –1 (FFFH)
Pulse
0
Setting prohibited
swallow
mode
255 (00FFH)
256 (0100H)
Division value N: N = x
x
216 –1 (FFFFH)
185
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.4 Reference Frequency Generator
16.4.1 Configuration and function of reference frequency generator
Figure 16-3 shows the configuration of the reference frequency generator.
As shown in the figure, the reference frequency generator divides the crystal oscillator’s 4.5 MHz to generate
the reference frequency “fr” of the PLL frequency synthesizer.
Twelve reference frequencies can be selected: 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50, and 100 kHz.
Reference frequency fr is selected by the PLL reference clock select register.
16.4.2 shows the configuration and function of the PLL reference clock select register.
Figure 16-3. Configuration of Reference Frequency Generator (RFG)
Control register
Address
Bit
31H
b
3
b
2
b
1
b
0
Flag
P
L
L
P
L
L
P
L
L
P
L
L
symbol
R
F
C
K
3
R
F
C
K
2
R
F
C
K
1
R
F
C
K
0
4-16 decoder
MUX
PLL disable signal
Divider
1 kHz
1.25 kHz
2.5 kHz
4.5 MHz
To φ-DET
50 kHz
100 kHz
186
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.4.2 Configuration and function of PLL reference clock select register
The configuration and function of the PLL reference clock select register are shown below.
Name
Flag symbol
Address
31H
Read/
write
b3
b2
b1
b0
P
L
L
P
L
P
L
P
L
L
PLL reference clock
select register
R/W
L
L
R
F
C
K
3
R
F
C
K
2
R
F
C
K
1
R
F
C
K
0
Sets reference frequency fr of PLL frequency synthesizer
1.25 kHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.5 kHz
5 kHz
10 kHz
6.25 kHz
12.5 kHz
25 kHz
50 kHz
3 kHz
Setting prohibited
Setting prohibited
Setting prohibited
1 kHz
9 kHz
100 kHz
PLL disabled
Power-on
Clock stop
CE
1
1
1
1
1
1
1
1
Retained
When the PLL is disabled by the PLL reference clock select register, the VCOH and VCOL pins are internally
pulled down.
The EO pin is floated.
For disabling the PLL, refer to 16.6.
187
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.5 Phase Comparator (φ-DET), Charge Pump, and Unlock Detection Block
16.5.1 Configuration of phase comparator, charge pump, and unlock detection block
Figure 16-4 shows the configuration of the phase comparator, charge pump, and unlock detection block.
The phase comparator compares the divided frequency output “fN” of the programmable divider with the
reference frequency output “fr” of the reference frequency generator, and outputs an up request (UP) or down
request (DW) signal.
The charge pump outputs the output of the phase comparator from the error out (EO) pin.
The unlock detection block detects the unlock status of the PLL frequency synthesizer.
The following subsections 16.5.2 to 16.5.4 explain the operations of the phase comparator, charge pump,
and unlock detection block respectively.
Figure 16-4. Configurations of Phase Comparator, Charge Pump, and Unlock Detection Block
PLLUL flag
fr
UP
Reference frequency
generator
Unlock FF
Phase comparator
φ
(
-DET)
fN
DW
Charge pump
EO
Programmable divider
PLL disable signal
16.5.2 Function of phase comparator
As shown in Figure 16-4, the phase comparator compares the divided frequency output “fN” of the
programmable divider with the reference frequency output “fr” of the reference frequency generator, and outputs
an up request or down request signal.
If the divided frequency fN is lower than the reference frequency fr, the phase comparator outputs the up
request signal; if fN is higher than fr, it outputs the down request signal.
Figure 16-5 shows the relationship among the reference frequency fr, divided frequency fN, up request signal,
and down request signal.
When the PLL is disabled, neither the up request nor down request signal is output.
The up request and down request signals are respectively input to the charge pump and unlock detection
block.
188
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 16-5. Relationship Between fr, fN, UP, and DW
(a) If fN is behind fr in phase
f
r
f
N
UP
DW
(b) If fN leads fr in phase
f
r
f
N
UP
DW
(c) If fN and fr are in phase
f
r
f
N
UP
DW
(d) If fN is lower than fr in frequency
f
r
f
N
UP
DW
16.5.3 Charge pump
As shown in Figure 16-4, the charge pump outputs the up request signal or down request signal from the phase
comparator to the error out (EO) pin.
Therefore, the relationship between the output of the error out pin, divided frequency fN, and reference
frequency fr is as follows.
When reference frequency fr > divided frequency fN: Low-level output
When reference frequency fr < divided frequency fN: High-level output
When reference frequency fr = divided frequency fN: Floating
189
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.5.4 Unlock detection block
As shown in Figure 16-4, the unlock detection block detects the unlock status of the PLL frequency
synthesizer by using the up request or down request signal from the phase comparator.
Because either of the up request or down request signal outputs a low level in the unlock status, this low-
level signal is used to detect the unlock status.
In the unlock status, the unlock flip-flop (FF) is set to 1.
The unlock status is detected by the PLL unlock FF judgement register (refer to 16.5.5).
The unlock FF is set at the cycle of reference frequency fr selected at that time.
When the contents of the PLL unlock FF judge register are read (by the PEEK instruction), the unlock FF is
reset (Read & Reset).
Therefore, the unlock FF must be detected at a cycle longer than the cycle 1/fr of the reference frequency
fr.
16.5.5 Configuration and function of unlock FF judge register
Name
Flag symbol
Address
05H
Read/
write
b
3
b2
b1
b
0
0
0
0
P
L
L
PLL unlock FF judge
register
R & Reset
U
L
Detects status of unlock FF
0
1
Unlock FF = 0: PLL lock status
Unlock FF = 1: PLL unlock status
Fixed to 0
Power-on
Clock stop
CE
0
0
0
Undefined
Retained
Retained
This register is a read-only register and is reset when its contents are read to the window register by the PEEK
instruction.
Because the unlock FF is set at the cycle of reference frequency fr, the contents of the PLL unlock FF judge
register must be written to the window register at a cycle longer than the cycle 1/fr of the reference frequency
fr.
The delay of the phase comparator up/down request signal is fixed to between 0.8 µs and 1.0 µs.
190
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.6 PLL Disabled Status
The PLL frequency synthesizer stops operation (is disabled) while the CE pin (pin 7) is low.
When the PLL is disabled by the PLL reference clock select register, the PLL frequency synthesizer also stops
operation.
Table 16-2 shows the operation of each block under each PLL disable condition.
When the VCOL and VCOH pins are disabled by the PLL mode select register, only the VCOL and VCOH
pins are internally pulled down, and the other blocks operate.
Because the PLL reference clock select register and PLL mode select register are not initialized (but hold
the previous status) on CE reset, they are restored to the original status when the CE pin has once gone low
and then back high again after the PLL has been disabled.
To disable the PLL on CE reset, therefore, initialize these registers in the program.
The PLL is disabled at power-on reset.
Table 16-2. Operation of Blocks Under PLL Disable Conditions
Condition
CE Pin = Low Level
(PLL Disabled)
CE Pin = High Level
PLL Reference Clock Select Register = 1111B PLL Mode Select Register = 0000B
Blocks
(PLL Disabled)
(VCOH, VCOL Disabled)
VCOL and
VCOH pins
Internally pulled down
Stops division
Internally pulled down
Internally pulled down
Programmable
counter
Stops division
Stops output
Operates
Operates
Operates
Reference frequency
generator
Stops output
Phase comparator
Charge pump
Stops output
Stops output
Floats error out pins
Floats error out pins
Operates
However, usually outputs low
level because there is no input.
16.7 Using PLL Frequency Synthesizer
To control the PLL frequency synthesizer, the following data is necessary.
(1) Division mode:
(2) Pin used:
Direct division (MF), pulse swallow (HF, VHF)
VCOL, VCOH
(3) Reference frequency: fr
(4) Division ratio:
N
The following subsections 16.7.1 to 16.7.3 explain how to set the PLL data in each division mode (MF, HF,
and VHF).
191
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.7.1 Direct division mode (MF)
(1) Selecting division mode
Select the direct division mode by using the PLL mode select register.
(2) Pin used
When the direct division mode is selected, the VCOL pin is enabled to operate.
(3) Setting reference frequency fr
Set the reference frequency by using the PLL reference clock select register.
(4) Calculating division value N
Calculate as follows:
fVCOL
N =
fr
where,
fVCOL: Input frequency of VCOL pin
fr:
Reference frequency
(5) Example of setting PLL data
How to set the data to receive broadcasting in the following MW band is explained below.
Reception frequency:
Reference frequency:
1,422 kHz (MW band)
9 kHz
Intermediate frequency: +450 kHz
Division value N:
fVCOL
1,422 + 450
9
N =
=
= 208 (decimal)
fr
= 0D0H (hexadecimal)
Set data to the PLL data register (PLLR: peripheral address 41H), PLL mode select register (RF address
21H), and PLL reference clock select register (RF address 31H) as follows.
PLL data register (RLLR)
PLL mode
PLL reference
select register clock select
register
0
0
0
0
1
1
0
1
0
0
0
0
don’t care
0
0
0
1
1
1
0
1
0
D
0
MF
9 kHz
192
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.7.2 Pulse swallow mode (HF)
(1) Selecting division mode
Select the pulse swallow mode by using the PLL mode select register.
(2) Pin used
When the pulse swallow mode is selected, the VCOL pin is enabled to operate.
(3) Setting reference frequency fr
Set the reference frequency by using the PLL reference clock select register.
(4) Calculating division value N
Calculate as follows:
fVCOL
N =
fr
where,
fVCOL: Input frequency of VCOL pin
fr:
Reference frequency
(5) Example of setting PLL data
How to set the data to receive broadcasting in the following SW band is explained below.
Reception frequency:
Reference frequency:
25.50 MHz (SW band)
5 kHz
Intermediate frequency: +450 kHz
Division value N:
fVCOL
25,500 + 450
5
N =
=
= 5190 (decimal)
fr
= 1446H (hexadecimal)
Set data to the PLL data register (PLLR: peripheral address 41H), PLL mode select register (RF address 21H),
and PLL reference clock select register (RF address 31H) as follows.
PLL data register (RLLR)
PLL mode
PLL reference
select register clock select
register
0
0
0
1
0
1
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
4
4
6
HF
5 kHz
193
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.7.3 Pulse swallow mode (VHF)
(1) Selecting division mode
Select the pulse swallow mode by using the PLL mode select register.
(2) Pin used
When the pulse swallow mode is selected, the VCOH pin is enabled to operate.
(3) Setting reference frequency fr
Set the reference frequency by using the PLL reference clock select register.
(4) Calculating division value N
Calculate as follows:
fVCOH
N =
fr
where,
fVCOH: Input frequency of VCOH pin
fr:
Reference frequency
(5) Example of setting PLL data
How to set the data to receive broadcasting in the following FM band is explained below.
Reception frequency:
Reference frequency:
100.0 MHz (FM band)
25 kHz
Intermediate frequency: +10.7 MHz
Division value N:
fVCOH
100.0 + 10.7
0.025
N =
=
= 4428 (decimal)
fr
= 114CH (hexadecimal)
Set data to the PLL data register (PLLR: peripheral address 41H), PLL mode select register (RF address 21H),
and PLL reference clock select register (RF address 31H) as follows.
PLL data register (RLLR)
PLL mode
PLL reference
select register clock select
register
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
0
0
0
1
0
0
1
1
0
1
1
4
C
VHF
25 kHz
194
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
16.8 Status on Reset
16.8.1 On power-on reset
The PLL is disabled on power-on reset because the PLL reference clock select register is initialized to 1111B.
16.8.2 On execution of clock stop instruction
The PLL is disabled when the CE pin goes low.
16.8.3 On CE reset
(1) CE reset after execution of clock stop instruction
The PLL is disabled because the PLL reference clock select register is initialized to 1111B by the clock stop
instruction.
(2) CE reset without clock stop instruction executed
Because the PLL reference clock select register retains the previous status, the previous status is restored
as soon as the CE pin has gone high.
16.8.4 In halt status
The set status is retained if the CE pin is high.
195
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
17. FREQUENCY COUNTER
17.1 Outline of Frequency Counter
Figure 17-1 illustrates the frequency counter.
The frequency counter has an IF counter function to count the intermediate frequency (IF) of an external input signal
and an external gate counter (FCG: Frequency Counter for external Gate signal) to detect the pulse width of an external
input signal.
The IF counter function counts the frequency input to the P1B3/FMIFC or P1B2/AMIFC pin at fixed intervals (1 ms,
4 ms, 8 ms, or open) by using a 16-bit counter.
The external gate counter function counts the frequency of the internal clock (1 kHz, 100 kHz, 900 kHz) from the
rising to the falling of the signal input to the P0B3/FCG1 or P0B2/FCG0 pin.
The IF counter and external gate counter functions cannot be used at the same time.
Figure 17-1. Outline of Frequency Counter
FCGCH1 flag
FCGCH0 flag
IFCCK1 flag
IFCCK0 falg
IFCSTRT flag
DBF
P0B
3
/FCG
1
0
P0B
2
/FCG
Gate time
control block
Start/stop
control block
IF counter
(16 bits)
I/O select
block
P1B3/FMIFC
P1B2/AMIFC
IFCG flag
IFCRES flag
IFCMD1 flag
IFCMD0 flag
Remarks 1. FCGCH1 and FCGCH0 (bits 1 and 0 of the FCG channel select register; refer to Figure 17-4) select
the pin used for the external gate counter function.
2. IFCMD1 and IFCMD0 (bits 3 and 2 of the IF counter mode select register; refer to Figure 17-3) select
the IF counter or external gate counter function.
3. IFCCK1 and IFCCK0 (bits 1 and 0 of the IF counter mode select register; refer to Figure 17-3) select
the gate time of the IF counter function and the reference frequency of the external gate counter
function.
4. IFCSTRT (bit 1 of the IF counter control register; refer to Figure 17-6) control starting of the IF
counter and external gate counter functions.
5. IFCG (bit 0 of the IF counter gate judge register; refer to Figure 17-7) detects opening/closing the
gate of the IF counter function.
6. IFCRES (bit 0 of the IF counter control register; refer to Figure 17-6) reset the count value of the
IF counter.
196
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
17.2 Input/Output Select Block and Gate Time Control Block
Figure 17-2 shows the configuration of the input/output select block and gate time control block.
The input/output select block consists of an IF counter input select block and FCG I/O select block.
The IF counter input select block selects whether the frequency counter is used as an IF counter or an external
gate counter, by using the IF counter mode select register. When the frequency counter is used as the IF counter,
either P1B3/FMIFC or P1B2/AMIFC pin and a count mode are selected. The pin not used for the IF counter is used
as a general-purpose input port pin.
The FCG I/O select block selects a pin to be used from either the P0B3/FCG1 or P0B2/FCG0 pin by using the FCG
channel select register, when the frequency counter is used as the external gate counter. The pin not used is used
as a general-purpose I/O port pin.
When using the frequency counter as the external gate counter, the pin to be used must be set in the input mode
by using the port 0B bit I/O select register. This is because the pin is set in the general-purpose output port mode
if it is set in the output mode even if the external gate counter function is selected by the IF counter mode select register
and FCG channel select register.
The gate time control block selects gate time by using the IF counter mode select register when the frequency
counter is used as the IF counter, or a count frequency when the frequency counter is used as the external gate counter.
Figure 17-3 shows the configuration of the IF counter mode select register.
Figure 17-4 shows the configuration of the FCG channel select register.
Figure 17-2. Configuration of I/O Select Block and Gate Time Control Block
FCGCH1 flag
FCGCH0 flag
IFCMD1 flag
IFCMD0 flag
P0B
3
/FCG
1
0
FCG
Selector
Gate signal
P0B
2
/FCG
Gate signal
generator
I/O port
IFCCK1 flag
IFCCK0 flag
To start/stop control
block
Selector
Frequency
generator
P1B /FMIFC
3
Frequency
P1B /AMIFC
2
FMIFC
AMIFC
Input port
197
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 17-3. Configuration of IF Counter Mode Select Register
Name
Flag symbol
Address
12H
Read/write
R/W
b3 b2 b1 b0
I
I
I
I
IF counter mode select
register
F
C
M
D
1
F
C
M
D
0
F
C
C
K
1
F
C
C
K
0
Selects gate time of IF counter and reference frequency of external gate counter
Reference frequency of
Gate time of IF counter
external gate counter
0
0
1
1
0
1
0
1
1 ms
4 ms
8 ms
Open
1 kHz
100 kHz
900 kHz
0 kHz
Selects function of IF counter or external gate counter
0
0
1
1
0
1
0
1
External gate counter (FCG)
IF counter (AMIFC pin, AMIF count mode)
IF counter (FMIFC pin, FMIF count mode)
IF counter (FMIFC pin, AMIF count mode)
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
Retained
Caution The IF counter and external gate counter functions cannot be used at the same time.
198
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 17-4. Configuration of FCG Channel Select Register
Name
Flag symbol
Address
24H
Read/write
R/W
b
3
b
2
b
1
b
0
0
0
F
F
FCG channel select
register
C
G
C
H
1
C
G
C
H
0
Selects pin used for FCG
0
0
1
1
0
1
0
1
P0B
2
/FCG
0
1
pin
pin
P0B
3
/FCG
FCG not used (general-purpose I/O port)
FCG not used (general-purpose I/O port)
Fixed to 0
Power-on
Clock stop
CE
0
0
1
1
1
1
Retained
199
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
17.3 Start/Stop Control Block and IF Counter
17.3.1 Configuration of start/stop control block and IF counter
Figure 17-5 shows the configuration of the start/stop control block and IF counter.
The start/stop control block starts the frequency counter or detects the end of counting.
The counter is started by the IF counter control register.
The end of counting is detected by the IF counter gate judge register. When the external gate counter function
is used, however, the end of counting cannot be detected by the IF counter gate judge register.
Figure 17-6 shows the configuration of the IF counter control register.
Figure 17-7 shows the configuration of the IF counter gate judge register.
17.3.2 and 17.3.3 describe the gate operation when the IF counter function is selected and that when the external
gate counter function is selected.
The IF counter is a 16-bit binary counter that counts up the input frequency when the IF counter function or external
gate counter function is selected.
When the IF counter function is selected, the frequency input to a selected pin is counted while the gate is opened
by an internal gate signal. The frequency count is counted without alteration in the AMIF count mode. In the FMIF
counter mode, however, the frequency input to the pin is halved and counted.
When the external gate counter function is selected, the internal frequency is counted while the gate is opened
by the signal input to the pin.
When the IF counter counts up to FFFFH, the following input becomes 0000H, and then counting continues.
The count value is read by the IF counter data register (IFC) via data buffer.
The count value is reset by the IF counter control register.
Figure 17-8 shows the configuration of the IF counter data register.
Figure 17-5. Configuration of Start/Stop Control Block and IF Counter
DBF
16
IF counter data
IFCSTRT flag
register (IFC)
IFCG flag
IFCRES flag
16
Gate signal
Frequency
RES
From gate time
select block
Start/Stop
control
IF counter
(16 bits)
200
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 17-6. Configuration of IF Counter Control Register
Name
Flag symbol
Address
23H
Read/write
W
b3 b2 b1 b0
0
0
I
I
IF counter control register
F
C
S
T
R
T
F
C
R
E
S
Resets data of IF counter and external gate counter
0
1
Nothing is affected
Resets counter
Starts IF counter and external gate counter
0
1
Nothing is affected
Starts counter
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
Retained
The IF counter control register is controlled by writing the contents of the window register to it using the POKE
instruction.
When the contents of the IF counter are read by the PEEK instruction, 0 is read in the window register.
201
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 17-7. Configuration of IF Counter Gate Judge Register
Name
Flag symbol
Address
04H
Read/write
R
b3 b2 b1 b0
0
0
0
I
IF counter gate judge register
F
C
G
Detects opening/closing of gate of frequency counter
When external gate counter
function is selected
When IF counter function is selected
Sets IFCSTRT flag to 1 and is set to
1 until gate is closed
Sets IFCSTRT flag to 1 and is set to
1 while gate is open, regardless of
input of P0B2/FCG0 and P0B3/FCG1
pins
0
1
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
R
Cautions 1. Do not read the contents of the IF counter data register (IFC) to the data buffer while the IFCG
flag is set to 1.
2. The gate of the external gate counter cannot be opened or closed by the IFCG flag. Use the
IFCSTRT flag to open or close the gate.
Remark R: Retained
202
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
17.3.2 Operation of gate when IF counter function is selected
(1) When gate time of 1, 4, or 8 ms is selected
The gate is opened for 1, 4, or 8 ms from the rising of the internal 1 kHz signal after the IFCSTRT flag has
been set to 1, as illustrated below.
While this gate is open, the frequency input from a selected pin is counted by a 16-bit counter.
When the gate is closed, the IFCG flag is cleared to 0.
The IFCG flag is automatically set to 1 when the IFCSTRT flag is set.
H
L
Internal 1 kHz
OPEN
1 ms
CLOSE
4 ms
8 ms
Gate time
Count period (IFCG flag = 1)
Gate is actually opened at this point
End of counting
IFG flag is cleared
IFCSTRT flag is set
IFCG flag is set at this point
(2) When gate is open
If opening of the gate is selected by the IFCCK1 and IFCCK0 flags, the gate is opened as soon as its opening
has been selected, as illustrated below.
If the counter is started by using the IFCSTRT flag while the gate is open, the gate is closed after an undefined
amount of time.
To open the gate, therefore, do not set the IFCSTRT flag to 1.
However, the counter can be reset by the IFCRES flag.
H
L
Internal 1 kHz
OPEN
Gate
CLOSE
Count period
Gate is closed after an undefined amount of time if IFCSTRT flag is set
during this period
Sets IFCCK1 = IFCCK0 = 1
Gate is actually opened at this point.
If gate is opened while IFCG flag is 1, it is closed after an undefined amount of time
The gate is opened or closed in the following two ways when opening the gate is selected as the gate time.
203
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(a) Resetting the gate to other than open by using IFCCK1 and IFCCK0 flags
OPEN
Gate
CLOSE
Count period
IFCCK1 = IFCCK0 = 1
Resetting the gate to other than open
by IFCCK1 and IFCCK0 flags
(b) Unselect pin used by using IFCMD1 and IFCMD0 flags
In this way, the gate remains open, and counting is stopped by disabling input from the pin.
OPEN
CLOSE
Gate
Count period
Sets IFCCK1 = IFCCK0 = 1
Sets IFCMD1 = IFCMD0 = 0 (FCG)
FMIFC and AMIFC pins are unselected and
count signal cannot be input
17.3.3 Gate operation when external gate counter function is selected
The gate is opened from the rising to the next rising of the signal input to a selected pin after the IFCSTRT flag
has been set to 1, as illustrated below.
While the gate is open, the internal frequency (1 kHz, 100 kHz, 900 kHz) is counted by a 16-bit counter.
The IFCG flag is set to 1 from the rising to the next rising of the external signal after the IFCSTRT flag has been
set.
In other words, the opening or closing of the gate cannot be detected by the IFCG flag when the external gate
counter function is selected.
H
External signal
L
OPEN
CLOSE
Gate
Count period
Gate is opened at
this point
End of counting
IFCG flag is “0”
IFCSTRT flag ← 1
If reset and started while gate is open
H
L
External signal
Gate
OPEN
CLOSE
Count period
Count period
Gate is opened at
this point
End of counting
IFCG flag is “0”
IFCSTRT flag ← 1
IFCSTRT flag ← 1
204
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 17-8. Configuration of IF Counter Data Register
Data buffer
DBF2 DBF1
DBF3
DBF0
Transfer data
GET can be executed
PUT changes nothing
16
Peripheral register
Name
IF counter
b
15
b
14
b
13
b
12
b
11
b
10
b
9
b
8
b
7
b
6
b
5
b
4
b3
b
2
b
1
b
Symbol Peripheral address
0
IFC
43H
Valid data
data register
Count value of frequency counter
0
IF counter function
• FMIF count mode of FMIFC pin
Counts rising edge of signal input to
P1B /FMIFC pin via 1/2 divider
3
• AMIF count mode of AMIFC pin
Counts rising edge of signal input to
P1B /AMIFC pin
2
• AMIF count mode of FMIFC pin
Counts rising edge of signal input to
x
P1B /FMIFC pin
3
External gate counter function
Counts rising edge of internal reference
frequency signal from rising edge to next
rising edge of signal input to P0B
or P0B /FCG pin
2/FCG
0
3
1
216 −1 (FFFFH)
The IF counter is cleared to 0000H when its count value has reached FFFFH, and then continues counting.
205
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
17.4 Using IF Counter Function
The following subsections 17.4.1 through 17.4.3 explain how to use the hardware of the IF counter function,
program example, and count error.
17.4.1 Using hardware of IF counter
Figure 17-9 shows the block diagram illustrating how the P1B3/FMIFC and P1B2/AMIFC pins are used.
Table 17-1 shows the range of the frequencies that can be input to the P1B3/FMIFC and P1B2/AMIFC pins.
Because the input pins of the IF counter have an internal amplifier, cut off the DC component of the input
signal by using capacitor C as shown in Figure 17-9.
When the P1B3/FMIFC or P1B2/AMIFC pin is selected as the IF counter pin, switch SW turns ON, applying
a voltage of about 1/2VDD to each pin.
If the voltage has not risen to a sufficient intermediate level at this time, the AC amplifier does not operate
normally, and consequently, the IF counter does not correctly operate.
Therefore, make sure that a sufficiently long wait time elapses from the time each pin is selected as an IF
counter until counting is started.
Figure 17-9. Function of Each IF Counter Pin
R
SW
C
External frequency
To internal counter
FMIFC
AMIFC
Table 17-1. Input Frequency Range of IF Counter
Input Pin
Input Frequency
(MHz)
Input Amplitude
(Vp-p)
P1B3/FMIFC
FMIF mode
5 to 15
10.5 to 10.9
0.3 to 1
0.3
0.1
0.3
P1B3/FMIFC
AMIF mode
P1B2/AMIFC
AMIF mode
0.3 to 1
0.3
0.1
0.44 to 0.46
206
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
17.4.2 Program example of IF counter function
A program example of the IF counter function is shown below.
As shown in this example, a wait time must elapse after an instruction that selects the P1B3/FMIFC or P1B2/
AMIFC pin as the IF counter pin has been executed before counting is started.
This is because the internal AC amplifier may not operate normally immediately after each pin has been
selected, as explained in 17.4.1.
Example To count frequency on P1B3/FMIFC pin (gate time: 8 ms)
INITFLG IFCMD1, NOT IFCMD0, IFCCK1, NOT IFCCK0
; Selects FMIFC pin and sets gate time to 8 ms.
Wait
; Internal AC amplifier stabilization time
LOOP:
SKT1
IFCG
; Detects opening/closing of gate.
BR
READ
Processing A
LOOP
; Branches to READ: when gate is closed.
; Do not read data of IF counter by this processing A.
; Reads value of IF counter data register to data buffer.
BR
READ:
GET
DBF, IFC
17.4.3 Error of IF counter
The IF counter may have a gate time error and a count error.
These errors are explained in (1) and (2) below.
(1) Error of gate time
The gate time of the IF counter is created by dividing the 4.5 MHz system clock.
Therefore, if the system clock deviates “+x” ppm, the gate time deviates “−x” ppm.
(2) Count error
The IF counter counts the frequency at the rising edge of an input signal.
If a high level is input to the pin when the gate is opened, therefore, one excess pulse is counted.
However, counting is not performed because of the status of the pin when the gate is closed.
Therefore, a count error of “+1, −0” may occur.
207
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
17.5 Error of External Gate Counter
The external gate counter has an internal frequency error and count error, as described in (1) and (2) below.
(1) Internal frequency error
The internal frequency of the external gate counter is created by dividing the 4.5 MHz system clock frequency.
Therefore, if this frequency has an error of “+x” ppm, the internal frequency accordingly has an error of “+x”
ppm.
(2) Count error
The external gate counter counts the frequency at the rising edge of the internal frequency.
Therefore, if the internal frequency is at low level when the gate is opened (when the input signal of the pin
rises), one extra pulse is counted.
However, this extra pulse may not be counted, depending on the count level of the internal frequency, when
the gate is closed (when the input signal of the pin rises next time).
Therefore, the count error is “+1, −0”.
17.6 Status on Reset
17.6.1 On power-on reset
The P1B3/FMIFC and P1B2/AMIFC pins are set in the general-purpose input port mode.
The P0B3/FCG1 and P0B2/FCG0 pins are set in the general-purpose I/O port mode.
17.6.2 On execution of clock stop instruction
The P1B3/FMIFC and P1B2/AMIFC pins are set in the general-purpose input port mode.
The P0B3/FCG1 and P0B2/FCG0 pins are set in the general-purpose I/O port mode.
17.6.3 On CE reset
The P1B3/FMIFC, P1B2/AMIFC, P0B3/FCG1, and P0B2/FCG0 pins retain the previous status.
17.6.4 In halt status
The P1B3/FMIFC, P1B2/AMIFC, P0B3/FCG1, and P0B2/FCG0 pins retain the status immediately before the
halt status was set.
208
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
18. BEEP
18.1 General
Figure 18-1 shows the outline of BEEP.
BEEP outputs 1 kHz, 3 kHz, 200 Hz, or 9 kHz clock from the P0B0/BEEP0 and P0B1/BEEP1 pins.
Figure 18-1. Outline of BEEP
BEEP1CK1 flag
BEEP1CK0 flag
P0BBIO1 flag
BEEP1SEL flag
Clock
generation block
1 kHz
3 kHz
200 Hz
Clock
select
block
I/O select
block
Output select
block
P0B
1
/BEEP
1
Output latch
Output latch
Clock
select
block
I/O select
block
Output select
block
P0B
0
/BEEP
0
9 kHz
P0BBIO0 flag
BEEP0SEL flag
BEEP0CK1 flag
BEEP0CK0 flag
Remarks 1. P0BBIO1 and P0BBIO0 (bits 1 and 0 of the port 0B bit I/O select register; refer to Figure 18-2) set the
P0B1/BEEP1 and P0B0/BEEP0 pins in the input/output mode.
2. BEEP1SEL and BEEP0SEL (bits 1 and 0 of the BEEP select register; refer to Figure 18-3) set the P0B1/
BEEP1 and P0B0/BEEP0 pin in the general-purpose output port or BEEP output mode.
3. BEEP1CK1, BEEP1CK0, BEEP0CK1, and BEEP0CK0 (bits 3 to 0 of the BEEP clock select register;
refer to Figure 18-4) set the output frequencies of BEEP1 and BEEP0.
209
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
18.2 I/O Select Block and Output Select Block
The I/O select block sets the P0B1/BEEP1 and P0B0/BEEP0 pins in the input or output mode by using the port 0B
bit I/O select register. These pins must be set in the output mode when they are used as the BEEP pins.
The output select block sets the P0B1/BEEP1 and P0B0/BEEP0 pins in the general-purpose output port or BEEP
output mode by using the BEEP select register.
Figure 18-2 shows the configuration and function of the port 0B bit I/O select register.
Figure 18-3 shows the configuration and function of the BEEP select register.
Figure 18-2. Configuration of Port 0B Bit I/O Select Register
Name
Flag symbol
Address
36H
Read/
write
b
3
b2
b1
b
0
Port 0B bit I/O select
register
P
0
B
B
I
P
0
B
B
I
P
0
B
B
I
P
0
B
B
I
R/W
O
3
O
2
O
1
O
0
Sets input or output of port
0
1
Sets P0B
0
0
/BEEP
0
0
pin in input mode
pin in output mode
Sets P0B
/BEEP
Sets input or output of port
pin in input mode
0
1
Sets P0B
1
1
/BEEP
1
1
Sets P0B
/BEEP
pin in output mode
Sets input or output of port
0
1
Sets P0B
2
2
/FCG
0
0
pin in input mode
pin in output mode
Sets P0B
/FCG
Sets input or output of port
pin in input mode
0
1
Sets P0B
3
3
/FCG
1
1
Sets P0B
/FCG
pin in output mode
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
0
0
0
0
210
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 18-3. Configuration of BEEP Select Register
Name
Flag symbol
Address
15H
Read/
write
b
3
b2
b1
b
0
BEEP select register
0
0
B
E
E
P
1
S
E
L
B
E
E
P
0
S
E
L
R/W
Selects general-purpose I/O port or BEEP
0
1
Uses P0B
0
/BEEP
0
0
pin as general-purpose I/O port
pin as BEEP
Uses P0B
0
/BEEP
Selects general-purpose I/O port or BEEP
0
1
Uses P0B
1
/BEEP
1
1
pin as general-purpose I/O port
pin as BEEP
Uses P0B
1
/BEEP
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
211
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
18.3 Clock Select Block and Clock Generator Block
The clock select block selects the output frequencies of the BEEP1 and BEEP0 pins by using the BEEP clock select
register.
The clock generator block generates the clock to be output to the BEEP1 and BEEP0 pins.
The clock frequency to be generated is 1 kHz, 3 kHz, 200 Hz, or 9 kHz.
Figure 18-4 shows the configuration and function of the BEEP clock select register.
Figure 18-4. Configuration of BEEP Clock Select Register
Name
Flag symbol
Address
25H
Read/
write
b
3
b2
b1
b
0
BEEP clock select
register
B
E
E
P
1
C
K
1
B
E
E
P
1
C
K
0
B
E
E
P
0
C
K
1
B
E
E
P
0
C
K
0
R/W
Sets output frequency of BEEP
0
0
0
1
1
0
1
0
1
1 kHz
3 kHz
200 Hz
9 kHz
Sets output frequency of BEEP
1
0
0
1
1
0
1
0
1
1 kHz
3 kHz
200 Hz
9 kHz
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
Retained
212
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
18.4 Output Waveform of BEEP
The duty cycle of the output waveform of BEEP is 50% except when f = 1 kHz.
The output waveform is shown below.
f = 9 kHz
55.6 µs 55.6 µs
f = 3 kHz
166.7
µ
s
166.7 µs
f = 1 kHz
555.6
µ
s
444.4 µs
f = 200 Hz
2.5 ms
2.5 ms
Remark f: Output frequency of BEEP
18.5 Status on Reset
18.5.1 At power-on reset
The P0B0/BEEP0 and P0B1/BEEP1 pins are set in the general-purpose input port mode.
18.5.2 At clock stop
The P0B0/BEEP0 and P0B1/BEEP1 pins are set in the general-purpose input port mode.
18.5.3 At CE reset
The P0B0/BEEP0 and P0B1/BEEP1 pins are set in the general-purpose input port mode.
213
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19. LCD CONTROLLER/DRIVER
The LCD (Liquid Crystal Display) controller/driver can display an LCD of up to 60 dots by outputting segment
and common signals in combination.
19.1 Configuration of LCD Controller/Driver
Figure 19-1 shows the block diagram of the LCD controller/driver.
As shown in the figure, the LCD controller/driver consists of a common signal output timing control block,
segment signal/key source signal output timing control block, segment signal/general-purpose output port select
block, LCD segment register, and key source data register/port YA group register.
The following section 19.2 outlines the function of each block.
Figure 19-1. Outline of LCD Controller/Driver
LCDEN flag
COM
COM
COM
2
1
0
Common
signal output
timing
KSEN flag
Segment signal/
key source
signal output
timing control
block
LCD19/P2H
LCD18/P2G
LCD17/P2F
LCD16/P2E
0
0
0
0
LCD segment resister
(data memory space)
Segment signal/
general-purpose
output port
LCD15/KS15/PYA15
select block
Key source data register/
port YA group register
DBF
LCD
0
/KS
0
/PYA
0
P2HSEL flag
P2GSEL flag
P2FSEL flag
P2ESEL flag
PYASEL flag
Remarks 1. P2HSEL, P2GSEL, P2FSEL, and P2ESEL (bits 3 to 0 of LCD port select register; refer to Figure
19-7) set the output of the LCD19/P2H0, LCD18/P2G0, LCD17/P2F0, and LCD16/P2E0 in the LCD
segment signal output or general-purpose output port mode.
2. PYASEL (bit 0 of LCD mode select register; refer to Figure 19-9) sets the output of the LCD15/KS15/
PYA15 through LCD0/KS0/PYA0 pins in the LCD segment signal output or general-purpose output
port mode.
3. LCDEN (bit 1 of LCD mode select register; refer to Figure 19-9) turns on/off all LCD displays.
4. KSEN (bit 2 of LCD mode select register; refer to Figure 19-9) sets the output of the key source
signal.
214
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.2 Functional Outline of LCD Controller/Driver
The LCD controller/driver can display up to 60 dots by using a combination of common signal output pins
(COM2 to COM0) and segment signal output pins (LCD19/P2H0 to LCD0/KS0/PYA0).
Figure 19-2 shows the relationship between common signal output pins, segment signal output pins, and
display dots.
As shown in this figure, three dots can be displayed at the intersections between one segment line and the
COM2 to COM0 pins.
The driving mode is 1/3 duty, 1/2 bias, and the drive voltage is supply voltage VDD.
The segment signal output pins (LCD19/P2H0 to LCD0/KS0/PYA0) can also be used as general-purpose output
port pins.
When these pins are used as general-purpose output port pins, ports 2H (LCD19/P2H0), 2G (LCD18/2G0), 2F
(LCD17/P2F0), 2E (LCD16/P2E0), and YA (LCD15/KS15/PYA15 to LCD0/KS0/PYA0) can be independently used.
Of the segment signal output pins, the LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins are also used as key source
signal output pins.
The key source signals and LCD segment signals are output by means of time-division multiplexing.
For details of the general-purpose output ports, refer to 10. GENERAL-PURPOSE PORTS.
For details of the key source signals, refer to 20. KEY SOURCE CONTROLLER/DECODER.
The following subsections 19.2.1 through 19.2.5 outline the function of each block of the LCD controller/
driver.
Figure 19-2. Common Signal Output, Segment Signal Output, and Display Dots
COM
2
pin
Display dot
COM
COM
1
0
pin
pin
Segment signal output pin (LCD )
n
19.2.1 LCD segment register
The LCD segment register sets dot data that is used to turn on/off the LCD.
Because this register is mapped in the data memory, it can be controlled by any data memory manipulation
instruction.
When the segment signal output pins are used as general-purpose output port pins, this register sets output
data.
For details, refer to 19.3.
19.2.2 Common signal output timing control block
The common signal output timing control block controls the common signal output timing of the COM2, COM1,
and COM0 pins.
These pins output a low level when the LCD is not displayed.
Whether the LCD is displayed or not is selected by the LCD mode select register (RF address 10H).
For details, refer to 19.4.
215
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.2.3 Segment signal/key source signal output timing control block
The segment signal/key source signal output timing control block controls the segment signal output timing
of the LCD19/P2H0 through LCD0/KS0/PYA0 pins.
These pins output a low level when the LCD is not displayed.
Whether the LCD is displayed or not is selected by the LCD mode select register.
The segment signal/key source signal output timing control block controls the timing of the segment and key
source signals output from the LCD15/KS15 through LCD0/KS0 pins.
Whether the key source signals are used or not is selected by the LCD mode select register.
For details, refer to 19.5.
19.2.4 Segment signal/general-purpose output port select block
The segment signal/general-purpose output port select block selects whether each segment signal output
pin is used for LCD display (to output a segment signal) or as a general-purpose output port pin.
This selection is made by using the P2HSEL to P2ESEL flags of LCD port select register and PYASEL flag
of LCD mode select register.
For details, refer to 19.4 and 19.5.
19.2.5 Key source data register/port YA group register
The key source data register/port YA group register sets the key source output data that is output from the
LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins.
The key source signal output data is set by the key source data register (KSR: peripheral address 42H) via
the data buffer.
For details, refer to 20. KEY SOURCE CONTROLLER/DECODER.
216
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.3 LCD Segment Register
The LCD segment register specifies whether each dot on the LCD is turned on or off.
19.3.1 Configuration of LCD segment register
Figure 19-3 shows the location and configuration of the LCD segment register in the data memory.
Figure 19-3. Location and Configuration of LCD Segment Register in Data Memory
Column address
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
DBF
BANK0
B
C
D
E
F
B
C
D
E
F
BANK1
0
1
2
3
4
5
6
BANK2
Data memory
LCD segment register
7
F
System register
C
D
E
LCDD19 LCDD18 LCDD17 LCDD16
5
6
0
1
2
3
4
5
6
7
8
9
A
B
LCDD15 LCDD14 LCDD13 LCDD12 LCDD11 LCDD10 LCDD9 LCDD8 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0
LCDD15
b3
b2
b1
b0
217
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.3.2 Function of LCD segment register
Figure 19-4 shows the relation of 1 nibble (4 bits) of the LCD segment register and LCD display dots.
As shown in this figure, the lower 3 bits of display data (on/off data) in 1 nibble of the LCD segment register
can be set.
The LCD display dot corresponding to a bit that is set to 1 is turned on, and the dot corresponding to a bit
that is reset to 0 is turned off.
The highest one bit can be used as data memory, however data should be set carefully because the address
is the same.
LCDD19 to LCDD16 of the LCD segment register also set output data when the LCD19/P2H0 to LCD16/P2E0
pins are used as output port pins. In this case, output data is set to the least significant bit. The higher 3 bits
can be used as data memory, however data setting requires caution because the addresses are the same.
When LCD display is not used, LCDD15 to LCDD0 can be used as normal data memory.
Figure 19-5 shows the relationship between each LCD segment register and LCD display dots that are turned
on/off.
Figure 19-4. Relationship of 1 Nibble of LCD Segment Register and LCD Display Dots
LCD segment register
Address
Bit
m
b3
b
2
b1
b
0
Can be used as
data memory
b
b
b
2
COM
COM
COM
2
1
0
pin
pin
pin
1
0
LCD pin
n
218
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 19-5. Relationship Between LCD Display Dot, Output of Each Pin and Each Data Setting Register
PYA
PYA
PYA
PYA
PYA
PYA
PYA
PYA
PYA
PYA
0/KS
1/KS
2/KS
3/KS
4/KS
5/KS
6/KS
7/KS
8/KS
9/KS
0
1
2
3
4
5
6
7
8
9
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
0
1
2
3
4
5
6
7
8
9
PYA10/KS10
PYA11/KS11
PYA12/KS12
PYA13/KS13
PYA14/KS14
PYA15/KS15
LCD10
LCD11
LCD12
LCD13
LCD14
LCD15
LCD16/P2E
0
LCD17/P2F
0
LCD18/P2G
0
LCD19/P2H
0
219
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.4 Segment Signal/General-Purpose Output Port Select Block
Figure 19-6 shows the configuration of the segment signal/general-purpose output port select block.
This block specifies whether each pin is used as a segment signal output pin or a general-purpose output port pin,
by using the P2HSEL through P2ESEL flags of the LCD port select register and the PYASEL flag of the LCD mode
select register. When each flag is 1, the corresponding pin is set in the general-purpose output port mode; when the
flag is 0, the pin is set in the segment signal output mode.
The LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins can simultaneously output segment signals and key source signals.
When port YA is selected, however, port output takes precedence.
Figure 19-7 shows the configuration and function of the LCD port select register.
Figure 19-9 shows the configuration and function of the LCD mode select register.
Figure 19-6. Configuration of Segment Signal/General-Purpose Output Port Select Block
P2HSEL flagNote
Port data
From bit 0 of LCDD19Note
1
0
LCD19/P2H
LCD16/P2E
0
0
From segment signal/key source
Segment signal signal output timing control block
PYASEL flag
Port data
From key source data register/
port YA group register
1
0
LCD15/KS15/PYA15
From segment signal/key source
Segment signal signal output timing control block
LCD
0/KS
0/PYA
0
Note P2GSEL flag and LCDD18 for LCD18/P2G0 pin.
P2FSEL flag and LCDD17 for LCD17/P2F0 pin.
P2ESEL flag and LCDD16 for LCD16/P2E0 pin.
220
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 19-7. Configuration of LCD Port Select Register
Name
Flag symbol
Address
11H
Read/
write
b
3
b
2
b
1
b
0
LCD port select
register
P
2
P
2
P
2
P
2
R/W
H
S
E
L
G
S
E
L
F
S
E
L
E
S
E
L
Selects LCD segment signal output pin or general-purpose output port
0
1
Uses LCD16/P2E
Uses LCD16/P2E
0
0
pin as LCD segment pin
pin as general-purpose output port pin
Selects LCD segment signal output pin or general-purpose output port
0
1
Uses LCD17
/
P2F
0
0
pin as LCD segment pin
Uses LCD17/P2F
pin as general-purpose output port pin
Selects LCD segment signal output pin or general-purpose output port
0
1
Uses LCD18/P2G
Uses LCD18/P2G
0
0
pin as LCD segment pin
pin as general-purpose output port pin
Selects LCD segment signal output pin or general-purpose output port
0
1
Uses LCD19/P2H
Uses LCD19/P2H
0
0
pin as LCD segment pin
pin as general-purpose output port pin
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
Retained
221
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.5 Common Signal Output Timing Control Block and Segment Signal/Key Source Signal Output
Timing Control Block
Figure 19-8 shows the configuration of the common signal output timing control block and segment signal/key
source signal output timing control block.
The common signal output timing control block controls the output timing of the COM2 to COM0 signals.
The segment signal/key source signal output timing control block controls the output timing of the segment signals
and key source signals of the LCD19/P2H0 through LCD0/KS0/PYA0 pins.
The common and segment signals are output when the LCDEN flag of the LCD mode select register is 1. By clearing
the LCDEN flag to 0, therefore, all LCD displays can be turned off.
The key source signal is output when the KSEN flag of the LCD mode select register is 1.
When LCD display is not performed, the COM2 to COM0 and LCD19/P2H0 to LCD0/KS0/PYA0 pins output a low level.
Figure 19-9 shows the configuration and function of the LCD mode select register.
Figure 19-8. Configuration of the Common Signal Output Timing Control Block and
Segment Signal/Key Source Signal Output Timing Control Block
Port data
To segment signal/
general-purpose output
port select block
b
b
b
0
1
2
LCDD19
|
LCDD16
Segment signal
timing control
LCDEN flag
Segment signal
Port data
Basic clock for
timing control
Key source data register/
port YA group register
To segment signal/
general-purpose output
port select block
b
b
b
0
1
2
Segment signal/
key source signal
timing control
LCDD15
|
LCDD0
Segment signal
KSEN flag
To common
signal
Common signal
timing control
output pin
222
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 19-9. Configuration of LCD Mode Select Register
Name
Flag symbol
Address
10H
Read/
write
b
3
b2
b1
b
0
LCD mode select
register
0
K
S
E
N
L
C
D
E
N
P
Y
A
S
E
L
R/W
Selects LCD segment output pin and general-purpose output port
LCD /KS /PYA to LCD15/KS15/PYA15 pins used as LCD segment
LCD /KS /PYA
0
1
0
0
0
0
0
0
to LCD15/KS15/PYA15 pins used as general-purpose output port
Turns on/off all LCD display dots
0
1
Display off (all segment and common signals are low)
Display on
Sets output of key source signal
Key source off
0
1
Key source on
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
0
Retained
223
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.6 Output Waveforms of Common and Segment Signals
Figures 19-10 to 19-12 show the output waveforms of the common and segment signals.
Figure 19-10 shows the output waveform with the key source signals not output, and Figures 19-11 and 19-
12 show the output waveform with the key source signals output.
As shown in Figure 19-10, the LCD driver outputs signals with a frame frequency of 83 Hz at 1/3 duty, 1/2
bias (voltage average mode).
As the common signals, three levels of voltages (GND, 1/2 VDD, and VDD) each having a phase difference
of 1/6 from the others are output from the COM1 and COM0 pins.
Therefore, voltages in a range of 1/2VDD 1/2 VDD are output. This display mode is called 1/2 bias drive mode.
As the segment signals, two levels (0, VDD) of voltages each having a phase corresponding to a display dot
are output from each segment signal output pin.
Because three display dots (A, B, and C) are turned on/off by one segment pin as shown in Figure 19-10,
eight types of phases <1> through <8> shown in Figure 19-10 are output by combination of each dot, and on
and off.
Each display dot is turned on when the potential difference between the common and segment signals
reaches VDD.
The duty factor at which each display dot is turned on is 1/3, and the frequency of the LCD clock is
167 Hz.
This display mode is called 1/3 duty drive mode.
224
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 19-10. Common Signal and Segment Signal Output Waveform
(When Key Source Signal Is Not Output)
Dot A
Dot B
Dot C
COM
COM
COM
2
1
0
pin
pin
pin
Each segment signal output pin (LCD )
n
Common signal
COM pin
2
V
DD
1/2 VDD
GND
COM pin
1
V
DD
1/2 VDD
GND
COM pin
0
V
DD
1/2 VDD
GND
Each segment pin
<1> A = off, B = off, C = off
<2> A = off, B = off, C = on
<3> A = off, B = on, C = off
<4> A = off, B = on, C = on
C = on
C = on
C = on
C = on
B = on
B = on
B = on
B = on
C = on B = on
<5> A = on, B = off, C = off
C = on B = on
C = on B = on
C= on B = on
A = on
A = on
A = on
A = on
A = on
A = on
<6> A = on, B = off, C = on
A = on C = on
A = on C = on
A = on C = on
A = on C = on
<7> A = on, B = on, C = off
A = on
B = on A = on
B = on A = on
B = on A = on
B = on A = on
<8> A = on, B = on, C = on
A = on C = on B = on A = on C = on B = on A = on C = on B = on A = on C = on B = on A = on
2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms
225
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 19-11. Common Signal and Segment Signal Output Waveform
(When “1” Is Output as Key Source Signal)
Dot A
Dot B
Dot C
COM
COM
COM
2
1
0
pin
pin
pin
Each segment signal output pin (LCD )
n
Common signal
COM pin
2
VDD
1/2 VDD
GND
COM pin
1
VDD
1/2 VDD
GND
COM pin
0
VDD
1/2 VDD
GND
Each segment pin (pin outputting "1" as key source)
<1> A = off, B = off, C = off
<2> A = off, B = off, C = on
C = on
C = on
C = on
C = on
<3> A = off, B = on, C = off
B = on
B = on
B = on
B = on
<4> A = off, B = on, C = on
C = on B = on
C = on B = on
C = on B = on
C = on B = on
<5> A = on, B = off, C = off
A = on
A = on
A = on
A = on
A = on
A = on
A = on
A = on
A = on
A = on
A = on
A = on
<6> A = on, B = off, C = on
A = on C = on
C = on
C = on
C = on
<7> A = on, B = on, C = off
A = on
<8> A = on, B = on, C = on
A = on
B = on
B = on
B = on
B = on
A = on
A = on
C = on B = on
A = on C = on B = on
A = on C = on B = on
A = on C = on
B = on
2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms
226
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 19-12. Common Signal and Segment Signal Output Waveform
(When “0” Is Output as Key Source Signal)
Dot A
Dot B
Dot C
COM
COM
COM
2
1
0
pin
pin
pin
Each segment signal output pin (LCD )
n
Common signal
COM pin
2
VDD
1/2 VDD
GND
COM pin
1
VDD
1/2 VDD
GND
COM pin
0
VDD
1/2 VDD
GND
Each segment pin (pin outputting "0" as key source)
<1> A = off, B = off, C = off
<2> A = off, B = off, C = on
C = on
C = on
C = on
C = on
<3> A = off, B = on, C = off
B = on
B = on
B = on
B = on
B = on
B = on
B = on
B = on
<4> A = off, B = on, C = on
C = on
C = on
C = on
C = on
<5> A = on, B = off, C = off
A = on
A = on
A = on
A = on
A = on
A = on
A = on
<6> A = on, B = off, C = on
A = on
<7> A = on, B = on, C = off
A = on
C = on
A = on C = on
C = on
A = on C = on
B = on
B = on
A = on
B = on A = on
B = on A = on
B = on
B = on
A = on
B = on A = on
B = on A = on
<8> A = on, B = on, C = on
A = on
C = on
A = on C = on
C = on
A = on C = on
2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms
227
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.7 Using LCD Controller/Driver
Figure 19-13 shows an example of wiring an LCD panel.
An example of a program that turns on a 7-segment LCD panel by using the LCD0 to LCD3 pins as shown
in Figure 19-13 is shown below.
Example
PMN0
MEM 0.01H
; Preset memory number and BK data storage area
Symbol definition of least significant bit of DBF as “CH” display flag
; Display table data
CH
FLG DBF0.2
;
LCDDATA:
;
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0
; Corresponds to LCD segment register
;
– f e
a g d
– b c
; Corresponds to LCD group register
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 B
0 0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 B
0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 B
0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 B
0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 B
0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 B
0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 1 B
0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 B
0 0 0 0 0 0 1 0 0 1 1 1 0 0 1 1 B
0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 1 B
0 0 0 0 0 0 1 1 0 1 1 1 0 0 1 1 B
0 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 B
0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 1 B
0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 B
0 0 0 0 0 0 1 1 0 1 1 0 0 0 1 0 B
; BLANK
; 1
; 2
; 3
; 4
; 5
; 6
; 7
; 8
; 9
; A
; B
; C
; D
; E
; F
CLR1
MOV
PYASEL
RPL, #1110B
MOV
AR3, #.DL.LCDDATA SHR 12 AND 0FH
AR2, #.DL.LCDDATA SHR 8 AND 0FH
AR1, #.DL.LCDDATA SHR 4 AND 0FH
MOV
MOV
MOV
AR0, #.DL.LCDDATA
AR0, PMN0
AND 0FH
ADD
ADDC
ADDC
ADDC
MOVT
MOV
AR1,
AR2,
AR3,
DBF,
RPH,
RPL,
#0
#0
#0
@AR
#0
#0
MOV
SKGE
SET1
BANK2
LD
PMN0, #0AH
CH
LCDD0, DBF0
LCDD1, DBF1
LCDD2, DBF2
LCDEN
LD
LD
SET1
228
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 19-13. Example of Wiring LCD Panel
229
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
19.8 Status on Reset
19.8.1 On power-on reset
The LCD19/P2H0 to LCD0/KS0/PYA0 pins are specified as LCD segment signal output pins, and output a low
level.
The COM2 to COM0 pins output a low level.
Therefore, the LCD display is turned off.
19.8.2 On execution of clock stop instruction
The LCD19/P2H0 to LCD0/KS0/PYA0 pins are specified as LCD segment signal output pins, and output a low
level.
The COM2 to COM0 pins output a low level.
Therefore, the LCD display is turned off.
19.8.3 On CE reset
Of the LCD19/P2H0 to LCD0/KS0/PYA0 pins, those that are specified as segment signal output pins output
segment signals, and those that are specified as general-purpose output port pins retain the current output
value.
The COM2 and COM0 pins output common signals.
19.8.4 In halt status
Of the LCD19/P2H0 to LCD0/KS0/PYA0 pins, those that are specified as segment signal output pins output
segment signals, and those that are specified as general-purpose output port pins retain the current output
value.
The COM2 and COM0 pins output common signals.
230
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20. KEY SOURCE CONTROLLER/DECODER
The key source controller/decoder can configure a key matrix of up to 64 keys by outputting key source signals
by means of the LCD segment signal output and time division.
20.1 Configuration of Key Source Controller/Decoder
Figure 20-1 shows the configuration of the key source controller/decoder.
As shown in the figure, the key source controller/decoder consists of a segment signal/general-purpose
output port select block, segment signal/key source signal timing control block, key source data register, key
input control block, and P0D port register.
The following section 20.2 outlines the function of each block.
Figure 20-1. Outline of Key Source Controller/Decoder
LCDEN flag
PYASEL flag
KSEN flag
LCD15/KS15/PYA15
From LCD
segment register
LCD14/KS14/PYA14
.....
Segment
signal/key
source signal
output timing
control block
Segment signal/
general-purpose
output port
LCD
LCD
LCD
2
1
0
/KS
/KS
/KS
2
1
0
/PYA
/PYA
/PYA
2
1
0
Key source
data register
(KSR)
select block
DBF
.........
P0D
P0D
P0D
P0D
3
2
1
0
/K
/K
/K
/K
3
2
1
0
KEYJ flag
Key input
control block
Key matrix
P0D port register
(data memory)
Remarks 1. PYASEL (bit 0 of the LCD mode select register; refer to 20.4.3 Configuration and function of
LCD mode select register) sets the LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins in the LCD segment
signal output or general-purpose output port mode.
2. LCDEN (bit 1 of the LCD mode select register; refer to 20.4.3 Configuration and function of LCD
mode select register) turns ON/OFF all LCD displays.
3. KSEN (bit 1 of the LCD mode select register; refer to 20.4.3 Configuration and function of LCD
mode select register) sets output of the key source signal.
4. KEYJ (bit 0 of the key input judge register; refer to 20.5.3 Configuration and function of key input
judge register) detects whether the latch contents of the key input pin are valid.
231
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.2 Functional Outline of Key Source Controller/Decoder
The key source controller/decoder can configure a key matrix of up to 64 keys by using key source signal
output pins (LCD15/KS15/PYA15 to LCD0/KS0/PYA0) and key input pins (P0D3/K3 to P0D0/K0).
Figure 20-2 shows the example of key matrix configuration.
The LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins are multiplexed with LCD segment signal output pins.
Therefore, the key source signals and LCD segment signals are output by means of time-division multiplexing.
The following subsections 20.2.1 through 20.2.3 outline the function of each block of the key source controller/
decoder.
Figure 20-2. Example of Key Matrix Configuration
Key source output pin
Key source input pin
20.2.1 Key source data register (KSR)
The key source data register sets the key source output data of the pin that outputs a key source signal.
Data is set to the key source data register via the data buffer.
When data is set to this register, the key source data is output from the LCD15/KS15/PYA15 to LCD0/KS0/PYA0
pins.
For details, refer to 20.3.
20.2.2 Segment signal/key source signal output timing control block
The segment signal/key source signal output timing block controls the output timing of the key source and
segment signals of the LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins.
Whether a key source signal is used or not is specified by the LCD mode select register.
The key source signal is not output when LCD display is not used. In this case, the above pins output a low
level.
Whether LCD display is not used or not is specified by the LCD mode select register.
For details, refer to 20.4.
20.2.3 Key input control block and P0D port register
The key input control block detects the key input signals input to the P0D3/K3 to P0D0/K0 pins in synchronization
with key source signal output timing.
To output the key source signals from the LCD15/KS15 through LCD0/KS0 pins, therefore, the P0D3/K3 to P0D0/
K0 pins are used as key input pins.
The key input data is read by the P0D port register (address 73H of BANK0) in the data memory.
For details, refer to 20.5.
232
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.3 Key Source Data Setting Block
20.3.1 Configuration of key source data setting block
Figure 20-3 shows the configuration of the key source data setting block.
Figure 20-3. Configuration of Key Source Data Setting Block
Data buffer (DBF)
Address
Symbol
Data
0CH
0DH
0EH
0FH
DBF3
DBF2
DBF1
DBF0
M
S
B
L
S
B
Peripheral address 42H
16
Key source data register
(KSR)
Key source data latch
20.3.2 Function of key source data setting block
The key source data setting block sets the key source data to be output from the LCD15/KS15/PYA15 to LCD0/
KS0/PYA0 pins.
The key source data is set to the key source data register (KSR: peripheral address 42H) via the data buffer.
Each bit of the key source data register corresponds to the LCD15/KS15/PYA15 to LCD0/KS0/PYA0 pins, and
sets the key source data of each pin.
When a bit of the key source data register is set to 1, the pin corresponding to this bit outputs a high level
as a key source signal; when the bit is reset to 0, the corresponding pin outputs a low level.
For the output timing, refer to 20.4.
The following subsections 20.3.3 explains the configuration and function of the key source data register.
Also refer to Figure 19-5 in 19. LCD CONTROLLER/DRIVER.
233
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.3.3 Configuration and function of key source data register (KSR)
The configuration and function of the key source data register are illustrated below.
Name
Symbol
Address
Bit
Data buffer
DBF3
0CH
DBF2
0DH
DBF1
0EH
DBF0
0FH
b
3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
b3
b2
b1
b0
Data
Transfer data
GET can be executed
16
PUT can be executed
Peripheral register
Peripheral
Peripheral
hardware
Name
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
address
Key source
data register
KSR
Key source
controller/decoder
42H
Valid data
Selects output pin of key source signal
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
LCD
0
1
2
3
4
5
6
7
8
9
/KS
/KS
/KS
/KS
/KS
/KS
/KS
/KS
/KS
/KS
0
1
2
3
4
5
6
7
8
9
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
/PYA
0
1
2
3
4
5
6
7
8
9
pin
pin
pin
pin
pin
pin
pin
pin
pin
pin
LCD10/KS10/PYA10 pin
LCD11/KS11/PYA11 pin
LCD12/KS12/PYA12 pin
LCD13/KS13/PYA13 pin
LCD14/KS14/PYA14 pin
LCD15/KS15/PYA15 pin
Does not output key source signal
Outputs key source signal
0
1
234
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.4 Output Timing Control Blocks and Segment/Port Select Block
20.4.1 Configuration of output timing control blocks and segment/port select block
Figure 20-4 shows the configuration of the common signal and segment signal/key source signal output timing
control blocks and segment signal/general-purpose output port select block.
Figure 20-4. Configuration of Timing Control Blocks and Port Select Block
LCDEN flag
KSEN flag
Basic clock for
timing control
PYASEL flag
Port data
Key source data register/
port YA group register
1
0
LCD15/KS15/PYA15
|
LCD
0
/KS
0
/PYA
0
b0
b1
b2
Segment signal/
key source
signal timing
control
LCDD15
|
LCDD0
Segment signal/
key source signal
To key input control block and KEYJ flag
20.4.2 Function of output timing control block
The segment signal/key source signal output timing control block controls the output timing of the key source
and segment signals.
The LCD segment signal is output when the LCDEN flag of the LCD mode select register is 1.
All the LCD display dots can be turned off by resetting the LCDEN flag to 0. At this time, a low level is output
as the segment signal, and the key source signal is not output.
To output the key source signal, therefore, the LCDEN flag must be 1.
The key source signal is also output when the KSEN flag of the LCD mode select register is 1.
Therefore, the KSEN flag is used to specify whether the key source signal is used or not.
To output the key source signal, therefore, the LCDEN and KSEN flags must be 1.
The following subsection 20.4.3 indicates the configuration and function of the LCD mode select register.
Subsection 20.4.4 shows the output waveforms of the key source and segment signals.
For the relationship between the common and segment signals of the LCD, and key source signal, refer to
19. LCD CONTROLLER/DRIVER.
235
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.4.3 Configuration and function of LCD mode select register
The LCD mode select register turns on/off all the LCD display dots, and specifies output of the key source
signal.
The configuration and function of this register are illustrated below.
Name
Flag symbol
Address
10H
Read/
write
b
3
b2
b1
b
0
LCD mode select
register
R/W
0
K
S
E
N
L
C
D
E
N
P
Y
A
S
E
L
Selects LCD segment output pin and general-purpose output port
Pins LCD /KS /PYA to LCD15/KS15/PYA15 used as LCD segment
Pins LCD /KS /PYA
0
1
0
0
0
0
0
0
to LCD15/KS15/PYA15 used as general-purpose output port
Turns on/off all LCD display
0
1
Display off (all segment and common output pins output low level)
Display on
Selects output of key source signal
Key source off
Key source on
0
1
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
0
0
Retained
20.4.4 Output waveforms of segment and key source signals
Figures 20-5 and 20-6 show the output waveforms of the key source and segment signals.
As shown in figures, the key source and segment signals are output by means of time-division multiplexing.
The key source signal is output for 220 µs at intervals of 4 ms.
To put it in another way, a pin corresponding to a bit of the key source data register that is set to 1 outputs
a high level for 220 µs every 4 ms, and a pin corresponding to a bit of the key source data register that is reset
to 0 outputs a low level for 220 µs every 4 ms.
When output of the key source signal is selected (KSEN flag = 1), pins that do not output key source signals
(LCD19/P2H0 to LCD16/P2E0) output the waveform shown in Figure 20-6. However, a waveform of 0 is output
as the key source data.
236
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 20-5. Output Waveforms of Segment and Key Source Signals
(When “1” Is Output as Key Source Signal)
Dot A
Dot B
Dot C
COM
COM
COM
2
1
0
pin
pin
pin
Segment signal
Key source signal
Each segment/key source signal output pin (LCD
n
/KS )
n
Common signal
COM pin
2
VDD
1/2 VDD
GND
COM pin
1
VDD
1/2 VDD
GND
COM pin
0
VDD
1/2 VDD
GND
Each segment pin (pin outputting "1" as key source)
<1> A = off, B = off, C = off
<2> A = off, B = off, C = on
C = on
C = on
C = on
C = on
<3> A = off, B = on, C = off
<4> A = off, B = on, C = on
B = on
B = on
B = on
B = on
B = on
C = on B = on
C = on B = on
C = on B = on
C = on
<5> A = on, B = off, C = off
A = on
A = on
A = on
A = on
A = on
A = on
A = on
A = on
<6> A = on, B = off, C = on
A = on C = on
C = on
C = on
A = on C = on
<7> A = on, B = on, C = off
A = on
B = on
A = on
A = on
B = on
A = on
A = on
B = on
A = on
B = on
B = on
A = on
A = on
<8> A = on, B = on, C = on
A = on C = on B = on
C = on B = on
C = on B = on
A = on C = on
Key source signal
µ
220
s
2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms
237
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 20-6. Output Waveforms of Segment and Key Source Signals
(When “0” Is Output as Key Source Signal)
Dot A
Dot B
Dot C
COM
COM
COM
2
1
0
pin
pin
pin
Segment signal
Key source signal
Each segment/key source signal output pin (LCD
n
/KS )
n
Common signal
COM pin
2
VDD
1/2 VDD
GND
COM pin
1
VDD
1/2 VDD
GND
COM pin
0
VDD
1/2 VDD
GND
Each segment pin (pin outputting "0" as key source)
<1> A = off, B = off, C = off
<2> A = off, B = off, C = on
C = on
C = on
C = on
C = on
<3> A = off, B = on, C = off
<4> A = off, B = on, C = on
B = on
B = on
B = on
B = on
B = on
B = on
C = on B = on
C = on
C = on B = on
C = on
<5> A = on, B = off, C = off
A = on
<6> A = on, B = off, C = on
A = on
A = on
A = on
A = on
A = on
A = on
A = on
C = on
A = on C = on
C = on
A = on C = on
<7> A = on, B = on, C = off
A = on
B = on
A = on
B = on A = on
B = on A = on
B = on
A = on
B = on A = on
B = on A = on
<8> A = on, B = on, C = on
A = on
C = on
B = on
A = on C = on
C = on
B = on
A = on C = on
Key source signal
220
s
µ
2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms
238
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.5 Key Input Control Block
20.5.1 Configuration of key input control block
Figure 20-7 shows the configuration of the key input control block.
Figure 20-7. Configuration of Key Input Control Block
VDD
Half release signal
P0D port register
P0D
P0D
3
/K
/K
3
0
Input latch
0
Segment signal/key source signal
output timing control block
High ON resistance
KEYJ flag
20.5.2 Function of key input control block
The key input control block controls the timing to read the key input signals from the P0D3/K3 to P0D0/K0 pins
and reads the key input data.
Figure 20-8 illustrates the key input signals and key input timing.
As shown in this figure, the internal-pull down resistors of the P0D3/K3 to P0D0/K0 pins are turned off while
the display data of the LCD segment is output, and turned on only for 220 µs while the key source signal is output.
For the duration of 220 µs during which the key source signal is output, the input signal of each key input
pin is connected to the input latch.
Therefore, the signal input to each key input pin can be detected in the 220 µs during which the key source
signal is output.
Figure 20-9 shows the timing chart of the key source signal, key input signal, and key input data (P0D port
register).
Whether a key source signal is output or not is detected by the KEYJ flag of the key input judge register (RF
address 16H).
The KEYJ flag is set after the key source signal has been output for 220 µs, and is reset when data has been
set to the key source data register and when the content of the KEYJ flag has been read.
By detecting the KEYJ flag after the key source signal data has been output to the key source data register,
and then detecting the status of each key input pin after the KEYJ flag has been set to 1, the key can be input.
The following subsection 20.5.3 explains the configuration and function of the key input judge register.
239
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 20-8. Key Source Signal and Key Input Timing
Dot A
Dot B
Dot C
COM
COM
COM
2
1
0
pin
pin
pin
Segment signal
Key source signal
Each segment/key source signal output pin (LCD
n
/KS )
n
Each segment pin (pin outputting "1" as key source, A = on, B = on, C = off)
H
Segment pin
L
Pull down
Key input pin
Open
1
0
KEYJ flag
Key source signal
220
µ
s
2 ms
2 ms
PUT KSR, DBF or
SKT 1 KEYJ
PUT KSR, DBF or
SKT1 KEYJ
Signal input to P0D
3
/K3
to P0D
0
/K0 pins is connected to input latch during this period.
If PUT KSR, DBF is executed during this period, KEYJ flag is not set for 4 ms.
Input data is latched at this point.
Caution The KEYJ flag is not set to 1 when in HALT mode.
240
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 20-9. Timing Chart of Key Source Signal, Key Input Signal, and Key Input Data (P0D port register)
H
Segment pin
L
<1> When P0D port register is “1”
H
Key input pin input signal
L
1
P0D port register
0
<2> When P0D port register is “0”
H
Key input pin input signal
L
1
P0D port register
0
The KEYJ flag is “0” during this period. If the value
of P0D is read, the status of the P0D pin is read.
Input data is latched at this point.
20.5.3 Configuration and function of key input judge register
The key input judge register detects the presence or absence of the key input signal latch when the LCD
segment signal output pins are shared with key source signal output.
The configuration and functions of this register are illustrated below.
Flag symbol
Name
Address
16H
Read/
write
b
3
b2
b1
b
0
Key input judge register
0
0
0
R & Reset
K
E
Y
J
Detects valid/invalid latch contents of key input signal
Invalid key latch contents
0
1
Valid latch contents
Fixed to 0
Power-on
Clock stop
CE
0
0
0
0
0
0
Caution The KEYJ flag is not set to 1 when in HALT mode.
The KEYJ flag retains the data prior to HALT instruction execution.
241
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.6 Using Key Source Controller/Decoder
20.6.1 Configuring key matrix
Figure 20-10 shows an example of configuring a key matrix.
As shown in this figure, the key matrix can be configured for up to 64 keys.
Because the key source signal output pins also output the LCD segment signals at the same time, diode A
must be used to prevent the reverse flow of the LCD segment signal if a momentary switch is used.
Diodes B and C are used to prevent sneaking of the key source signal.
Use a PNP transistor as the transistor switch.
The following (1) explains the points to be noted when an NPN transistor is used.
(2) through (4) explain the points to be noted if diodes A, B, and C are not used.
Figure 20-10. Example of Key Matrix Configuration
A
To LCD
panel
B
76
62
75
61
74
60
73
59
67
57
66
56
65
55
64
54
63
53
62
52
61
51
60
50
59
49
58
48
52
43
50
42
(80 pin)
(64 pin)
Configuration of each switch
Momentary switch
K
Alternate switch
K
Diode switch
K
KS
KS
KS
KS
KS
C
KS
KS
K
K
K
Or
C
K
242
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(1) Notes on using NPN transistor switch
When an NPN transistor switch is used, the low level may not be accurately read as illustrated in the figure
below.
If KS is low and a high level is input to the base of the transistor
in the figure on the left, voltage VK input to K is as follows.
VDD
High
R
A
RB
VK =
× (VDD – VBE)
RA + RB
KS
Low
K
A low level must be input to K at this time because KS is low.
However, the voltage input to K changes depending on RA and
RB, as indicated by the above expression.
Internal resistor
RB
Therefore, a low level may not be input depending on the values
of RA and RB.
(2) Notes when diode A is not used
An example of a circuit where diode A is missing is shown below.
Suppose switches SW1 and SW2 are on, KS15 outputs a high level, and KS14 outputs a low level, as shown
below.
If diode A is missing, currents I1 and I2 indicated by the dotted lines flow.
Consequently, the high level of KS15 and low level of KS14 are not output correctly because of I2, and the key
input data of K3 cannot be accurately read.
If KS15 and KS14 are used to output LCD segment signals, the LCD cannot be turned on/off correctly.
SW1
LCD
SW2
LCD
Low
High
I1
I
2
K2
K3
KS14
KS15
243
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(3) Notes when diode B is not used
An example of a circuit where diode B is not used is shown below.
Suppose switches SW1, SW2, and SW4 are on, and KS7 outputs a high level, as shown below.
If diode B is missing, currents I1 and I2 flow as indicated by the dotted lines.
Consequently, a high level is input to K2 because of I2 despite that switch SW3 is off, and it is judged that SW3
is on.
SW1
SW2
SW3
SW4
High
Low
I2
I1
K2
K3
KS7
KS8
(4) Note when diode C is not used
An example of a circuit where diode C is not used is shown below.
Suppose switches SW2, SW3, and SW4 are on, and KS8 outputs a high level, as shown below.
If diode C is missing, currents I1, I2, and I3 flow as indicated by the dotted lines.
Consequently, a high level is input to K2 because of I2 despite the fact that switch SW1 is off, and it is judged
that SW1 is on.
Moreover, KS8 cannot output a high level correctly because of I3.
SW1
SW2
SW3
SW4
Low
High
I2
I1
I3
K2
K3
KS7
KS8
244
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.6.2 Reading alternate switches and diode switches
Here is a program example.
Example To read statuses of alternate and diode switches of LCD15/KS15/PYA15 to LCD8/KS8/PYA8 pins to
addresses 20H to 27H of BANK0 of data memory
KS8
NIBBLE8 0.20H
KEY_IN
MEM
0.73H
; P0D port register
KEY_LOAD:
CLR1
PYASEL
; Sets LCD15/KS15/PYA15 to LCD8/KS8/PYA8 pins
; to LCD segment
SET2
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
LCDEN, KSEN
DBF3, #0000B
DBF2, #0001B
DBF1, #0000B
DBF0, #0000B
IXM, #0000B
IXL, #0000B
RPH, #0000B
RPL, #0000B
; LCD segment and key source signal output
; Sets key source data
; Outputs low level from KS8
KSCAN:
LOOP:
PUT
KSR, DBF
; Outputs signal of key source data
; Determines if key input is latched
SKF1
BR
KEYJ
KCHECK
Processing A
; Waits until key input is latched
BR
LOOP
KCHECK:
MOV
SET1
ST
RPL#.DM.KEY_IN SHR 3 AND 0EH
IXE
KS8, KEY_IN
IXE
; Stores key input data to data memory
CLR1
MOV
INC
ADD
ADD
SKT1
BR
RPL, #0000B
IX
DBF2, DBF2
DBF3, DBF3
CY
; Updates value of key source data and
; scans key again
; Determines if all key source lines are input
KSCAN
KEY_END:
; End of input
245
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.6.3 Inputting momentary switch by binary search
The key source controller/decoder requires 4 ms to input the key of one key source signal line.
To input the keys of 16 key source signals, therefore, it takes 64 ms.
It is therefore convenient if the binary search method explained in (1) and (2) below is used.
(1) Flowchart
When KS7 to KS0 are used as key source signals of momentary switch
START
Initialization
; Sets key source controller
RA
0000B
; Sets offset address of table storing key source data to RA
AR
DBF
KSR
KSDATA+RA
@AR
; Outputs key source data at offset address specified by RA
DBF
N
Y
KEYJ = 1?
Y
; Waits until data is latched to key input latch (4 ms)
; Saves key input data to RB
RB
P0D port register
; If key input data and RA are "0", inputs all keys again because no
; key is input
RA = RB = 0?
N
Y
; If RA is greater than "7", input of one key source ends and waits for
; chattering
RA > 7?
N
RA
RA+RA
; If RA is less than "7", updates RA and continues binary search
N
Y
RB = 0?
Y
RA
RA+1
; If there is no key input data, checks all keys again
RB = 0?
N
Chattering wait
; Even if this chattering wait is missing, chattering occurs for 4 ms
; Inputs key input determined by binary search to RC again
DBF
KSR
KSR
DBF
N
Y
KEYJ = 1?
Y
RC
P0D port register
; If RC = 0, occurrence of chattering is determined, and keys are input
; from beginning
RC = 0?
N
Checking of key data
; Stores key input data before chattering to RB, data after chattering
; to RC, and key source data to RA
END
246
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example of table data for binary search
Table Data
(Key Source Data)
b15 b14 b13 b12 b11 b10 b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
0000B
0001B
0010B
0011B
0100B
0101B
0110B
0111B
1000B
1001B
1010B
1011B
1100B
1101B
1110B
1111B
(2) Program example
RA
RB
RC
MEM
MEM
MEM
0.1AH
0.1BH
0.1CH
; General-purpose work register
; General-purpose work register
; General-purpose work register
KEY_IN MEM
0.73H
; P0D port register
KSDATA:
;
KKKKKKKKKKKKKKKK
SSSSSSSSSSSSSSSS
1111119876543210
543210
;
;
;
DW
0000000011111111B
0000000011110000B
0000000000001100B
0000000000110000B
0000000000000010B
0000000000001000B
0000000000100000B
0000000010000000B
0000000000000001B
0000000000000010B
0000000000000100B
0000000000001000B
0000000000010000B
0000000000100000B
0000000001000000B
0000000010000000B
; RA = 0
; RA = 1
; RA = 2
; RA = 3
; RA = 4
; RA = 5
; RA = 6
; RA = 7
; RA = 8
; RA = 9
; RA = 10
; RA = 11
; RA = 12
; RA = 13
; RA = 14
; RA = 15
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
KEY_LOAD:
CLR1 PYASEL
SET2 LCDEN, KSEN
; Sets LCD15/KS15/PYA15 to LCD8/KS8/PYA8 pins
; to LCD segment
; LCD segment and key source signal output
247
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
START:
KSCAN:
MOV
RA, #0000B
MOV
MOV
MOV
MOV
MOV
ADD
AR3, #.DL.KSDATA SHR 0CH AND 0FH
AR2, #.DL.KSDATA SHR 8 AND 0FH
AR1, #.DL.KSDATA SHR 4 AND 0FH
AR0, #.DL.KSDATA AND 0FH
RPL, #.DL.AR0 SHR 3 AND 0EH
AR0, RA
ADDC AR1, #0
ADDC AR2, #0
ADDC AR3, #0
MOV
RPL, #0
MOVT DBF, @AR
; Reads table data
PUT
KSR, DBF
; Outputs signal of key source data
; Determines if key input is latched
LOOP1:
SKF1 KEYJ
BR
BR
KCHECK
Processing A
; Waits until key input is latched
LOOP1
KCHECK:
MOV
LD
PRL, #.DM.RB SHR 3 AND 0EH
RB, KEY_IN
; Stores key input data to RB
; All keys are checked?
SKNE RA, #0000B
SKE
BR
RB, #0000B
Key input
START
BR
; There is no key input
Key input:
SKLT RA, #1000B
; Key sources are narrowed down to one?
BR
LASTCHK
; If not, updates value of RA, and scans keys again
ADD
SKE
ADD
BR
RA, RA
RB, #0000B
RA, #0001B
KSCAN
LASTCHK:
MOV
RPL, #0
SKNE RB, #0000B
BR START
; Key input to one key source?
; If not, it is determined that chattering occurs
Chattering wait
248
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
LOOP2:
SKF1 KEYJ
; Determines if key input is latched
BR
KEYDEC
Processing B
; Waits until key input is latched
BR
LOOP2
KEYDEC:
MOV
LD
RPL, #.DM.RC SHR 3 AND 0EH
RC, KEY_IN
; Stores key input data to latch
SET2 CAP, Z
; Compares key input data after chattering with key input
; data before chattering wait
SUB
SKT1
BR
RC, RB
Z
START
; If data differ
KEY_END:
; Stores key source data to RA, key input data before
; chattering to RB, and key input data after chattering to RC
249
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
20.7 Status on Reset
20.7.1 On power-on reset
The LCD19/P2H0 to LCD0/KS0/PYA0 pins are specified as the LCD segment signal output pins and output a
low level (display off). A low level is output as the key source signal.
20.7.2 On execution of clock stop instruction
The LCD19/P2H0 to LCD0/KS0/PYA0 pins are specified as the LCD segment signal output pins and output a
low level (display off). A low level is output as the key source signal.
20.7.3 On CE reset
The output data is retained as is if the key source signal is being output.
20.7.4 In halt status
The output data is retained as is if the key source signal is being output.
If key input is specified as a halt status releasing condition, the halt status is released when a high level is
input to the P0D3/K3 to P0D0/K0 pins.
If the key source controller is used, however, the halt status is released only by a high level that is input within
220 µs during which the key source data is output.
For an explanation of how to release the halt status by key input, refer to 21.4 Halt Function.
Figure 20-11. KEYJ Flag Status in Halt Status
H
Key input pin
L
1
KEYJ flag
0
Halt status
Halt released status
Halt is released by inputting
INT or TMCY (timer carry)
KEYJ flag is not set in halt status
KEYJ flag is set at this point
250
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21. STANDBY
The standby function is used to reduce the current consumption of the device during back up.
21.1 Configuration of Standby Block
Figure 21-1 shows the configuration of the standby block.
As shown in the figure, the standby block is divided into two blocks: halt control block and clock stop control
block.
The halt control block consists of a halt controller, interrupt control block, timer carry, and key input pins
P0D0/K0 to P0D3/K3, and controls the operation of the CPU (program counter, instruction decoder, and ALU
block).
The clock stop control block controls the 4.5 MHz crystal oscillator, CPU, system register, and control
registers, by using the clock stop controller.
Figure 21-1. Configuration of Standby Block
Halt block
Interrupt
block
Halt controller
Basic timer 0
HALT h
CPU
P0D
P0D
P0D
P0D
3/K
2/K
1/K
0
/K
3
2
1
0
pin
pin
pin
pin
Program counter (PC)
Input latch
Instruction decoder
ALU
Clock stop block
CE flag
System register
Control register
Clock stop controller
STOP s
CE pin
X
OUT pin
XIN pin
Internal block
Remark CE (bit 0 of the CE pin level judge register; refer to 21.3.5 Configuration and function of CE pin level
judge register)
Detects the CE pin status.
251
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.2 Standby Function
The standby function reduces the current consumption of the device by stopping some or all its operations.
The standby function can be used in two modes: halt and clock stop.
The halt mode is to reduce the current consumption of the device by executing a dedicated instruction “HALT
h” and stopping the operation of the CPU.
The clock stop mode is to reduce the current consumption of the device by executing a dedicated instruction
“STOP s” and stopping the 4.5 MHz crystal oscillator.
In addition to the halt and clock stop modes, the operation mode of the device can be also set by the CE pin.
The CE pin is used to control the operation of the PLL frequency synthesizer and reset the device, and can
be said to be a type of the standby function in that it controls the operation of the PLL frequency synthesizer.
The following section 21.3 explains how to set the operation mode of the device by using the CE pin.
Sections 21.4 and 21.5 explain the halt and clock stop modes respectively.
21.3 Selecting Device Operation Mode with CE Pin
The CE pin controls the following functions (1) through (3) by using the level and rising edge of an externally
input signal.
(1) Controls operation of PLL frequency synthesizer
(2) Enables or disables clock stop instruction
(3) Resets device
21.3.1 Controlling operation of PLL frequency synthesizer
The PLL frequency synthesizer can operate only when the CE pin is high.
The PLL frequency synthesizer is automatically disabled when the CE pin is low.
At this time, the VCOH and VCOL pins are internally pulled down, and the EO pin is floated.
The PLL frequency synthesizer can be disabled by the PLL reference clock select register at any time when
the CE pin is high.
21.3.2 Enabling and disabling clock stop instruction
The clock stop instruction “STOP s” is enabled only when the CE pin is low.
The STOP s instruction is executed as a no-operation (NOP) instruction if it is executed when the CE pin is
high.
21.3.3 Resetting device
The device can be reset (CE reset) by raising the CE pin.
The device can also be reset through power application (power-on reset).
For details, refer to 22. RESET.
252
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.3.4 Inputting signal to CE pin
The CE pin does not accept a low or high level of less than 110 to 165 µs to prevent malfunctioning due to
noise.
The level of the signal input to the CE pin can be detected by using the CE flag of the CE pin level judge register
(RF address 07H).
Figure 21-2 shows the relationship between the input signal and CE flag.
Figure 21-2. Relationship Between Signal Input to CE Pin and CE Flag
H
CE pin
L
1
CE flag
0
µ
µ
µ
110 to 165 s
Less than 110 to 165
s
110 to 165
s
Less than
110 to 165
µ
s
CE reset
PLL operation enabled
PLL disabled
PLL disabled
STOP s instruction disabled (NOP) STOP s instruction enabled
STOP s instruction enabled (NOP)
CE reset is executed in synchronization
with next setting of timer carry FF
21.3.5 Configuration and function of CE pin level judge register
The CE pin level judge register detects the level of the signal input to the CE pin.
The configuration and function of this register are illustrated below.
Name
Flag symbol
Address
07H
Read/
write
b
3
b2
b
1
b
0
0
0
0
C
E
CE pin level judge register
R
Detects level input to CE pin
0
1
Low level
High level
Fixed to 0
Power-on
Clock stop
CE reset
0
0
0
–
–
–
– : Determined depending on pin status
The CE flag is not affected by a low or high level of less than 110 to 165 µs.
253
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.4 Halt Function
The halt function stops the operation clock of the CPU by executing the HALT h instruction.
When the HALT h instruction is executed, the program stops at the HALT h instruction, until the halt status
is released later.
Therefore, the current consumption of the device can be reduced in the halt status by the operating current
of the CPU.
The halt status can be released by key input, timer carry, or interrupt.
The releasing condition of the key input, timer carry, and interrupt is specified by the operand “h” of the HALT
h instruction.
The HALT h instruction is valid regardless of the input level of the CE pin.
The following subsections 21.4.1 through 21.4.6 explain the halt status, halt release condition, and each halt
release condition.
21.4.1 Halt status
All the operations of the CPU are stopped in the halt status.
In other words, program execution is stopped at the HALT h instruction.
However, the peripheral hardware units continue the operations set before the HALT h instruction is executed.
For the operations of the peripheral hardware units, refer to 21.6 Device Operations in Halt and Clock Stop
Status.
254
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.4.2 Halt release condition
Figure 21-3 shows the halt release conditions.
As shown in this figure, the halt release conditions are set by 4-bit data specified by operand “h” of the HALT
h instruction.
The halt status is released when the condition specified as “1” by operand “h” is satisfied.
When the halt status is released, the execution starts from the instruction next to the HALT h instruction.
If two or more release conditions are specified, and if any one of the specified conditions is satisfied, the halt
condition is released.
If the device is reset (power-on reset or CE reset), the halt status is released, and each reset operation is
performed.
If 0000B is set as the halt release condition “h”, no release condition is set.
At this time, the halt status is released if the device is reset (power-on reset or CE reset).
The following subsections 21.4.3 through 21.4.5 explains halt release conditions set by key input, basic timer
0, and interrupt.
21.4.6 shows an example when two or more release conditions are specified.
Figure 21-3. Halt Release Condition
HALT h (4 bits)
Operand bit
b3
b
2
b
1
b
0
Sets halt release condition
/K to P0D /K
Releases if high level is input to P0D pin (P0D
Releases if basic timer 0 carry FF is set to 1
Undefined (fixed to 0)
3
3
0
0)
Releases if interrupt (INT pin or timer) is acknowledged
Does not release even if condition is satisfied
Releases if condition is satisfied
0
1
255
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.4.3 Releasing halt status by key input
Releasing the halt status by key input is specified by the HALT 0001B instruction.
If releasing the halt status by key input is specified, the halt status is released when a high level is input to
any of the four pins P0D0/K0 to P0D3/K3.
The following paragraphs (1) through (3) explain the points to be noted when using a general-purpose output
port for a key source signal and when multiplexing LCD segment signal outputs with key source signal outputs.
(1) Notes on using general-purpose output port for key source signal
P0D3/K3
Latch
P0D
P0D
P0D
2/K2
1/K1
0/K
0
Switch A
General-purpose output port
The HALT 0001B instruction is executed after a general-purpose output port for key source signal goes
high.
If an alternate switch such as switch A in the above figure is used at this time, a high level is always applied
to the P0D0/K0 pin while switch A is closed, and the halt status is immediately released.
Therefore, care must be exercised in using the alternate switch.
When using a general-purpose output port for key source signal, reset the KSEN flag of the LCD mode
select register (RF address 10H) to 0.
At this time, the P0D0/K0 to P0D3/K3 pins are automatically pulled down.
256
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) Notes on multiplexing LCD segment signal and key source signal outputs
P0D
3
/K
3
Latch
P0D
P0D
P0D
2
1
0
/K
/K
/K
2
1
0
LCD15/KS15/PYA15
LCD segment signal
H
L
LCD segment
signal output
waveform
220 s
µ
Key source signal
Execute the HALT 0001B instruction after setting key source signal output data.
At this time, the halt status is not released even if a high level of the LCD segment signal is input to the
pin whose key source signal output data is “0”.
To multiplex an LCD segment signal output with a key source signal output, set the KSEN flag of the LCD
mode select register to 1.
The key source signal data (setting the pin that outputs a key source) is set by the key source data register
(KSR: peripheral address 42H) via the data buffer.
The internal key latch circuit when an LCD segment signal output is multiplexed with a key source signal
output latches data only while the key source signal is output, and is disconnected from the external
source while the LCD segment signal is output.
The internal pull-down resistor is on only when the key source signal is output.
(3) When releasing from halt status using other microcontrollers
P0D
3/K3
Output port
Latch
P0D
P0D
P0D
2/K2
1/K1
0/K
0
Microcontroller, etc.
General-purpose output port or LCD segment signal output
The P0D0/K0 to P0D3/K3 pins can also be used as general-purpose input port pins with pull-down
resistors.
Therefore, the halt status can also be released by using other microcontrollers as shown above.
257
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.4.4 Releasing halt status by basic timer 0
Releasing the halt status by basic timer 0 is set by the HALT 0010B instruction.
When the release of the halt status is set by basic timer 0, the halt status is released as soon as the basic
timer 0 carry FF has been set to 1.
The basic timer 0 carry FF corresponds to the BTM0CY flag of the basic timer 0 carry FF judge register on
a one-to-one basis, as explained in 12. TIMER, and is set to 1 at fixed time intervals (1 ms, 5 ms, 100 ms, or
250 ms).
Therefore, the halt status can be released at fixed time intervals.
Example
M1
MEM
0.10H
0010B
; 1-second counter
; Symbol definition
HLTTMR DAT
INITFLG NOT BTM0CK1, BTM0CK0
; Embedded macro
; Sets basic timer 0 carry FF setting time to 250 ms
LOOP:
HALT
HLTTMR
; Sets release condition by basic timer 0 carry FF and
halt status
SKT1
BR
BTM0CY
LOOP
; Embedded macro
; Branches to LOOP if BTM0CY flag is not set
ADD
SKT1
BR
M1, #0100B ; Adds 0100B to contents of M1
CY
; Embedded macro
LOOP
; Executes processing A if carry occurs
Processing A
BR
LOOP
In this example, the halt status is released every 250 ms and processing A is executed every 1 second.
21.4.5 Releasing halt status by interrupt
Releasing the halt status by an interrupt is set by the HALT 1000B instruction.
If releasing the halt status by an interrupt is set, the halt status is released as soon as the interrupt has been
acknowledged.
Four interrupt sources are available as explained in 11. INTERRUPTS.
Therefore, the interrupt source to be used to release the halt status must be specified by program in advance.
So that the interrupt is acknowledged, all the interrupts must be enabled (by the EI instruction), each interrupt
is enabled (by setting the corresponding interrupt enable flag), in addition that the interrupt request must be
issued from each interrupt source.
Even if an interrupt request is issued, if that interrupt is not enabled, the interrupt is not acknowledged and
the halt status is not released.
When the halt status has been released because the interrupt has been acknowledged, the program flow
branches to the vector address of the interrupt.
If the RETI instruction is executed after the interrupt processing, the program flow returns to the instruction
next to the HALT instruction.
Here is an example.
258
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example
HLTINT DAT
INTTM DAT
1000B ; Symbol definition of halt condition
0003H ; Interrupt vector address symbol definition
0004H ; Interrupt vector address symbol definition
INTPIN DAT
START:
BR
; Program address 0000H
MAIN
ORG
INTTM
; 12-bit timer interrupt vector address (0003H)
INTTIMER
BR
ORG
INTPIN
; INT pin interrupt vector address (0004H)
Processing A
BR EI_RETI
; Interrupt processing by INT pin
INTTIMER:
Processing B
; Interrupt processing by 12-bit timer
EI_RETI:
EI
RETI
SET2
SET2
MAIN:
IPTM, IP0
; Embedded macro
BTM1CK1, BTM1CK0
; Embedded macro
; Sets time interval of 12-bit timer to 1 ms
LOOP:
Processing C
; Main routine processing
; Enables all interrupts
EI
HALT
; <1>
BR
HLTINT ; Specifies releasing halt by interrupt
LOOP
In this example, the halt status is released when the 12-bit timer interrupt is acknowledged, and processing
B is executed. When the INT pin interrupt is acknowledged, processing A is executed.
Each time the halt status is released, processing C is executed.
If the INT pin interrupt request and 12-bit timer interrupt request are issued at the same time in the halt status,
processing A of the INT pin, which has the higher hardware priority, is executed.
If “RETI” is executed after execution of processing A, execution restores to the BR LOOP instruction in <1>,
but the BR LOOP instruction is not executed, and the 12-bit timer interrupt is immediately acknowledged.
If “RETI” is executed after processing B of the 12-bit timer interrupt has been executed, the BR LOOP
instruction is executed.
259
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Caution When executing the HALT instruction that will set the release condition where by the halt status
is released by the setting of the interrupt request flag (IRQ×××) when the interrupt enable flag
(IP×××) is set, describe a NOP instruction immediately before the HALT instruction.
If a NOP instruction is described immediately before the HALT instruction, a time of one
instruction is generated in between the IRQ××× manipulation instruction and HALT instruction.
In the case of the CLR1 IRQ××× instruction, for example, clearing IRQ××× is correctly reflected
on the HALT instruction (refer to Example 1 below). If a NOP instruction is not described
immediately before the HALT instruction, the CLR1 IRQ××× instruction is not correctly reflected
on the HALT instruction, and the HALT mode is not set (refer to Example 2 below).
Example 1. Program that correctly executes HALT instruction
; Sets IRQ×××
CLR1
NOP
IRQ×××
; Describes NOP instruction immediately before
; HALT instruction
; (clearing IRQ××× is correctly reflected on HALT
; instruction)
HALT
1000B
; Correctly executes HALT instruction
; (HALT mode is set)
2. Program that does not set HALT mode
; Sets IQR×××
CLR1
HALT
IRQ×××
; Clearing IRQ××× is not reflected on HALT instruction
; (but on instruction next to HALT)
1000B
; HALT instruction is ignored (HALT mode is not set)
260
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.4.6 If two or more release conditions are simultaneously set
If two or more release conditions are simultaneously set, and if even one of the conditions is satisfied, the
halt status is released.
The method to identify the release condition that is satisfied when two or more release conditions are specified
is shown below.
Example
HLTINT
HLTTMR
HLTKEY
INTPIN
DAT 1000B
DAT 0010B
DAT 0001B
DAT 0004H
; INT pin interrupt vector address symbol
; definition
START:
ORG
BR
MAIN
INTPIN
Processing A
; INT pin interrupt processing
; Basic timer 0 processing
EI
RETI
TMRUP
Processing B
RET
KEYDEC:
MAIN:
; Key input processing
Processing C
RET
MOVT
DBF, @AR
; Sets key source output data (table reference)
; to key source data register (KSR)
PUT
KSR, DBF
SET2
KSEN, LCDEN
; Embedded macro
; Multiplexes LCD segment signal output with
; key source signal output
; Embedded macro
SET2
SET1
EI
BTM0CK1, BTM0CK0
IP
;
Sets basic timer 0 carry FF setting time to 1 ms
; Embedded macro
; Enables INT pin interrupt
LOOP:
HALT
HLTINT OR HLTTMR OR HLTKEY
; Specifies interrupt, basic timer 0, and key input
; as halt release conditions
; Embedded macro
SKF1
BTM0CY
; Detects BTM0CY flag
CALL
SKF1
TMRUP
KEYJ
; Basic timer 0 processing if set to 1
; Embedded macro
; Detects key input latchNote
; Key input processing if latched
CALL
BR
KEYDEC
LOOP
Note If the target key source output data is not output, the KEYJ flag is not set (1).
261
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.5 Clock Stop Function
The clock stop function stops the 4.5 MHz crystal oscillator by executing the STOP s instruction (clock
stop status).
Therefore, the current consumption of the device is decreased to the minimum value of 10 µA.
Specify “0000B” as operand “s” of the STOP s instruction.
The STOP s instruction is valid only while the CE pin is low.
It is executed as a no-operation (NOP) instruction even when executed while the CE pin is high.
In other words, the STOP s instruction must be executed while the CE pin is low.
The clock stop status is released by raising the level of the CE pin from low to high (CE reset).
The following subsections 21.5.1 through 21.5.3 explain the clock stop status, how to release the clock stop
status, and notes on using the clock stop instruction.
21.5.1 Clock stop status
Because the crystal oscillator is stopped in the clock stop status, all the device operations, such as those
of the CPU and peripheral hardware, are stopped.
For the operations of the CPU and peripheral hardware, refer to 21.6 Device Operations in Halt and Clock
Stop Status.
The power failure detector does not operate in the clock stop status even if the supply voltage VDD of the device
is lowered to 2.3 V. Therefore, the data memory can be backed up at a low voltage. For details of the power
failure detector, refer to 22. RESET.
21.5.2 Releasing clock stop status
The clock stop status is released either by raising the level of the CE pin from low to high (CE reset), or by
lowering the supply voltage VDD of the device to 2.3 V or less once, and then increasing it to 3.5 V (power-on
reset).
Figures 21-4 and 21-5 show how the clock stop is released on CE reset and power-on reset respectively.
If the clock stop status is released by power-on reset, the power failure detector operates.
For details of power-on reset, refer to 22.4 Power-on Reset.
262
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 21-4. Releasing Clock Stop Status by CE Reset
5 V
V
DD
0 V
H
CE pin
L
H
XOUT pin
L
About 50 ms
Program starts from address 0 (CE reset)
STOP s instruction
Operation is as follows if clock stop instruction is not used
5 V
VDD
0 V
H
CE pin
L
H
XOUT pin
L
0 - tSET
Program starts from address 0 (CE reset)
CE reset is effected in synchronization with setting of
basic timer 0 carry FF after CE pin has gone high
Figure 21-5. Releasing Clock Stop Status by Power-on Reset
5 V
VDD
2.3 V
0 V
H
CE pin
L
H
XOUT pin
L
About 50 ms
STOP s instruction
Program starts from address 0
(Power-on reset)
Operation is as follows if clock stop instruction is not used
3.5 V
5 V
VDD
0 V
H
CE pin
L
H
XOUT pin
L
About 50 ms
Program starts from address 0
(Power-on reset)
Oscillation stops
263
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.5.3 Notes on using clock stop instruction
The clock stop (STOP s) instruction is valid only while the CE pin is low.
Therefore, processing to be performed if the CE pin happens to be high must be taken into consideration.
Take the following program as an example.
Example
XTAL
DAT
0000B ; Symbol definition of clock stop condition
CEJDG:
; <1>
SKF1
BR
CE
; Embedded macro
; Detects input level of CE pin
; Branches to main processing if CE = high
MAIN
Processing A
; Processing of CE = low
; <2>
; <3>
STOP
BR
XTAL
; Clock stop
$ – 1
MAIN:
Main processing
BR CEJDG
In the above example, the status of the CE pin is detected in <1>. If the CE pin is low, processing A is
performed and then the clock stop instruction “STOP XTAL” in <2> is executed.
If the CE pin goes high while the STOP XTAL instruction in <2> is executed, however, the STOP XTAL
instruction is treated as a no-operation (NOP) instruction.
Should branch instruction “BR$ – 1” in <3> be missing at this time, the program would execute the main
processing, causing malfunctioning.
Therefore, either a branch instruction must be inserted as in <3>, or the program must be designed in the
manner that malfunctioning does not occur even if the main processing is executed.
If a branch instruction is used as in <3>, CE reset is executed in synchronization with the next setting of the
timer carry FF even while the CE pin is high.
5 V
V
DD
0 V
H
CE pin
L
Main
processing
Processing A
Program starts from address 0
in synchronization with setting of
basic timer 0 carry FF (CE reset).
<1> <1> <1> <2> STOP XTAL is treated as
Detection
NOP instruction because
CE pin is high.
of CE pin
264
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
21.6 Device Operations in Halt and Clock Stop Status
Table 21-1 shows the operations of the CPU and peripheral hardware in the halt status and clock stop status.
As shown in this table, all the peripheral hardware units continue the normal operation in the halt status,
except that instruction execution is stopped.
All the peripheral hardware units stop operation in the clock stop status.
The control registers that control the operations of the peripheral hardware units operate normally in the halt
status (i.e., are not initialized), but are initialized to specific values in the clock stop status (as soon as the STOP
s instruction has been executed).
To put in another way, the peripheral hardware units continue the operations set by the control registers in
the halt status, and operate in accordance with the control registers that are initialized to specific values in the
clock stop status.
For the values to which the control registers are initialized, refer to 8. REGISTER FILE (RF).
The following shows an example.
Example When the P0A0/SI1 pin of port 0A is specified as an output port pin, and the P0A1/SO1 and P0A2/SCK1
pins are used for the serial interface
HLTINT
XTAL
DAT
DAT
1000B
0000B
INITFLG P0ABI02, P0ABI01, P0ABI00
; <1>
SET3
P0A2, P0A1, P0A0
; <2>
INITFLG SI01HIZ, SI01CK1, SI01CK0
CLR1
SET1
EI
IRQSI01
IPSI01
; <3>
SET1
; <4>
HALT
; <5>
STOP
SI01TS
HLTINT
XTAL
In the above example, the P0A2 through P0A0 pins output a high level in <1>, the condition of serial interface
1 is set in <2>, and serial communication is started in <3>.
When the HALT instruction is executed in <4>, serial communication continues and the halt status is released
when the interrupt by serial interface 1 is acknowledged.
If the STOP instruction in <5> is executed instead of the HALT instruction in <4>, the contents of all the control
registers set in <1>, <2>, and <3> are initialized. Consequently, serial communication is stopped, and all the
pins of port 0A are set in the general-purpose input port mode.
265
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 21-1. Device Operations in Halt Status and Clock Stop Status
Peripheral Hardware
Status
CE Pin = High
CE Pin = Low
Halt
Clock Stop
Halt
Clock Stop
Program counter
Stops at address of
HALT instruction
STOP instruction is
invalid (NOP)
Stops at address of
HALT instruction
Initialized to 0000H
and stops
System register
Peripheral register
Control register
Timer
Retained
Retained
InitializedNote
Retained
Retained
Retained
Retained
Retained
InitializedNote
Normal operation
Normal operation
Disabled
Stops operation
Disabled
PLL frequency synthesizer Normal operation
A/D converter
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Normal operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
D/A converter
BEEP output
Serial interface
Frequency counter
LCD controller/driver
Key source controller/
decoder
General-purpose I/O port
Normal operation
Normal operation
Normal operation
Normal operation
Input port
Input port
Retained
General-purpose input port Normal operation
General-purpose output
port
Normal operation
Note For the values to which these registers are initialized, refer to 5. SYSTEM REGISTER (SYSREG) and 8.
REGISTER FILE (RF).
21.7 Notes on Processing Each Pin in Halt and Clock Stop Status
The halt status is used to reduce the current consumption, when only the watch operates, for example.
The clock stop function is used to reduce the current consumption when only the contents of the data memory
are to be retained.
Therefore, the current consumption must be reduced as much as possible in the halt and clock stop statuses.
At this time, the current consumption may increase depending on the status of each pin, and therefore the
points shown in Table 21-2 must be noted.
266
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 21-2. Notes on Status of Each Pin in Halt and Clock Stop Statuses (1/2)
Pin Function
Pin Symbol
Status of Each Pin and Notes on Processing
Halt
Clock Stop
General-
Port 0A
Port 0B
P0A2/SCK1
P0A1/SO1
P0A0/SI1
P0B3/FCG1
P0B2/FCG0
P0B1/BEEP1
P0B0/BEEP0
P1A2
Previous status before halt status is
set is retained as is.
Allthesepinsaresetingeneral-purpose
input port mode.
purpose
I/O port
(1) In output mode
All input ports, except port 1D (P1D3
to P1D0), are designed to prevent
increase in current consumption due
to noise even if they are externally
floated. Port 1D (P1D3 to P1D0) must
be externally pulled down or up so
that current consumption does not
increase due to noise.
Current consumption increases
ifthesepinsareexternallypulled
downwhiletheyoutputhighlevel,
orexternallypulledupwhilethey
output low level.
PayattentiontoN-chopen-drain
output pins (P0C3 to P0C0/
PWM0).
Port 1A
Port 1D
P1A1
Port 0D (P0D3/K3 to P0D0/K0) is
internally pulled down.
(2) In input mode
P1A0
(exceptP0B3/FCG1, P0B2/FCG0,
P1B3/FMIFC, P1B2/AMIFC)
P1D3
P1D2
P1D1
P1D0
Current consumption increases
due to noise if these pins are
floated.
General-
purpose
input port
Port 0D
Port 1B
Port 0C
Port 1C
P0D3/K3
(3) Port 0D (P0D3/K3 to P0D0/K0)
P0D2/K2
Current consumption increases
ifthesepinsareexternallypulled
up because they have pull-down
resistors.
P0D1/K1
P0D0/K0
P1B3/FMIFC
P1B2/AMIFC
P1B1/ADC1
P1B0/ADC0
(4) P0B3/FCG1, P0B2/FCG0, P1B3/
FMIFC, P1B2/AMIFC
Current consumption increases
when P0B3/FCG1, P0B2/FCG0,
P1B3/FMIFC, P1B2/AMIFC pins
are used for IF counter because
internal amplifier operates.
Thesepinsaresetingeneral-purpose
output port mode.
General-
purpose
P0C3
P0C2
output port
Because IF counter is not
automatically disabled even if
CE pin goes low, it must be
initialized by program as
necessary.
Output contents are retained as is.
P0C1/PWM1
P0C0/PMW0
P1C3
Therefore, current consumption
increases if these pins are externally
pulled down while they output high
level, or pulled up while they output
low level.
P1C2
P0B3/FCG1, P0B2/FCG0, P1B3/
FMIFC, P1B2/AMIFC are
designed to prevent increase in
currentconsumptionduetonoise
even if they are set in general
purpose input port mode and
floated.
P1C1
P1C0
Interrupt
INT
Current consumption increase due to external noise if this pin is floated.
267
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Table 21-2. Notes on Status of Each Pin in Halt and Clock Stop Statuses (2/2)
Pin Function
Pin Symbol
Status of Each Pin and Notes on Processing
Halt
Clock Stop
All pins are set in LCD segment signal
output mode and output low level
(display off).
Sameasabovegeneral-purposeoutput
ports applies if these pins are used in
general-purpose output port mode.
LCD segment
LCD19/P2H0
LCD18/P2G0
LCD17/P2F0
LCD16/P2E0
LCD15/KS15/PYA15
|
If they output key source signals,
currentconsumptionincreasesviaport
0D (with pull-down resistor) if there is
switch that is always ON such as
transistor switch and if “1” is output as
key source data.
LCD0/KS0/PYA0
PLL frequency
synthesizer
VCOL
VCOH
EO
Currentconsumptionincreasesduring PLL is disabled.
PLL operation.
These pins are as follows.
These pins are as follows when PLL
is disabled.
VCOL and VCOH: Internally pulled
down
VCOL and VCOH: Internally pulled
down
EO:
Floated
EO:
Floated
PLL is automatically disabled when
CE pin goes low.
Crystal oscillator
XIN
Current consumption changes due to
oscillation waveform of crystal
oscillator.
XIN pin is internally pulled down, and
XOUT pin outputs high level.
XOUT
Current consumption decreases as
oscillation amplitude increases.
Because oscillation amplitude is
influenced by crystal resonator and
load capacitor used, evaluation must
be performed.
268
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22. RESET
The reset function is used to initialize the device operation.
22.1 Configuration of Reset Block
Figure 22-1 shows the configuration of the reset block.
The device is reset in two ways: by applying supply voltage VDD (power-on reset or VDD reset) and by using
the CE pin (CE reset).
The power-on reset block consists of a voltage detector that detects a voltage input to the VDD pin, a power
failure detector, and a reset controller.
The CE reset block consists of a circuit that detects the rising of a signal input to the CE pin, and a reset
controller.
Figure 22-1. Configuration of Reset Block
Power failure detection block
XOUT
Timer FF block
Selector
X
IN
Divider
BTM0CY flag read
R
Q
Basic timer 0 carry
STOP s
instruction
S
Basic timer 0 carry
disable FF
Reset signal
IRES
Forced halt by basic
timer 0 carry
Power-on-clear signal (POC)
Voltage
detector
V
DD
RES
Control register
System register
Stack
Reset controller
STOP instruction
Rising
detector
RESET
CE
Program counter
269
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.2 Reset Function
Power-on reset is effected when supply voltage VDD rises from a specific level, and CE reset is effected when
the CE pin goes high.
Power-on reset initializes the program counter, stack, system register, and control registers, and executes
the program from address 0000H.
CE reset initializes the program counter, stack, system register, and some control registers, and executes
the program from address 0000H.
The major differences between power-on reset and CE reset are the control registers that are initialized and
the operation of the power failure detector that is explained in 22.6.
Both power-on reset and CE reset are controlled by the reset signals IRES, RES, and RESET output from
the reset controller shown in Figure 22-1.
Table 22-1 shows the relationship between the IRES, RES, and RESET signals, and power-on reset, and CE
reset.
The reset controller also operates when the clock stop instruction (STOP s) explained in 21. STANDBY is
executed.
The following sections 22.3 and 22.4 explain CE reset and power-on reset respectively.
Section 22.5 explains the relationship between CE reset and power-on reset.
Table 22-1. Relationship Between Internal Reset Signals and Each Reset Operation
Internal Reset Signal
Output Signal
Control Operation by Each Reset Signal
CE Reset
Power-on
Reset
Clock Stop
IRES
×
Forcibly sets device in halt status.
Halt status is released when basic timer 0 carry
FF is set.
RES
×
Initializes some control registers.
RESET
Initializes program counter, stack, system
register, and some control registers.
270
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.3 CE Reset
CE reset is effected when the CE pin goes high.
When the CE pin goes high, the RESET signal is output in synchronization with the rising edge of the next
basic timer 0 carry FF setting pulse, and the device is reset.
When CE reset is effected, the RESET signal initializes the program counter, stack, system register, and
some control registers, and the program is executed starting from address 0000H.
For the value to which each of the above registers is initialized, refer to the description of each register.
The operation of CE reset differs depending on whether the clock stop instruction is used.
The differences in operation are explained in the following subsections 22.3.1 and 22.3.2.
Subsection 22.3.3 explains the points to be noted on using CE reset.
22.3.1 CE reset when clock stop (STOP s) instruction is not used
Figure 22-2 shows the operation of CE reset when the clock stop (STOP s) instruction is not used.
When the STOP s instruction is not used, the basic timer clock select register of the control registers is not
initialized.
After the CE pin has gone high, therefore, the RESET signal is output at the rising edge of the basic timer
0 carry FF setting pulse (1 ms, 5 ms, 100 ms, 250 ms) selected at that time, and the device is reset.
Figure 22-2. CE Reset Operation When Clock Stop Instruction Is Not Used
5 V
V
DD
0 V
H
CE
L
H
X
OUT
L
H
Basic timer 0 carry
FF setting pulse
L
H
IRES
RES
L
H
L
H
RESET
Normal
L
Normal operation
operation
CE reset is effected at rising of basic
timer 0 carry FF setting pulse.
If selected basic timer 0 carry FF setting time is tSET
,
this period “t” is 0 < t < tSET depending on timing of rising of CE pin.
During this period, program operation continues.
271
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.3.2 CE reset when clock stop (STOP s) instruction is used
Figure 22-3 shows the operation of CE reset when the clock stop (STOP s) instruction is used.
When the STOP s instruction is used, the IRES, RES, and RESET signals are output as soon as the STOP
s instruction has been executed.
At this time, the basic timer clock select register of the control registers is initialized to 0000B by the RES
signal, the basic timer 0 carry FF setting signal is set to 100 ms.
Because the IRES signal is output while the CE pin is low, the halt status, which can be released by the basic
timer 0 carry, is forcibly set.
However, the device stops operation because the clock is stopped.
When the CE pin goes high, the clock stop status is released, and oscillation starts.
Because the halt status that can be released by the basic timer 0 carry is set at this time by the IRES signal,
the program starts from address 0 when the CE pin goes high and then the basic timer 0 carry FF setting pulse
rises.
Because the basic timer 0 carry FF setting pulse is initialized to 100 ms, CE reset is effected 50 ms after the
CE pin has gone high.
Figure 22-3. CE Reset Operation When Clock Stop Instruction Is Used
5 V
VDD
0 V
H
CE
L
H
XOUT
L
H
Basic timer 0 carry
FF setting pulse
L
H
IRES
L
H
RES
L
H
RESET
L
Normal operation
Clock stop status
Halt status
50 ms
Stop s instruction Clock oscillation starts
Stop released
CE reset
Program starts from address 0.
22.3.3 Notes on CE reset
Because CE reset is effected regardless of the instruction under execution, the following points <1> and <2>
must be noted.
(1) Time to execute timer processing such as watch
When developing a watch program by using basic timer 0 or basic timer 1, the processing of that program
must be completed within a specific time.
For details, refer to 12.2.6 Notes on using basic timer 0 and 12.3.5 Notes on using basic timer 1.
(2) Processing of data and flag used for program
Care must be exercised in rewriting the contents of data or a flag that cannot be processed with one
instruction and whose contents must not change even when CE reset is effected, such as a security code.
This is explained in detail using the following examples.
272
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example 1.
R1
MEM
MEM
MEM
MEM
MEM
MEM
0.01H
0.02H
0.03H
0.04H
0.11H
0.12H
; First digit of key input data of security code
R2
R3
R4
M1
M2
; Second digit of key input data of security code
; First digit data for changing security code
; Second digit data for changing security code
; First digit of current security code
; Second digit of current security code
START:
Key input processing
R1 ← contents of key A ; Security code input wait mode
R2 ← contents of key B ; Substitutes contents of pressed key into R1 and R2.
SET2
SUB
SUB
SKT1
BR
CMP, Z ;<1> ; Compares security code with input data.
R1, M1
R2, M2
Z
ERROR
; Input data is different from security code.
MAIN:
Key input processing
R3 ← contents of key C ; Security code rewriting mode
R4 ← contents of key D ; Substitutes contents of pressed key into R3 and R4.
ST
ST
BR
M1, R3 ;<2> ; Rewrites security code.
M2, R4 ;<3>
MAIN
ERROR:
Must not operate
Suppose the current security code is “12H” in the above program, the contents of data memory areas M1 and
M2 are “1H” and “2H”, respectively.
If CE reset is effected, the contents of the key input are compared with security code “12H” in <1>. If they
match, normal processing is performed.
If the security code is changed by the main processing, the new code is written to M1 and M2 in <2> and <3>.
Suppose the security code is changed to “34H”, “3H”, and “4H” are written to M1 and M2, respectively, in <2>
and <3>.
If a CE reset is effected at the point where <2> is executed, the program is executed from address 0000H
without <3> being executed.
Consequently, the security code is changed to “32H”, making it impossible to clear the security.
In this case, use the program shown in Example 2 below.
273
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example 2.
R1
MEM
MEM
MEM
MEM
MEM
MEM
0.01H
0.02H
0.03H
0.04H
0.11H
0.12H
0.13H.0
; First digit of key input data of security code
R2
R3
R4
M1
M2
; Second digit of key input data of security code
; First digit data for changing security code
; Second digit data for changing security code
; First digit of current security code
; Second digit of current security code
; “1” while security code is changed
CHANGE FLG
START:
Key input processing
R1 ← contents of key A ; Security code input wait mode
R2 ← contents of key B ; Substitutes contents of pressed key into R1 and R2.
SKT1
CHANGE ;<4> ; If CHANGE flag is “1”
BR
SECURITY_CHK
ST
M1, R3
M2, R4
CHANGE
; rewrites M1 and M2.
ST
CLR1
SECURITY_CHK:
SET2
CMP, Z ;<1> ; Compares security code with input data.
SUB
R1, M1
R2, M2
Z
SUB
SKT1
BR
ERROR
; Input data is different from security code.
MAIN:
Key input processing
R3 ← contents of key C ; Security code rewriting mode
R4 ← contents of key D ; Substitutes contents of pressed key into R3 and R4.
SET1
CHANGE ;<5> ; Until security code is changed
; Sets CHANGE flag to 1.
ST
M1, R3 ;<2> ; Rewrites security code
M2, R4 ;<3>
ST
CLR1
CHANGE
; When security code has been changed, sets
; CHANGE flag to 0.
BR
MAIN
ERROR:
Must not operate
In the program in Example 2, the CHANGE flag is set to 1 in <5> before the security code is changed in <2>
and <3>.
Therefore, the security code is rewritten in <4> even if a CE reset is effected before <3> is executed.
274
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.4 Power-on Reset
Power-on reset is effected when the supply voltage VDD of the device rises from a specific level (called power-
on-clear voltage).
If the supply voltage VDD is lower than the power-on-clear voltage, a power-on clear signal (POC) is output
from the voltage detector shown in Figure 22-1.
When the power-on-clear voltage is output, the crystal oscillator is stopped, and the device operation is
stopped.
While the power-on-clear signal is output, the IRES, RES, and RESET signals are output.
If supply voltage VDD exceeds the power-on-clear voltage, the power-on-clear signal is cleared, and crystal
oscillation is started. At the same time, the IRES, RES, and RESET signals are also cleared.
At this time, the halt status is set to be released by the basic timer 0 carry due to the IRES signal. Therefore,
power-on reset is effected at the rising edge of the next basic timer 0 carry FF setting signal.
The basic timer 0 carry FF setting signal is initialized to 100 ms by the RESET signal. For this reason, reset
is effected 50 ms after supply voltage VDD has exceeded the power-on-clear voltage, and the program is started
from address 0.
This operation is illustrated in Figure 22-4.
The program counter, stack, system register, and control registers are initialized as soon as the power-on-
clear signal has been output.
For the value to which each of the above registers is to be initialized, refer to the description of each register.
The power-on-clear voltage is 3.5 V (rated value) during normal operation, and 2.3 V (rated value) in the clock
stop status.
The operations performed when the power-on-clear voltage is at the respective levels are explained in 22.4.1
and 22.4.2.
The operation to be performed if the supply voltage VDD rises from 0 V is explained in 22.4.3.
Figure 22-4. Operation of Power-on Reset
5 V
VDD
Power-on clear voltage
0 V
H
CE
L
H
XOUT
L
H
Basic timer 0 carry
FF setting pulse
L
H
Power-on clear signal
L
H
IRES
L
H
RES
L
H
RESET
L
Normal operation
Device operation stops Halt status
50 ms
Power-on clear released Power-on reset
Oscillation starts
Program starts
from address 0.
275
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.4.1 Power-on reset during normal operation
Figure 22-5 (a) shows the operation.
As shown in the figure, the power-on-clear signal is output and the device operation stops regardless of the
input level of the CE pin, if the supply voltage VDD drops below 3.5 V.
If VDD rises beyond 3.5 V again, the program starts from address 0000H after 50 ms of halt status.
“Normal operation” is when the clock stop instruction is not used and includes the halt status that is set by
the halt instruction.
22.4.2 Power-on reset in clock stop status
Figure 22-5 (b) shows the operation.
As shown in the figure, the power-on-clear signal is output and the device operation stops if supply voltage
VDD drops below 2.3 V.
However, it seems as if the device operation has not changed because the device is in the clock stop status.
When supply voltage VDD rises beyond 3.5 V next time, the program starts from address 0000H after a 50
ms halt.
22.4.3 Power-on reset when supply voltage VDD rises from 0 V
Figure 22-5 (c) shows the operation.
As shown in the figure, the power-on-clear signal is output until supply voltage VDD rises from 0 V to 3.5 V.
When VDD rises beyond the power-on-clear voltage, the crystal oscillator starts operating, and the program
starts from address 0000H after a 50 ms halt.
276
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 22-5. Power-on Reset and Supply Voltage VDD
(a) During normal operation (including halt status)
5 V
3.5 V
Power-on-clear voltage
V
DD
0 V
H
CE
L
H
X
OUT
L
H
Power-on-
clear signal
L
Normal operation
Device operation stops Halt status
50 ms
Power-on clear released
Oscillation starts
Power-on reset
Program starts from address 0.
(b) In clock stop status
5 V
3.5 V
Power-on-clear voltage
2.3 V
VDD
0 V
H
CE
L
H
XOUT
L
H
Power-on-
clear signal
L
Normal operation
Clock stop
Device operation stops Halt status
50 ms
STOP s instruction
Power-on clear released
Oscillation starts
Power-on reset
Program starts from address 0.
(c) When supply voltage VDD rises from 0 V
5 V
Power-on-clear voltage
3.5 V
V
DD
0 V
H
CE
L
H
X
OUT
L
H
Power-on-
clear signal
L
Device operation stops Halt status
50 ms
Power-on clear released
Oscillation starts
Power-on reset
Program starts from address 0.
277
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.5 Relationship Between CE Reset and Power-on Reset
There is a possibility that power-on reset and CE reset are effected at the same time when power is first
applied.
The reset operations performed at this time are explained in 22.5.1 through 22.5.3.
22.5.4 explains the points to be noted in raising supply voltage VDD.
22.5.1 If VDD pin and CE pin rise simultaneously
Figure 22-6 (a) shows the operation.
At this time, the program starts from address 0000H due to power-on reset.
22.5.2 If CE pin rises in forced halt status of power-on reset
Figure 22-6 (b) shows the operation.
At this time, the program starts from address 0000H due to power-on reset in the same manner as in 22.5.1.
22.5.3 If CE pin rises after power-on reset
Figure 22-6 (c) shows the operation.
At this time, the program starts from address 0000H due to power-on reset, and the program starts from
address 0000H again at the rising of the next basic timer 0 carry FF setting signal because of CE reset.
278
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 22-6. Relationship Between Power-on Reset and CE Reset
(a) If VDD and CE pins rise simultaneously
5 V
3.5 V
Power-on-clear voltage
V
DD
0 V
H
L
CE
H
Basic timer 0 carry
FF setting pulse
L
Operation Halt status
stops 50 ms
Normal operation
Power-on reset
Program starts
(b) If CE pin rises in halt status
5 V
Power-on-clear voltage
3.5 V
V
DD
0 V
H
L
CE
H
Basic timer 0 carry
FF setting pulse
L
Operation
stops
Halt status
50 ms
Normal operation
Power-on reset
Program starts
(c) If CE pin rises after power-on reset
5 V
Power-on-clear voltage
3.5 V
VDD
0 V
H
L
CE
H
Basic timer 0 carry
FF setting pulse
L
Operation
stops
Halt status
50 ms
Normal operation
Power-on reset
Program starts
CE reset
Program starts
279
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.5.4 Notes on raising supply voltage VDD
When raising supply voltage VDD, keep in mind the following points (1) and (2).
(1) When raising supply voltage VDD from power-on clear voltage
It is necessary to raise supply voltage VDD to higher than 3.5 V at least once.
This is illustrated in Figure 22-7.
Suppose, for example, only a voltage less than 3.5 V is applied on application of VDD with a program that
backs up VDD at 2.3 V by using the clock stop instruction, as shown in Figure 22-7, the power-on-clear
signal is continuously output, and the program does not operate.
Because the output ports of the device output undefined values, the current consumption increases in
some cases.
If the device is backed up by batteries, therefore, the back-up time is substantially shortened.
Figure 22-7. Notes on Raising VDD
5 V
3.5 V
Power-on-
clear voltage
V
DD
2.3 V
0 V
H
CE
L
H
XOUT
L
H
Basic timer 0 carry
FF setting pulse
L
H
Power-on-
clear signal
Opera-
tion
stops
L
Halt status
50 ms
Operation stops
Normal operation
Back up
Current consumption may increase
during this period because
output ports are undefined.
Initialization is
executed during
this period, and
then clock stop
instruction is
executed.
Power-on reset
Program starts
STOP s
instruction
280
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
(2) Restoring from clock stop status
To restore the device from the back-up status while supply voltage VDD is backed up at 2.3 V by using
the clock stop instruction, VDD must be raised to 3.5 V or higher within 50 ms after the CE pin has gone
high.
As shown in Figure 22-8, the device is restored from the clock stop status by means of CE reset. Because
the power-on clear voltage is changed to 3.5 V 50 ms after the CE pin has gone high, power-on reset
is effected unless VDD is 3.5 V or higher at this point.
The same applies when VDD is lowered.
Figure 22-8. Restoring from Clock Stop Status
5 V
3.5 V
2.3 V
Power-on-
clear voltage
V
DD
0 V
H
CE
L
H
XOUT
L
H
Basic timer 0 carry
FF setting pulse
L
H
Power-on-
clear signal
L
Processing
where
CE = low
Back up by clock
stop instruction
Halt status
50 ms
Normal operation
Back up
CE reset
Program starts
STOP s
instruction
Power-on clear voltage is
Power-on clear voltage is
changed to 3.5 V at this point.
Therefore, VDD must rise to 3.5 V
or higher before this point.
changed to 2.3 V at this point.
Therefore, VDD must not fall
below 3.5 V before this point.
281
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.6 Power Failure Detection
Power failure detection is used to judge whether power-on reset by application of supply voltage VDD, or CE
reset has been effected when the device is reset, as shown in Figure 22-9.
Because the contents of the data memory and ports are undefined on power application, these contents are
initialized by means of power failure detection.
A power failure can be detected in two ways: by using the power failure detector to detect the BTM0CY flag,
and by detecting the contents of the data memory (RAM judgement).
22.6.1 and 22.6.2 explain how a power failure is detected by using the power failure detector and BTM0CY
flag.
22.6.3 and 22.6.4 explain how a power failure is detected by RAM judgement method.
Figure 22-9. Power Failure Detection Flow Chart
Program starts
Power failure
Power
failure detection
Not power
failure
Initializes data
memory and
output ports
22.6.1 Power failure detector
The power failure detector consists of a voltage detector, a basic timer 0 carry disable flip-flop that is set by
the output (power-on-clear signal) of the voltage detector, and a basic timer 0 carry, as shown in Figure 22-1.
The basic timer 0 carry disable FF is set to 1 by the power-on-clear signal, and is reset to 0 when an instruction
that reads the BTM0CY flag is executed.
When the basic timer 0 carry disable FF is set to 1, the BTM0CY flag is not set to 1.
When the power-on-clear signal is output (at power-on reset), the program is started with the BTM0CY flag
reset, and the BTM0CY flag is disabled from being set until an instruction that reads the BTM0CY flag is
executed.
Once the instruction that reads the BTM0CY flag has been executed, the BTM0CY flag is set each time the
basic timer 0 carry FF setting pulses has risen. It can be judged whether power-on reset (power failure) or CE
reset (not power failure) has been effected by detecting the contents of the BTM0CY flag when the device is
reset. Power-on reset has been effected if the BTM0CY flag is reset to 0; CE reset has been effected if it is
set to 1.
The voltage at which a power failure can be detected is the same as the voltage at which power-on reset is
effected, or VDD = 3.5 V during crystal oscillation, or VDD = 2.3 V in the clock stop status.
Figure 22-10 shows the transition of the status of the BTM0CY flag.
Figures 22-11 and 22-10 show the timing chart and the operation of the BTM0CY flag.
282
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 22-10. Status Transition of BTM0CY Flag
CE = low
CE = any
CE = high
<1>
V
DD = low
Operation stops
V
DD = L → 3.5 V
<2>
Crystal oscillation starts
Forced halt (approx. 50 ms)
<3>
Power-on reset
CE = L CE = H
<6>
Disables setting of
BTM0CY flag.
<4>
<7>
<5>
STOP 0
CE = H → L
CE = L → H
CE = L → H
BTM0CY = 0
Normal
operation
Normal
operation
<8>
Clock stop
CE reset
Normal operation
Basic timer 0 carry
FF setting pulse rises.
CE reset wait
<9>
Crystal oscillation starts
Forced halt (50 ms)
<10>
<11>
SKT1 BTM0CY or
SKF1 BTM0CY
SKT1 BTM0CY or
SKF1 BTM0CY
<12>
<13>
<14>
<15>
STOP 0
CE = H → L
CE = L → H
CE = L → H
BTM0CY = 1
Normal
operation
Normal
operation
Clock stop
CE reset
<16>
Normal operation
CE reset wait
Basic timer 0 carry
FF setting pulse rises.
Enables setting
of BTM0CY flag
<17>
Crystal oscillation starts
Forced halt (50 ms)
283
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Figure 22-11. Operation of BTM0CY Flag
(a) When BTM0CY flag never detected (SKT1 BTM0CY or SKF1 BTM0CY is not executed)
5 V
V
DD
0 V
H
CE
L
H
Basic timer 0 carry
FF setting pulse
L
H
BTM0CY
L
Operation in
Figure 22-10
<1> <2> <6>
<3>
<5>
<8>
<7>
<6>
<5>
<4>
<9>
<7>
<6>
<1>
Timer time
changed
STOP
0000 B
(b) When detecting power failure by BTM0CY flag
5 V
V
DD
0 V
H
CE
L
H
Basic timer 0 carry
FF setting pulse
L
H
BTM0CY
L
SKTI instruction
Operation in
Figure 22-10
<13>
<16>
<14>
<13>
<12>
<17>
<14>
<1>
<1> <2> <6><14>
<15>
<15>
<3>
Timer time
changed
<11>
STOP
0000 B
BTM0CY = 0
Power failure
BTM0CY = 1
No power failure
BTM0CY = 1
No power failure
284
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.6.2 Notes on detecting power failure by BTM0CY flag
The following points must be noted when using the BTM0CY flag for watch counting.
(1) Updating watch
When developing a watch program by using the basic timer 0 carry, the watch must be updated after a
power failure has been detected.
This is because counting of the watch is skipped once because the BTM0CY flag is reset to 0 when the
BTM0CY flag is read on detection of a power failure.
(2) Watch updating processing time
The processing to update the watch must be completed before the next basic timer 0 carry FF setting
pulse rises.
This is because, if the CE pin goes high during the watch updating processing, CE reset is effected without
the watch updating processing completed.
For further information on (1) and (2) above, refer to 12.2.6 (3) Correction of basic timer 0 carry on
CE reset.
When detecting a power failure, the following points must be noted.
(3) Timing of power failure detection
To count the watch by using the BTM0CY flag, the BTM0CY flag must be read to detect a power failure
within the time since the program has started from address 0000H until the next basic timer 0 carry FF
setting pulse rises.
For example if the basic timer 0 carry FF setting time is set to 5 ms, and a power failure is detected 6
ms after the program has been started, the BTM0CY flag is overlooked once.
For details, refer to 12.2.6 (3) Correction of basic timer 0 carry on CE reset.
Power failure detection and initial processing must be completed within the basic timer 0 carry FF setting
time as shown in the following example.
This is because, if the CE pin goes high and CE reset is effected during power failure detection processing
and initial processing, these processing may be stopped in midway, and thus problems may occur.
To change the basic timer 0 carry FF setting time by the initial processing, the instruction that changes
the time must be executed at the end of the initial processing, and the instruction must be one instruction.
This is because the initial processing may not be completely executed because of CE reset if the basic
timer 0 carry FF setting time is changed before the initial processing is executed, as shown in the following
example.
285
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example
START:
; Program address 0000H
;<1>
Processing on reset
;<2>
SKT1
BTM0CY
; Power failure detection
BR
INITIAL
BACKUP:
;<3>
Watch updating
BR
MAIN
INITIAL:
;<4>
Initial processing
;<5>
INITFLG BTM0CK1, NOT BTM0CK0
; Embedded macro
Sets basic timer 0 carry FF setting time to 5 ms
;
MAIN:
Main processing
SKT1
BTM0CY
MAIN
BR
Watch updating
BR
MAIN
286
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example of operation
5 V
V
DD
0 V
H
L
CE
5 ms pulse
50 ms
5 ms
<4>
50 ms pulse
50 ms
H
L
Basic timer 0 carry
FF setting pulse
<1>
<1>
<3>
<2> Power failure detection
<2> Power failure detection
If processing time of <1> + <3>
If processing time of <1> + <4> is
longer than 100 ms, CE reset is effected is too long, CE reset is effected.
in middle of processing <4>.
CE reset
< 5 >
CE reset
CE reset may be effected immediately depending
on when basic timer 0 carry FF setting time is changed.
Therefore, if <5> is executed before <4>,
power failure processing <4> may not be
completely executed.
22.6.3 Power failure detection by RAM judgement method
The RAM judgement method is to detect a power failure by judging whether the contents of the data memory
at a specific address are the specified value.
An example of a program that detects a power failure by the RAM judgement method is shown below.
The RAM judgement method detects a power failure by comparing an undefined value with the specified value
because the contents of the data memory are undefined on application of supply voltage VDD.
Therefore, there is a possibility that a wrong judgment may be made as explained in 22.6.4 Notes on
detecting power failure by RAM judgement method.
287
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Example Program to detect power failure by RAM judgement method
M012
MEM
MEM
MEM
MEM
MEM
MEM
DAT
DAT
DAT
DAT
DAT
DAT
0.12H
0.34H
0.56H
1.07H
1.28H
1.6FH
1010B
0101B
0110B
1001B
1100B
0011B
M034
M056
M107
M128
M16F
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
START:
SET2
SUB
CMP, Z
M012, #DATA0
M034, #DATA1
M056, #DATA2
; If M012 = DATA0 and
; M034 = DATA1 and
; M056 = DATA2 and
SUB
SUB
BANK1
SUB
M107, #DATA3
M128, #DATA4
M16F, #DATA5
; M107 = DATA3 and
; M128 = DATA4 and
; M16F = DATA5,
SUB
SUB
BANK0
SKF1
BR
Z
BACKUP
; branches to BACKUP
;INITIAL:
Initial processing
MOV
M012, #DATA0
M034, #DATA1
M056, #DATA2
MOV
MOV
BANK1
MOV
MOV
MOV
BR
M107, #DATA3
M128, #DATA4
M16F, #DATA5
MAIN
BACKUP:
MAIN:
Backup processing
Main processing
288
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
22.6.4 Notes on detecting power failure by RAM judgement method
The value of the data memory on application of supply voltage VDD is basically undefined, and therefore, the
following points (1) and (2) must be noted.
(1) Data to be compared
Where the number of bits of the data memory to be compared by the RAM judgement method is “n bits”,
the probability at which the value of the data memory matches the value to be compared on application
of VDD is (1/2)n.
This means that backup is judged at a probability of (1/2)n when a power failure is detected by the RAM
judgement method.
To lower this probability, as many bits as possible must be compared.
Because the contents of the data memory on application of VDD are likely to be the same value such as
“0000B” and “1111B”, it is recommended to mix “0” and “1” as data to be compared, such a “1010B” and
“0110B” to reduce the possibility of a wrong judgment.
(2) Notes on program
If VDD rises from the level at which the data memory contents may be destroyed as shown in Figure 22-
12, and even if the value of the data memory area to be compared is normal, the values of the other data
memory areas may be destroyed.
This is judged as backup if a power failure is detected by the RAM judgement method. Therefore,
consideration must be given so that the program does not hang up even if the contents of the data memory
are destroyed.
Figure 22-12. VDD and Destruction of Data Memory Contents
5 V
V
DD
Data memory destruction start voltage
0 V
Data memory
Data memory for RAM judgement (normal)
Values of data memory areas not used for RAM judgement may be destroyed.
289
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
23. INSTRUCTION SET
23.1 Outline of Instruction Set
b15
0
1
14
11
b
to b
BIN
HEX
0000
0001
0010
0011
0100
0101
0110
0111
0
1
2
3
4
5
6
7
ADD
SUB
ADDC
SUBC
AND
XOR
OR
r, m
r, m
r, m
r, m
r, m
r, m
r, m
ADD
SUB
ADDC
SUBC
AND
XOR
OR
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
m, #n4
INC
AR
INC
IX
RORC
MOVT
PUSH
POP
GET
PUT
r
DBF, @AR
AR
AR
DBF, p
p, DBF
WR, rf
rf, WR
@AR
@AR
PEEK
POKE
BR
CALL
RET
RETSK
RETI
EI
DI
STOP
HALT
NOP
s
h
1000
1001
1010
1011
1100
1101
1110
1111
8
9
LD
r, m
ST
m, r
SKE
MOV
SKNE
BR
m, #n4
SKGE
MOV
SKLT
CALL
MOV
SKT
m, #n4
m, @r
m, #n4
A
B
C
D
E
F
@r, m
m, #n4
addr (page 0)
addr (page 1)
addr (page 0)
m, #n4
BR
m, #n
SKF
m, #n
290
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
23.2 Legend
AR:
ASR:
addr:
BANK:
CMP:
CY:
DBF:
h:
Address register
Address stack register indicated by stack pointer
Program memory address (lower 11 bits)
Bank register
Compare flag
Carry flag
Data buffer
Halt release condition
INTEF:
INTR:
INTSK:
IX:
Interrupt enable flag
Register automatically saved to stack when interrupt occurs
Interrupt stack register
Index register
MP:
MPE:
m:
Data memory row address pointer
Memory pointer enable flag
Data memory address indicated by mR, mC
Data memory row address (higher)
Data memory column address (lower)
Bit position (4 bits)
mR:
mC:
n:
n4:
Immediate data (4 bits)
PAGE:
PC:
p:
Page (bit 11 of program counter)
Program counter
Peripheral address
pH:
Peripheral address (higher 3 bits)
Peripheral address (lower 4 bits)
General register column address
Register file address
pL:
r:
rf:
rfR:
Register file address (higher 3 bits)
Register file address (lower 4 bits)
Stack pointer
nfC:
SP:
s:
Stop release condition
WR:
(×):
Window register
Contents addressed by ×
291
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
23.3 Instruction Set List
Instructions Mnemonic
Operand
Operation
Instruction Code
op Code
Operand
mC
Add
ADD
ADDC
INC
r, m
(r) ← (r) + (m)
00000
10000
00010
10010
00111
00111
00001
10001
00011
10011
00110
10110
00100
10100
00101
10101
11110
11111
01001
01011
11001
11011
00111
mR
mR
mR
mR
r
m, #n4
r, m
(m) ← (m) + n4
(r) ← (r) + (m) + CY
mC
n4
r
mC
m, #n4
AR
(m) ← (m) + n4 + CY
AR ← AR + 1
mC
n4
000 1001 0000
000 1000 0000
IX
IX ← IX + 1
Subtract
SUB
SUBC
OR
r, m
(r) ← (r) – (m)
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mR
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
mC
r
m, #n4
r, m
(m) ← (m) – n4
(r) ← (r) – (m) – CY
(m) ← (m) – n4 – CY
n4
r
m, #n4
r, m
n4
r
Logical
(r) ← (r)
(m)
n4
(m)
n4
(m)
n4
operation
m, #n4
r, m
(m) ← (m)
(r) ← (r)
n4
r
AND
XOR
m, #n4
r, m
(m) ← (m)
(r) ← (r)
n4
r
m, #n4
m, #n
m, #n
m, #n4
m, #n4
m, #n4
m, #n4
r
(m) ← (m)
n4
n
Judge
SKT
CMP ← 0, if (m)
CMP ← 0, if (m)
(m) – n4, skip if zero
n = n, then skip
SKF
n = 0, then skip
n
Compare
SKE
n4
n4
n4
n4
r
SKNE
SKGE
SKLT
RORC
(m) – n4, skip if not zero
(m) – n4, skip if not borrow
(m) – n4, skip if borrow
Rotate
CY → (r) b3 → (r) b2 → (r) b1 → (r) b0
000 0111
Transfer
LD
r, m
(r) ← (m)
(m) ← (r)
01000
11000
01010
mR
mR
mR
mC
mC
mC
r
r
r
ST
m, r
MOV
@r, m
if MPE = 1: (MP, (r)) ← (m)
if MPE = 0: (BANK, mR, (r)) ← (m)
m, @r
if MPE = 1: (m) ← (MP, (r))
11010
mR
mC
r
if MPE = 0: (m) ← (BANK, mR, (r))
m, #n4
(m) ← n4
11101
00111
mR
mC
n4
MOVT
DBF, @AR
SP ← SP – 1, ASR ← PC, PC ← AR,
DBF ← (PC), PC ← ASR, SP ← SP + 1
000 0001 0000
PUSH
POP
AR
SP ← SP – 1, ASR ← AR
AR ← ASR, SP ← SP + 1
WR ← (rf)
00111
00111
00111
000 1101 0000
000 1100 0000
AR
PEEK
WR, rf
rfR
0011
rfC
292
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Instructions Mnemonic
Operand
Operation
Instruction Code
op Code
00111
00111
00111
01100
01101
00111
11100
Operand
0010
Transfer
Branch
POKE
GET
PUT
BR
rf, WR
(rf) ← WR
DBF ← (p)
(p) ← DBF
rfR
pH
pH
rfC
pL
pL
DBF, p
p, DBF
addr
1011
1010
PC10 – 0 ← addr, PAGE ← 0
PC10 – 0 ← addr, PAGE ← 1
PC ← AR
addr
@AR
addr
000 0100 0000
addr
Subroutine CALL
SP ← SP – 1, ASR ← PC
PC10 – 0 ← addr, PAGE ← 0
@AR
SP ← SP – 1, ASR ← PC
PC ← AR
00111
000 0101 000
RET
PC ← ASR, SP ← SP + 1
00111
00111
00111
00111
00111
00111
00111
00111
000 1110 0000
001 1110 0000
010 1110 0000
000 1111 0000
001 1111 0000
RETSK
RETI
PC ← ASR, SP ← SP + 1 and skip
PC ← ASR, INTR ← INTSK, SP ← SP + 1
Interrupt
Others
EI
INTEF ← 1
INTEF ← 0
STOP
DI
STOP
HALT
NOP
s
010 1111
011 1111
s
h
HALT
h
No operation
100 1111 0000
293
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
23.4 Assembler (RA17K) Embedded Macro Instructions
Legend
flag n: FLG symbol
n:
Bit number
< >:
Can be omitted
Mnemonic
SKTn
Operand
flag 1, ... flag n
flag 1, ... flag n
flag 1, ... flag n
flag 1, ... flag n
flag 1, ... flag n
Operation
if (flag 1) to (flag n) = all “1”, then skip
if (flag 1) to (flag n) = all “0”, then skip
(flag 1) to (flag n) ← 1
n
Embedded
macro
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
1 ≤ n ≤ 4
SKFn
SETn
CLRn
(flag 1) to (flag n) ← 0
NOTn
if (flag n) = “0”, then (flag n) ← 1
if (flag n) = “1”, then (flag n) ← 0
INITFLG
BANKn
<NOT> flag 1,
if description = NOT flag n, then (flag n) ←0
if description = flag n, then (flag n) ← 1
1 ≤ n ≤ 4
0 ≤ n ≤ 2
... <<NOT> flag n>
(BANK) ← n
294
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
24. RESERVED SYMBOLS
24.1 Data Buffer (DBF)
Symbol Name
DBF3
Attribute
MEM
Value
0.0CH
R/W
R/W
R/W
R/W
R/W
Description
Bits 15 through 12 of DBF
Bits 11 through 8 of DBF
Bits 7 through 4 of DBF
Bits 3 through 0 of DBF
DBF2
MEM
0.0DH
0.0EH
0.0FH
DBF1
MEM
DBF0
MEM
24.2 System Register (SYSREG)
Symbol Name
AR3
AR2
AR1
AR0
WR
Attribute
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
FLG
Value
0.74H
R/W
R
Description
Bits 15 through 12 of address register
Bits 11 through 8 of address register
Bits 7 through 4 of address register
Bits 3 through 0 of address register
Window register
0.75H
R
0.76H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0.77H
0.78H
BANK
IXH
0.79H
Bank register
0.7AH
0.7AH
0.7AH.3
0.7BH
0.7BH
0.7CH
0.7DH
0.7EH
0.7FH
Index register, high
MPH
MPE
IXM
Memory pointer, high
Memory pointer enable flag
Index register, middle
Memory pointer, low
MEM
MEM
MEM
MEM
MEM
MEM
FLG
MPL
IXL
Index register, low
RPH
RPL
PSW
BCD
CMP
CY
General register pointer, high
General register pointer, low
Program status word
BCD operation flag
0.7EH.0
0.7FH.3
0.7FH.2
0.7FH.1
0.7FH.0
FLG
Compare flag
FLG
Carry flag
Z
FLG
Zero flag
IXE
FLG
Index enable flag
295
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
24.3 LCD Segment Register
Symbol Name
LCDD0
Attribute
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
MEM
Value
2.6F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCD segment register
LCDD1
2.6E
2.6D
2.6C
2.6B
2.6A
2.69
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
2.68
LCDD8
2.67
LCDD9
2.66
LCDD10
LCDD11
LCDD12
LCDD13
LCDD14
LCDD15
LCDD16
LCDD17
LCDD18
LCDD19
2.65
2.64
2.63
2.62
2.61
2.60
2.5FH
2.5EH
2.5DH
2.5CH
296
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
24.4 Port Register
Symbol Name
P0A2
Attribute
FLG
Value
R/W
R/W
Description
0.70H.2
Bit 2 of port 0A
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0A1
FLG
0.70H.1
R/W
Bit 1 of port 0A
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0A0
P0B3
FLG
0.70H.0
R/W
Bit 0 of port 0A
FLG
0.71H.3
R/W
Bit 3 of port 0B
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0B2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0B1 FLG 0.71H.1 R/W Bit 1 of port 0B
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.71H.2
R/W
Bit 2 of port 0B
P0B0
FLG
0.71H.0
R/W
Bit 0 of port 0B
P0C3
FLG
0.72H.3
R/W
Bit 3 of port 0C
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0C2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0C1 FLG 0.72H.1 R/W Bit 1 of port 0C
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.72H.2
R/W
Bit 2 of port 0C
P0C0
FLG
0.72H.0
R/W
Bit 0 of port 0C
P0D3
FLG
0.73H.3
R
Bit 3 of port 0D
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0D2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0D1 FLG 0.73H.1 Bit 1 of port 0D
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.73H.2
R
Bit 2 of port 0D
R
P0D0
FLG
0.73H.0
R
Bit 0 of port 0D
P1A2
FLG
1.70H.2
R/W
Bit 2 of port 1A
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1A1
FLG
1.70H.1
R/W
Bit 1 of port 1A
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1A0
P1B3
FLG
FLG
1.70H.0
1.71H.3
R/W
R/W
Bit 0 of port 1A
Bit 3 of port 1B
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1B2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1B1 FLG 1.71H.1 R/W Bit 1 of port 1B
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
1.71H.2
R/W
Bit 2 of port 1B
P1B0
FLG
1.71H.0
R/W
Bit 0 of port 1B
P1C3
FLG
1.72H.3
R/W
Bit 3 of port 1C
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1C2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1C1 FLG 1.72H.1 R/W Bit 1 of port 1C
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
1.72H.2
R/W
Bit 2 of port 1C
P1C0
FLG
1.72H.0
R/W
Bit 0 of port 1C
P1D3
FLG
1.73H.3
R
Bit 3 of port 1D
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1D2
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1D1 FLG 1.73H.1 Bit 1 of port 1D
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
1.73H.2
R
Bit 2 of port 1D
R
P1D0
FLG
1.73H.0
R
Bit 0 of port 1D
P2E0
FLG
2.5FH.0
R/W
Bit 0 of port 2E
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P2F0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P2G0 FLG 2.5DH.0 R/W Bit 0 of port 2G
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
2.5EH.0
R/W
Bit 0 of port 2F
P2H0
FLG
2.5CH.0
R/W
Bit 0 of port 2H
297
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
24.5 Register File (Control Register)
Symbol Name
SP
Attribute
MEM
Value
0.81H
0.82H.3
R/W
R/W
R/W
Description
Stack pointer
SIO1TS
FLG
Serial interface start flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SIO1HIZ
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SIO1CK1 FLG 0.82H.1 R/W Serial interface clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.82H.2
R/W
P0A1/SO1 pin select flag
SIO1CK0
FLG
FLG
FLG
FLG
FLG
FLG
0.82H.0
0.84H.0
0.85H.0
0.86H.0
0.87H.0
0.89H.3
R/W
Serial interface clock select flag
IF counter gate status flag
PLL unlock FF flag
IFCG
R
PLLUL
ADCCMP
CE
R
R
ADC judge flag
R
CE pin status flag
BTM1CK1
R/W
Basic timer 0 clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BTM1CK0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BTM0CK1 FLG 0.89H.1 R/W Basic timer 1 clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.89H.2
R/W
Basic timer 0 clock select flag
BTM0CK0
FLG
FLG
FLG
0.89H.0
0.8CH.0
0.8DH.0
R/W
R/W
R
Basic timer 1 clock select flag
TMCK
12-bit timer clock select flag
TMOVF
Timer/counter overflow detector flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TMRPT
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
TMRES FLG 0.8EH.1 R/W Timer/counter reset flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.8EH.2
R/W
12-bit timer mode select flag
TMEN
FLG
0.8EH.0
R/W
Timer/counter start/stop flag
KSEN
FLG
0.90H.2
R/W
Key source latch enable flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LCDEN
FLG
0.90H.1
R/W
LCD enable flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PYASEL
P2HSEL
FLG
FLG
0.90H.0
0.91H.3
R/W
R/W
Port YA select flag
Port 2H select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P2GSEL
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P2FSEL FLG 0.91H.1 R/W Port 2F select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.91H.2
R/W
Port 2G select flag
P2ESEL
FLG
0.91H.0
R/W
Port 2E select flag
IFCMD1
FLG
0.92H.3
R/W
IF counter mode select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IFCMD0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IFCCK1 FLG 0.92H.1 R/W IF counter clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FLG
0.92H.2
R/W
IF counter mode select flag
IFCCK0
FLG
0.92H.0
R/W
IF counter clock select flag
PWM1SEL
FLG
0.93H.1
R/W
P0C1/PWM1 pin select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PWM0SEL
ADCCH1
FLG
0.93H.0
R/W
P0C0/PWM0 pin select flag
FLG
0.94H.1
R/W
A/D converter channel select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
ADCCH0
FLG
0.94H.0
R/W
A/D converter channel select flag
BEEP1SEL
FLG
0.95H.1
R/W
P0B1/BEEP1 pin select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BEEP0SEL
FLG
0.95H.0
R/W
P0B0/BEEP0 pin select flag
KEYJ
FLG
0.96H.0
R
Key input judge flag
298
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Symbol Name
BTM0CY
IEG
Attribute
FLG
Value
0.97H.0
0.9FH.0
0.0A1H.1
R/W
R
Description
Basic timer 0 carry flag
FLG
R/W
R/W
INT pin interrupt edge select flag
PLL mode select flag
PLLMD1
FLG
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PLLMD0
FLG
0.0A1H.0
R/W
PLL mode select flag
IFCSTRT
FLG
0.0A3H.1
R/W
IF counter start flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IFCRES
FLG
0.0A3H.0
R/W
IF counter reset flag
FCGCH1
FLG
0.0A4H.1
R/W
External gate counter channel select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
FCGCH0
FLG
0.0A4H.0
R/W
External gate counter channel select flag
BEEP1CK1
FLG
0.0A5H.3
R/W
BEEP1 clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BEEP1CK0
FLG
0.0A5H.2
R/W
BEEP1 clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BEEP0CK1 FLG 0.0A5H.1 R/W BEEP0 clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
BEEP0CK0
P1DGIO
IPSIO1
FLG
FLG
FLG
0.0A5H.0
0.0A7H.0
0.0AFH.3
R/W
R/W
R/W
BEEP0 clock select flag
Port 1D group I/O select flag
Serial interface interrupt enable flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IPBTM1
FLG
0.0AFH.2
R/W
Basic timer 1 interrupt enable flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IPTM FLG 0.0AFH.1 R/W 12-bit timer interrupt enable flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IP
FLG
0.0AFH.0
R/W
INT pin interrupt enable flag
PLLRFCK3
FLG
0.0B1H.3
R/W
PLL reference clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PLLRFCK2
FLG
0.0B1H.2
R/W
PLL reference clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PLLRFCK1 FLG 0.0B1H.1 R/W PLL reference clock select flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PLLRFCK0
FLG
0.0B1H.0
R/W
PLL reference clock select fla
P1ABIO2
FLG
0.0B5H.2
R/W
I/O select flag of P1A2 pin
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1ABIO1
FLG
0.0B5H.1
R/W
I/O select flag of P1A1 pin
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P1ABIO0
P0BBIO3
FLG
FLG
0.0B5H.0
0.0B6H.3
R/W
R/W
I/O select flag of P1A0 pin
I/O select flag of P0B3 pin
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0BBIO2
FLG
0.0B6H.2
R/W
I/O select flag of P0B2 pin
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0BBIO1 FLG 0.0B6H.1 R/W I/O select flag of P0B1 pin
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0BBIO0
FLG
0.0B6H.0
R/W
I/O select flag of P0B0 pin
P0ABIO2
FLG
0.0B7H.2
R/W
I/O select flag of P0A2 pin
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0ABIO1
FLG
0.0B7H.1
R/W
I/O select flag of P0A1 pin
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
P0ABIO0
IRQSIO1
IRQBTM1
IRQTM
INT
FLG
FLG
FLG
FLG
FLG
0.0B7H.0
0.0BCH.0
0.0BDH.0
0.0BEH.0
0.0BFH.3
R/W
R/W
R/W
R/W
R
I/O select flag of P0A0 pin
Serial interface interrupt request flag
Basic timer 1 interrupt request flag
12-bit timer interrupt request flag
INT pin interrupt status flag
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
IRQ FLG 0.0BFH.0 R/W INT pin interrupt request flag
299
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
24.6 Peripheral Hardware Register
Symbol Name
ADCR
Attribute
DAT
Value
02H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
A/D converter reference voltage setting register
Serial interface presettable shift register
PWM0 data register
SIO1SFR
PWMR0
PWMR1
AR
DAT
03H
04H
05H
40H
41H
42H
DAT
DAT
PWM1 data register
DAT
Address register
PLLR
DAT
PLL data register
KSR
DAT
Key source data register
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PYA
DAT
DAT
DAT
DAT
42H
43H
46H
47H
R/W
PYA group register
IF counter data register
Timer modulo register
Timer counter
IFC
R
TMM
TMC
R/W
R
24.7 Others
Symbol Name
Attribute
DAT
Value
Description
DBF
IX
0FH
01H
Fixed operand value of PUT, GET, and MOVT instructions
Fixed operand value of INC instruction
DAT
300
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
25. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY (µPD17P012 ONLY)
The µPD17P012 includes a 4,096 × 16-bit one-time PROM program memory.
The pins used for the write/verify operations of this one-time PROM are listed in Table 25-1. Clock input from the
CLK pin, instead of address input, is used for updating addresses.
Table 25-1. Pins Used for Program Memory Write/Verify
Pin Name
VPP
Function
Pin used to apply the program voltage when writing, reading, or verifying the program memory. Apply
+12.5 V.
VDD1, VDD2
Power supply. Supply +6 V to these pins when writing, reading, or verifying the program memory.
CLK
Clock input to update addresses when writing, reading, or verifying the program memory.
Program memory addresses are updated by inputting a pulse to the CLK pin four times.
MD0 to MD3
D0 to D7
Input to select the operation mode when writing, reading, or verifying the program memory.
8-bit data I/O when writing, reading, or verifying the program memory.
25.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the VDD pin and +12.5 V to the VPP pin after the reset status (VDD = 5 V and RESET = 0
V) has continued for a certain time, the µPD17P012 enters the program memory write/verify mode. The following
operation modes can be set by setting pins MD0 to MD3 as shown below. Pins not listed in Table 25-1 should be left
open, or connected to GND via a pull-down resistor (470 Ω) (refer to PIN CONFIGURATION (2) µPD17P012 (b) PROM
programming mode).
Table 25-2. Operation Mode Setting
Operation Mode Setting
Operation Mode
VPP
VDD
MD0
H
MD1
L
MD2
H
MD3
L
+12.5 V
+6 V
Program memory address 0-clear mode
Write mode
L
H
H
H
L
L
H
H
Verify mode
H
×
H
H
Program inhibit mode
×: Don’t care (L or H)
301
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
25.2 Program Memory Write Procedure
Program memory can be written at high speed using the following procedure.
(1) Pull down unused pins via a resistor. Set the CLK pin to low.
(2) Supply 5 V to the VDD pin. Set the VPP pin to low.
(3) Wait for 10 µs and then supply 5 V to the VPP pin.
(4) Set the mode setting pin to program memory address 0-clear mode.
(5) Supply +6 V to the VDD pin and +12.5 V to the VPP pin.
(6) Set the program inhibit mode.
(7) Write data in the 1 ms write mode.
(8) Set the program inhibit mode.
(9) Set the verify mode. If the data is correct, go to step (10). If not, repeat steps (7) to (9).
(10) (X: Number of write operations from steps (7) to (9)) × 1 ms additional write.
(11) Set the program inhibit mode.
(12) Input four pulses to the CLK pin to increment the program memory address by one.
(13) Repeat steps (7) to (12) until the end address is reached.
(14) Set the program memory address 0-clear mode.
(15) Change the VDD and VPP pins to 5 V.
(16) Turn off the power.
The following figure shows steps (2) to (12).
X repetitions
Additional
write
Address
increment
Reset
Write
Verify
V
PP
V
DD
V
PP
GND
V
+ 1
DDVDD
V
DD
GND
CLK
Hi-z
Hi-z
Hi-z
Hi-z
D
0
to D
MD
MD
MD
MD
7
Data input
Data output
Data input
0
1
2
3
302
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
25.3 Program Memory Read Procedure
(1) Pull down unused pins to GND via a resistor. Set the CLK pin to low.
(2) Supply 5 V to the VDD pin. Set the VPP pin to low.
(3) Wait for 10 µs and then supply 5 V to the VPP pin.
(4) Set the mode setting pin to program memory address 0-clear mode.
(5) Supply +6 V to the VDD pin and +12.5 V to the VPP pin.
(6) Set the program inhibit mode.
(7) Set the verify mode. Addresses are incremented by one for each 4-pulse cycle input to the CLK pin.
(8) Set the program inhibit mode.
(9) Set the program memory address 0-clear mode.
(10) Change the VDD and VPP pins to 5 V.
(11) Turn off the power.
The following figure shows steps (2) to (9).
Reset
VPP
VDD
VPP
GND
VDD +1
VDD
VDD
One cycle
GND
CLK
Hi-Z
Hi-Z
D0 to D7
Data output
Data output
MD0
MD1
MD2
MD3
“L”
303
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
26. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
Condition
Rating
−0.3 to +6.0
−0.3 to +6.3
−0.3 to +13.5
−0.3 to VDD + 0.3
−0.3 to VDD + 0.3
14.0
Unit
V
VDD
µPD17012
µPD17P012
µPD17P012
V
PROM program voltage
Input voltage
VPP
VI
V
V
Output voltage
VO
Other than P0C0 to P0C3
P0C0 to P0C3 (µPD17012)
P0C0 to P0C3 (µPD17P012)
Per pin
V
Output breakdown voltage
VBDS
V
10.0
V
Output current, high
Output current, low
IOH
IOL
−12
mA
mA
mA
mA
mW
°C
°C
Total for all pins
−20
Per pin
15
Total for all pins
30
Overall error
Pt
200
Operating ambient temperature
Storage temperature
TA
Tstg
When overall function operates
−40 to +85
−55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VDD1
Condition
When overall function operate
When PLL stops and CPU operates
When crystal oscillation stops
P0C0 to P0C3 (µPD17012)
MIN.
4.5
TYP. MAX.
Unit
V
5.0
5.0
5.5
5.5
VDD2
3.5
V
Data retention voltage
VDDR
2.3
5.5
V
Output breakdown voltage
VBDS
12.0
9.0
V
P0C0 to P0C3 (µPD17P012)
V
Operating ambient temperature
TA
−40
+85
500
50
°C
ms
ms
VP-P
VP-P
Supply voltage rise time
trise
VDD: 0 → 4.5 V
VDD: 2.3 → 3.5 V
VCOH, VCOL
Input amplitude
VIN1
VIN2
0.5
0.5
VDD
VDD
AMIFC, FMIFC
304
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
DC Characteristics (TA = −40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Supply current
Symbol
Conditions
MIN.
TYP. MAX.
Unit
mA
IDD1
With CPU operating, PLL stopped, sine wave input to
XIN pin (fIN = 4.5 MHz, VIN = VDD)
1.0
2.0
(µPD17012)
IDD2
With CPU operating, PLL stopped, sine wave input to
XIN pin (fIN = 4.5 MHz, VIN = VDD)
0.5
1.0
mA
HALT instruction used
Supply current
IDD1
IDD2
With CPU operating, PLL stopped, sine wave input to
XIN pin (fIN = 4.5 MHz, VIN = VDD)
2.5
2.0
3.5
3.0
mA
mA
(µPD17P012)
With CPU operating, PLL stopped, sine wave input to
XIN pin (fIN = 4.5 MHz, VIN = VDD)
HALT instruction used
Data retention voltage
Data retention current
VDDR1
VDDR2
VDDR3
IDDR1
IDDR2
IDDR3
IDDR4
VOM
With crystal oscillation Power failure detection by timer FF
3.5
2.3
2.0
V
V
With crystal
Power failure detection by timer FF
Data memory retained
oscillation stopped
V
With crystal
VDD = 5 V, TA = 25°C
2.0
2.0
1.0
1.0
4.0
20.0
2.0
µA
µA
µA
µA
V
oscillation stopped
VDD = 2.3 V, TA = 25°C
VDD = 2.3 V
10.0
2.7
Intermediate-level output
voltage
COM0 to COM2
VDD = 5.0 V
2.3
Input voltage, high
VIH1
P0A1, P0B0 to P0B3, P1A0 to P1A2, P1B0 to P1B3,
P1D0 to P1D3
0.7VDD
VDD
V
VIH2
VIH3
VIL1
P0A0, P0A2, CE, INT
P0D0 to P0D3
0.8VDD
0.6VDD
0
VDD
VDD
V
V
V
Input voltage, low
Output current, high
Output current, low
P0A1, P0B0 to P0B3, P0D0 to P0D3, P1A0 to P1A2,
P1B0 to P1B3, P1C0 to P1C3Note, P1D0 to P1D3
0.2VDD
VIL2
IOH1
P0A0, P0A2, CE, INT
0
0.2VDD
V
P0A0 to P0A2, P0B0 to P0B3, P1A0 to P1A2,
−1.0
mA
P1C0 to P1C3, P1D0 to P1D3
VOH = VDD − 1 V
IOH2
LCD0 to LCD19, EO
VOH = VDD − 1 V
−1.0
mA
mA
IOL1
P0A0 to P0A2, P0B0 to P0B3, P1A0 to P1A2,
P1C0 to P1C3, P1D0 to P1D3
1.0
VOL = 1 V
VOL = 1 V
VOL = 1 V
VIH = VDD
VIH = VDD
VIH = VDD
VIH = VDD
VOH = 12 V
VOH = 9 V
IOL2
IOL3
IIH1
IIH2
IIH3
IIH4
IL1
LCD0 to LCD19, EO
1.0
1.0
10
mA
mA
mA
mA
mA
µA
P0C0 to P0C3
Input current, high
VCOH pin pulled down
VCOL pin pulled down
XIN pin pulled down
0.1
0.1
10
P0D0 to P0D3 pin pulled down
P0C0 to P0C3 (µPD17012)
P0C0 to P0C3 (µPD17P012)
150
1.0
1.0
1.0
Output off leakage
current
µA
µA
IL2
EO
VOH = VDD, VOL = 0 V
µA
Note During PROM programming mode
305
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
AC Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
0.90
TYP. MAX.
3.0
Unit
Operating frequency
fIN1
VCOL pin, MF mode,
VCOL pin, MF mode,
VCOL pin, HF mode,
VCOL pin, HF mode,
MHz
(µPD17012)
sine wave input VIN = 0.15 Vp-p
sine wave input VIN = 0.3 Vp-p
sine wave input VIN = 0.15 Vp-p
sine wave input VIN = 0.3 Vp-p
0.50
5
20
25
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fIN2
5
40
fIN3
VCOH pin, VHF mode,
VCOH pin, VHF mode,
60
130
250
1.0
0.46
15
sine wave input VIN = 0.15 Vp-p
sine wave input VIN = 0.3 Vp-p
30
fIN4
fIN5
fIN6
fIN7
fIN1
fIN2
AMIFC pin, AMIF count mode,
sine wave input VIN = 0.3 Vp-p
0.3
0.44
5
AMIFC pin, AMIF count mode,
sine wave input VIN = 0.1 Vp-p
FMIFC pin, FMIF count mode,
sine wave input VIN = 0.3 Vp-p
FMIFC pin, FMIF count mode,
sine wave input VIN = 0.1 Vp-p
10.5
0.50
5
10.9
20
Operating frequency
VCOL pin, MF mode,
VCOL pin, HF mode,
VCOL pin, HF mode,
VCOH pin, VHF mode,
VCOH pin, VHF mode,
(µPD17P012)
sine wave input VIN = 0.5 Vp-p
sine wave input VIN = 0.15 Vp-p
sine wave input VIN = 0.3 Vp-p
sine wave input VIN = 0.15 Vp-p
sine wave input VIN = 0.3 Vp-p
25
5
30
fIN3
60
130
250
1.0
0.46
15
30
fIN4
fIN5
fIN6
fIN7
AMIFC pin, AMIF count mode,
sine wave input VIN = 0.3 Vp-p
AMIFC pin, AMIF count mode,
sine wave input VIN = 0.1 Vp-p
FMIFC pin, FMIF count mode,
sine wave input VIN = 0.3 Vp-p
FMIFC pin, FMIF count mode,
sine wave input VIN = 0.1 Vp-p
0.3
0.44
5
10.5
10.9
AD Converter Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP. MAX.
6
Unit
bit
A/D conversion resolution
A/D conversion total error
1.0
1.5
LSB
306
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Reference Characteristics (TA = +25°C, VDD = 5.0 V)
Parameter
Supply current
Symbol
Conditions
MIN.
TYP. MAX.
12
Unit
mA
IDD3
With CPU and PLL operating, sine wave input to
VCOH pin (fIN = 130 MHz, VIN = 0.3 Vp-p)
(µPD17012)
IDD4
IDD3
IDD4
With CPU and PLL operating, sine wave input to
VCOH pin (fIN = 250 MHz, VIN = 0.3 Vp-p)
13
15
16
mA
mA
mA
Supply current
With CPU and PLL operating, sine wave input to
VCOH pin (fIN = 130 MHz, VIN = 0.3 Vp-p)
(µPD17P012)
With CPU and PLL operating, sine wave input to
VCOH pin (fIN = 250 MHz, VIN = 0.3 Vp-p)
Output current, high
Output current, low
IOH3
IOL4
IOM1
IOM2
COM0 to COM2
COM0 to COM2
COM0 to COM2
COM0 to COM2
VOH = VDD −1 V
−300
300
−25
25
µA
µA
µA
µA
VOL = 1 V
VOH = VDD − 1 V
VOL = 1 V
Output current,
intermediate
PROM Programming Characteristics (µPD17P012 only)
DC Programming Characteristics (TA = 25°C, VDD = 6.0 0.25 V, VPP = 12.5 0.5 V)
Parameter
Symbol
VIH1
VIH2
VIL1
VIL2
ILI
Conditions
Pins other than CLK
MIN.
0.7VDD
VDD – 0.5
0
TYP.
MAX.
VDD
Unit
Input voltage, high
V
V
CLK
VDD
Input voltage, low
Pins other than CLK
CLK
0.2VDD
0.4
V
0
V
Input leakage current
Output voltage, high
Output voltage, low
VDD supply current
VPP supply current
VIN = VIL or VIH
IOH = –1 mA
IOL = 1.0 mA
10
µA
V
VOH
VOL
IDD
VDD – 1.0
1.0
30
30
V
mA
mA
IPP
MD0 = VIL, MD1 = VIH
Cautions 1. Ensure that VPP does not exceed +13.5 V including overshoot.
2. VDD must be applied before VPP, and cut after VPP.
307
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
AC Programming Characteristics (TA = 25°C, VDD = 6.0 0.25 V, VPP = 12.5 0.5 V)
Parameter
Symbol Note 1
Conditions
MIN.
TYP.
MAX.
Unit
µs
µs
µs
µs
µs
ns
µs
µs
ms
ms
µs
µs
µs
µs
µs
µs
MHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
Address setup timeNote 2 (to MD0↓)
MD1 setup time (to MD0↓)
tAS
tAS
2
2
tM1S
tDS
tOES
tDS
Data setup time (to MD0↓)
Address hold timeNote 2 (from MD0↑)
Data hold time (from MD0↑)
2
tAH
tAH
2
tDH
tDH
2
Delay time from MD0↑ to data output float
tDF
tDF
0
130
VPP setup time (to MD3↑)
tVPS
tVDS
tPW
tVPS
tVCS
tPW
tOPW
tCES
tDV
2
VDD setup time (to MD3↑)
Initial program pulse width
Additional program pulse width
MD0 setup time (to MD1↑)
Delay time from MD0↓ to data output
MD1 hold time (from MD0↑)
MD1 recovery time (from MD0↓)
Program counter reset time
CLK input high-/low-level widths
CLK input frequency
2
0.95
0.95
2
1.0
1.05
21.0
tOPW
tM0S
tDV
MD0 = MD1 = VIL
1
tM1H
tM1R
tPCR
tXH, tXL
fX
tOEH
tOR
tM1H + tM1R ≥ 50 µs
2
2
—
10
—
—
—
—
—
—
0.125
4.19
Initial mode setting time
tI
2
2
2
2
MD3 setup time (to MD1↑)
MD3 hold time (from MD1↓)
MD3 setup time (to MD0↓)
tM3S
tM3H
tM3SR
Program memory read
Program memory read
Program memory read
Program memory read
Program memory read
Delay time from addressNote 2 to data output tDAD
tACC
tOH
2
Hold time from addressNote 2 to data output
tHAD
tM3HR
tDFR
tRES
0
2
130
MD3 hold time (from MD0↑)
—
—
Delay time from MD
Reset setup time
3
↓ to data output float
2
10
Notes 1. Symbol of corresponding µPD27C256A (the µPD27C256 is a maintenance product).
2. The internal address signal is incremented by 1 on the 3rd fall of a four-clock input (CLK) cycle, and is not
connected to a pin.
308
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Program Memory Write Timing
tRES
tVPS
VPP
VDD
GND
VPP
VDD
tVDS
VDD + 1
VDD
tXH
GND
CLK
tXL
Hi-Z
D0 to D7
MD0
Data input
Data output
Data input
Data input
tDH
tAH
tI
tDS
tDS
tDH
tDV
tDF
tAS
tPW
tM1R
tMOS
tOPW
MD1
MD2
tPCR
tM1S
tM1H
tM3H
tM3S
MD3
Program Memory Read Timing
tRES
tVPS
VPP
V
DD
VPP
GND
tVDS
V
DD + 1
V
DD
V
DD
t
XH
GND
CLK
tXL
t
DAD
tHAD
D
0
to D
MD
MD
MD
MD
7
0
1
2
3
Data output
Data output
tDV
t
DFR
t
I
tM3HR
“L”
t
PCR
tM3SR
309
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
27. PACKAGE DRAWINGS
64-PIN PLASTIC QFP (14x20)
A
B
detail of lead end
51
52
33
32
S
C
D
R
Q
64
1
20
19
F
M
G
J
H
I
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
23.6 0.4
20.0 0.2
14.0 0.2
17.6 0.4
1.0
1.0
0.40 0.10
0.20
J
1.0 (T.P.)
1.8 0.2
0.8 0.2
K
L
+0.10
0.15
M
−0.05
N
P
Q
R
S
0.10
2.7 0.1
0.1 0.1
5° 5°
3.0 MAX.
P64GF-100-3B8,3BE,3BR-4
310
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
80-PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
21
20
1
F
J
M
G
H
I
P
K
S
N
S
L
M
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
G
H
I
17.20 0.20
14.00 0.20
14.00 0.20
17.20 0.20
0.825
0.825
0.32 0.06
0.13
J
0.65 (T.P.)
1.60 0.20
0.80 0.20
K
L
+0.03
0.17
M
−0.07
N
P
0.10
1.40 0.10
0.125 0.075
Q
+7°
3°
R
S
−3°
1.70 MAX.
P80GC-65-8BT-1
311
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
28. RECOMMENDED SOLDERING CONDITIONS
The µPD17012 and 17P012 should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, contact an NEC sales representative.
Table 28-1. Surface Mounting Type Soldering Conditions
(1) µPD17012GF-xxx-3BE: 64-pin plastic QFP (14 × 20)
µPD17P012GF-3BE:
64-pin plastic QFP (14 × 20)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), IR35-207-2
Note
Count: Twice or less, Exposure limit: 7 days
for 20 hours)
(after that, prebake at 125°C
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), VP15-207-2
Note
Count: Twice or less, Exposure limit: 7 days
for 20 hours)
(after that, prebake at 125°C
Wave soldering
Soldering bath temperature: 260°C max., Time: 10 seconds max., Count: Once, WS60-207-1
Preheating temperature: 120°C max. (package surface temperature), Exposure
Note
limit: 7 days
(after that, prebake at 125°C for 20 hours)
Partial heating
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
−
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD17012GC-xxx-8BT: 80-pin plastic QFP (14 × 14)
µPD17P012GC-8BT:
80-pin plastic QFP (14 × 14)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
VPS
Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), IR35-00-2
Count: Twice or less
Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), VP15-00-2
Count: Twice or less
Wave soldering
Partial heating
Soldering bath temperature: 260°C max., Time: 10 seconds max., Count: Once,
Preheating temperature: 120°C max. (package surface temperature)
WS60-00-1
Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)
−
Caution Do not use different soldering methods together (except for partial heating).
312
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR
When using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the figure
below to avoid an adverse effect from wiring capacitance.
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high
fluctuating current flows.
•
•
Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor
to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Also caution is required for the following three points when connecting the capacitor and adjusting the
operating frequency.
<1> If capacitances C1 and C2 are too high, the oscillation startup characteristic may be degraded or the current
consumption may rise.
<2> The trimmer capacitor for adjusting the oscillation frequency is generally connected to the XIN pin. However,
depending on the crystal resonator used, the oscillation stabilization may be affected (in this case, connect
the trimmer capacitor to the XOUT pin). Therefore, oscillation should be evaluated by the crystal resonator
that is actually being used.
<3> Adjust the oscillation frequency while measuring the LCD drive waveform (83.3 Hz) or VCO oscillation
frequency. If the probe is connected to the XOUT or XIN pin, the oscillation frequency cannot be measured
correctly due to the probe capacitance.
µ
PD17012, 17P012
XOUT
XIN
4.5 MHz crystal resonator
C1
C2
313
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
APPENDIX B. DEVELOPMENT TOOLS
The following development tools are available for program development of the µPD17012 and 17P012.
Hardware
Name
Description
In-circuit emulator
IE-17K,
IE-17K and IE-17K-ET are in-circuit emulators that can be commonly used with any model
in 17K Series. IE-17K and IE-17K-ET are connected to a host machine, which is a PC-9800 series
Note 1
TM
IE-17K-ET
or IBM PC/AT , with RS232-C. When these in-circuit emulators are used in combination with the
systemevaluationboard(SEboard)dedicatedtoeachmodel, theyoperateasemulatorscorresponding
®
to that model. When human interface software SIMPLEHOST is used, a more sophisticated
debugging environment can be created.
SE board
SE-17012 is SE board for µPD17012 and 17P012. This SE board can be used alone to evaluate the
(SE-17012)
system (SE-17012) or in combination with an in-circuit emulator for debugging.
Emulation probe
(EP-17202GF)
EP-17202GF is an emulation probe for the 64-pin plastic QFP (GF-3BE type) of the µPD17012 and
17P012. The SE board and target system are connected when the EP-17202GF is used in
Note 2
combination with the EV-9200G-64
.
Emulation probe
(EP-17K80GC)
EP-17K80GC is an emulation probe for the 80-pin plastic QFP (GC-8BT type) of the µPD17012 and
17P012. The SE board and target system are connected when the EP-17K80GC is used in
Note 2
combination with the EV-9200GC-80
.
Conversion socket
EV-9200G-64 is a conversion socket for a 64-pin plastic QFP (GF-3BE type). It is used to connect
the EP-17202GF to the target system.
Note 2
(EV-9200G-64
)
Conversion socket
EV-9200GC-80 is a conversion socket for an 80-pin plastic QFP (GC-8BT type). It is used to connect
the EP-17K80GC to the target system.
Note 2
(EV-9200GC-80
)
PROM programmer
AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers corresponding to µPD17P012.
They can program the µPD17P012 when connected to program adapters AF-9776B and PA-
17P012GC.
Note 3
AF-9703
Note 3
AF-9704
Note 3
AF-9705
Note 3
AF-9706
Program adapter
AF-9776B is an adapter for programming the 64-pin plastic QFP (GF-3BE type) of the µPD17P012.
It is used in combination with the AF-9703, AF9704, AF-9705, or AF-9706.
Note 3
(AF-9776B
)
Program adapter
(PA-17P012GC)
PA-17P012GCisanadapterforprogrammingthe80-pinplasticQFP(GC-8BTtype)oftheµPD17P012.
It is used in combination with the AF-9703, AF9704, AF-9705, or AF-9706.
Notes 1. Low-cost model: external power supply type
2. One EV-9200G-64 is provided with the EP-17202GF. Five EV-9200G-64s are also available as a set.
One EV-9200GC-80 is provided with the EP-17K80GC. Five EV-9200GC-80s are also available as
a set.
3. These are products of Ando Electric Co., Ltd. For details, consult Ando Electric Co, Ltd. (TEL: +81-
3-3733-1166).
314
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Software
Name
Outline
Host Machine
OS
Supply
Media
Order Code
17K assembler
(RA17K)
RA17K is an assembler
common to the 17K Series
products. To develop the
program of the µPD17012,
the RA17K is used in
combination with the device
file.
PC-9800 series Japanese
3.5"2HD µSAA13RA17K
3.5"2HC µSAB13RA17K
µSBB13RA17K
TM
Windows
IBM PC/AT-
compatible
Japanese
Windows
English
Windows
Device file
(AS17012)
AS17012 is a device file for
µPD17012 and µPD17P012.
It is used in combination with
an assembler common to the
17K Series (RA17K).
PC-9800 series Japanese
Windows
3.5"2HD µSAA13AS17012
3.5"2HC µSAB13AS17012
µSBB13AS17012
IBM PC/AT-
compatible
Japanese
Windows
English
Windows
Support software
(SIMPLEHOST)
SIMPLEHOST is software
that serves as a human
interface on Windows for
program development using
an in-circuit emulator and
personal computer.
PC-9800 series Japanese
Windows
3.5"2HD µSAA13ID17K
3.5"2HC µSAB13ID17K
µSBB13ID17K
IBM PC/AT-
compatible
Japanese
Windows
English
Windows
315
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
316
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-3067-5899
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 250-3583
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
317
Data Sheet U10101EJ4V0DS
µPD17012, 17P012
SIMPLEHOST is a trademark of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of June, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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