UPD178076GF-XXX-3BA [NEC]
8-Bit Microcontroller ; 8位微控制器\n
| 型号： | UPD178076GF-XXX-3BA |
| 厂家： | 
NEC |
| 描述： | 8-Bit Microcontroller
|
| 文件： | 总72页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD178076,178078,178096,178098
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178076, 178078, 178096, and 178098 are 8-bit single-chip CMOS microcontrollers containing hardware
for digital tuning systems.
These microcontrollers employ a 78K/0 series architecture CPU and allow easy access to internal memories at
high speed and easy control of peripheral hardware units. The high-speed 78K/0 series instructions are ideal for
system control.
As peripheral hardware, a prescaler, PLL frequency synthesizer, and frequency counter for digital tuning systems
are provided, as well as many I/O ports, timers, A/D converter, serial interface, and a power-ON clear circuit. In
addition, the µPD178076 and 178078 have an asynchronous serial interface (UART) mode, and the µPD178096 and
178098 have an IEBusTM controller.
Moreover, a flash memory model, the µPD178F098, that operates in the same supply voltage range as the mask
ROM models, and various development tools are also under development.
For the detailed functional description, refer to the following User’s Manuals:
µPD178078, 178098 Subseries User’s Manual : U12790E
78K/0 Series User’s Manual - Instruction
: U12326E
FEATURES
High-capacity ROM and RAM
•
Item Program Memory (ROM)
Data Memory
Internal high-speed RAM Internal buffer RAM Internal extension RAM
Part Number
µPD178076, 178096
µPD178078, 178098
48K bytes
60K bytes
1024 bytes
32 bytes
1024 bytes
2048 bytes
Instruction cycle:
Hardware for PLL frequency synthesizer
dual modulus prescaler, programmable divider,
phase comparator, charge pump
•
•
•
•
•
0.32 µs (with crystal resonator of fX = 6.3 MHz)
Many internal hardware units
General-purpose I/O ports, A/D converter, serial
interface (UART mode: µPD178076 and 178078
only), IEBus controller (µPD178096 and 178098
only), timers, frequency counter, power-ON clear
circuit
Vectored interrupt sources
• µPD178076, 178078: 22
• µPD178096, 178098: 21
Supply voltage
:VDD = 4.5 to 5.5 V (during PLL and CPU
operations)
:VDD = 3.5 to 5.5 V (during CPU operation)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark shows major revised points.
Document No. U12885EJ3V0DS00
Date Published June 2000 N CP(K)
Printed in Japan
1997, 2000
©
µPD178076, 178078, 178096, 178098
APPLICATION FIELD
Car stereos
ORDERING INFORMATION
Part Number
Package
µPD178076GF-×××-3BA
µPD178078GF-×××-3BA
µPD178096GF-×××-3BA
µPD178098GF-×××-3BA
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
100-pin plastic QFP (14 × 20)
Remark ××× indicates ROM code suffix, which is E×× when the I2C bus is used.
2
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
DEVELOPMENT OF 8-BIT DTS SERIES
Models under mass production
Models under development
Flash memory model or
PROM model
Mask ROM model
µPD178048 subseries
80 pins
µPD178F048
80 pins
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
Internal OSD controller
8-bit PWM × 4 channels
14-bit PWM × 1 channel
100 pins
100 pins
µPD178098 subseries
Internal IEBus controller
100 pins
µPD178F098
Internal IEBus controller and UART
µPD178078 subseries
Internal UART
80 pins
µPD178034 subseries
µPD178F134
80 pins
Internal LCD and UART
Internal LCD and UART
µPD178F124
80 pins
µPD178024 subseries
80 pins
Internal UART
Internal UART
80 pins
80 pins
µPD178018A subseries
80 pins
µPD178P018A
µPD178003 subseries
Limits functions of µPD178018A subseries
Data Sheet U12885EJ3V0DS00
3
µPD178076, 178078, 178096, 178098
FUNCTIONAL OUTLINE
(1/2)
Item
µPD178076
48K bytes
High-speed RAM 1024 bytes
µPD178078
60K bytes
µPD178096
48K bytes
µPD178098
60K bytes
Internal
memory
ROM
Buffer RAM
32 bytes
Extension RAM
1024 bytes
2048 bytes
1024 bytes
2048 bytes
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution • 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.08 µs (with crystal resonator of fX = 6.3 MHz)
Note 1
time
• 0.44 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (with crystal resonator of fX = 4.5 MHz)
Instruction set
• 16-bit operation
• Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test Boolean operation)
• BCD adjustment, etc.
I/O port
Total
:
:
:
80 pins
8 pins
• CMOS input
• CMOS I/O
64 pins
• N-ch open-drain output : 8 pins
A/D converter
Serial interface
8-bit resolution × 8 channels
2
Note 2
2
Note 2
• 3-wire/SBI/2-wire/I C bus
mode
• 3-wire/SBI/2-wire/I C bus
mode
selectable: 1 channel
selectable: 1 channel
• 3-wire mode: 1 channel
• 3-wire mode: 1 channel
• 3-wire mode (with automatic transmit/
receive function of up to 32 bytes):
1 channel
• 3-wire mode (with automatic transmit/
receive function of up to 32 bytes):
1 channel
• UART mode: 1 channel
IEBus controller
Timer
Not provided
Provided
• Basic timer (timer carry FF (10 Hz))
• 16-bit timer/event counter
• 8-bit timer/event counter
• Watchdog timer
:
:
:
:
1 channel
1 channel
2 channels
1 channel
Buzzer output
BEEP0 pin: 1 kHz, 1.5 kHz, 3 kHz, 4 kHz
BUZ pin: 0.77 kHz, 1.54 kHz, 3.08 kHz, 6.15 kHz (with crystal resonator of fX = 6.3 MHz)
Notes 1. When using the IEBus controller of the µPD178096 or 178098, the 4.5-MHz crystal resonator cannot
be used. Use the 6.3-MHz crystal resonator.
2. When the I2C bus mode is used (including when the mode is implemented in software without using
the peripheral hardware), consult NEC when ordering a mask.
4
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2/2)
Item
Maskable
µPD178076
Internal : 13
µPD178078
µPD178096
Internal : 12
External: 8
µPD178098
Vectored
interrupt
source
External: 8
Internal: 1
1
Non-maskable
Software
PLL
Division mode
2 types
frequency
synthesizer
• Direct division mode (VCOL pin)
• Pulse swallow mode (VCOL and VCOH pins)
Reference
frequency
Seven types selectable in software (1, 3, 9, 10, 12.5, 25, 50 kHz)
Charge pump
Error out output: 2 pins
Phase
Unlock detectable in software
comparator
Frequency counter
Frequency measurement
• AMIFC pin: For 450-kHz counting
• FMIFC pin: For 450-kHz/10.7-MHz counting
Standby function
Reset
• HALT mode
• STOP mode
• Reset by RESET pin
• Internal reset by watchdog timer
• Reset by power-ON clear circuit
• Detection of less than 4.5 VNote (Reset does not occur, however.)
• Detection of less than 3.5 VNote (during CPU operation)
• Detection of less than 2.3 VNote (in STOP mode)
Supply voltage
Package
• VDD = 4.5 to 5.5 V (during CPU, PLL operation)
• VDD = 3.5 to 5.5 V (during CPU operation)
• 100-pin plastic QFP (14 × 20)
Note These voltages are the maximum values. In practice, the chip may be reset at voltages lower than these.
Data Sheet U12885EJ3V0DS00
5
µPD178076, 178078, 178096, 178098
PIN CONFIGURATION (Top View)
• 100-pin plastic QFP (14 × 20)
µPD178076GF-×××-3BA, 178078GF-×××-3BA
µPD178096GF-×××-3BA, 178098GF-×××-3BA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
P00/INTP0
P01/INTP1
P20/SI1
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P06/INTP6
P05/INTP5
P04/INTP4
P124
P123
P122
P121 /RX0
P120 /TX0
P77
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P70/SI3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P76
P75[/TXD0]
P74[/RXD0]
P137
P136
P135
P134
P133
P132
P131/TO51
P130/TO50
P37/BUZ
P36/BEEP0
P35/TI51
P34/TI50
P33/TI01
P32/TI00
P31/TO0
P30/VM45
P03/INTP3
P02/INTP2
P71/SO3
P72/SCK3
P73
P50
P51
P52
P53
P54
P55
P56
P57
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
AVDD
P14/ANI4
P15/ANI5
P16/ANI6
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
6
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Cautions 1. Directly connect the IC (Internally Connect) pin to GND0, GND1, or GND2.
2. Keep the voltage at AVDD, VDDPORT, and VDDPLL pins same as that at the VDD pin.
3. Keep the voltage at AVSS, GNDPORT, and GNDPLL pins same as that at GND0, GND1, or
GND2.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.
Remark [ ] : µPD178076 and 178078 only
{ }: µPD178096 and 178098 only
Pin Name
P130-P137
REGCPU
REGOSC
RESET
RXD0Note 1
RX0Note 2
SB0, SB1
: Port 13
AMIFC
: AM intermediate frequency counter
input
: Regulator for CPU power supply
: Regulator for oscillation circuit
: Reset input
ANI0-ANI7
AVDD
: A/D converter input
: A/D converter power supply
: A/D converter ground
: Busy output
: Buzzer output
: Error out output
: FM intermediate frequency counter
input
: UART0 serial data input
: IEBus serial data input
: Serial data bus input/output
AVSS
BUSY
BEEP0, BUZ
EO0, EO1
FMIFC
SCK0, SCK1, SCK3 : Serial clock input/output
SCL
: Serial clock input/output
: Serial data input/output
: Serial data input
SDA0, SDA1
SI0, SI1, SI3
GNDPLL
GND0-GND2
IC
: PLL ground
: Ground
SO0, SO1, SO3 : Serial data output
STB
: Strobe output
: Internally connected
: Interrupt input
: Port 0
TI00, TI01
TI50, TI51
TO0
: 16-bit timer capture trigger input
: 8-bit timer clock input
: 16-bit timer output
INTP0-INTP7
P00-P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P77
P100-P102
P120-P124
: Port 1
TO50, TO51
TXD0Note 1
TX0Note 2
VCOL, VCOH
VDDPORT
VDDPLL
: 8-bit timer output
: Port 2
: UART0 serial data output
: IEBus serial data output
: Local oscillation input
: Port power supply
: Port 3
: Port 4
: Port 5
: Port 6
: PLL power supply
: Port 7
VDD
: Power supply
: Port 10
VM45
: VDD = 4.5 V monitor output
: Crystal resonator
: Port 12
X1, X2
Notes 1. µPD178076 and 178078 only
2. µPD178096 and 178098 only
Data Sheet U12885EJ3V0DS00
7
µPD178076, 178078, 178096, 178098
BLOCK DIAGRAM
(1) µPD178076, 178078
TO0/P31
TI00/P32
TI01/P33
16-bit TIMER/
EVENT COUNTER
8
8
8
8
8
8
8
8
3
5
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT10
PORT 12
PORT 13
P00-P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P77
P100-P102
P120-P124
P130-P137
TI50/P34
TO50/P130
8-bit TIMER/
EVENT COUNTER 50
TI51/P35
TO51/P131
8-bit TIMER/
EVENT COUNTER 51
WATCHDOG TIMER
BASIC TIMER
ROM
PD178078
: 60 Kbyte
PD178076
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
78K/0
CPU
CORE
µ
SERIAL
INTERFACE 0
µ
: 48 Kbyte
SI1/P20
SO1/P21
SCK1/P22
STB/P23
SERIAL
INTERFACE 1
BUSY/P24
SI3/P70
SO3/P71
SERIAL
INTERFACE 3
RAM
PD178078
: 3 Kbyte
PD178076
µ
SCK3/P72
µ
TXD0/P75
RXD0/P74
: 2 Kbyte
UART0
8
INTP0/P00-
8
INTERRUPT
CONTROL
INTP7/P07
ANI0/P10-
ANI7/P17
8
BEEP0/P36
BUZ/P37
A/D
CONVERTER
BUZZER OUTPUT
AVDD
AVSS
RESET
X1
RESET
CPU
X2
SYSTEM
CONTROL
PERIPHERAL
AMIFC/P101
FMIFC/P102
FREQUENCY
COUNTER
VDDPORT
GNDPORT
V
DD
EO0
EO1
PLL
VM45/P30
REGOSC
REGCPU
GND0
VCOL
VCOH
V
V
OSC
CPU
VOLTAGE
REGULATOR
PLL
VDDPLL
VOLTAGE
REGULATOR
GND1
GNDPLL
IC
GND2
8
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2) µPD178096, 178098
TO0/P31
TI00/P32
TI01/P33
16-bit TIMER/
EVENT COUNTER
8
8
8
8
8
8
8
8
3
5
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
PORT10
PORT 12
PORT 13
P00-P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P77
P100-P102
P120-P124
P130-P137
TI50/P34
TO50/P130
8-bit TIMER/
EVENT COUNTER 50
TI51/P35
TO51/P131
8-bit TIMER/
EVENT COUNTER 51
WATCHDOG TIMER
BASIC TIMER
ROM
PD178098
: 60 Kbyte
PD178096
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
78K/0
CPU
CORE
µ
SERIAL
INTERFACE 0
µ
: 48 Kbyte
SI1/P20
SO1/P21
SCK1/P22
STB/P23
SERIAL
INTERFACE 1
BUSY/P24
SI3/P70
SO3/P71
SERIAL
INTERFACE 3
RAM
PD178098
: 3 Kbyte
PD178096
µ
SCK3/P72
µ
RX0/P121
TX0/P120
: 2 Kbyte
IEBus0
8
INTP0/P00-
8
INTERRUPT
CONTROL
INTP7/P07
ANI0/P10-
ANI7/P17
8
BEEP0/P36
BUZ/P37
A/D
CONVERTER
BUZZER OUTPUT
AVDD
AVSS
RESET
X1
RESET
CPU
X2
SYSTEM
CONTROL
PERIPHERAL
AMIFC/P101
FMIFC/P102
FREQUENCY
COUNTER
VDDPORT
GNDPORT
V
DD
EO0
EO1
PLL
VM45/P30
REGOSC
REGCPU
GND0
VCOL
VCOH
V
V
OSC
CPU
VOLTAGE
REGULATOR
PLL
VDDPLL
VOLTAGE
REGULATOR
GND1
GNDPLL
IC
GND2
Data Sheet U12885EJ3V0DS00
9
µPD178076, 178078, 178096, 178098
CONTENTS
1. PIN FUNCTION LIST...................................................................................................................... 11
1.1 Port Pins .................................................................................................................................. 11
1.2 Pins Other Than Port Pins...................................................................................................... 12
1.3 I/O Circuits of Pins and Recommended Connections of Unused Pins.............................. 14
2. MEMORY SPACE ............................................................................................................................ 18
2.1 Memory Size Select Register (IMS) ....................................................................................... 19
2.2 Internal Extension RAM Size Select Register (IXS) ............................................................. 20
3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS ......................................................... 21
3.1 Ports ......................................................................................................................................... 21
3.2 Clock Generation Circuit ........................................................................................................ 22
3.3 Timers ...................................................................................................................................... 22
3.4 Buzzer Output Control Circuit ............................................................................................... 26
3.5 A/D Converter.......................................................................................................................... 27
3.6 Serial Interface ........................................................................................................................ 28
3.7 IEBus Controller (µPD178096 and 178098 only) .................................................................. 32
3.8 PLL Frequency Synthesizer................................................................................................... 35
3.9 Frequency Counter ................................................................................................................. 36
4. INTERRUPT FUNCTION ................................................................................................................. 37
5. STANDBY FUNCTION .................................................................................................................... 43
6. RESET FUNCTION.......................................................................................................................... 43
7. INSTRUCTION SET......................................................................................................................... 44
8. ELECTRICAL SPECIFICATIONS ................................................................................................... 47
9. PACKAGE DRAWING ..................................................................................................................... 63
10. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 64
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................. 65
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 67
10
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
1. PIN FUNCTION LIST
1.1 Port Pins (1/2)
Pin Name
P00-P07
I/O
Function
At Reset
Input
Shared by:
I/O
Port 0.
INTP0-INTP7
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P10-P17
Input
I/O
Port 1.
Input
Input
ANI0-ANI7
8-bit input port.
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40-47
Port 2.
SI1
8-bit I/O port.
SO1
Can be set in input or output mode in 1-bit units.
SCK1
STB
BUSY
SI0/SB0/SDA0
SO0/SB1/SDA1
SCK0/SCL
VM45
TO0
I/O
Port 3.
Input
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
TI00
TI01
TI50
TI51
BEEP0
BUZ
I/O
I/O
I/O
I/O
Port 4.
Input
Input
Input
Input
–
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P50-P57
P60-P67
Port 5.
–
–
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
Port 6.
8-bit I/O port.
Can be set in input or output mode in 1-bit units.
P70
Port 7.
SI3
P71
8-bit I/O port.
SO3
SCK3
–
P72
Can be set in input or output mode in 1-bit units.
P73
Note 1
P74
RXD0
Note 1
P75
TXD0
P76, P77
–
Data Sheet U12885EJ3V0DS00
11
µPD178076, 178078, 178096, 178098
1.1 Port Pins (2/2)
Pin Name
P100
I/O
Function
At Reset
Input
Shared by:
–
I/O
I/O
Port 10.
P101
3-bit I/O port.
AMIFC
FMIFC
P102
Can be set in input or output mode in 1-bit units.
Note 2
P120
Port 12.
Input
TX0
RX0
Note 2
P121
5-bit I/O port.
P122-P124
P130
Can be set in input or output mode in 1-bit units.
Port 13.
–
Output
Low-level
output
TO50
TO51
P131
8-bit output port.
P132-P137
N-ch open-drain output port (15 V withstand)
–
Notes 1. µPD178076 and 178078 only.
2. µPD178096 and 178098 only.
1.2 Pins Other Than Port Pins (1/2)
Pin Name
I/O
Function
At Reset
Input
Shared by:
P00-P07
INTP0-INTP7 Input
External maskable interrupt input whose valid edge
(rising edge, falling edge, or both rising and falling edges)
can be specified.
SI0
Input
Output
I/O
Serial data input to serial interface.
Input
Input
Input
P25/SB0/SDA0
P20
SI1
SI3
P70
SO0
SO1
SO3
SB0
Serial data output from serial interface.
P26/SB1/SDA1
P21
P71
Serial data input/output to/from
serial interface.
N-ch open drain I/O
P25/SI0/SDA0
P26/SO0/SDA1
P25/SI0/SB0
P26/SO0/SB1
P27/SCL
P22
SB1
SDA0
SDA1
SCK0
SCK1
SCK3
SCL
STB
I/O
Serial clock input/output to/from serial interface.
Input
P72
N-ch open drain I/O
P27/SCK0
P23
Output
Input
Strobe output for serial interface automatic transmission/
reception.
Input
Input
BUSY
Busy input for serial interface automatic transmission/
reception.
P24
VW45
TI00
TI01
TI50
TI51
Output
Input
VDD = 4.5 V monitor output
Input
Input
P30
P32
P33
P34
P35
External count clock input to 16-bit timer 0.
Input
External count clock input to 8-bit timer 50.
External count clock input to 8-bit timer 51.
Input
12
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
1.2 Pins Other Than Port Pins (2/2)
Pin Name
TO0
I/O
Function
At Reset
Input
Shared by:
P31
Output
16-bit timer 0 output.
8-bit timer 50 output.
8-bit timer 51 output.
Buzzer output.
TO50
Low-level
output
P130
P131
P36
TO51
BEEP0
BUZ
Output
Input
P37
ANI0-ANI7
EO0, EO1
Input
Analog input to A/D converter.
Input
–
P10-P17
–
Output
Error out output from charge pump of PLL frequency
synthesizer.
VCOL
Input
Inputs local oscillation frequency of PLL (in HF and MF
modes).
–
–
VCOH
AMIFC
FMIFC
Input
Input
Input
Inputs local oscillation frequency of PLL (in VHF mode).
Input to AM intermediate frequency counter.
Input to FM intermediate frequency or AM intermediate
frequency counter.
–
Input
Input
–
P101
P102
RXD0
TXD0
Input
Serial data input to asynchronous serial interface (UART0).
µPD178076 and 178078 only.
Input
Input
P74
P75
Output
Serial data output from asynchronous serial interface
(UART0). µPD178076 and 178078 only.
IEBus controller data output. µPD178096 and 178098 only.
IEBus controller data input. µPD178096 and 178098 only.
System reset input.
TX0
Output
Input
Input
Input
–
Input
P120
RX0
Input
P121
RESET
X1
–
–
–
–
–
–
–
–
Connection of crystal resonator for system clock oscillation.
X2
REGOSC
–
Regulator for oscillation circuit. Connect this pin to GND via
0.1-µF capacitor.
REGCPU
–
Regulator for CPU power supply. Connect this pin to GND
via 0.1-µF capacitor.
–
–
VDD
–
–
–
–
–
Positive power supply.
–
–
–
–
–
–
–
–
–
–
GND0-GND2
VDDPORT
GNDPORT
AVDD
Ground.
Port power supply.
Port ground.
A/D converter positive power supply. Keep voltage at this
pin same as that at VDD.
AVSS
–
A/D converter ground. Keep voltage at this pin same as
that at GND0 through GND2.
PLL positive power supply.
–
–
Note
VDDPLL
–
–
–
–
–
–
–
–
–
Note
GNDPLL
PLL ground.
IC
Internally connected. Directly connect this pin to GND0,
GND1, or GND2.
Note Connect a capacitor of about 1000 pF between the VDDPLL and GNDPLL pins.
Data Sheet U12885EJ3V0DS00
13
µPD178076, 178078, 178096, 178098
1.3 I/O Circuits of Pins and Recommended Connections of Unused Pins
Table 1-1 shows the types of the I/O circuits of the respective pins and the recommended connections of the pins
when they are not used.
For the configuration of the I/O circuit of each pin, refer to Figure 1-1.
Table 1-1. I/O Circuit Type of Each Pin (1/2)
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pin
P00/INTP0-P07/INTP7
8
I/O
Input: Individually connect them to VDD, VDDPORT, GND0
to GND2, or GNDPORT via resistor.
Output: Leave open.
P10/ANI0-P17/ANI7
25
Input
I/O
Connect them to VDD, VDDPORT, GND0 to GND2, or
GNDPORT.
P20/SI1
5-K
5
Input: Individually connect them to VDD, VDDPORT, GND0
to GND2, or GNDPORT via resistor.
Output: Leave open.
P21/SO1
P22/SCK1
P23/STB
5-K
5
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/VM45
P31/TO0
5-K
10-D
5
P32/TI00
5-K
P33/TI01
P34/TI50
P35/TI51
P36/BEEP0
P37/BUZ
5
P40-P47
P50-P57
P60-P67
P70/SI3
5-K
5
P71/SO3
P72/SCK3
P73
5-K
5
P74/RXD0
P75/TXD0
P76, P77
5-K
5
P100
P101/AMIFC
P102/FMIFC
P120/TX0
P121/RX0
P122-P124
5-K
5
14
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Table 1-1. I/O Circuit Type of Each Pin (2/2)
Pin Name
P130/TO50
I/O Circuit Type
19
I/O
Output
Recommended Connection of Unused Pin
Open these pins.
P131/TO51
P132-P137
EO0
DTS-EO1
EO1
VCOL, VCOH
REGOSC, REGCPU
DTS-AMP2
–
Input
Input
Disable PLL in software and select pull-down.
–
–
Connect these pins to GND0, GND1, or GND2 via 0.1-µF
capacitor.
RESET
AVDD
AVSS
IC
2
–
–
Connect this pin to VDD or VDDPORT.
DirectlyconnectthesepinstoGND0toGND2,orGNDPORT.
Data Sheet U12885EJ3V0DS00
15
µPD178076, 178078, 178096, 178098
Figure 1-1. I/O Circuits of Respective Pins (1/2)
Type 2
Type 5
V
DD
data
P-ch
IN/OUT
IN
output
disable
N-ch
input
enable
Schmitt trigger input with hysteresis characteristics
Type 5-K
Type 8
V
DD
V
DD
data
P-ch
data
P-ch
N-ch
IN/OUT
IN/OUT
output
disable
N-ch
output
disable
input
enable
Type 10-D
Type 19
VDD
data
P-ch
OUT
IN/OUT
open drain
N-ch
N-ch
output disable
input
enable
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
16
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 1-1. I/O Circuits of Respective Pins (2/2)
Type 25
Type DTS-EO1
VDDPLL
P-ch
N-ch
Comparator+
P-ch
DW
–
IN
VREF (Threshold voltage)
OUT
input
enable
UP
N-ch
GNDPLL
Type DTS-AMP
VDDPLL
IN
Note
GNDPLL
Note This switch is selectable in software only for the VCOL and VCOH pins.
Remark VDD and GND are the positive power supply and ground pins for all port pins. Take VDD and GND as
VDDPORT and GNDPORT.
Data Sheet U12885EJ3V0DS00
17
µPD178076, 178078, 178096, 178098
2. MEMORY SPACE
Figure 2-1 shows the memory map of the µPD178076, 178078, 178096, and 178098.
Figure 2-1. Memory Map
FFFFH
Special function registers
(SFR)
256 × 8 bits
FF00H
FEFFH
General-purpose
registers
32 × 8 bits
FEE0H
FEDFH
Internal high-speed RAM
1024 × 8 bits
FB00H
FAFFH
Cannot be used
FAE0H
Data memory
nnnnH
FADFH
Internal buffer RAM
space
Program area
32 × 8 bits
FAC0H
FABFH
1000H
0FFFH
Cannot be used
F800H
F7FFH
CALLF entry area
0800H
07FFH
Internal extension
RAMNotes 1,3
mmmmH
Program area
mmmmH–1
0080H
007FH
Cannot be usedNote 2
nnnnH+1
nnnnH
CALLT table area
Vector table area
0040H
003FH
Program
memory space
Internal ROMNotes 1, 3
0000H
0000H
Notes 1. The internal ROM and internal extension RAM capacities differ depending on the model (refer to the
table below).
Internal ROM End Address
nnnnH
Internal Extension RAM First Address
mmmmH
Target Model Name
µPD178076, 178096
µPD178078, 178098
BFFFH
EFFFH
F400H
F000H
2. The µPD178078 and 178098 do not have this unusable area.
18
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Note 3. The initial values of the memory size select register (IMS) and internal extension RAM size select
register (IXS) are CFH and 0CH, respectively. The following values must be set to the registers of
each model.
Part Number
µPD178076, 178096
µPD178078, 178098
IMS
IXS
CCH
CFH
0AH
08H
2.1 Memory Size Select Register (IMS)
This register is used to select the capacity of the internal memory.
Set CCH to this register of the µPD178076 and 178096. Set CFH to the IMS of the µPD178078 and 178098.
Use an 8-bit memory manipulation instruction to set the IMS.
This register is set to CFH at reset.
Figure 2-2. Format of Memory Size Select Register (IMS)
Symbol
7
6
5
4
0
3
2
1
0
Address
FFF0H
At reset
CFH
R/W
R/W
IMS RAM2 RAM1 RAM0
ROM3 ROM2 ROM1 ROM0
RAM2 RAM1 RAM0
Selects internal high-speed RAM capacity
1
1
0
1024 bytes
Others
Setting prohibited
RAM3 RAM2 RAM1 RAM0
Selects internal ROM capacity
1
1
1
1
0
1
0
1
48K bytes
60K bytes
Others
Setting prohibited
Data Sheet U12885EJ3V0DS00
19
µPD178076, 178078, 178096, 178098
2.2 Internal Extension RAM Size Select Register (IXS)
This register is used to select the capacity of the internal extension RAM.
Set 0AH of this register of the µPD178076 and 178096. Set 08H of the IXS of the µPD178078 and 178098.
Use an 8-bit memory manipulation instruction to set the IXS.
This register is set to 0CH at reset.
Figure 2-3. Format of Internal Extension RAM Size Select Register (IXS)
Symbol
IXS
7
0
6
0
5
0
4
3
2
1
0
Address
FFF4H
At reset
0CH
R/W
R/W
IXRAM4
I
XRAM3
I
XRAM2
I
XRAM1
I
XRAM0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
Selects internal extension RAM capacity
0
0
1
1
0
0
0
1
0
0
2048 bytes
1024 bytes
Others
Setting prohibited
20
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
3. FEATURES OF PERIPHERAL HARDWARE FUNCTIONS
3.1 Ports
The following three types of ports are available:
• CMOS input (port 1)
: 8 pins
• CMOS I/O (ports 0, 2 through 7, 10, and 12) : 64 pins
• N-ch open-drain output (port 13)
Total
: 8 pins
: 80 pins
Table 3-1. Port Functions
Name
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 10
Port 12
Port 13
Pin Name
P00-P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
P70-P77
P100-P102
P120-P124
P130-P137
Function
I/O port. Can be set in input or output mode in 1-bit units.
Input-only port.
I/O port. Can be set in input or output mode in 1-bit units.
I/O port. Can be set in input or output mode in 1-bit units.
I/O port. Can be set in input or output mode in 1-bit units.
I/O port. Can be set in input or output mode in 1-bit units.
I/O port. Can be set in input or output mode in 1-bit units.
I/O port. Can be set in input or output mode in 1-bit units.
I/O port. Can be set in input or output mode in 1-bit units.
I/O port. Can be set in input or output mode in 1-bit units.
N-ch open-drain output port.
Data Sheet U12885EJ3V0DS00
21
µPD178076, 178078, 178096, 178098
3.2 Clock Generation Circuit
The instruction execution time can be changed as follows:
• 0.32 µs/0.64 µs/1.27 µs/2.54 µs/5.08 µs (system clock: 6.3-MHz crystal resonator)
• 0.44 µs/0.89 µs/1.78 µs/3.56 µs/7.11 µs (system clock: 4.5-MHz crystal resonator)Note
Note When using the IEBus controller of the µPD178096 and 178098, the 4.5-MHz crystal resonator cannot
be used. Use the 6.3-MHz crystal resonator.
Figure 3-1. Block Diagram of Clock Generation Circuit
Prescaler
Clock to other than
peripheral hardware
X1
X2
System
clock
oscillator
Prescaler
f
X
f
2
X
f
X
f
X
f
X
22
23
24
Standby
control
circuit
Wait
control
circuit
CPU clock
(fCPU
)
3
STOP
0
0
0
0
0
PCC2 PCC1 PCC0
Processor clock control register (PCC)
Internal bus
3.3 Timers
Five timer channels are provided.
• Basic timer
: 1 channel
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watchdog timer
: 1 channel
Figure 3-2. Block Diagram of Basic Timer
6.3 MHz or
Divider circuit
INTBTM0
4.5 MHzNote
Note When using the IEBus controller of the µPD178096 and 178098, the 4.5-MHz crystal resonator cannot
be used. Use the 6.3-MHz crystal resonator.
22
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 3-3. Block Diagram of 16-Bit Timer/Event Counter
Internal bus
Capture/compare
control register 0
(CPU)
CRC02 CRC01 CRC00
INTTM00
Noise
rejection
circuit
16-bit capture/compare
register 00 (CR00)
TI01/P33
Coincidence
fX/2
fX/22
fX/26
16-bit timer counter 0
(TM0)
Clear
Output
control
circuit
TO0/P31
Coincidence
Noise
fX/23
rejection
circuit
2
Output latch
(P31)
PM31
Noise
rejection
circuit
16-bit capture/compare
register 01 (CR01)
TI00/P32
INTTM01
CRC02
PRM01PRM00
TMC03TMC02TMC01 OVF0
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
16-bit timer
mode control
register 0 (TMC0)
Timer output control
register 0 (TOC0)
Prescaler mode
register 0 (PRM0)
Internal bus
Data Sheet U12885EJ3V0DS00
23
µPD178076, 178078, 178096, 178098
Figure 3-4. Block Diagram of 8-Bit Timer/Event Counter 50
Internal bus
8-bit compare
Selector
INTTM50
register 50 (CR50)
TI50/P34
/2
Coincidence
f
X
/23
f
f
f
f
X
X
X
X
S
INV
/25
/27
/29
Q
8-bit timer counter
50 (TM50)
OVF
TO50/P130
R
f
X
/211
Clear
Output latch
(P130)
S
R
Level
inversion
3
Selector
TCE50 TMC506 TMC504 LVS50 LVR50 TMC501 TOE50
TCL502 TCL501 TCL500
Timer mode control
register 50 (TMC50)
Timer clock select
register 50 (TCL50)
Internal bus
Figure 3-5. Block Diagram of 8-Bit Timer/Event Counter 51
Internal bus
8-bit compare
register 51 (CR51)
Selector
INTTM51
TI51/P35
/2
/23
Coincidence
f
X
f
f
f
f
X
S
Q
X
X
X
/25
INV
/27
/29
8-bit timer counter
51 (TM51)
OVF
TO51/P131
R
f
X
/211
Clear
Output latch
(P131)
S
R
Level
inversion
3
Selector
TCE51 TMC516 TMC514 LVS51 LVR51 TMC511 TOE51
TCL512 TCL511 TCL510
Timer mode control
register 51 (TMC51)
Timer clock select
register 51 (TCL51)
Internal bus
24
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 3-6. Block Diagram of Watchdog Timer
INTWDT
RESET
Clock input
control circuit
Divided clock
select circuit
f
/28
X
Divider circuit
Output
control
circuit
RUN
Division mode
select circuit
3
WDT mode signal
OSTS2OSTS1OSTS0
Oscillation stabilization Watchdog timer clock
WDCS2 WDCS1 WDCS0
RUN WDTM4 WDTM3
Watchdog timer mode
register (WDTM)
time select register (OSTS) select register (WDCS)
Internal bus
Data Sheet U12885EJ3V0DS00
25
µPD178076, 178078, 178096, 178098
3.4 Buzzer Output Control Circuit
Two types of buzzer output control circuits are provided.
• BEEP0 ... 1 kHz/1.5 kHz/3 kHz/4 kHz
• BUZ
... 0.77 kHz/1.54 kHz/3.08 kHz/6.15 kHz (system clock: 6.3-MHz crystal resonator)
Figure 3-7. Block Diagram of Buzzer Output Control Circuit (BEEP0)
1 kHz
1.5 kHz
Selector
BEEP0/P36
3 kHz
4 kHz
Output latch
PM36
(P36)
BEEP BEEP BEEP BEEP0 clock select
CL02 CL01 CL00 register (BEEPCL0)
Internal bus
Figure 3-8. Block Diagram of Buzzer Output Control Circuit (BUZ)
f
f
f
f
X
X
X
X
/210
/211
/212
/213
Selector
BUZ/P37
Output latch
(P37)
PM37
Clock output
select register (CKS)
BZOE BCS1 BCS0
Internal bus
Remark fX: System clock frequency
26
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
3.5 A/D Converter
An A/D converter with a resolution of 8 bits × 8 channels is provided.
Figure 3-9. Block Diagram of A/D Converter
ANI0/P10
Sample & hold circuit
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
AVDD
AVSS
Voltage comparator
ADCS3
AVSS
Successive
approximation register
(SAR)
INTAD
Control
circuit
Control
circuit
Voltage
comparator
A/D conversion result
register 3 (ADCR3)
Power-fail compare threshold
value register 3 (PFT3)
4
ADS33 ADS32 ADS31 ADS30
ADCS3
0
FR32 FR31 FR30
0
0
0
PFEN3 PFCM3PFHRM3
Analog input channel specification
register 3 (ADS3)
A/D converter mode register 3
(ADM3)
Power-fail compare mode register 3
(PFM3)
Internal bus
Data Sheet U12885EJ3V0DS00
27
µPD178076, 178078, 178096, 178098
3.6 Serial Interface
The µPD178076 and 178078 have four serial interface channels, and the µPD178096 and 178098 have three
channels.
• Serial interface 0
• Serial interface 1
• Serial interface 3
• Serial interface UART0: µPD178076 and 178078 only
Table 3-2. Types and Functions of Serial Interfaces
Note
Function
Serial interface 0
Serial interface 1
Serial interface 3
(MSB first)
UART0
–
3-wire serial I/O mode
(MSB/LSB first
selectable)
(MSB/LSB first
selectable)
3-wire serial I/O mode with
automatic transmit/receive
function
–
(MSB/LSB first
selectable)
–
–
SBI (serial bus interface) mode
2-wire serial I/O mode
(MSB first)
(MSB first)
(MSB first)
–
–
–
–
–
–
–
–
–
–
–
–
2
I C bus mode
UART (asynchronous serial
interface) mode
(Dedicated baud
rate generator)
Note µPD178076 and 178078 only.
28
Data Sheet U12885EJ3V0DS00
Figure 3-10. Block Diagram of Serial Interface 0
Internal bus
Serial bus interface control
Serial operating mode register 0 (CSIM0)
CSIM CSIM CSIM CSIM
register 0 (SBIC0)
Slave address register 0
(SVA0)
CSIE0 COI WUP
0
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
04
03
02
01
SVAM
Coincidence
BSYE
Control circuit
CLR SET
Serial I/O shift register
(SIO0)
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
Selector
output latch
D
Q
P25
PM25
Output control
Note
Selector
Acknowledge
output circuit
PM26
Note
ACKD
CMDD
RELD
Output control
Stop condition/
P26 output latch
start condition/
acknowledge
detector
WUP
CLD
Interrupt request
signal generator
INTCSI0
µ
Serial clock
counter
SCK0/SCL/P27
PM27
Output control
1/16
divider
fX X
/22-f /29
Selector
Selector
Serial clock
control circuit
2
4
CSIM01
CSIM01
P27 output latch
CLD SIC SVAM CLC WREL WAT1 WAT0
Interrupt timing
SCL03 SCL02 SCL01 SCL00
Serial interface clock
select register 0 (SCL0)
specification register 0 (SINT0)
Internal bus
Note Example in I2C bus mode operation.
Remark Output Control performs selection between CMOS output and N-ch open drain output.
Figure 3-11. Block Diagram of Serial Interface 1
Internal bus
Automatic data transmit/
receive address pointer
register (ADTP)
Internal buffer RAM
Internal bus
Automatic data transmit/receive
interval specification register (ADTI)
Automatic data transmit/receive
control register (ADTC)
Serial operating
mode register 1 (CSIM1)
ATE
DIR1
DIR1
ADTI7 ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
RE ARLD ERCE ERR TRF STRB BUSY1 BUSY0
CSIE1 DIR1 ATE LSCK1 SCL11 SCL10
TRF
Serial I/O shift register 1
(SIO1)
SI1/P20
ADTI0-ADTI4
Coincidence
Selector
PM21
PM23
SO1/P21
P21 output latch
5-Bit counter
STB/P23
Hand-
shake
BUSY/P24
µ
ARLD
INTCSI1
Serial clock counter
SIO1 write
Clear
fX/24-fX/26
CSIE1
Selector
SCK1/P22
R
S
Q
PM22
LSCK1
P22 output latch
µPD178076, 178078, 178096, 178098
Figure 3-12. Block Diagram of Serial Interface 3
Internal bus
8
Serial I/O shift
register 3 (SIO3)
SI3/P70
PM71
SO3/P71
P71 output latch
Interrupt request
signal generation
circuit
Serial clock
counter
SCK3/P72
INTCSI3
f
f
f
X
X
X
/24
/25
/26
Serial clock
control circuit
Selector
PM72
P72 output latch
Figure 3-13. Block Diagram of Serial Interface UART0 (µPD178076 and 178078 only)
Internal bus
Asychronous serial interface
mode register 0 (ASIM0)
Receive buffer
register 0
(RXB0)
TXE0 RXE0 PS01 PS00 CL0 SL0 ISRM0
0
Asynchronous serial interface
status register 0 (ASIS0)
Receive shift
register 0
(RX0)
Transmit shift
register
(TXS0)
PE0 FE0 OVE0
RXD0/P74
TXD0/P75
Reception
control circuit
(parity check)
INTSER0
PM75
P75 output latch
INTSR0
Transmission
control circuit
(parity append)
INTST0
Baud rate
generator
fX/2-fX
/28
TPS02 TPS01 TPS00 MDL03 MDL02 MDL01 MDL00
Baud rate generator
control register 0 (BRGC0)
Internal bus
Data Sheet U12885EJ3V0DS00
31
µPD178076, 178078, 178096, 178098
3.7 IEBus Controller (µPD178096 and 178098 only)
The µPD178096 and 178098 have an IEBus controller. The functions of this IEBus controller are limited as
compared with the existing IEBus interface functions of the µPD78098 subseries.
Table 3-3 compares the interfaces of the µPD78098 subseries and µPD178098 subseries.
Table 3-3. Comparison of IEBus Interface (between µPD78098 Subseries and µPD178098 Subseries)
Item
µPD78098 Subseries IEBus
Modes 0, 1, and 2
µPD178098 Subseries IEBus
Fixed to mode 1
Communication mode
Note
Internal system clock
Internal buffer size
fX = 6.0 (6.29) MHz
fX = 6.3 MHz
Transmit buffer: 33 bytes (FIFO)
Receive buffer: 40 bytes (FIFO)
Up to 4 frames can be received.
Transmit buffer: 1 byte
Receive buffer: 1 byte
CPU processing
Communication start processing
(data setting)
Communication start processing
(data setting)
Setting and management of each
communication status
Setting and management of each
communication status
Writing data to transmit buffer
Reading data from receive buffer
Writing data per 1 byte
Reading data per 1 byte
Management of transmission such as
slave status
Management of multiple frames, re-master
request processing
Hardware processing
Bit processing (modulation/demodulation,
error detection)
Bit processing (modulation/demodulation,
error detection)
Field processing (generation/management)
Arbitration result detection
Field processing (generation/management)
Arbitration result detection
Parity processing (generation/error detection)
Automatic answering of ACK/NACK
Automatic data re-transmission processing
Automatic re-master processing
Transmission processing such as automatic
slave status
Parity processing (generation/error detection)
Automatic answering of ACK/NACK
Automatic data re-transmission processing
Multiple frame reception processing
Note The IEBus controller of the µPD178098 subseries operates at fX = 6.3 MHz, and not at fX = 4.5 MHz.
Remark fX: System clock frequency
32
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 3-14. Block Diagram of IEBus Controller (µPD178096 and 178098 only)
CPU interface block
8
12
12
12
8
8
8
8
8
8
8
8
BCR0 (8)
UAR (12)
SAR (12)
PAR (12)
CDR (8) DLR (8)
DR (8) USR (8) ISR (8) SSR (8) SCR (8) CCR (8)
Internal registers
8
8
8
8
8
12
12
12
8
8
8
8
Internal bus
8
12
8
RX0/P121
TX0/P120
NF
MPX
PSR (8 bits)
12-bit latch
Interrupt
control
circuit
INT request
TX/RX
Comparator
Parity generation
error detection
Collision
detection
Interrupt control block
MPX
ACK
generation
IEBus interface block
5
Internal bus R/W
CLK
Field processing block
Bit processing block
Data Sheet U12885EJ3V0DS00
33
µPD178076, 178078, 178096, 178098
The IEBus mainly consists of the following six internal blocks:
• CPU interface block
• Interrupt control block
• Internal registers
• Bit processing block
• Field processing block
• IEBus interface block
<CPU interface block>
This block interfaces between the CPU (78K/0) and IEBus.
<Interrupt control block>
This block passes interrupt request signals from the IEBus to the CPU.
<Internal registers>
These are control registers that are used to control the IEBus and settings of each field.
<Bit processing block>
This block generates and disassembles bit timing, and mainly consists of a bit sequence ROM, 8-bit preset timer,
and decision unit.
<Field processing block>
This block generates each field in a communication frame and mainly consists of a field sequence ROM, 4-bit
down counter, and decision unit.
<IEBus interface block>
This is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, collision
detector, parity detector, parity generation circuit, and ACK/NACK generation circuit.
34
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
3.8 PLL Frequency Synthesizer
Figure 3-15. Block Diagram of PLL Frequency Synthesizer
Internal bus
PLL
PLL mode
Select register
(PLLMD)
data transfer
register (PLLNS)
VCOH VCOL PLL PLL
PLL data register
PLL
NS0
DMD DMD MD1 MD0 (PLLRL, PLLRH, PLLR0)
2
2
f
N
VCOH
VCOL
EO1
EO0
Phase
Mixer
Input select
block
Programmable
divider
comparator
- DET)
Charge pump
(
φ
f
r
6.3 MHz
or
Reference
frequency
generator
Unlock
F/F
Note 1
4.5 MHzNote 2
Voltage control
generator
4
Note 1
Lowpass filter
PLL PLL PLL PLL
RF3 RF2 RF1 RF0
PLL
UL0
PLL reference
mode register
(PLLRF)
PLL unlock
F/F Judge register
(PLLUL)
Internal bus
Notes 1. These are external circuits.
2. When the IEBus controller of the µPD178096 and 178098 is used, the 4.5-MHz crystal resonator
cannot be used. Use the 6.3-MHz crystal resonator.
Data Sheet U12885EJ3V0DS00
35
µPD178076, 178078, 178096, 178098
3.9 Frequency Counter
Figure 3-16. Block Diagram of Frequency Counter
2
Gate time
control block
FMIFC/P102
AMIFC/P101
IF counter
register
(IFCR)
block
Start/stop
control
block
Input select
block
2
IFC IFC IFC IFC
MD1 MD0 CK1 CK0
IFC
JG0
IFC IFC
ST RES
IF counter
IF counter
gate judge
register
IF counter
control
register (IFCCR)
mode select
register (IFCMD)
Internal bus
36
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
4. INTERRUPT FUNCTION
(1) µPD178076 and 178078
The µPD178076 and 178078 have the following three types and 22 sources of interrupts:
• Non-maskable : 1Note
• Maskable
• Software
: 21Note
: 1
Note Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and
either of them can be selected.
Table 4-1. Interrupt Sources (µPD178076 and 178078) (1/2)
Vector
Table
Basic
Interrupt Source
Trigger
Default
Priority
Internal/
External
Interrupt Type
Non-maskable
Maskable
Configuration
Note 1
Note 2
Name
INTWDT Overflow of watchdog timer
(when watchdog timer mode 1 is selected)
INTWDT Overflow of watchdog timer
(when interval timer mode is selected)
Pin input edge detection
Address Type
–
0
Internal
0004H
(A)
(B)
(C)
1
2
3
4
5
6
7
8
9
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
External
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
INTCSI0 End of transfer by serial interface 0
INTCSI1 End of transfer by serial interface 1
INTCSI3 End of transfer by serial interface 3
Internal
(B)
10
11
12
INTTM50 Generation of coincidence signal of 8-bit
timer/event counter 50
13
INTTM51 Generation of coincidence signal of 8-bit
timer/event counter 51
001EH
14
15
16
INTSER0 Reception error of serial interface UART0
0020H
0022H
0024H
INTSR0
INTST0
End of reception by serial interface UART0
End of transmission by serial interface
UART0
17
INTBTM0 Generation of coincidence signal of basic
timer
0026H
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
Data Sheet U12885EJ3V0DS00
37
µPD178076, 178078, 178096, 178098
Table 4-1. Interrupt Sources (µPD178076 and 178078) (2/2)
Vector
Table
Basic
Interrupt Source
Trigger
Default
Priority
Internal/
External
Interrupt Type
Maskable
Configuration
Note 1
Name
Note 2
Address Type
18
INTTM00 Generation of signal indicating coincidence Internal
between 16-bit timer counter (TM0) and
0028H
(B)
capture/compare register (CR00) (when
CR00 is used as compare register)
Detection of input edge of TI00/P32 pin
(when CR00 is used as capture register)
External
(D)
(B)
19
INTTM01 Generation of signal indicating coincidence Internal
between 16-bit timer counter (TM0) and
002AH
capture/compare register (CR01) (when
CR01 is used as compare register)
Detection of input edge of TI01/P33 pin
(when CR01 is used as capture register)
External
–
(D)
Note 3
Note 3
20
21
22
–
–
–
–
–
–
INTAD
BRK
End of conversion by A/D converter
Execution of BRK instruction
Internal
–
0030H
003EH
(B)
(E)
Software
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
3. There are no interrupt sources corresponding to vector addresses 002CH and 002EH.
38
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2) µPD178096 and 178098
The µPD178096 and 178098 have the following three types and 21 sources of interrupts:
• Non-maskable : 1Note
• Maskable
• Software
: 20Note
: 1
Note Two types of watchdog interrupt sources (INTWDT), non-maskable and maskable, are available, and
either of them can be selected.
Table 4-2. Interrupt Sources (µPD178096 and 178098) (1/2)
Vector
Table
Basic
Interrupt Source
Trigger
Default
Priority
Internal/
External
Interrupt Type
Non-maskable
Maskable
Configuration
Note 1
Note 2
Name
Address Type
–
0
INTWDT
Overflow of watchdog timer
Internal
0004H
(A)
(B)
(C)
(when watchdog timer mode 1 is selected)
INTWDT
Overflow of watchdog timer
(when interval timer mode is selected)
1
2
3
4
5
6
7
8
9
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
INTCSI0
INTCSI1
INTCSI3
Pin input edge detection
External
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
End of transfer by serial interface 0
End of transfer by serial interface 1
End of transfer by serial interface 3
Internal
(B)
10
11
12
INTTM50 Generation of coincidence signal of 8-bit
timer/event counter 50
13
INTTM51 Generation of coincidence signal of 8-bit
timer/event counter 51
001EH
Note 3
Note 3
Note 3
14
15
16
17
–
–
–
–
–
–
–
–
INTBTM0 Generation of coincidence signal of basic
timer
Internal
0026H
(B)
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
3. There are no interrupt sources corresponding to vector addresses 0020H, 0022H, and 0024H.
Data Sheet U12885EJ3V0DS00
39
µPD178076, 178078, 178096, 178098
Table 4-2. Interrupt Sources (µPD178096 and 178098) (2/2)
Vector
Table
Basic
Interrupt Source
Trigger
Default
Priority
Internal/
External
Interrupt Type
Maskable
Configuration
Note 1
Name
Note 2
Address Type
18
INTTM00 Generation of signal indicating coincidence Internal
between 16-bit timer counter (TM0) and
0028H
(B)
capture/compare register (CR00) (when
CR00 is used as compare register)
Detection of input edge of TI00/P32 pin
(when CR00 is used as capture register)
External
(D)
(B)
19
INTTM01 Generation of signal indicating coincidence Internal
between 16-bit timer counter (TM0) and
002AH
capture/compare register (CR01) (when
CR01 is used as compare register)
Detection of input edge of TI01/P33 pin
(when CR01 is used as capture register)
External
Internal
(D)
(B)
20
21
INTIE1
INTIE2
IEBus0 data access request
002CH
002EH
IEBus0 communication error and start/end
of communication
22
–
INTAD
BRK
End of conversion by A/D converter AD1
Execution of BRK instruction
0030H
003EH
(B)
(E)
Software
–
Notes 1. If two or more maskable interrupts occur at the same time, they are acknowledged or kept pending
according to their default priorities. The default priority 0 is the highest, while 22 is the lowest.
2. (A) to (E) under the heading Basic Configuration Type corresponds to (A) to (E) in Figure 4-1.
40
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Figure 4-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
address generation
circuit
Interrupt
request
Priority control
circuit
Standby release
signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Vector table
address generation
circuit
Priority control
circuit
Interrupt
request
IF
Standby release
signal
(C) External maskable interrupt (INTP0 through INTP7)
Internal bus
External interrupt
rising/falling edge enable
registers (EGP, EGN)
MK
IE
PR
ISP
Vector table
address generation
circuit
Priority control
circuit
Edge detection
circuit
Interrupt
request
IF
Standby release
signal
Data Sheet U12885EJ3V0DS00
41
µPD178076, 178078, 178096, 178098
Figure 4-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupts (INTTM00, INTTM01)
Internal bus
Prescaler mode register
(PRM0)
MK
IE
PR
ISP
Vector table
address generation
circuit
Priority control
circuit
Interrupt
request
Edge detection
circuit
IF
Standby release
signal
(E) Software interrupt
Internal bus
Vector table
address generation
circuit
Interrupt
request
Priority control
circuit
Remark IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
42
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
5. STANDBY FUNCTION
There are the following two standby functions to reduce the system power consumption.
• HALT mode : The CPU operating clock is stopped.
The average consumption current can be reduced by intermittent operation in combination with
the normal operating mode.
• STOP mode : The system clock oscillation is stopped. All operations by the system clock are stopped and
current consumption can be considerably reduced.
Figure 5-1. Standby Function
System Clock Operation
HALT
Instruction
STOP
Instruction
Interrupt
Request
Interrupt
Request
HALT Mode
STOP Mode
(System clock
oscillation stopped)
(Clock supply to CPU is
stopped, oscillation
continued)
6. RESET FUNCTION
There are the following three reset methods.
• External reset input by RESET pin
• Internal reset by watchdog timer hang-up time detection
• Internal reset by Power-On Clear (POC).
Data Sheet U12885EJ3V0DS00
43
µPD178076, 178078, 178096, 178098
7. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR,
ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
Operand
[HL + byte]
[HL + B]
[HL + C]
#byte
A
r Note
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
First
Operand
A
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
ROL
RORC
ROLC
ADDC ADDC
SUB SUB
SUBC SUBC
ADDC ADDC
SUB SUB
SUBC SUBC
XOR
CMP
AND
OR
AND
OR
AND
OR
AND
OR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
DBNZ
DBNZ
B,C
sfr
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL + byte]
[HL + B]
[HL + C]
X
C
MULU
DIVUW
Note Except r = A
44
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
#word
ADDW
AX
rp Note
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
First Operand
AX
MOVW
XCHW
MOVW
MOVW
SUBW
CMPW
rp
MOVW
MOVW Note
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp = BC, DE or HL
Data Sheet U12885EJ3V0DS00
45
µPD178076, 178078, 178096, 178098
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
MOV1
$addr16
BT
None
SET1
First Operand
A.bit
BF
CLR1
BTCLR
sfr.bit
MOV1
MOV1
MOV1
BT
SET1
CLR1
BF
BTCLR
BT
saddr.bit
PSW.bit
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
[HL].bit
CY
MOV1
BT
SET1
CLR1
BF
BTCLR
MOV1
MOV1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
SET1
CLR1
NOT1
AND1
OR1
AND1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
(4) Call instruction/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
First Operand
Basic instruction
BR
CALL
BR
BR, BC, BNC
BZ, BNZ
Compound
instruction
BT, BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
46
Data Sheet U12885EJ3V0DS00
µPD178076,178078,178096,178098
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
VDD
VDDPORT
AVDD
VDDPLL
VI
–0.3 to +6.0
–0.3 to VDD + 0.3Note 1
–0.3 to VDD + 0.3Note 1
–0.3 to VDD + 0.3Note 1
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
16
V
V
V
V
V
V
V
Input voltage
Output voltage
Output breakdown
voltage
VO
Excluding P130 to P137
VBDS
P130-P137
N-ch open drain
Analog input voltage
High-level output
current
VAN
P10-P17
1 pin
Analog input pin
–0.3 to VDD + 0.3
V
IOH
–8
mA
mA
mA
Total of P00-P01, P20-P27, P50-P57, and P70-P73
Total of P02-P07, P30-P37, P40-P47, P60-P67,
P74-P77, and P120-P124
–15
–15
Total of P100-P102
–10
16
8
mA
mA
mA
mA
mA
mA
mA
Note 2
Low-level output
current
IOL
1 pin
Peak value
r.m.s
Total of P00-P01, P20-P27, P50-P57, Peak value
and P70-P73 r.m.s
30
15
30
15
Total of P02-P07, P30-P37, P40-P47, Peak value
P60-P67, P74-P77, P120-P124, and r.m.s
P130-P137
Total of P100-102
Peak value
r.m.s
20
mA
mA
°C
10
Operating temperature
Storage temperature
TA
–40 to +85
–55 to +125
Tstg
°C
Notes 1. Keep the voltage at VDDPORT, AVDD, and VDDPLL same as that at the VDD pin.
2. Calculate the r.m.s as follows: [r.m.s] = [Peak value] x √Duty
Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality
of the product may be degraded. The absolute maximum ratings, therefore, are the values
exceeding which the product may be physically damaged. Be sure to use the product with these
ratings never being exceeded.
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Data Sheet U12885EJ3V0DS00
47
µPD178076,178078,178096,178098
Recommended Supply Voltage Ranges (TA = –40 to +85°C)
Parameter
Symbol
VDD1
Conditions
When CPU and PLL are operating
When CPU is operating and PLL is stopped
When crystal oscillation stops
MIN.
4.5
TYP.
5.0
MAX.
5.5
Unit
V
Supply voltage
VDD2
3.5
5.0
5.5
V
Data retention voltage
Output breakdown
voltage
VDDR
2.3
5.5
V
VBDS
P130-P137 (N-ch open drain)
15
V
DC Characteristics (TA = –40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
V
High-level input
voltage
VIH1
P10-P17, P21, P23, P30, P31, P36, P37, P40-P47,
P50-P57, P60-P67, P71, P73, P75-P77, P100-P102,
0.7 VDD
VDD
P120, P122-P124
VIH2
P00-P07, P20, P22, P24-P27, P32-P35, P70, P72,
P74, P121, RESET
0.8 VDD
0
VDD
V
V
Low-level input
voltage
VIL1
P10-P17, P21, P23, P30, P31, P36, P37, P40-P47,
P50-P57, P60-P67, P71, P73, P75-P77, P100-P102,
P120, P122-P124
0.3 VDD
VIL2
P00-P07, P20, P22, P24-P27, P32-P35, P70, P72,
P74, P121, RESET
0
0.2 VDD
V
High-level output
voltage
VOH1
P00-P07, P20-P24, P30-P37, 4.5 V ≤ VDD ≤ 5.5 V,
VDD – 1.0
VDD – 0.5
VDD – 1.0
V
V
P40-P47, P50-P57, P60-P67, IOH = –1 mA
P70-P77, P100-P102,
P120-P124
3.5 V ≤ VDD < 4.5 V,
IOH = –100 µA
VOH2
VOH1
EO0, EO1
VDD = 4.5 to 5.5 V,
IOH = –3 mA
V
Low-level output
voltage
P00-P07, P20-P27, P30-P37, 4.5 V ≤ VDD ≤ 5.5 V,
1.0
0.5
1.0
3
V
P40-P47, P50-P57, P60-P67, IOL = 1 mA
P70-P77, P100-P102,
P120-P124, P130-P137,
3.5 V ≤ VDD < 4.5 V,
V
IOL = 100 µA
VOL2
ILIH
EO0, EO1
VDD = 4.5 to 5.5 V,
IOL = 3 mA
V
High-level input
leakage current
P00-P07, P10-P17,
P20-P24, P30-P37,
VI = VDD
µA
P40-P47, P50-P57,
P60-P67, P70-P77,
P100-P102, P120-P124,
RESET
Remark Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Data Sheet U12885EJ3V0DS00
48
µPD178076,178078,178096,178098
DC Characteristics (TA = –40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
–3
Unit
Low-level input
leakage current
ILIL
P00-P07, P10-P17,
P20-P27, P30-P37,
P40-P47, P50-P57,
P60-P67, P70-P77,
VI = 0 V
µA
P100-P102, P120-P124,
RESET
Output off
ILOH1
ILOL1
ILOH2
P130-P137
P130-P137
VO = 15 V
VO = 0 V
VO = VDD
–3
3
µA
µA
µA
leakage current
P25-P27
–3
(at N-ch open drain I/O)
ILOL2
P25-P27
VO = 0 V
3
µA
(at N-ch open drain I/O)
ILOH3
ILOL3
IDD1
EO0, EO1
EO0, EO1
VO = VDD
VO = 0 V
–3
3
µA
µA
Note
Supply current
When CPU is operating
and PLL is stopped.
Sine wave input to X1 pin
VI = VDD
fx = 4.5 MHz
2.5
4.0
15
mA
(µPD178076, 178078)
IDD2
fx = 6.3 MHz
20
mA
(µPD178076, 178078,
178096, 178098)
IDD3
In HALT mode with PLL
stopped.
fx = 4.5 MHz
0.2
0.3
0.8
1.0
mA
mA
(µPD178076, 178078)
Sine wave input to X1 pin
VI = VDD
IDD4
fx = 6.3 MHz
(µPD178076, 178078,
178096, 178098)
VDDR1
VDDR2
When crystal resonator is oscillating
3.5
2.2
5.5
V
V
Data retention
voltage
When crystal oscillation is
stopped
Power-failure detection
function
VDDR3
IDDR1
Data memory retained
2.0
V
Data retention
current
When crystal oscillation is
stopped
TA = 25°C,
2.0
2.0
4.0
20
µA
VDD = 5 V
IDDR2
µA
Note Excluding AVDD current and VDDPLL current.
Remarks 1. fX: System clock oscillation frequency
2. Unless otherwise specified, the characteristics of a multiplexed pin are the same as those of the
corresponding port pin.
Data Sheet U12885EJ3V0DS00
49
µPD178076,178078,178096,178098
Reference Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
5
MAX.
Unit
mA
Supply current
IDD5
When CPU and PLL are operating.
Sine wave input to VCOH pin
At fIN = 160 MHz, VIN = 0.15 VP-P
AC Characteristics
(1) Basic operation (TA = –40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Cycle time
Symbol
Conditions
MIN.
0.32
0.44
TYP.
MAX.
5.08
7.11
Unit
µs
TCY
At fX = 6.3 MHz
At fX = 4.5 MHz
Note 1
(minimum instruction
execution time)
µs
TI00, TI01 input
high-/low-level
widths
tTIH0,
tTIL0
4/fsamNote 2
s
TI50, TI51 input
frequency
fTI5
2
MHz
ns
TI50, TI51 input
high-/low-level
widths
tTIH5,
tTIL5
200
1
Interrupt input
high-/low-level
widths
tINTH,
tINTL
INTP0-INTP7
µs
µs
RESET pin
tRSL
10
low-level width
Notes 1. When the IEBus controller of the µPD178096 and 178098 is used, the 4.5-MHz crystal resonator
cannot be used. Use the 6.3-MHz crystal resonator.
2. fsam = fX/2, fX/4, fX/64 selectable by bits 0 and 1 (PRM00 and PRM01) of the prescaler mode register
0 (PRM0). However, fsam = fX/8 when the valid edge of TI00 is selected as the count clock.
Data Sheet U12885EJ3V0DS00
50
µPD178076,178078,178096,178098
(2) Serial interface (TA = –40 to +85°C, VDD = 3.5 to 5.5 V)
(a) Serial interface 0
(i) 3-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
Symbol
Test Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tKCY1
1600
SCK0 high-/low-level width
tKH1,
tKL1
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKCY1/2 – 50
t
KCY1/2 – 100
100
SI0 setup time (to SCK0
↑
)
tSIK1
150
SI0 hold time (from SCK0
↑
)
tKSI1
400
SO0 output delay time from SCK0↓
tKSO1
C = 100 pF Note
300
Note C is the load capacitance of SCK0 and SO0 output line.
(ii) 3-wire serial I/O mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
Symbol
Test Conditions
VDD = 4.5 to 5.5 V
MIN.
800
1600
400
800
100
400
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tKCY2
SCK0 high-/low-level width
tKH2,
tKL2
VDD = 4.5 to 5.5 V
SI0 setup time (to SCK0
SI0 hold time (from SCK0
SO0 output delay time from SCK0↓
↑
)
tSIK2
tKSI2
tKSO2
↑
)
C = 100 pF Note
300
SCK0 at rising or falling edge time tR2, tF2
1000
Note C is the load capacitance of SO0 output line.
Data Sheet U12885EJ3V0DS00
51
µPD178076,178078,178096,178098
(iii) SBI mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
Symbol
Test Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY3
3200
SCK0 high-/low-level width
tKH3,
tKL3
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKCY3/2 – 50
t
KCY3/2 – 150
100
SB0, SB1 setup time (to SCK0
↑
)
tSIK3
300
SB0, SB1 hold time (from SCK0↑)
tKSI3
tKCY3/2
0
SB0, SB1 output delay time from
tKSO3
R = 1 kΩ
VDD = 4.5 to 5.5 V
250
SCK0↓
C = 100 pF Note
0
1000
SB0, SB1↓ from SCK0
↑
tKSB
tSBK
tSBH
tSBL
tKCY3
tKCY3
tKCY3
tKCY3
SCK0↓ from SB0, SB1↓
SB0, SB1 high-level width
SB0, SB1 low-level width
Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(iv) SBI mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
Symbol
Test Conditions
VDD = 4.5 to 5.5 V
MIN.
800
3200
400
1600
100
300
tKCY4/2
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY4
SCK0 high-/low-level width
tKH4,
tKL4
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
SB0, SB1 setup time (to SCK0
↑
)
tSIK4
SB0, SB1 hold time (from SCK0↑)
tKSI4
SB0, SB1 output delay time from
tKSO4
R = 1 kΩ
VDD = 4.5 to 5.5 V
250
SCK0↓
C = 100 pF Note
0
1000
SB0, SB1↓ from SCK0
↑
tKSB
tSBK
tSBH
tSBL
tKCY4
tKCY4
tKCY4
tKCY4
SCK0↓ from SB0, SB1↓
SB0, SB1 high-level width
SB0, SB1 low-level width
SCK0 at rising or falling edge time tR4, tF4
1000
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line.
Data Sheet U12885EJ3V0DS00
52
µPD178076,178078,178096,178098
(v) 2-wire serial I/O mode (SCK0 ... internal clock output)
Parameter
SCK0 cycle time
Symbol
tKCY5
tKH5
Test Conditions
MIN.
1600
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
R = 1 kΩ
C = 100 pF Note
SCK0 high-level width
SCK0 low-level width
t
KCY5/2 – 160
tKL5
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKCY5/2 – 50
tKCY5/2 – 100
300
SB0, SB1 setup time (to SCK0
↑
)
tSIK5
350
SB0, SB1 hold time (from SCK0↑)
tKSI5
600
SB0, SB1 output delay time from
tKSO5
0
300
SCK0↓
Note R and C are the load resistance and load capacitance of SCK0, SB0 and SB1 output line.
(vi) 2-wire serial I/O mode (SCK0 ... external clock input)
Parameter
SCK0 cycle time
Symbol
tKCY6
tKH6
Test Conditions
MIN.
1600
650
800
100
tKCY6/2
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 high-level width
SCK0 low-level width
tKL6
SB0, SB1 setup time (to SCK0
↑
)
tSIK6
SB0, SB1 hold time (from SCK0↑)
tKSI6
SB0, SB1 output delay time from
tKSO6
R = 1 kΩ
C = 100 pF Note
VDD = 4.5 to 5.5 V
300
500
SCK0↓
0
SCK0 at rising or falling edge time tR6, tF6
1000
Note R and C are the load resistance and load capacitance of SB0 and SB1 output line.
Data Sheet U12885EJ3V0DS00
53
µPD178076,178078,178096,178098
(vii) I2C Bus mode (SCL ... internal clock output)
Parameter
SCL cycle time
Symbol
tKCY7
tKH7
Test Conditions
MIN.
10
TYP.
MAX.
Unit
µs
ns
R = 1 kΩ
C = 100 pF Note
SCL high-level width
tKCY7 – 160
tKCY7 – 50
200
SCL low-level width
tKL7
ns
SDA0, SDA1 setup time (to SCL↑)
tSIK7
ns
SDA0, SDA1 hold time
tKSI7
0
ns
(from SCL↓)
SDA0, SDA1 output delay time
tKSO7
tKSB
VDD = 4.5 to 5.5 V
0
0
300
500
ns
ns
ns
(from SCL↓)
SDA0, SDA1↓ from SCL
↑
↑
or
200
SDA0, SDA1 from SCL
↑
SCL↓ from SDA0, SDA1↓
SDA0, SDA1 high-level width
tSBK
400
500
ns
ns
tSBH
Note R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line.
(viii) I2C Bus mode (SCL ... external clock input)
Parameter
SCL cycle time
Symbol
tKCY8
Test Conditions
MIN.
1000
400
200
0
TYP.
MAX.
Unit
ns
SCL high-/low-level width
tKH8, tKL8
tSIK8
ns
SDA0, SDA1 setup time (to SCL↑)
ns
SDA0, SDA1 hold time
tKSI8
ns
(from SCL↓)
SDA0, SDA1 output delay time
tKSO8
tKSB
R = 1 kΩ
C = 100 pF Note
VDD = 4.5 to 5.5 V
0
0
300
500
ns
ns
ns
from SCL↓
SDA0, SDA1↓ from SCL
↑
or
200
SDA0, SDA1↑ from SCL↑
SCL↓ from SDA0, SDA1↓
tSBK
tSBH
400
500
ns
ns
ns
SDA0, SDA1 high-level width
SCL at rising or falling edge time
tR8, tF8
1000
Note R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
Data Sheet U12885EJ3V0DS00
54
µPD178076,178078,178096,178098
(b) Serial interface 1
(i) 3-wire serial I/O mode (SCK1 ... internal clock output)
Parameter
SCK1 cycle time
SCK1 high/low-level width
Symbol
Test Conditions
MIN.
800
TYP.
MAX.
Unit
ns
tKCY9
tKH9,
tKL9
tKCY9/2 – 50
ns
SI1 setup time (to SCK1
SI1 hold time (from SCK1
SO1 output delay time (from SCK1↓)
↑
)
tSIK9
tKSI9
tKSO9
100
400
ns
ns
ns
↑
)
C = 100 pF Note
300
Note C is the load capacitance of SCK1 and SO1 output line.
(ii) 3-wire serial I/O mode (SCK1 ... external clock input)
Parameter
SCK1 cycle time
SCK1 high/low-level width
Symbol
Test Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
tKCY10
tKH10,
tKL10
ns
SI1 setup time (to SCK1
SI1 hold time (from SCK1
SO1 output delay time (from SCK1↓
↑
)
tSIK10
tKSI10
tKSO10
100
400
ns
ns
ns
ns
↑
)
)
C = 100 pF Note
300
SCK1 at rising or falling edge time tR10, tF10
1000
Note C is the load capacitance of SO1 output line.
Data Sheet U12885EJ3V0DS00
55
µPD178076,178078,178096,178098
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... internal clock
output)
Parameter
SCK1 cycle time
SCK1 high/low-level width
Symbol
Test Conditions
MIN.
800
TYP.
MAX.
Unit
ns
tKCY11
tKH11,
tKCY11/2 – 50
ns
tKL11
SI1 setup time (to SCK1
SI1 hold time (from SCK1
SO1 output delay time (from SCK1↓
STB from SCK1
↑
)
tSIK11
tKSI11
tKSO11
tSBD
100
400
ns
ns
ns
ns
ns
ns
↑
)
)
C = 100 pF Note
300
↑
↑
tKCY11/2 – 100
tKCY11/2 – 30
100
tKCY11/2 + 100
tKCY11/2 + 30
Strobe signal high-level width
tSBW
Busy signal setup time
tBYS
(to busy signal detection timing)
Busy signal hold time
(from busy signal detection timing)
tBYH
100
200
ns
ns
SCK1 from busy inactive
↓
tSPS
Note C is the load capacitance of SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1 ... external clock
input)
Parameter
SCK1 cycle time
SCK1 high/low-level width
Symbol
Test Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
tKCY12
tKH12,
tKL12
ns
SI1 setup time (to SCK1
SI1 hold time (from SCK1
SO1 output delay time (from SCK1↓
↑
)
tSIK12
tKSI12
tKSO12
100
400
ns
ns
ns
ns
↑
)
)
C = 100 pF Note
300
SCK1 at rising or falling edge time tR12, tF12
1000
Note C is the load capacitance of SO1 output line.
Data Sheet U12885EJ3V0DS00
56
µPD178076,178078,178096,178098
(c) Serial interface 3
(i) 3-wire serial I/O mode (SCK3 ... internal clock output)
Parameter
SCK3 cycle time
SCK3 high/low-level width
Symbol
Test Conditions
MIN.
800
TYP.
MAX.
Unit
ns
tKCY13
tKH13,
tKL13
t
KCY13/2 – 50
ns
SI3 setup time (to SCK3
SI3 hold time (from SCK3
SO3 output delay time (from SCK3↓)
↑
)
tSIK13
tKSI13
tKSO13
100
400
ns
ns
ns
↑
)
C = 100 pF Note
300
Note C is the load capacitance of SCK3 and SO3 output line.
(ii) 3-wire serial I/O mode (SCK3 ... external clock input)
Parameter
SCK3 cycle time
SCK3 high/low-level width
Symbol
Test Conditions
MIN.
800
400
TYP.
MAX.
Unit
ns
tKCY14
tKH14,
tKL14
ns
SI3 setup time (to SCK3
SI3 hold time (from SCK3
SO3 output delay time (from SCK3↓
↑
)
tSIK14
tKSI14
tKSO14
100
400
ns
ns
ns
ns
↑
)
)
C = 100 pF Note
300
SCK3 at rising or falling edge time tR14, tF14
1000
Note C is the load capacitance of SO3 output line.
(d) Serial interface UART0 (Dedicated baud rate generator output)Note
Parameter
Transfer rate
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
bps
38400
Note µPD178076 and 178078 only.
Data Sheet U12885EJ3V0DS00
57
µPD178076,178078,178096,178098
AC Timing Test Point (Excluding X1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
TI Timing
t
TIL0
t
TIH0
TI00, TI01
1/fTI5
t
TIL5
t
TIH5
TI50,TI51
Interrupt Input Timing
t
INTL
t
INTH
INTP0 to INTP7
RESET Input Timing
t
RSL
RESET
Data Sheet U12885EJ3V0DS00
58
µPD178076,178078,178096,178098
Serial Transfer Timing
3-wire serial I/O mode:
t
KCYm
t
KLm
t
KHm
t
Fn
t
Rn
SCK0, SCK1, SCK3
t
SIKm
t
KSIm
SI0, SI1, SI3
Input Data
t
KSOm
SO0, SO1, SO3
Output Data
Remark m = 1, 2, 9, 10, 13, 14
n = 2, 10, 14
SBI mode (bus release signal transfer):
t
KCY3, 4
t
KL3, 4
t
KH3, 4
t
F4
t
R4
SCK0
t
SIK3, 4
t
KSB
t
SBL
t
SBK
t
SBH
t
KSI3, 4
SB0, SB1
t
KSO3, 4
Data Sheet U12885EJ3V0DS00
59
µPD178076,178078,178096,178098
SBI mode (command signal transfer):
t
KCY3, 4
t
KL3, 4
R4
t
KH3, 4
t
F4
t
SCK0
t
SIK3, 4
t
KSI3, 4
t
SBK
t
KSB
SB0, SB1
t
KSO3, 4
2-wire serial I/O mode:
t
KCY5, 6
t
KL5, 6
R6
t
KH5, 6
t
t
F6
SCK0
t
SIK5, 6
t
KSI5, 6
t
KSO5, 6
SB0, SB1
I2C bus mode:
t
F8
t
R8
t
KCY7, 8
SCL
t
KSB
t
KSB
t
SIK7, 8
t
KL7, 8
t
KSI7, 8
t
KH7, 8
t
KSO7, 8
t
SBK
SDA0, SDA1
tSBH
t
SBK
Data Sheet U12885EJ3V0DS00
60
µPD178076,178078,178096,178098
3-wire serial I/O mode with automatic transmit/receive function:
SO1
SI1
D2
D1
D0
D7
D2
D1
D0
D7
t
SIK11
,
12
t
KSI11
,
12
t
KH11
,
12
t
F12
t
KSO11 12
,
SCK1
STB
t
R12
t
SBD
t
SBW
t
KL11 12
,
t
KCY11 12
,
3-wire serial I/O mode with automatic transmit/receive function (busy processing):
10 Note
SCK1
7
8
9 Note
10 + nNote
1
t
BYS
t
BYH
t
SPS
BUSY
(Active high)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
IEBus Controller CharacteristicsNote 1 (TA = –40 to +85°C, VDD = 3.5 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
IEBus system
fs
Fixed to mode 1
6.3Note 2
MHz
clock frequency
Notes 1. µPD178096 and 178098 only.
2. Although the system clock frequency is 6.0 MHz in the IEBus standard, in these products, normal
operation is guaranteed at 6.3 MHz.
Remark 6.0 MHz and 6.3 MHz cannot both be used as the IEBus system clock frequency.
Data Sheet U12885EJ3V0DS00
61
µPD178076,178078,178096,178098
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 3.5 to 5.5 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
Total conversion
VDD = 4.5 to 5.5 V
±1.0
±1.4
45.7
VDD
%FSR
%FSR
µs
Notes 1, 2
error
Conversion time
tCONV
VIAN
15.2
0
Analog input voltage
V
Notes 1. Excluding quantization error (±0.2%FSR)
2. This value is indicated as a ratio to the full-scall value.
PLL Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Symbol
fIN1
Conditions
MIN.
0.5
10
TYP.
MAX.
3.0
Unit
MHz
MHz
MHz
MHz
VCOL pin, MF mode, sine wave input, VIN = 0.15 VP-P
VCOL pin, HF mode, sine wave input, VIN = 0.15 VP-P
VCOH pin, VHF mode, sine wave input, VIN = 0.15 VP-P
VCOH pin, VHF mode, sine wave input, VIN = 0.3 VP-P
fIN2
40
fIN3
60
130
160
fIN4
40
Remark The above values are the result of NEC’s evaluation of the device. If the device is likely to be affected
by noise in your application, it is recommended to use the device at a voltage higher than the above
values.
IFC Characteristics (TA = –40 to +85°C, VDD = 4.5 to 5.5 V)
Parameter
Operating
frequency
Symbol
Conditions
MIN.
0.4
TYP.
MAX.
0.5
Unit
fIN5
AMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
MHz
fIN6
fIN7
FMIFC pin, FMIF count mode, sine wave input,
VIN = 0.15 VP-P
10
11
MHz
MHz
FMIFC pin, AMIF count mode, sine wave input,
VIN = 0.15 VP-P
0.4
0.5
Remark The above values are the result of NEC’s evaluation of the device. If the device is likely to be affected
by noise in your application, it is recommended to use the device at a voltage higher than the above
values.
Data Sheet U12885EJ3V0DS00
62
µPD178076,178078,178096,178098
9. PACKAGE DRAWING
100-PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
S
C D
R
Q
31
30
100
1
F
G
J
M
H
I
P
K
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
23.6±0.4
20.0±0.2
14.0±0.2
17.6±0.4
0.8
0.6
0.30±0.10
0.15
J
0.65 (T.P.)
1.8±0.2
0.8±0.2
K
L
+0.10
0.15
M
−0.05
N
P
Q
R
S
0.10
2.7±0.1
0.1±0.1
5°±5°
3.0 MAX.
P100GF-65-3BA1-4
Data Sheet U12885EJ3V0DS00
63
µPD178076,178078,178096,178098
10. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended, consult NEC.
Table 10-1. Soldering Conditions for Surface-Mount Type
µPD178076GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
µPD178078GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
µPD178096GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
µPD178098GF-XXX-3BA: 100-pin plastic QFP (14 × 20)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Conditions Symbol
Package peak temperature: 235°C, Time: 30 sec max. (210°C min.),
IR35-00-3
Number of times: 3 max.
VPS
Package peak temperature: 215°C, Time: 40 sec max. (200°C min.),
VP15-00-3
WS60-00-1
Number of times: 3 max.
Wave soldering
Solder bath temperature: 260°C max., Time: 10 sec max.,
Number of times: 1, Preheating temperature: 120°C max.,
(Package surface temperature)
Partial heating
Pin temperature: 300°C max., Time: 3 sec max (per device side)
–
Caution Do not use two or more soldering methods in combination (except partial heating).
Data Sheet U12885EJ3V0DS00
64
µPD178076, 178078, 178096, 178098
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for development of systems using the µPD178078 and 178098
subseries.
Language processor software
Notes 1, 2, 3
RA78K/0
Assembler package common to 78K/0 series
Notes 1, 2, 3
Notes 1, 2, 3
CC78K/0
C compiler package common to 78K/0 series
DF178098
CC78K0-L
Device file for µPD178078 subseries and µPD178098 subseries
C compiler library source file common to 78K/0 series
Notes 1, 2, 3
Flash memory writing tools
Fashpro III
Dedicated flash programmer
(Part number:
Note 4
FL-PR3
, PG-FL3)
Note 4
FA-100GF-3BA
Flash programmer adapter
Debugging tools
• When in-circuit emulator IE-78K0-NS is used
IE-78K0-NS
In-circuit emulator common to 78K/0 series
IE-70000-MC-PS-B
IE-78K0-NS-PA
IE-70000-98-IF-C
Power supply unit for IE-78K0-NS
Performance board for enhancing and expanding the IE-78K0-NS function
Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine
(C bus supported)
IE-70000-CD-IF-A
IE-70000-PC-IF-C
PC card and interface cable necessary when a notebook-type PC is used as host machine (PCMCIA
socket supported)
TM
Interface adapter necessary when a IBM PC/AT compatible machine is used as host machine (ISA
bus supported)
IE-70000-PCI-IF
Interface adapter necessary when a PC with a PCI bus is used as host machine
Emulation board to emulate µPD178078 and 178098 subseries
Emulation probe for 100-pin plastic QFP (GF-3BA type)
Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type)
System simulator common to 78K/0 series
IE-178098-NS-EM1
Note 4
NP-100GF
EV-9200GF-100
Notes 1, 2
SM78K0
Notes 1, 2
ID78K0-NS
Integrated debugger common to 78K/0 series
Notes 1, 2, 3
DF178098
Device file for µPD178078 subseries and µPD178098 subseries
Notes 1. PC-9800 series (Japanese WindowsTM) based
2. IBM PC/AT compatible machine (Japanese/English windows) based
3. HP9000 series 700TM (HP-UXTM) based, SPARCstationTM (SunOSTM, SolarisTM) based, NEWSTM
(NEWS-OSTM) based
4. Products of Naito Densei Machida Mfg. Co., Ltd. (Tel: 044-822-3813).
Remark Use the RA78K0, CC78K0, and SM78K0 in combination with the DF178098.
Data Sheet U12885EJ3V0DS00
65
µPD178076, 178078, 178096, 178098
• When in-circuit emulator IE-78001-R-A is used
IE-78001-R-A
In-circuit emulator common to 78K/0 series
IE-70000-98-IF-C
Interface adapter necessary when PC-9800 series (except notebook type) is used as host machine
(C bus supported)
IE-70000-PC-IF-C
Interface adapter necessary when IBM PC/AT compatible machine is used as host machine (ISA
bus supported)
IE-70000-PCI-IF
IE-78000-R-SV3
IE-178098-NS-EM1
IE-78K0-R-EX1
EP-78064GF-R
EV-9200GF-100
Interface adapter necessary when a PC with a PCI bus is used as host machine
Interface adapter and cable necessary when EWS is used as host machine
Emulation board to emulate µPD178078 and 178098 subseries
Emulation probe conversion board necessary when using IE-178098-NS-EM1 on IE-78001-R-A
Emulation probe for 100-pin plastic QFP (GF-3BA type)
Socket mounted on board of target system created for 100-pin plastic QFP (GF-3BA type)
System simulator common to 78K/0 series
Notes 1, 2
SM78K0
Notes 1, 2
ID78K0
Integrated debugger common to 78K/0 series
Notes 1, 2, 3
DF178098
Device file for µPD178078 subseries and µPD178098 subseries
Real-time OS
Notes 1, 2, 3
RX78K/0
Real-time OS for 78K/0 series
OS for 78K/0 series
Notes 1, 2, 3
MX78K0
Notes 1. PC-9800 series (Japanese Windows) based
2. IBM PC/AT compatible machine (Japanese/English windows) based
3. HP9000 series 700 (HP-UX) based, SPARCstation (SunOS, Solaris) based, NEWS (NEWS-OS)
based
Remark Use the SM78K0 in combination with the DF178098.
66
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
APPENDIX B. RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Device Documents
Document No.
Title
Japanese
U12885J
English
This document
U12920E
µPD178076, 178078, 178096, 178098 Data Sheet
µPD178F098 Data Sheet
U12920J
U12790J
U12326J
U12704J
µPD178078, 178098 Subseries User’s Manual
78K/0 Series User’s Manual - Instruction
78K/0 Series Application Note
U12790E
U12326E
Basics (I)
U12704E
Development Tool Documents (User’s Manual)
Document No.
Japanese English
U11802E
Title
RA78K0 Assembler Package
CC78K0 C Compiler
Operation
U11802J
U11801J
U11789J
Assembly Language
Structured Assembly
Language
U11801E
U11789E
Operation
U11517J
U11518J
U14142J
U13731J
U14013J
EEU-934
U10181J
U10092J
U11517E
U11518E
To be prepared
U13731E
U14013E
EEU-1469
U10181E
U10092E
Language
IE-78001-R-A
IE-78K0-NS
IE-178098-NS-EM1
EP-78064
SM78K0 System Simulator Windows Based
SM78K Series System Simulator
Reference
External Parts User
Open Interface
Specifications
ID78K0 Integrated Debugger EWS Based
ID78K0 Integrated Debugger PC Based
ID78K0 Integrated Debugger Windows Based
ID78K0-NS Integrated Debugger Windows Based
Reference
Reference
Guide
U11151J
U11539J
U11649J
U12900J
U14379J
—
U11539E
U11649E
Reference
Operation
U12900E
To be prepared
Caution The contents of the above documents are subject to change without notice. Please ensure that
the latest versions are used in design work, etc.
Data Sheet U12885EJ3V0DS00
67
µPD178076, 178078, 178096, 178098
Related Documents for Embedded Software (User’s Manual)
Document No.
Title
Japanese
U11537J
English
U11537E
78K/0 Series Real-time OS
Fundamental
Installation
U11536J
U12257J
U11536E
U12257E
78K/0 Series OS MX78K0
Fundamental
Other Documents
Document No.
Japanese English
Title
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
Semiconductor Device Mounting Technology Manual
X13769X
C10535J
C11531J
C10983J
C10535E
C11531E
C10983E
C11892E
—
Quality Guides on NEC Semiconductor Devices
NEC Semiconductor Device Reliability and Quality Control
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892J
Semiconductor Device Quality/Reliability Handbook
Microcomputer Product Series Guide
C12769J
U11416J
—
Caution The contents of the above documents are subject to change without notice. Ensure that the
latest versions are used in design work, etc.
68
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
[MEMO]
Data Sheet U12885EJ3V0DS00
69
µPD178076, 178078, 178096, 178098
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and trans-
ported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
IEBus is a trademark of NEC Corporation.
Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
70
Data Sheet U12885EJ3V0DS00
µPD178076, 178078, 178096, 178098
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-2719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12885EJ3V0DS00
71
µPD178076, 178078, 178096, 178098
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD178076GF-XXX-3BA-A
Microcontroller, 8-Bit, MROM, 6.3MHz, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
NEC
UPD178096GF-XXX-3BA
Microcontroller, 8-Bit, MROM, 6.3MHz, CMOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
NEC
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