UPA103 [NEC]
HIGH FREQUENCY NPN TRANSISTOR ARRAY; 高频NPN晶体管阵列
| 型号： | UPA103 |
| 厂家： | 
NEC |
| 描述： | HIGH FREQUENCY NPN TRANSISTOR ARRAY |
| 文件： | 总8页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
COMPOUND TRANSISTOR
µPA103
HIGH FREQUENCY NPN TRANSISTOR ARRAY
FEATURES
•
FIVE MONOLITHIC 9 GHz fT TRANSISTORS:
Two of these use a common emitter pin and can be used as differential amplifiers
OUTSTANDING hFE LINEARITY
•
•
TWO PACKAGE OPTIONS:
µPA103B: Superior thermal dissipation due to studded ceramic package
µPA103G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting
DESCRIPTION AND APPLICATIONS
The µPA103 is a user configurable Silicon bipolar transistor array consisting of a common emitter pair and three
individual bipolar transistors. It is available in a surface mount 14-pin plastic SOP package and a 14-pin ceramic package.
Typical applications include: differential amplifiers and oscillators, high speed comparators, advanced cellular phone
systems, electro-optic and other signal processing up to 1.5 gigabits/second.
ORDERING INFORMATION
PART NUMBER
µPA103B-E1
µPA103G-E1
PACKAGE
14-pin ceramic package
14-pin plastic SOP (225 mil)
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
SYMBOLS
VCBO*
VCEO*
VEBO*
IC*
PARAMETERS
UNITS
RATINGS
Collector to Base Voltage
Collector to Emitter Voltage
Emitter to Base Voltage
Collector Current
V
V
15
6
V
2.5
40
mA
PT
Power Dissipation
µPA103B
mW
mW
650
350
µPA103G
TJ
Junction Temperature
µPA103B
°C
°C
200
125
µPA103G
TSTG
Storage Temperature
µPA103B
°C
°C
–55 to +200
–55 to +125
µPA103G
* Absolute maximum ratings for each transistor.
Caution electro-static sensitive devices
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. P10708EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
1995, 1999
©
µPA103
PACKAGE DIMENSIONS (UNIT: mm)
µPA103B
14 PIN CERAMIC PACKAGE
φ
0.8
TOP VIEW
0.35
1.27
6.2
5.0 MAX.
4.5 MIN.
0.08
2. 7
MAX.
SIDE VIEW
2.3 MIN.
φ1.6
BOTTOM VIEW
1.8
3.0
µPA103G
14 PIN PLASTIC SOP (225 mil)
14
8
detail of lead end
+7°
–3°
3°
1
7
10.2 ± 0.26
6.55 ± 0.2
4.38 ± 0.1
1.49
1.1 ± 0.16
0.6 ± 0.2
1.42 MAX
0.10
+0.10
–0.05
1.27
0.15
+0.10
–0.05
M
0.10
0.40
0.1 ± 0.1
+0.21
–0.20
1.59
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
See connection diagram for description of leads.
2
Data Sheet P10708EJ2V0DS00
µPA103
ELECTRICAL CHARACTERISTICS (Unless otherwise specified TA = +25 ˚C µPA103B, µPA103G common)
SYMBOLS
ICBO
PARAMETERS AND CONDITIONS
UNITS
µA
MIN.
TYP.
MAX.
1.0
1.0
250
1.1
1.0
20
Collector Cutoff Current at VCB = 5 V, IE = 0 (Q1 to Q5)
Emitter Cutoff Current at VEB = 1 V, IC = 0 (Q1 to Q5)
IEBO
µA
hFE
Direct Current Amplification at VCE = 3 V, IC = 5 mA (Q1 to Q5)
Direct Current Amplification Ratio at VCE = 3 V, IC = 5 mA, (Q1, Q2)
Emitter to Base Voltage at VCE = 3 V, IC = 5 mA (Q1, Q2)
Emitter to Base Voltage Difference, VCE = 3 V, IC = 5 mA |Q1 - Q2|
Collector to Base Capacitance at VCB = 3 V, f = 1 MHz (Q1 to Q5)
Emitter to Base Capacitance at VEB = 0, f = 1 MHz (Q1 to Q4)
Collector/Substrate Capacitance at VCS = 3 V, f = 1 MHz (Q1 to Q4)
Gain Bandwidth Product* at VCE = 3 V, IC = 10 mA
40
100
1.0
0.8
8.0
0.9
1.4
1.4
9.0
hFE1/hFE2
VBE
0.9
V
mV
pF
∆VBE
CCB
1.8
2.8
2.8
CEB
pF
CCS
pF
fT
GHz
* Measured by installing a single transistor in a Micro-X package: the value shown is a reference value.
CONNECTION DIAGRAM (Top View)
µPA103B
14
13
SUB
12
11
10
9
8
Q5
Q1
Q4
Q3
Q2
1
2
3
4
µPA103G
11
5
6
7
14
13
SUB
12
10
9
8
Q5
Q4
Q3
Q1
Q2
1
2
3
4
5
6
7
Data Sheet P10708EJ2V0DS00
3
µPA103
TYPICAL PERFORMANCE CHARACTERISTICS (TA = +25 °C)
COLLECTOR CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
COLLECTOR CURRENT vs.
BASE TO EMITTER VOLTAGE
10
8
200
100
100
50
80
20
10
60
6
5
40
4
2
1
I
B
= 20 µA
2
0.5
VCE = 3 V
0
0.1
0
1
2
3
4
5
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
Base to Emitter Voltage, VBE (V)
Collector to Emitter Voltage, VCE (V)
DC CURRENT GAIN vs.
COLLECTOR CURRENT
GAIN BANDWIDTH PRODUCT vs.
COLLECTOR CURRENT
12
10
8
1000
500
VCE = 5 V
200
100
50
3 V
6
1 V
20
20
10
4
0.5
1
2
5
10 20
50
1
2
5
10
50
Collector Current, I (mA)
C
Collector Current, I
C
(mA)
GAIN AND NOISE FIGURE OF
INDIVIDUAL TRANSISTOR
20
VCC = 3 V
f = 1 GHz
8
6
4
2
0
GAIN
10
NF
0
1
2
5
10
20
50 100
(mA)
Collector Current, I
C
4
Data Sheet P10708EJ2V0DS00
µPA103
TYPICAL HIGH SPEED COMPARATOR
R
3
5
R
4
6
R1
R2
ANALOG INPUT
REFERENCE
Q
1
R
R
Q
2
Q
7
Q
8
Q
5
Q
6
Q
3
Q
4
Q
9
Q
10
OUTPUT
LATCH
LATCH
FEATURES:
1. High Sensitivity
2. Low Positive Feedback time
3. Optimized latch recovery time
Q
11
Q
µ
12
µ
µ
µ
µ
µ
TYPICAL DIFFERENTIAL OSCILLATOR
VCC
VCC
C
1
2
R2
C
V
OUT
Q
2
Q
1
RFC
4
BENEFITS:
1. Ease of Integration
2. Very Low Distortion
BIAS
AC
SHORT
3. Automatic Gain Control
4. Minimum Loading on Tank Circuit
5. Very Low 1/f Noise
TYPICAL COMMON MODE DIFFERENTIAL AMP
V
CC (10 V)
100
Ω
100 pF
OUT
IN
1 KΩ
V
BB1 (5 V)
1 KΩ
V
BB2
1 KΩ
FEATURES:
1. High Gain
1000 pF
160 Ω
2. Stable
3. Auto Gain Control
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
Data Sheet P10708EJ2V0DS00
5
µPA103
NOTES ON CORRECT USE
(1) Observe precautions for handling because of electro-static sensitive devices.
(2) Form a ground pattern as wide as possible to minimize ground impedance (to prevent undesired operation).
(3) Design circuits connected Sub pin to the lowest voltage to prevent latch-up.
(4) Design circuits as each pin voltage difference within 15 V maximum.
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered in the following recommended conditions. Other soldering methods and conditions
than the recommended conditions are to be consulted with our sales representatives.
µPA103G
Recommended
Soldering process
Infrared ray reflow
Soldering conditions
condition symbol
Package peak temperature: 235 °C, Hour: within 30 s. (more than 210 °C),
IR35-00-2
Time: 2 times, Limited days: no.Note
VPS
Package peak temperature: 215 °C, Hour: within 40 s. (more than 200 °C),
Time: 2 times, Limited days: no.Note
VP15-00-2
WS60-00-1
Wave soldering
Pin part heating
Soldering tub temperature: less than 260 °C, Hour: within 10 s.
Time: 1 time, Limited days: no.Note
Pin area temperature: less than 300 °C, Hour: within 3 s./pin
Limited days: no.Note
µPA103B
Soldering process
Infrared ray reflow
Soldering conditions
Symbol
Peak package’s surface temperature: 230 °C or below,
Reflow time: 10 seconds or below (210 °C or higher),
Number of reflow process: 1, Exposure limit*: None
Partial heating method
Terminal temperature: 260 °C or below,
Flow time: 10 seconds or below,
Exposure limit*: None
Note It is the storage days after opening a dry pack, the storage conditions are 25 °C, less than 65 % RH.
Caution The combined use of soldering method is to be avoided (However, except the pin area heating
method).
For details of recommended soldering conditions for surface mounting, refer to information
document SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL (C10535E).
6
Data Sheet P10708EJ2V0DS00
µPA103
[MEMO]
Data Sheet P10708EJ2V0DS00
7
µPA103
NESAT (NEC Silicon Advanced Technology) is a trademark of NEC Corporation.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
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rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
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• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
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