NP80N03KLE [NEC]

SWITCHING N-CHANNEL POWER MOS FET; 切换N沟道功率MOS FET
NP80N03KLE
型号: NP80N03KLE
厂家: NEC    NEC
描述:

SWITCHING N-CHANNEL POWER MOS FET
切换N沟道功率MOS FET

晶体 晶体管 功率场效应晶体管 开关 脉冲
文件: 总8页 (文件大小:86K)
中文:  中文翻译
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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
NP80N03CLE,NP80N03DLE,NP80N03ELE NP80N03KLE  
SWITCHING  
N-CHANNEL POWER MOS FET  
DESCRIPTION  
ORDERING INFORMATION  
These products are N-channel MOS Field Effect  
Transistor designed for high current switching  
applications.  
PART NUMBER  
NP80N03CLE  
NP80N03DLE  
NP80N03ELE  
NP80N03KLE  
PACKAGE  
TO-220AB  
TO-262  
FEATURES  
TO-263 (MP-25ZJ)  
TO-263 (MP-25ZK)  
Channel Temperature 175 degree rated  
Super Low On-state Resistance  
RDS(on)1 = 7.0 mMAX. (VGS = 10 V, ID = 40 A)  
RDS(on)2 = 9.0 mMAX. (VGS = 5 V, ID = 40 A)  
Low Ciss : Ciss = 2600 pF TYP.  
(TO-220AB)  
Built-in Gate Protection Diode  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC) Note1  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT  
30  
V
V
±20  
±80  
A
Drain Current (Pulse) Note2  
A
±320  
Total Power Dissipation (TA = 25°C)  
Total Power Dissipation (TC = 25°C)  
Channel Temperature  
1.8  
W
W
°C  
°C  
A
(TO-262)  
PT  
120  
Tch  
175  
Storage Temperature  
Tstg  
–55 to +175  
50 / 40 / 9  
2.5 / 160 / 400  
Single Avalanche Current Note3  
Single Avalanche Energy Note3  
IAS  
EAS  
mJ  
Notes 1. Calculated constant current according to MAX. allowable channel  
temperature.  
(TO-263)  
2. PW 10 µs, Duty cycle 1%  
3. Starting Tch = 25°C, RG = 25 , VGS = 20 0 V (see Figure 4.)  
THERMAL RESISTANCE  
Channel to Case Thermal Resistance  
Channel to Ambient Thermal Resistance  
Rth(ch-C)  
1.25  
83.3  
°C/W  
°C/W  
Rth(ch-A)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
Document No.  
Date Published December 2002 NS CP(K)  
Printed in Japan  
D14032EJ4V0DS00 (4th edition)  
The mark shows major revised points.  
1999, 2000  
NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE  
ELECTRICAL CHARACTERISTICS (TA = 25°C)  
CHARACTERISTICS  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
Gate to Source Threshold Voltage  
Forward Transfer Admittance  
SYMBOL  
IDSS  
TEST CONDITIONS  
VDS = 30 V, VGS = 0 V  
MIN. TYP. MAX. UNIT  
10  
±10  
2.5  
µA  
µA  
V
IGSS  
VGS = ±20 V, VDS = 0 V  
VDS = VGS, ID = 250 µA  
VDS = 10 V, ID = 40 A  
VGS = 10 V, ID = 40 A  
VGS = 5 V, ID = 40 A  
VGS = 4.5 V, ID = 40 A  
VDS = 25 V  
VGS(th)  
| yfs |  
RDS(on)1  
RDS(on)2  
RDS(on)3  
Ciss  
1.5  
20  
2.0  
41  
S
Drain to Source On-state Resistance  
5.3  
6.8  
7.5  
7.0  
9.0  
11  
mΩ  
mΩ  
mΩ  
pF  
pF  
pF  
ns  
Input Capacitance  
2600 3900  
Output Capacitance  
Reverse Transfer Capacitance  
Turn-on Delay Time  
Rise Time  
Coss  
VGS = 0 V  
590  
270  
20  
12  
60  
14  
48  
28  
10  
14  
1.0  
34  
22  
890  
490  
44  
Crss  
f = 1 MHz  
td(on)  
tr  
td(off)  
tf  
VDD = 15 V, ID = 40 A  
VGS = 10 V  
31  
ns  
Turn-off Delay Time  
Fall Time  
RG = 1 Ω  
120  
35  
ns  
ns  
Total Gate Charge 1  
Total Gate Charge 2  
Gate to Source Charge  
Gate to Drain Charge  
Body Diode Forward Voltage  
Reverse Recovery Time  
Reverse Recovery Charge  
QG1  
VDD = 24 V, VGS = 10 V, ID = 80 A  
VDD = 24 V  
72  
nC  
nC  
nC  
nC  
V
QG2  
42  
QGS  
VGS = 5 V  
QGD  
VF(S-D)  
trr  
ID = 80 A  
IF = 80 A, VGS = 0 V  
IF = 80 A, VGS = 0 V  
di/dt = 100 A/µs  
ns  
Qrr  
nC  
TEST CIRCUIT 1 AVALANCHE CAPABILITY  
TEST CIRCUIT 2 SWITCHING TIME  
D.U.T.  
L
D.U.T.  
V
V
GS  
R
L
RG  
= 25 Ω  
90%  
V
GS  
Wave Form  
V
GS  
10%  
0
R
G
PG.  
PG.  
50 Ω  
V
DD  
V
DD  
V
GS = 200V  
DS  
90%  
d(on)  
90%  
V
DS  
V
0
GS  
BVDSS  
10% 10%  
V
DS  
Wave Form  
0
I
AS  
V
DS  
τ
I
D
t
t
r
t
d(off)  
tf  
V
DD  
t
on  
toff  
τ = 1 µs  
Duty Cycle 1%  
Starting Tch  
TEST CIRCUIT 3 GATE CHARGE  
D.U.T.  
= 2 mA  
I
G
RL  
PG.  
50 Ω  
V
DD  
2
Data Sheet D14032EJ4V0DS  
NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE  
TYPICAL CHARACTERISTICS (TA = 25°C)  
Figure2. TOTAL POWER DISSIPATION vs.  
CASE TEMPERATURE  
Figure1. DERATING FACTOR OF FORWARD BIAS  
SAFE OPERATING AREA  
140  
120  
100  
80  
100  
80  
60  
40  
20  
0
60  
40  
20  
0
0
25 50 75 100 125 150 175 200  
0
25 50 75 100 125 150 175 200  
- Case Temperature - ˚C  
T
C
TC - Case Temperature - ˚C  
Figure4. SINGLE AVALANCHE ENERGY  
DERATING FACTOR  
Figure3. FORWARD BIAS SAFE OPERATING AREA  
450  
400  
350  
300  
250  
200  
150  
100  
50  
1000  
100  
10  
400 mJ  
I
D(pulse)  
I
D(DC)  
P
o
w
Limiteedr Dissipation  
I
AS = 9 A  
40 A  
50 A  
160 mJ  
1
T
C
= 25˚C  
Single pulse  
2.5 mJ  
50  
0.1  
0.1  
0
1
10  
100  
25  
75  
100  
125  
150  
175  
VDS  
-
Drain to Source Voltage - V  
Starting Tch - Starting Channel Temperature - ˚C  
Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH  
1000  
100  
10  
Rth(ch-A) = 83.3˚C/W  
Rth(ch-C) = 1.25˚C/W  
1
0.1  
0.01  
Single pulse  
100 1000  
µ
10  
1 m  
10 m  
100 m  
1
10  
100  
µ
PW - Pulse Width - s  
3
Data Sheet D14032EJ4V0DS  
NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE  
Figure6. FORWARD TRANSFER CHARACTERISTICS  
Figure7. DRAIN CURRENT vs.  
DRAIN TO SOURCE VOLTAGE  
1000  
400  
350  
300  
250  
200  
150  
100  
50  
Pulsed  
Pulsed  
V
GS = 10 V  
100  
5 V  
10  
1
T
A
= 50˚C  
25˚C  
75˚C  
150˚C  
175˚C  
4.5 V  
0
0.1  
4.0  
2.0  
0.0  
1.0  
3.0  
1
2
5
6
3
4
VDS - Drain to Source Voltage - V  
V
GS - Gate to Source Voltage - V  
Figure8. FORWARD TRANSFER ADMITTANCE vs.  
DRAIN CURRENT  
Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs.  
GATE TO SOURCE VOLTAGE  
100  
50  
V
DS = 10 V  
Pulsed  
Pulsed  
40  
30  
20  
10  
10  
T
A
= 175˚C  
75˚C  
25˚C  
1
0.1  
50˚C  
ID = 40 A  
0.01  
0.01  
0
0.1  
1
10  
100  
0
2
4
6
8
10 12 14 16 18  
I
D
- Drain Current - A  
VGS - Gate to Source Voltage - V  
Figure10. DRAIN TO SOURCE ON-STATE  
Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs.  
CHANNEL TEMPERATURE  
RESISTANCE vs. DRAIN CURRENT  
Pulsed  
3.0  
V
DS = V  
GµS  
30  
20  
I
D
= 250 A  
2.5  
2.0  
1.5  
1.0  
V
GS = 4.5 V  
5 V  
10 V  
10  
0
0.5  
0
1
10  
100  
1000  
50  
0
50  
100  
150  
I
D
- Drain Current - A  
Tch - Channel Temperature - ˚C  
4
Data Sheet D14032EJ4V0DS  
NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE  
Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs.  
Figure13. SOURCE TO DRAIN DIODE  
FORWARD VOLTAGE  
CHANNEL TEMPERATURE  
12  
10  
1000  
100  
10  
Pulsed  
Pulsed  
VGS = 4.5 V  
5 V  
10 V  
V
GS = 10 V  
8
6
4
2
0
V
GS = 0 V  
1
I
D
= 40 A  
150  
ch - Channel Temperature - ˚C  
100  
0.1  
0
50  
50  
0
1.5  
1.0  
- Source to Drain Voltage - V  
0.5  
T
V
SD  
Figure14. CAPACITANCE vs. DRAIN TO  
SOURCE VOLTAGE  
Figure15. SWITCHING CHARACTERISTICS  
1000  
100  
10000  
V
GS = 0 V  
f = 1 MHz  
t
f
Ciss  
t
d(off)  
1000  
100  
10  
C
oss  
rss  
t
d(on)  
C
10  
1
t
r
0.1  
1
10  
100  
0.1  
1
10  
100  
ID - Drain Current - A  
V
DS - Drain to Source Voltage - V  
Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS  
Figure16. REVERSE RECOVERY TIME vs.  
DRAIN CURRENT  
16  
14  
12  
10  
8
40  
35  
30  
25  
20  
15  
10  
5
1000  
100  
di/dt = 100 A/µs  
V
GS = 0 V  
V
GS  
V
DD = 24 V  
15 V  
6 V  
6
10  
1
4
VDS  
2
I
D
= 80 A  
70 80  
0
0
0
10  
20 30 40 50  
60  
0.1  
1
10  
100  
Q
G
- Gate Charge - nC  
I
F
- Drain Current - A  
5
Data Sheet D14032EJ4V0DS  
NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE  
PACKAGE DRAWINGS (Unit: mm)  
1) TO-220AB (MP-25)  
2) TO-262 (MP-25 Fin Cut)  
4.8 MAX.  
1.3±0.2  
10.6 MAX.  
10.0 TYP.  
4.8 MAX.  
1.3±0.2  
φ
3.6±0.2  
10 TYP.  
4
1
2
3
4
1
2 3  
1.3±0.2  
1.3±0.2  
2.8±0.2  
0.5±0.2  
0.75±0.3  
2.54 TYP.  
2.54 TYP.  
0.75±0.1  
2.54 TYP.  
0.5±0.2  
1.Gate  
2.8±0.2  
2.54 TYP.  
1.Gate  
2.Drain  
3.Source  
2.Drain  
4.Fin (Drain)  
3.Source  
4.Fin (Drain)  
3) TO-263 (MP-25ZJ)  
4) TO-263 (MP-25ZK)  
4.8 MAX.  
10 TYP.  
10.0±0.3  
4.45±0.2  
1.3±0.2  
1.3±0.2  
No plating  
7.88 MIN.  
4
4
0.025 to  
0.25  
1
2
3
1.4±0.2  
0.7±0.2  
0.5±0.2  
0.75±0.2  
2.54 TYP.  
2.54 TYP.  
2.54  
0.25  
1.Gate  
1
2
3
2.Drain  
3.Source  
4.Fin (Drain)  
1.Gate  
2.Drain  
3.Source  
4.Fin (Drain)  
6
Data Sheet D14032EJ4V0DS  
NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE  
EQUIVALENT CIRCUIT  
Drain  
Remark The diode connected between the gate and source of  
the transistor serves as a protector against ESD. When  
this device actually used, an additional protection circuit  
is externally required if a voltage exceeding the rated  
voltage may be applied to this device.  
Body  
Diode  
Gate  
Gate  
Protection  
Diode  
Source  
7
Data Sheet D14032EJ4V0DS  
NP80N03CLE,NP80N03DLE,NP80N03ELE,NP80N03KLE  
The information in this document is current as of December, 2002. The information is subject to  
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data  
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not  
all products and/or types are available in every country. Please check with an NEC Electronics sales  
representative for availability and additional information.  
No part of this document may be copied or reproduced in any form or by any means without the prior  
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may  
appear in this document.  
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual  
property rights of third parties by or arising from the use of NEC Electronics products listed in this document  
or any other liability arising from the use of such products. No license, express, implied or otherwise, is  
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.  
Descriptions of circuits, software and other related information in this document are provided for illustrative  
purposes in semiconductor product operation and application examples. The incorporation of these  
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defined above).  
M8E 02. 11-1  

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