MC-4516CB64S-A10 [NEC]
Synchronous DRAM Module, 16MX64, 6ns, MOS, SODIMM-144;
| 型号： | MC-4516CB64S-A10 |
| 厂家： | 
NEC |
| 描述： | Synchronous DRAM Module, 16MX64, 6ns, MOS, SODIMM-144 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516CB64S
16 M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
The MC-4516CB64S is a 16,777,216 words by 64 bits synchronous dynamic RAM module (Small Outline DIMM) on
which 8 pieces of 128 M SDRAM : µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 16,777,216 words by 64 bits organization
• Clock frequency and Clock access time
Family
/CAS Latency
Clock frequency
(MAX.)
Burst cycle time
(MIN.)
Power consumption (MAX.)
Standby
Active
(CMOS level input )
MC-4516CB64S-A80
MC-4516CB64S-A10
MC-4516CB64S-A10B
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
100 MHz
100 MHz
77 MHz
6 ns
6 ns
6 ns
7 ns
7 ns
8 ns
7,776 mW
7,488 mW
7,200 mW
6,912 mW
6,624 mW
6,336 mW
14.4 mW
100 MHz
67 MHz
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single +3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice.
The mark • shows major revised points.
Document No. M13611EJ2V0DS00 (2nd edition)
Date Published September 1998 NS CP(K)
Printed in Japan
1998
©
MC-4516CB64S
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-4516CB64S-A80
MC-4516CB64S-A10
MC-4516CB64S-A10B
MC-4516CB64S-A10BL
125 MHz
100 MHz
100 MHz
100 MHz
144-pin Small Outline DIMM
(Socket Type)
8 pieces of µPD45128841G5
(400 mil TSOP (II))
Edge connector : Gold plated
26.67 mm (1.05 inch) height
2
MC-4516CB64S
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector : Gold plated)
[ MC-4516CB64S ]
2
4
Vss
Vss
DQ 0
DQ 1
DQ 2
DQ 3
1
/xxx indicates active low signal.
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
3
6
5
8
7
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
9
VCC
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQ 4
DQ 5
DQ 6
DQ 7
Vss
DQMB4
DQMB5
Vcc
DQMB0
DQMB1
V
CC
A3
A0
A1
A4
A5
A2
Vss
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 8
DQ 9
DQ 10
DQ 11
VCC
DQ 44
DQ 45
DQ 46
DQ 47
Vss
NC
NC
DQ 12
DQ 13
DQ 14
DQ 15
Vss
NC
NC
62
64
CKE0
Vcc
CLK0
Vcc
/RAS
/WE
/CS0
NC
61
63
66
/CAS
NC
65
68
67
70
NC
NC
69
72
71
74
CLK1
Vss
NC
73
76
Vss
NC
75
A0 - A11
: Address Inputs
78
NC
77
80
NC
NC
79
[Row : A0 - A11, Column : A0 - A9]
BA0 (A13),
82
Vcc
VCC
81
84
DQ 48
DQ 49
DQ 50
DQ 51
Vss
DQ 16
DQ 17
DQ 18
DQ 19
Vss
83
86
85
88
87
90
89
BA1(A12)
DQ0 - DQ63
CLK0, CLK1
CKE0
: SDRAM Bank Select
92
91
94
DQ 52
DQ 53
DQ 54
DQ 55
Vcc
DQ 20
DQ 21
DQ 22
DQ 23
Vcc
93
: Data Inputs/Outputs
: Clock Input
96
95
98
97
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
: Clock Enable Input
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
A7
A6
BA0 (A13)
Vss
A8
Vss
/CS0
BA1 (A12)
A11
A9
A10
/RAS
Vcc
Vcc
DQMB6
DQMB7
Vss
DQMB2
DQMB3
Vss
/CAS
DQ 56
DQ 57
DQ 58
DQ 59
Vcc
DQ 60
DQ 61
DQ 62
DQ 63
Vss
SCL
Vcc
DQ 24
DQ 25
DQ 26
DQ 27
/WE
DQMB0 - DQMB7 : DQ Mask Enable
VCC
SDA
SCL
VCC
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
DQ 28
DQ 29
DQ 30
DQ 31
Vss
SDA
VCC
SS
V
NC
: No Connection
3
MC-4516CB64S
Block Diagram
/WE
/CS0
DQMB0
DQMB4
DQM /CS /WE
DQM /CS /WE
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
D0
D4
DQMB5
DQMB1
DQM
DQM
/CS /WE
/CS /WE
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D1
D5
DQ 8
DQMB6
DQMB2
DQM
/CS /WE
DQM
/CS /WE
DQ 23
DQ 22
DQ 21
DQ 20
DQ 19
DQ 18
DQ 17
DQ 16
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D2
D6
DQMB3
DQMB7
/CS
DQM /CS /WE
DQM
/WE
DQ 31
DQ 30
DQ 29
DQ 28
DQ 27
DQ 26
DQ 25
DQ 24
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D3
D7
CLK : D0, D4
SERIAL PD
CLK0
CLK1
CLK : D1, D5
10 Ω
10 Ω
SCL
SDA
A0
A1
A2
CLK : D2, D6
CLK : D3, D7
A0 - A11
BA0
A0 - A11: D0 - D7
/RAS
/CAS
CKE0
/RAS: D0 - D7
A13: D0 - D7
A12: D0 - D7
/CAS: D0 - D7
CKE: D0 - D7
BA1
VCC
VSS
D0 - D7
D0 - D7
C
Remark D0 - D7 : µPD45128841 (4 M words × 8 bits × 4 banks)
4
MC-4516CB64S
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
8
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
Low level input voltage
VCC + 0.3
+ 0.8
70
V
VIL
V
Operating ambient temperature
TA
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
TYP.
MAX.
55
Unit
pF
Input capacitance
A0 - A11, BA0 (A13),
BA1 (A12), /RAS, /CAS, /WE
CLK0, CLK1
CI2
CI3
CI4
CI5
CI/O
36
55
55
10
10
CKE0
/CS0
DQMB0 -DQMB7
DQ0 - DQ63
Data input/output capacitance
pF
5
MC-4516CB64S
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
ICC1
Test condition
MIN. MAX. Unit Notes
Operating current
/CAS latency = 2 -A80
960 mA
840
1
Burst length = 1, tRC ≥ tRC(MIN.)
IO = 0 mA
-A10
-A10B
/CAS latency = 3 -A80
-A10
800
1,000
880
-A10B
840
Precharge standby current
in power down mode
ICC2P
ICC2PS
ICC2N
8
4
mA
CKE ≤ VIL(MAX.), tCK = 15 ns
CKE ≤ VIL(MAX.), tCK = ∞
Precharge standby current
in non power down mode
160 mA
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
ICC2NS
ICC3P
48
CKE ≥ VIH(MIN.), tCK = ∞ , Input signals are stable.
CKE ≤ VIL(MAX.), tCK = 15 ns
Active standby current in
power down mode
40
32
mA
ICC3PS
ICC3N
CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
200 mA
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
ICC3NS
ICC4
96
CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
Operating current
(Burst mode)
/CAS latency = 2 -A80
920 mA
720
2
tCK ≥ tCK(MIN.) , IO = 0 mA
-A10
-A10B
640
/CAS latency = 3 -A80
1,080
920
-A10
-A10B
840
Refresh current
ICC5
/CAS latency = 2 -A80
2,080 mA
1,920
1,760
2,160
2,000
1,840
3
tRC ≥ tRC(MIN.)
-A10
-A10B
/CAS latency = 3 -A80
-A10
-A10B
-
Self refresh current
ICC6
16
6.4
+ 8
mA
CKE ≤ 0.2 V
-
L
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
II(L)
IO(L)
VOH
VOL
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 8
µA
µA
V
– 1.5 + 1.5
2.4
0.4
IO = + 4.0 mA
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
6
MC-4516CB64S
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
T
• AC measurements assume t = 1ns.
IH
IL
• Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V and V .
T
IH (MIN.)
IL (MAX.)
and V
• If t is longer than 1ns, reference level for measuring timing of input signals is V
.
• An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
t
SETUP
t
HOLD
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
7
MC-4516CB64S
Synchronous Characteristics
Parameter
Symbol
-A80
MAX.
-A10
MAX.
-A10B
Unit Note
MIN.
8
MIN.
10
MIN.
10
MAX.
Clock cycle time
/CAS latency = 3
tCK3
tCK2
tAC3
tAC2
tCH
ns
ns
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
10
13
15
Access time from CLK
6
6
6
7
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
CLK high level width
CLK low level width
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3.5
3.5
3
tCL
Data-out hold time
tOH
1
Data-out low-impedance time
tLZ
0
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
6
6
6
7
3
7
8
3
Data-in setup time
2.5
1
Data-in hold time
tDH
Address setup time
tAS
2.5
1
Address hold time
tAH
CKE setup time
tCKS
tCKH
tCKSP
tCMS
2.5
1
CKE hold time
CKE setup time (Power down exit)
2.5
2.5
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
1
1
1
ns
Note 1. Output load
1.4 V
50Ω
Z = 50Ω
Output
50 pF
8
MC-4516CB64S
Asynchronous Characteristics
Parameter
Symbol
-A80
-A10
-A10B
MIN. MAX.
Unit Note
MIN.
MAX.
MIN.
MAX.
REF to REF/ACT command period (Operation)
REF to REF/ACT command period (Refresh)
ACT to PRE command period
tRC
tRC1
tRAS
tRP
70
70
48
20
20
16
8
70
90
ns
ns
78
90
120,000
50
120,000
60
120,000 ns
PRE to ACT command period
20
30
ns
ns
Delay time ACT to READ/WRITE command
ACT(0) to ACT(1) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
20
30
20
20
ns
10
10
ns
Data-in to ACT(REF) command /CAS latency = 3 tDAL3 1CLK+20
1CLK+20
1CLK+30
ns
period (Auto precharge)
Mode register set cycle time
Transition time
/CAS latency = 2 tDAL2 1CLK+20
1CLK+20
1CLK+30
ns
tRSC
tT
2
2
1
2
1
CLK
0.5
30
64
30
64
30
64
ns
Refresh time
tREF
ms
9
MC-4516CB64S
Serial PD
Byte No.
0
Function Described
Hex
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into 80H
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
3
4
5
6
7
8
9
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
0AH
01H
40H
00H
01H
80H
A0H
A0H
60H
60H
70H
00H
80H
08H
00H
01H
8FH
04H
06H
01H
01H
00H
0EH
A0H
D0H
F0H
60H
70H
80H
00H
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
256 bytes
SDRAM
12 rows
10 columns
1 bank
64 bits
0
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 Cycle time
CL =3 Access time
-A80
-A10
10 ns
10 ns
6 ns
-A10B/-A10BL
-A80
10
-A10
6 ns
-A10B/-A10BL
7 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
SDRAM width
Non-parity
Normal
×8
Error checking SDRAM width
Minimum clock delay
None
1 clock
1, 2, 4, 8, F
4 banks
2, 3
Burst length supported
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
0
SDRAM module attributes
SDRAM device attributes : General
CL = 2 Cycle time
CL = 2 Access time
-A80
10 ns
13 ns
15 ns
6 ns
-A10
-A10B/-A10BL
-A80
24
-A10
7 ns
-A10B/-A10BL
8 ns
25-26
10
MC-4516CB64S
(2/2)
Byte No.
27
Function Described
Hex
14H
14H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
20 ns
tRP(MIN.)
-A80
-A10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
20 ns
30 ns
16 ns
20 ns
20 ns
20 ns
20 ns
30 ns
48 ns
50 ns
60 ns
128 M bytes
2 ns
-A10B/-A10BL 1EH
28
29
30
tRRD(MIN.)
tRCD(MIN.)
tRAS(MIN.)
-A80
-A10
10H
14H
-A10B/-A10BL 14H
-A80
-A10
14H
14H
-A10B/-A10BL 1EH
-A80
-A10
30H
32H
-A10B/-A10BL 3CH
20H
31
32
Module bank density
Command and add
setup time
-A80
-A10
20H
20H
2 ns
-A10B/-A10BL 25H
2.5 ns
1 ns
33
34
35
-A80
-A10
10H
10H
Command and add
hold time
1 ns
-A10B/-A10BL 10H
1 ns
-A80
-A10
20H
20H
2 ns
Data signal input setup
time
2 ns
-A10B/-A10BL 25H
2.5 ns
1 ns
-A80
-A10
10H
10H
Data signal input hold
time
1 ns
-A10B/-A10BL 10H
00H
1 ns
36-61
62
SPD revision
-A80
-A10
12H
12H
1.2 A
1.2 A
1.2 A
-A10B/-A10BL 12H
63
Checksum
-A80
-A10
F0H
56H
for bytes 0 - 62
-A10B/-A10BL BEH
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
Intel specification
frequency
-A80
-A10
64H
64H
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
0
0
1
1
1
100 MHz
100 MHz
66 MHz
-A10B/-A10BL 66H
127
Intel specification /CAS
latency support
-A80
-A10
C7H
C5H
-A10B/-A10BL C7H
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348XJ).
11
MC-4516CB64S
★
Package Drawing
[MC-4516CB64S]
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Y
M1 (AREA B)
N
R
Q
L
M
M2 (AREA A)
S
A
H
(OPTIONAL HOLES)
U1
U2
T
C
B
I
E
D
A1 (AREA A)
F
ITEM MILLIMETERS
A
67.6
67.6±0.15
23.2
A1
B
C
29.0
D
4.6
detail of A part
D1
D2
E
1.5±0.10
4.0
D2
32.8
W
F
3.7
H
0.8 (T.P.)
3.3
I
20.0
L
D1
X
M
M1
M2
26.67±0.15
4.67
V
22.0
N
Q
R
3.8 MAX.
R2.0
4.0±0.10
φ
S
1.8
T
1.0±0.1
U1
3.2 MIN.
U2
V
4.0 MIN.
0.25 MAX.
0.6±0.05
2.55 MIN.
2.0 MIN.
W
X
Y
12
MC-4516CB64S
[MEMO]
13
MC-4516CB64S
[MEMO]
14
MC-4516CB64S
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
15
MC-4516CB64S
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
相关型号：
MC-4516CD641ES-A10L
Synchronous DRAM Module, 16MX64, 6ns, MOS, 31.75 MM HEIGHT, 0.80 MM PITCH, DIMM-144
NEC
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