78042FG [NEC]
8-BIT SINGLE-CHIP MICROCOMPUTER; 8位单片机
| 型号： | 78042FG |
| 厂家： | 
NEC |
| 描述： | 8-BIT SINGLE-CHIP MICROCOMPUTER |
| 文件： | 总72页 (文件大小：502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
mPD78042F, 78043F, 78044F, 78045F
8-BIT SINGLE-CHIP MICROCOMPUTER
The mPD78042F, mPD78043F, mPD78044F, and mPD78045F are 8-bit single-chip microcomputers that incorpo-
rate many hardware peripherals such as an FIP® controller/driver, 8-bit resolution A/D converter, timer, serial
interface, and interrupt controller.
The one-time PROM and EPROM models that can operate in the same voltage range as that of masked ROM
models, and various development tools are provided.
The functions of these microcomputers are described in detail in the following User’s Manual. Be sure
to read this manual when you design a system using any of these microcomputers.
mPD78044F Sub-Series User’s Manual : U10908E
78K/0 Series User's Manual, Instruction: IEU-1372
FEATURES
• High-capacity ROM and RAM
Data memory
Item
Program memory
(ROM)
Product name
mPD78042F
mPD78043F
mPD78044F
mPD78045F
Internal high-speed RAM
512 bytes
Buffer RAM
64 bytes
FIP display RAM
48 bytes
16K bytes
24K bytes
32K bytes
40K bytes
1024 bytes
• Wide range of instruction execution time - from
high-speed (0.4 ms) to ultra low-speed (122 ms)
• I/O ports: 68
• 8-bit resolution A/D converter: 8 channels
• Serial interface: 2 channels
• Timer: 6 channels
• FIP controller/driver: total display outputs: 34
• Power supply voltage: VDD = 2.7 to 5.5 V
★
APPLICATIONS
CD players, cassete tape recorders, tuners, minicomponent stereos, VCRs, microwave ovens, ECRs, etc.
ORDERING INFORMATION
Part number
Package
mPD78042FGF-¥¥¥-3B9
mPD78043FGF-¥¥¥-3B9
mPD78044FGF-¥¥¥-3B9
mPD78045FGF-¥¥¥-3B9
80-pin plastic QFP (14 ¥ 20 mm)
80-pin plastic QFP (14 ¥ 20 mm)
80-pin plastic QFP (14 ¥ 20 mm)
80-pin plastic QFP (14 ¥ 20 mm)
Remark ¥¥¥ indicates ROM code number.
The information in this document is subject to change without notice.
The mark ★ shows major revised points.
Document No. U10700EJ1V0DS00 (1st edition)
Date Published July 1996 P
Printed in Japan
1996
©
mPD78042F, 78043F, 78044F, 78045F
★
78K/0 SERIES PRODUCT DEVELOPMENT
The 78K/0 series products were developed as shown below. The sub-series names are indicated in frames.
Products under
mass production
Products under
development
The Y Subseries is compatible with the I2C bus.
For control
A timer added to the µPD78054 and external interface functions enhanced.
100-pin
100-pin
80-pin
µPD78078
µPD78070A
µPD78058F
µPD78054
µPD78018F
µPD78014
µPD780001
µPD78002
µPD78083
µPD78078Y
µPD78070AY
µPD78058FY
µPD78054Y
µPD78018FY
µPD78014Y
ROM-less product of the µPD78078
Counter-measure against EMI noise added to the µPD78054
An UART and D/A converter added to the µPD78014 and I/O
80-pin
function enhanced.
Low-voltage (1.8 V) versions of the µPD78014. ROM and RAM variations
enhanced.
64-pin
64-pin
An A/D converter and 16-bit timer added to the µPD78002.
An A/D converter added to the µPD78002
64-pin
64-pin
µPD78002Y
Basic subseries for control
These products include an UART and can operate at a low voltage (1.8 V).
42/44-pin
For FIP driving
The I/O and FIP C/D of the µPD78044F enhanced.
Total indication output pins: 53
100-pin
80-pin
64-pin
µPD780208
µPD78044F
µPD78024
A 6-bit U/D counter added to the µPD78024.
78K/0
series
Total indication output pins: 34
Basic subseries for FIP driving. Total indication output pins: 26
For LCD driving
SIO of the µPD78064 enhanced and ROM/RAM expanded.
100-pin
100-pin
µPD780308
µPD78064B
µPD780308Y
Counter-measure against EMI noise added to the µPD78064.
Basic subseries for LCD driving. These products include an UART.
µ
100-pin
PD78064
PD78064Y
µ
Compatible with IEBusTM
An IEBus controller added to the µPD78054.
80-pin
µPD78098
For LV
PWM output, LV digital code decoder, built-in Hsync counter.
100-pin
µPD78P0914
2
mPD78042F, 78043F, 78044F, 78045F
The table below shows the main differences between subseries.
Function
Timer
ROM
8-bit 8-bit
A/D D/A
Serial
VDD Min. External
value expansion
I/O
capacity
interface
Subseries name
8-bit 16-bit Watch WDT
For control
mPD78078
32K-60K
–
4ch 1ch 1ch 1ch 8ch 2ch 3ch (UART : 1ch) 88 pins 1.8 V
61 pins 2.7 V
mPD78070A
mPD78058F
mPD78054
mPD78018F
mPD78014
mPD780001
mPD78002
mPD78083
mPD780208
mPD78044F
mPD78024
mPD780308
mPD78064B
mPD78064
mPD78098
48K-60K
16K-60K
8K-60K
8K-32K
8K
2ch
69 pins
★
2.0 V
–
2ch
1ch
53 pins 1.8 V
2.7 V
–
–
1ch
–
39 pins
–
8K-16K
8K-16K
32K-60K
16K-40K
24K-32K
48K-60K
32K
–
53 pins
8ch
1ch (UART : 1ch) 33 pins 1.8 V
–
–
For FIP
driving
2ch 1ch 1ch 1ch 8ch
–
–
2ch
74 pins 2.7 V
68 pins
54 pins
For LCD
driving
2ch 1ch 1ch 1ch 8ch
3ch (UART : 1ch) 57 pins 1.8 V
2ch (UART : 1ch) 2.0 V
–
★
★
16K-32K
32K-60K
Compatible
with IEBus
2ch 1ch 1ch 1ch 8ch 2ch 3ch (UART : 1ch) 69 pins 2.7 V
For LV
mPD78P0914
32K
6ch
–
–
1ch 8ch
–
2ch
54 pins 4.5 V
3
mPD78042F, 78043F, 78044F, 78045F
FUNCTIONAL OUTLINE
Product name
mPD78043F
mPD78042F
16K bytes
mPD78044F
mPD78045F
40K bytes
Item
Internal
memory
ROM
32K bytes
1024 bytes
24K bytes
512 bytes
64 bytes
48 bytes
Internal high-speed RAM
Buffer RAM
FIP display RAM
General registers
8 bits ¥ 32 registers (8 bits ¥ 8 registers ¥ 4 banks)
Instruction
cycle
Variable instruction execution time
For main system clock
For subsystem clock
0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (at 5.0 MHz)
122 ms (at 32.768 kHz)
Instruction set
• Multiplication/division (8 bits ¥ 8 bits, 16 bits ÷ 8 bits)
• Bit (set, reset, test, Boolean algebra)
I/O ports (including those
multiplexed with FIP pins)
Total
: 68 lines
2 lines
: 27 lines
5 lines
• CMOS input
:
• CMOS I/O
• N-ch open-drain
• P-ch open-drain I/O
• P-ch open-drain output
:
: 16 lines
: 18 lines
FIP controller/driver
Total
: 34 lines
• Segments
• Digits
: 9 to 24 lines
: 2 to 16 lines
A/D converter
Serial interface
• 8-bit resolution ¥ 8 channels
• Power supply voltage: AVDD = 4.0 to 5.5 V
★
• 3-wire serial I/O/SBI/2-wire serial I/O selectable modes: 1 channel
•
3-wire serial I/O mode (with automatic transmission/
reception function of up to 64 bytes)
: 1 channel
Timer
• 16-bit timer/event counter
• 8-bit timer/event counter
• Watch timer
: 1 channel
: 2 channels
: 1 channel
: 1 channel
: 1 channel
• Watchdog timer
• 6 bit up/down counter
Timer output
Clock output
3 lines (one for 14-bit PWM output)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz
(Main system clock: at 5.0 MHz)
32.768 kHz (Subsystem clock: at 32.768 kHz)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz (Main system clock: at 5.0 MHz)
Vectored
interrupt
Maskable interrupt
Non-maskable interrupt
Software interrupt
Internal 10 lines, external 4 lines
Internal 1 line
1 line
Text input
Internal 1 line
Power supply voltage
Package
VDD = 2.7 to 5.5 V
★
80-pin plastic QFP (14 ¥ 20 mm)
4
mPD78042F, 78043F, 78044F, 78045F
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ........................................................................................
2. BLOCK DIAGRAM.....................................................................................................................
3. PINS FUNCTIONS .....................................................................................................................
6
8
9
9
3.1
3.2
3.3
PORT PINS ......................................................................................................................................
PINS OTHER THAN PORT PINS...................................................................................................
PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS........................................................
11
13
4. MEMORY SPACE ...................................................................................................................... 16
5. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 17
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
PORTS .............................................................................................................................................
CLOCK GENERATOR CIRCUIT ....................................................................................................
TIMER/EVENT COUNTER ..............................................................................................................
CLOCK OUTPUT CONTROL CIRCUIT .........................................................................................
BUZZER OUTPUT CONTROL CIRCUIT .......................................................................................
A/D CONVERTER ...........................................................................................................................
SERIAL INTERFACE ......................................................................................................................
FIP CONTROLLER/DRIVER ..........................................................................................................
17
18
18
21
21
22
22
24
6. INTERRUPT FUNCTION AND TEST FUNCTION .................................................................... 26
6.1
6.2
INTERRUPT FUNCTION.................................................................................................................
TEST FUNCTION ............................................................................................................................
26
29
7. STANDBY FUNCTION............................................................................................................... 30
8. RESET FUNCTION .................................................................................................................... 30
9. INSTRUCTION SET ................................................................................................................... 31
10. ELECTRICAL SPECIFICATIONS ............................................................................................. 34
11. CHARACTERISTIC CURVE (REFERENCE VALUE) .............................................................. 58
12. PACKAGE DRAWING............................................................................................................... 63
13. RECOMMENDED SOLDERING CONDITIONS........................................................................ 64
APPENDIX A DEVELOPMENT TOOLS ......................................................................................... 65
APPENDIX B RELATED DOCUMENTS......................................................................................... 67
★
★
★
5
mPD78042F, 78043F, 78044F, 78045F
1. PIN CONFIGURATION (TOP VIEW)
•
80-pin plastic QFP (14 ¥ 20 mm)
mPD78042FGF-¥¥¥-3B9, mPD78043FGF-¥¥¥-3B9
mPD78044FGF-¥¥¥-3B9, mPD78045FGF-¥¥¥-3B9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P94/FIP6
P93/FIP5
P92/FIP4
P114/FIP22
P115/FIP23
P116/FIP24
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
2
3
4
P91/FIP3
P90/FIP2
P81/FIP1
P80/FIP0
P117/FIP25
P120/FIP26
P121/FIP27
P122/FIP28
P123/FIP29
P124/FIP30
P125/FIP31
P126/FIP32
P127/FIP33
VDD
5
6
7
V
DD
8
9
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P23/STB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P22/SCK1
P21/SO1
P70
P71
P20/SI1
P72
RESET
P74
IC
P00/INTP0/TI0
P01/INTP1
P02/INTP2
P03/INTP3/CI0
P30/TO0
P73
AVSS
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P31/TO1
P32/TO2
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1. Connect the IC (Internally Connected) pins directly to the VSS.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
6
mPD78042F, 78043F, 78044F, 78045F
P00-P04
P10-P17
P20-P27
P30-P37
P70-P74
P80, P81
P90-P97
: Port 0
: Port 1
: Port 2
: Port 3
: Port 7
: Port 8
: Port 9
SCK0, SCK1 : Serial clock
PCL
: Programmable clock
: Buzzer clock
: Strobe
BUZ
STB
BUSY
: Busy
FIP0-FIP33 : Fluorescent indicator panel
VLOAD
: Negative power supply
: Crystal (main system clock)
: Crystal (subsystem clock)
: Reset
P100-P107 : Port 10
X1, X2
XT1, XT2
RESET
P110-P117 : Port 11
P120-P127 : Port 12
INTP0-INTP3 : Interrupt from peripherals
ANI0-ANI7 : Analog input
TI0-TI2
: Timer input
: Timer output
: Counter input
: Serial bus
AVDD
AVSS
AVREF
VDD
: Analog power supply
TO0-TO2
CI0
: Analog ground
: Analog reference voltage
: Power supply
SB0, SB1
SI0, SI1
SO0, SO1
: Serial input
: Serial output
VSS
: Ground
IC
: Internally connected
7
mPD78042F, 78043F, 78044F, 78045F
2. BLOCK DIAGRAM
P00
TO0/P30
16-bit timer/
event counter
P01-P03
P04
Port 0
Port 1
Port 2
TI0/INTP0/P00
TO1/P31
TI1/P33
8-bit timer/
event counter 1
P10-P17
P20-P27
TO2/P32
TI2/P34
8-bit timer/
event counter
2
P30-P37
P70-P74
P80, P81
Port 3
Port 7
Port 8
Port 9
Port 10
Watchdog timer
Watch timer
6-bit up/down
counter
CI0/INTP3/P03
78K/0
CPU core
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
ROM
Serial
interface 0
P90-P97
P100-P107
SI1/P20
SO1/P21
Serial
interface 1
SCK1/P22
P110-P117
P120-P127
Port 11
Port 12
STB/P23
BUSY/P24
ANI0/P10-
ANI7/P17
RAM
A/D converter
AVDD
AVSS
FIP0-FIP33
VLOAD
FIP
AVREF
controller/driver
INTP0/TI0/P00-
INTP3/CI0/P03
Interrupt control
Buzzer output
RESET
X1
BUZ/P36
PCL/P35
System control
X2
XT1/P04
XT2
Clock output
control
VDD
VSS
IC
Remark The capacities of the internal ROM and RAM differ depending on the product.
8
mPD78042F, 78043F, 78044F, 78045F
3. PINS FUNCTIONS
3.1 PORT PINS (1/2)
Pin name
P00
I/O
Input
I/O
Function
On reset
Input
Shared by:
INTP0/TI0
INTP1
Port 0
Input only
P01
P02
P03
P04
5-bit I/O port
Can be specified for input or output in 1-bit
units. When used as an input port pin, a built-in
pull-up resistor can be used by software.
Input only
Input
INTP2
INTP3/CI0
XT1
Note 1
Input
I/O
Input
Input
P10-P17
Port 1
ANI0-ANI7
8-bit I/O port
Can be specified for input or output in 1-bit units.
When used as an input port pin, a built-in pull-up resistor can be
Note 2
used by software.
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
I/O
Port 2
Input
SI1
8-bit I/O port
SO1
SCK1
STB
Can be specified for input or output in 1-bit units.
When used as an input port pin, a built-in pull-up resistor can be
used by software.
BUSY
SI0/SB0
SO0/SB1
SCK0
TO0
I/O
Port 3
Input
8-bit I/O port
TO1
Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
TO2
TI1
When used as an input port pin, a built-in pull-up resistor can be
used by software.
TI2
PCL
A pull-down resistor can be connected in 1-bit units by the mask
option.
BUZ
—
Notes 1. When the P04/XT1 pins is used as an input port pin, bit 6 (FRC) of the processor clock control register
(PCC) must be set to 1. At this time, do not use the feedback resistor of the subsystem clock oscillator
circuit.
2. When the P10/ANI0 through P17/ANI7 pins are used as the analog input lines of the A/D converter, be
sure to place the port 1 in the input mode. In this case, the built-in pull-up resistors are automatically
unused.
9
mPD78042F, 78043F, 78044F, 78045F
3.1 PORT PINS (2/2)
Pin name
P70-P74
I/O
I/O
Function
On reset
Input
Shared by:
—
Port 7
5-bit N-ch open-drain I/O port
Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
A pull-up resistor can be connected in 1-bit units by the mask
option.
P80, P81
Output
Output
Output
I/O
Port 8
Output
Output
Output
Input
FIP0, FIP1
2-bit P-ch open-drain high-voltage output port.
Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by the
mask option (whether VLOAD or VSS is connected can be
specified in bit units).
P90-P97
Port 9
FIP2-FIP9
8-bit P-ch open-drain high-voltage output port.
Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by the
mask option (whether VLOAD or VSS is connected can be
specified in 4-bit units).
P100-P107
P110-P117
Port 10
FIP10-FIP17
FIP18-FIP25
8-bit P-ch open-drain high-voltage output port.
Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by the
mask option (whether VLOAD or VSS is connected can be
specified in 4-bit units).
Port 11
8-bit P-ch open-drain high-voltage I/O port.
Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by the
mask option (whether VLOAD or VSS is connected can be
specified in 4-bit units).
P120-P127
I/O
Port 12
Input
FIP26-FIP33
8-bit P-ch open-drain high-voltage I/O port
Can be specified for input or output in 1-bit units.
Can directly drive LEDs.
A pull-down resistor can be connected in 1-bit units by the mask
option (whether VLOAD or VSS is connected can be specified in
4-bit units).
1 0
mPD78042F, 78043F, 78044F, 78045F
3.2 PINS OTHER THAN PORT PINS (1/2)
Pin name
INTP0
I/O
Function
Valid edge (rising, falling, or both rising and falling edges) can
be specified.
On reset
Input
Shared by:
P00/TI0
Input
INTP1
INTP2
INTP3
SI0
P01
External interrupt input
P02
Falling edge-active external interrupt input
Serial data input lines of serial interface
Input
Input
P03/CI0
P25/SB0
P20
Input
Output
I/O
SI1
SO0
SO1
SB0
Serial data output lines of serial interface
Serial data I/O lines of serial interface
Serial clock I/O lines of serial interface
Input
Input
Input
Input
P26/SB1
P21
P25/SI0
P26/SO0
P27
SB1
SCK0
SCK1
STB
I/O
P22
Output
Automatic transmission/reception strobe output line of serial
interface
P23
BUSY
TI0
Input
Input
Automatic transmission/reception busy input line of serial interface Input
P24
External count clock input to 16-bit timer (TM0)
External count clock input to 8-bit timer (TM1)
External count clock input to 8-bit timer (TM2)
16-bit timer output (multiplexed with 14-bit PWM output)
8-bit timer output
Input
Input
P00/INTP0
P33
TI1
TI2
P34
TO0
TO1
TO2
CI0
Output
P30
P31
P32
Input
Clock input to 6-bit up/down counter
Input
Input
P03/INTP3
P35
PCL
Output
Clock output (for trimming main system clock and subsystem
clock)
BUZ
Output
Output
Buzzer output
Input
P36
FIP0, FIP1
FIP2-FIP9
FIP10-FIP15
High-voltage, high-current digit/segment output of FIP
controller/driver
Output
P80, P81
P90-P97
P100-P105
Output
Output
High-voltage, high-current digit/segment output of FIP
controller/driver
Output
FIP16, FIP17
FIP18-FIP25
FIP26-FIP33
VLOAD
High-voltage segment output of FIP controller/driver
Connects pull-down resistor to FIP controller/driver
Output
Input
P106, P107
P110-P117
P120-P127
—
—
—
1 1
mPD78042F, 78043F, 78044F, 78045F
3.2 PINS OTHER THAN PORT PINS (2/2)
Pin name
ANI0-ANI7
AVREF
AVDD
AVSS
RESET
X1
I/O
Input
Function
A/D converter analog input lines
On reset
Input
—
Shared by:
P10-P17
Input
—
A/D converter reference voltage input line
Analog power supply to A/D converter. Connected to the VDD pin.
A/D converter ground line. Connected to the VSS pin.
System reset input
—
—
—
—
—
—
—
—
—
Input
Input
—
—
Connect crystal for main system clock oscillation
—
X2
—
XT1
Input
—
Connect crystal for subsystem clock oscillation
Input
—
P04
XT2
—
—
—
—
VDD
—
Positive power supply
—
VSS
—
Ground potential
—
IC
—
Internal connection. Connected directly to the VSS pin.
—
1 2
mPD78042F, 78043F, 78044F, 78045F
3.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
Table 3-1 shows the I/O circuit type of each pin and the processing of unused pins.
For the configuration of the I/O circuit of each type, refer to Fig. 3-1.
Table 3-1 I/O Circuit Type
Pin name
P00/INTP0/TI0
I/O Circuit type
I/O
Input
Recommended connections when unused
Connected to VSS.
2
P01/INTP1
P02/INTP2
P03/INTP3/CI0
P04/XT1
8-A
I/O
Individually connected to VSS with a resistor.
16
11
Input
I/O
Connected to VDD or VSS.
P10/ANI0-P17/ANI7
P20/SI1
Individually connected to VDD or VSS with a resistor.
8-A
5-A
8-A
5-A
8-A
10-A
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
5-C
P31/TO1
P32/TO2
P33/TI1
8-B
5-C
P34/TI2
P35/PCL
P36/BUZ
P37
P70-P74
13-B
14-A
P80/FIP0, P81/FIP1
P90/FIP2-P97/FIP9
P100/FIP10-P107/FIP17
P110/FIP18-P117/FIP25
P120/FIP26-P127/FIP33
RESET
Output
I/O
Open
15-C
Individually connected to VDD or VSS with a resistor.
2
Input
—
—
XT2
16
—
Open
AVREF
Connected to VSS.
Connected to VDD.
Connected to VSS.
AVDD
AVSS
VLOAD
IC
Connected directly to VSS.
1 3
mPD78042F, 78043F, 78044F, 78045F
Fig. 3-1 Pin I/O Circuits (1/2)
Type 2
Type 8-A
V
DD
Pull-up
enable
P-ch
V
DD
IN
Data
P-ch
IN/OUT
N-ch
Output
disable
Schmitt trigger input with hysteresis characteristics
Type 5-A
Type 8-B
V
DD
V
DD
Pull-up
enable
P-ch
Pull-up
enable
P-ch
V
DD
V
DD
Data
P-ch
Data
P-ch
IN/OUT
IN/OUT
Output
disable
N-ch
Output
disable
N-ch
(Mask
option)
Input
enable
Type 5-C
Type 10-A
V
DD
VDD
Pull-up
enable
Pull-up
enable
P-ch
P-ch
VDD
P-ch
V
DD
Data
Data
P-ch
IN/OUT
IN/OUT
Output
disable
Open-drain
Output disable
N-ch
N-ch
(Mask
option)
Input
enable
1 4
mPD78042F, 78043F, 78044F, 78045F
Fig. 3-1 Pin I/O Circuits (2/2)
VDD
Type 15-C
Type 11
V
DD
V
DD
Pull-up
enable
P-ch
P-ch
P-ch
VDD
Data
IN/OUT
Data
P-ch
IN/OUT
N-ch
Output
disable
N-ch
P-ch
N-ch
Comparator
+
–
(Mask
option)
N-ch
RD
VLOAD
(Threshold voltage)
REF
V
(Mask
option)
Input enable
Type 13-B
Type 16
VDD
Feedback
cut-off
(Mask
option)
IN/OUT
P-ch
Data
Output disable
N-ch
VDD
RD
P-ch
Input buffer with intermediate
withstand voltage
XT1
XT2
Type 14-A
V
DD
V
DD
P-ch
P-ch
OUT
Data
(Mask
option)
N-ch
VLOAD
(Mask
option)
1 5
mPD78042F, 78043F, 78044F, 78045F
4. MEMORY SPACE
Fig. 4-1 shows the memory map for mPD78042F, mPD78043F, mPD78044F, and mPD78045F.
Fig. 4-1 Memory Map
FFFFH
Special function
register (SFR)
256 × 8 bits
FF00H
FEFFH
General register
32 × 8 bits
FEE0H
FEDFH
Internal high-speed RAMNote
nnnnH
mmmmH
mmmmH – 1
Program area
Inhibited
FB00H
FAFFH
Data
memory
space
1000H
0FFFH
Buffer RAM
64 × 8 bits
FAC0H
FABFH
CALLF entry area
Program area
Inhibited
0800H
07FFH
FA80H
FA7FH
FIP display RAM
48 × 8 bits
FA50H
FA4FH
0080H
007FH
Inhibited
CALLT table area
Vector table area
nnnnH + 1
nnnnH
0040H
003FH
Program
memory
space
Internal ROMNote
0000H
0000H
Note The internal ROM and internal high-speed RAM capacities vary depending on the product. (See the table
below.)
Product name
Last Address of Internal
ROM
First address of internal
high-speed RAM
nnnnH
3FFFH
5FFFH
7FFFH
9FFFH
mmmmH
FD00H
mPD78042F
mPD78043F
mPD78044F
mPD78045F
FB00H
1 6
mPD78042F, 78043F, 78044F, 78045F
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
I/O ports are classified into the following five types:
• CMOS input (P00, P04)
: 2
• CMOS input/output (P01 - P03, ports 1 - 3)
• N-ch open-drain input/output (port 7)
• P-ch open-drain output (ports 8 - 10)
• P-ch open-drain input/output (ports 11 and 12)
: 27
: 5
: 18
: 16
Total
: 68
Table 5-1 Port Function
Product
Port 0
Pin
P00, P04
P01-P03
Function
Input-only port
I/O port. Can be specified for input or output in 1-bit units. When used as input port,
internal pull-up resistor can be connected through software.
Port 1
Port 2
Port 3
P10-P17
P20-P27
P30-P37
I/O port. Can be specified for input or output in 1-bit units. When used as input port,
internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units. When used as input port,
internal pull-up resistor can be connected through software.
I/O port. Can be specified for input or output in 1-bit units. When used as input port,
internal pull-up resistor can be connected through software.
Pull-down resistor can be connected in 1-bit units by the mask option.
Can directly drive LED.
Port 7
Port 8
P70-P74
P80, P81
N-ch open-drain I/O port. Can be specified for input or output in 1-bit units.
Pull-up resistor can be connected in 1-bit units by the mask option.
Can directly drive LED.
P-ch open-drain output port with high withstand voltage. Pull-down resistor can be
connected in 2-bit units by the mask option (connection to VLOAD or VSS can be specified in
2-bit units).
Can directly drive LED.
Port 9
P90-P97
P-ch open-drain output port with high withstand voltage. Pull-down resistor can be
connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in
4-bit units).
Can directly drive LED.
Port 10
Port 11
Port 12
P100-P107
P110-P117
P120-P127
P-ch open-drain output port with high withstand voltage. Pull-down resistor can be
connected in 1-bit units by the mask option (connection to VLOAD or VSS can be specified in
4-bit units).
Can directly drive LED.
P-ch open-drain I/O port with high withstand voltage. Can be specified for input or output
in 1-bit units. Pull-down resistor can be connected in 1-bit units by the mask option
(connection to VLOAD or VSS can be specified in 4-bit units).
Can directly drive LED.
P-ch open-drain I/O port with high withstand voltage. Can be specified for input or output
in 1-bit units.
Pull-down resistor can be connected in 1-bit units by the mask option (connection to
VLOAD or VSS can be specified in 4-bit units).
Can directly drive LED.
1 7
mPD78042F, 78043F, 78044F, 78045F
5.2 CLOCK GENERATOR CIRCUIT
The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock.
The instruction time can be changed.
• 0.4 ms/0.8 ms/1.6 ms/3.2 ms/6.4 ms (with main system clock: 5.0 MHz)
• 122 ms (with subsystem clock: 32.768 kHz)
Fig. 5-1 Clock Generator Circuit Block Diagram
XT1/P04
fXT
Subsystem
Clock output circuit
Watch timer
clock oscillator
XT2
Noise
eliminator
fX
8
fX
16
Prescaler
1
X1
X2
Main system
clock oscillator
2
Prescaler
Clock to
hardware peripherals
fX
fXT
2
fX
2
fX
fX
fX
22
23 24
Standby
control
circuit
STOP
CPU clock (fCPU)
To INTP0
sampling clock
5.3 TIMER/EVENT COUNTER
Six channels of timer/event counters are provided.
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
: 1 channel
: 1 channel
• Watchdog timer
• 6-bit up/down counter
Table 5-2 Timer/Event Counter Groups and Configurations
16-bit timer/
8-bit timer/
Watch
timer
Watchdog
timer
6-bit up/
event counter
event counter
down counter
Interval timer
1 channel
1 channel
1 output
1 output
1 input
1 output
1
2 channels
1 channel
1 channel
—
External event counter
Timer output
2 channels
—
—
1 channel
2 outputs
—
—
—
PWM output
—
—
—
—
Pulse width measurement
Square wave output
Interrupt Request
Test input
—
—
—
—
—
2 outputs
—
—
2
1
1
1
—
—
1 input
—
—
1 8
mPD78042F, 78043F, 78044F, 78045F
Fig. 5-2 16-Bit Timer/Event Counter Block Diagram
Internal bus
16-bit compare
register (CR00)
INTTM0
PWM
pulse
output
control
circuit
16-bit timer/event
counter output
control circuit
Match
TO0/P30
fX
fX/2
fX/22
fX/23
16-bit timer register (TM0)
Clear
Edge
detector
Selector
TI0/P00/INTP0
INTP0
16-bit capture
register (CR01)
Internal bus
Fig. 5-3 8-Bit Timer/Event Counter Block Diagram
Internal bus
INTTM1
8-bit compare
register (CR10)
8-bit compare
register (CR20)
Output
control
circuit
Match
TO2/P32
INTTM2
Match
fX/2 -fX
/210
8-bit timer
register 1 (TM1)
f
X
/212
8-bit timer
register 2 (TM2)
TI1/P33
Clear
fX/2-fX
/210
Selector
Clear
f
X
/212
TI2/P34
Output
control
circuit
TO1/P31
Internal bus
1 9
mPD78042F, 78043F, 78044F, 78045F
Fig. 5-4 Watch Timer Block Diagram
f
W
214
f
X
/28
5-bit counter
f
W
INTWT
Prescaler
f
XT
f
W
213
f
W
24
f
W
25
f
W
26
f
W
27
f
W
28
fW
29
INTTM3
Fig. 5-5 Watchdog Timer Block Diagram
f
X
24
f
WDT
Prescaler
f
X
23
f
WDT
f
WDT
22
f
WDT
23
f
WDT
24
f
WDT
25
f
WDT
26
f
WDT
28
INTWDT
Maskable
interrupt
request
2
8-bit
counter
RESET
INTWDT
Nonmaskable
interrupt
request
Fig. 5-6 6-Bit Up/Down Counter Block Diagram
INTP3/INTUD
Selector
Clear
6-bit up/down counter
Edge detector
CI0/P03/INTP3
(UDC)
Load
Match
Underflow
6-bit up/down counter
compare register (UDCC)
Internal bus
Caution When using the 6-bit up/down counter, set the CI0/P03/INTP3 pin in the input mode (set bit 3 of
port mode register 0 (PM03) to 1).
2 0
mPD78042F, 78043F, 78044F, 78045F
5.4 CLOCK OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the clock:
• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz (with main system clock: 5.0 MHz)
• 32.768 kHz (with subsystem clock: 32.768 kHz)
Fig. 5-7 Clock Output Control Circuit Block Diagram
fX /23
fX /24
fX /25
fX /26
fX /27
fX /28
fXT
PCL/P35
Sync circuit
Output control circuit
5.5 BUZZER OUTPUT CONTROL CIRCUIT
Clocks of the following frequencies can be output to the buzzer:
• 1.2 kHz/2.4 kHz/4.9 kHz (with main system clock: 5.0 MHz)
Fig. 5-8 Buzzer Output Control Circuit Block Diagram
f
f
f
X
X
X
/210
/211
/212
BUZ/P36
Output control circuit
2 1
mPD78042F, 78043F, 78044F, 78045F
5.6 A/D CONVERTER
An 8-bit resolution 8-channel A/D converter is provided.
This A/D converter can be started in the following two modes:
• Hardware start
• Software start
Fig. 5-9 A/D Converter Block Diagram
Series resistor string
AVDD
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
AVREF
Sample & hold circuit
Voltage comparator
AVSS
Successive approximation
register (SAR)
Control
circuit
Falling edge
detector
INTAD
INTP3
INTP3/P03
A/D conversion result
register (ADCR)
Internal bus
5.7 SERIAL INTERFACE
Two channels of clocked serial interfaces are provided.
• Serial interface channel 0
• Serial interface channel 1
Table 5-3 Serial Interface Groups and Functions
Function
Serial interface channel 0
• (MSB/LSB first selectable)
• (MSB first)
Serial interface channel 1
3-wire serial I/O mode
SBI (serial bus interface) mode
2-wire serial I/O mode
• (MSB/LSB first selectable)
—
—
• (MSB first)
3-wire serial I/O mode with
automatic transmission/
reception function
—
• (MSB/LSB first selectable)
2 2
mPD78042F, 78043F, 78044F, 78045F
Fig. 5-10 Serial Interface Channel 0 Block Diagram
Internal bus
SI0/SB0/P25
SO0/SB1/P26
Serial I/O shift
register 0 (SIO0)
Output
latch
Busy/acknowledge
output circuit
Bus release/
command/acknowledge
detector
Interrupt request
signal generator
INTCSI0
Serial clock
counter
SCK0/P27
fX X
/22 -f /29
Serial clock
control circuit
TO2
Fig. 5-11 Serial Interface Channel 1 Block Diagram
Internal bus
Automatic data
transmission/
reception interval
specification register
(ADTI)
Automatic data trans-
mission/reception
Buffer RAM
address pointer (ADTP)
Match
Serial I/O shift register 1
(SIO1)
SI1/P20
SO1/P21
STB/P23
5-bit counter
Handshake
control
circuit
BUSY/P24
SCK1/P22
Interrupt
request signal
generator
Serial clock
counter
INTCSI1
f
X
/22-f
TO2
X
/29
Serial clock control
circuit
Selector
2 3
mPD78042F, 78043F, 78044F, 78045F
5.8 FIP CONTROLLER/DRIVER
An FIP controller/driver having the following features is provided:
(a) Automatic output of segment signals (DMA operation) and digit signals
by automatically reading display data
(b) Display mode registers (DSPM0 and DSPM1) that can control an FIP of 9 to 24 segments and 2 to 16 digits
(c) Port pins not used for FIP display can be used as output port or I/O port pins.
(d) Display mode register (DSPM1) can adjust luminance in eight steps.
(e) Hardware suitable for key scan application using segment pins
(f) High-voltage output buffer (FIP driver) that can directly drive an FIP
(g) Display output pins can be connected to a pull-down resistor by the mask option.
Fig. 5-12 Selecting Display Modes
Selecting number of digits
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Caution If the total number of digits and segments exceeds 34, the specified number of digits takes
precedence.
2 4
mPD78042F, 78043F, 78044F, 78045F
Fig. 5-13 FIP Controller/Driver Block Diagram
Internal bus
Display data memory
Digit signal
generator
Segment data latch
Port output latch
Buffer with high withstand voltage
FIP0/P80 FIP1/P81
FIP33/P127
2 5
mPD78042F, 78043F, 78044F, 78045F
6. INTERRUPT FUNCTION AND TEST FUNCTION
6.1 INTERRUPT FUNCTION
The following three types of interrupt functions are available:
• Non-maskable interrupt : 1
• Maskable interrupt
• Software interrupt
: 13
: 1
Table 6-1 Interrupt Source List
Note 2
Interrupt source
Trigger
Note 1
Vector
table
address
Basic
configuration
type
Internal/
external
Interrupt
type
Default
priority
Name
Non-maskable
Maskable
—
0
INTWDT
Watchdog timer overflow
Internal
External
0004H
(A)
(B)
(with watchdog timer mode 1 selected)
INTWDT
Watchdog timer overflow
(with interval timer mode selected)
1
2
3
4
INTP0
Pin input edge detection
0006H
0008H
000AH
000CH
(C)
(D)
INTP1
INTP2
INTP3
INTUD
INTCSI0
INTCSI1
INTTM3
6-bit up/down counter match signal generation Internal
End of serial interface channel 0 transfer
(B)
5
6
7
000EH
0010H
0012H
End of serial interface channel 1 transfer
Reference time interval signal from watch
timer
8
9
INTTM0
INTTM1
INTTM2
16-bit timer/event counter match signal
generation
0014H
0016H
0018H
8-bit timer/event counter 1 match signal
generation
10
8-bit timer/event counter 2 match signal
generation
11
12
—
INTAD
INTKS
BRK
End of A/D converter conversion
001AH
001CH
003EH
Key scan timing from FIP controller/driver
Software
Execution of BRK instruction
—
(E)
Notes 1. Default priority is the priority order when several maskable interrupts are generated at the same time.
0 is the highest order and the 12 is the lowest order.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Fig. 6-1.
2 6
mPD78042F, 78043F, 78044F, 78045F
Fig. 6-1 Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal bus
Vector table
Interrupt
request
Priority
control circuit
address
generator
Standby
release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
PR
ISP
Vector table
Priority
control circuit
address
Interrupt
request
IF
generator
Standby
release signal
(C) External maskable interrupt (INTP0)
Internal bus
MK
Sampling clock
select register
(SCS)
External interrupt
mode register
(INTM0)
IE
PR
ISP
Vector table
address
generator
Priority
control circuit
Interrupt
request
Edge
detector
Sampling
clock
IF
Standby
release signal
2 7
mPD78042F, 78043F, 78044F, 78045F
Fig. 6-1 Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal bus
MK
External interrupt
mode register
(INTM0)
IE
PR
ISP
Vector table
address
generator
Priority
control circuit
Interrupt
request
Edge
detector
IF
Standby
release signal
(E) Software interrupt
Internal bus
Vector table
address
generator
Interrupt
request
Priority
control circuit
IF
IE
: Interrupt request flag
: Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
2 8
mPD78042F, 78043F, 78044F, 78045F
6.2 TEST FUNCTION
The following test function is available.
Test input source
Trigger
Overflow of watch timer
Internal/external
Name
INTWT
Internal
Fig. 6-2 Basic Configuration of Test Function
Internal bus
MK
Standby
release signal
Test input
source
IF
(INTWT)
IF : Test request flag
MK : Test mask flag
2 9
mPD78042F, 78043F, 78044F, 78045F
7. STANDBY FUNCTION
The standby function is to reduce the current dissipation of the system and can be effected in the following two
modes:
• HALT mode : In this mode, the operating clock of the CPU is stopped. By using this mode in combination with
the normal operation mode, the system can be operated intermittently, so that the average current
dissipation can be reduced.
• STOP mode : Oscillation of the main system clock is stopped. All the operations on the main system clock are
stopped, and therefore, the current dissipation of the system can be minimized with only the
subsystem clock oscillating.
Fig. 7-1 Standby Function
CSS = 1
CSS = 0
Main system
clock operation
Subsystem
clock operationNote
HALT instruction
STOP
instruction
HALT instruction
Interrupt
request
Interrupt
request
Interrupt
request
STOP mode
HALT mode
HALT modeNote
(Oscillation of main system
clock stopped)
(Clock supply to CPU stopped.
Oscillation continues)
(Clock supply to CPU stopped.
Oscillation continues)
Note By stopping the main system clock, the current dissipation can be reduced. When the CPU operates on
the subsystem clock, stop the main system clock by setting bit 7 (MCC) of the processor clock control
register (PCC). The STOP instruction cannot be used.
Caution When the main system clock is stopped and the subsystem clock is operating, to switch again
from the subsystem clock to the main system clock, allow sufficient time for the oscillation to
settle before switching, by coding the program accordingly.
8. RESET FUNCTION
The system can be reset in the following two modes:
• External reset by RESET pin
• Internal reset by watchdog timer that detects hang up
3 0
mPD78042F, 78043F, 78044F, 78045F
9. INSTRUCTION SET
(1) 8-bit instruction
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
operand
[HL + byte]
#byte
A
rNote
sfr
saddr
!addr16
PSW
[DE]
[HL]
[HL + B] $addr16
[HL + C]
1
None
First
operand
A
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROR
XCH
ADD
ADDC
SUB
SUBC
AND
OR
ROL
RORC
ROLC
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
B, C
sfr
DBNZ
DBNZ
★
MOV
MOV
MOV
saddr
MOV
ADD
ADDC
SUB
SUBC
AND
OR
INC
DEC
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL + byte]
[HL + B]
MOV
[HL + C]
X
C
MULU
DIVUW
Note Except for r = A
3 1
mPD78042F, 78043F, 78044F, 78045F
(2) 16-bit instruction
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second
operand
#word
AX
rpNote
sfrp
saddrp !addr16
SP
None
First
operand
AX
rp
ADDW
SUBW
CMPW
MOVW MOVW MOVW MOVW MOVW
XCHW
Note
MOVW MOVW
INCW
DECW
PUSH
POP
sfrp
MOVW MOVW
MOVW MOVW
MOVW
saddrp
!addr16
SP
MOVW MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instruction
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second
operand
A.bit
sfr.bit
saddr.bit PSW.bit [HL].bit
CY
$addr16
None
First
operand
A.bit
MOV1
BT
SET1
CLR1
BF
BTCLR
sfr.bit
MOV1
MOV1
MOV1
MOV1
BT
SET1
CLR1
BF
BTCLR
saddr.bit
PSW.bit
[HL].bit
CY
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
MOV1
AND1
OR1
SET1
CLR1
NOT1
XOR1
XOR1
XOR1
XOR1
XOR1
3 2
mPD78042F, 78043F, 78044F, 78045F
(4) Call/Branch instruction
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second
operand
AX
!addr16 !addr11 [addr5] $addr16
First
operand
Basic operation
BR
CALL
BR
CALLF CALLT BR
BC
BNC
BZ
BNZ
Compound
operation
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
3 3
mPD78042F, 78043F, 78044F, 78045F
★
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Symbol
VDD
Conditions
Rating
–0.3 to +7.0
Unit
V
Power supply
voltage
VDD – 40 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
V
VLOAD
AVDD
AVREF
AVSS
VI1
V
V
V
–0.3 to VDD + 0.3
Input voltage
P00-P04, P10-P17 (except when used as analog input pins),
P20-P27, P30-P37, X1, X2, XT2, RESET
V
Note 1
–0.3 to +16
V
V
VI2
P70-P74
N-ch open drain
P-ch open drain
VDD – 40 to VDD + 0.3
–0.3 to VDD + 0.3
VI3
P110-P117, P120-P127
Output voltage
VO1
VO2
VO3
VAN
IOH
P01-P03, P10-P17, P20-P27, P30-P37
P70-P74
V
Note 1
–0.3 to +16
V
VDD – 40 to VDD + 0.3
V
P80, P81, P90-P97, P100-P107, P110-P117, P120-P127
AVSS – 0.3 to AVREF + 0.3
Analog input voltage
ANI0-ANI7
Analog input pin
V
–10
–30
–30
–120
30
Output current,
high
P01-P03, P10-P17, P20-P27, P30-P37 per pin
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
°C
P01-P03, P10-P17, P20-P27, P30-P37 total
P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 per pin
P80, P81, P90-P97, P100-P107, P110-P117, P120-P127 total
Output current,
low
IOL
P01-P03, P10-P17, P20-P27, P30-P37,
P70-P74 per pin
Peak value
rms value
Peak value
rms value
Peak value
rms value
Note 2
15
100
P70-P74 total
Note 2
60
50
P01-P03, P10-P17, P20-P27, P30-P37 total
Note 2
20
PTNote 3
800
600
Total power
dissipation
TA = –40 to +60 °C
TA = +85 °C
–40 to +85
Operating
ambient
TA
temperature
–65 to +150
°C
Storage
Tstg
temperature
Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently. The
device should be operated within the limits specified under DC and AC Characteristics.
Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
Notes 1. For pins to which pull-up resistors are connected by the mask option, the rating is –0.3 to VDD + 0.3.
2. To obtain the rms value, calculate [rms value] = [peak value] ¥ √duty.
3 4
mPD78042F, 78043F, 78044F, 78045F
Notes 3. Permissible total power loss differs depending on the temperature (see the following figure).
800
600
400
200
–40
0
+40
Temperature [°C]
+80
How to calculate total power loss
The following three power consumption are available for the mPD78042F. The sum of the three power consumption
should be less than the total power loss PT (80 % or less of ratings is recommended).
1
CPU power consumption: calculate VDD (MAX.) ¥ IDD1 (MAX.).
2
Output pin power consumption: Normal output and display output are available. Power consumption when
maximum current flows into each output pin.
3
Pull-down resistor power consumption: Power consumption by pull-down resistor connected to display
output pin by the mask option.
3 5
mPD78042F, 78043F, 78044F, 78045F
The following total power consumption calculation example assumes the case where the characters shown in the
figure on the next page are displayed.
Example: The operating conditions are as follows:
VDD = 5 V ±10 %, operating at 5.0 MHz
Supply current (IDD) = 21.6 mA
Display outputs: 11 grids ¥ 10 segments (cut width is 1/16)
It is assumed that up to 15 mA flows to each grid pin, and that up to 3 mA flows to each segment pin.
It is also assumed that all display outputs are turned off at key scan timings.
Display output voltage: grid
segment VO3 = VDD – 0.4 V (Voltage drop of 0.4 V is assumed.)
Voltage applied to fluorescent indication panel (VLOAD) = –30 V
VO3 = VDD – 2 V (Voltage drop of 2 V is assumed.)
Mask-option pull-down resistor = 25 kΩ
3
The total power loss is calculated by determining power consumption
conditions.
to
under the above
1
Power consumption of CPU: 5.5 V ¥ 21.6 mA = 118.8 mW
1
2
Power consumption at output pins:
total current for all grids
number of grids + 1
Grid:
(VDD – VO3) ¥
¥ digit width (1 – cut width) =
15 mA ¥ 11 grids
2 V ¥
¥ (1 – 1/16) = 25.8 mW
11 grids + 1
total segment current for all dots to be lit
number of grids + 1
Segment: (VDD – VO3) ¥
0.4 V ¥
=
3 mA ¥ 31 dots
= 3.1 mW
11 grids + 1
3
Power consumption at pull-down resistors:
Grid:
(VO3 – VLOAD)2
number of grids
number of grids + 1
11 grids
¥
¥ digit width =
pull-down resistance
(5.5 V – 2 V – (–30 V))2
¥
¥ (1 – 1/16) = 38.6 mW
25 kΩ
11 grids + 1
Segment:
(VO3 – VLOAD)2
number of dots to be lit
number of grids + 1
31 dots
¥
=
pull-down resistance
(5.5 V – 0.4 V – (–30 V))2
¥
= 127.3 mW
25 kΩ
11 grids + 1
2
3
Total power consumption =
+
+
= 118.8 + 25.8 + 3.1 + 38.6 + 127.3 = 313.6 mW
1
In this example, the total power consumption does not exceed the rated value for the permissible total power loss
shown in the graph on the previous page. Therefore, the calculation result in this example (313.6 mW) satisfies the
requirement. If the total power consumption exceed the rated value for the permissible total power loss, the power
consumption must be reduced, by reducing the number of built-in pull-down resistors.
3 6
mPD78042F, 78043F, 78044F, 78045F
3 7
mPD78042F, 78043F, 78044F, 78045F
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
Resonator
Recommended circuit
Parameter
Conditions
MIN.
1
TYP.
MAX.
5
Unit
Ceramic
Oscillation frequency
MHz
Note 1
SS X1
V
X2
resonator
(fX)
Oscillation settling
4
5
ms
C1
C2
Note 2
time
Crystal
Oscillation frequency
1
4.19
MHz
SS X1
X2
V
Note 1
(fX)
C1
C2
Oscillation settling
VDD = 4.5 to 5.5 V
10
30
5
ms
Note 2
time
External
clock
X1 input frequency
1
MHz
Note 1
(fX)
X1
X2
X1 input high, low-level
width (tXH, tXL)
100
500
ns
µ
PD74HCU04
Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Charac-
teristics.
2. Time required until oscillation becomes stable after VDD is applied or the STOP mode is disabled.
Cautions 1. If the main system clock oscillator is to be used, wire the area inside the broken line square
as follows to avoid influence of wiring capacitance:
• Make wiring as short as possible.
• Do not cross other signal lines.
• Do not get close to lines with fluctuating large current.
• Make sure that the connecting points of the capacitor of the oscillator always have the same
electric potential as VSS.
• Do not connect the oscillator to a ground pattern that conducts a large current.
• Do not take out signal from the oscillator.
2. When switching to the main system clock again after the subsystem clock has been used with
the main system clock stopped, be sure to set the program to provide enough time for the
oscillation to stabilize.
3 8
mPD78042F, 78043F, 78044F, 78045F
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
Resonator
Crystal
Recommended circuit
Parameter
Conditions
MIN.
32
TYP.
MAX.
35
Unit
kHz
Oscillation frequency
32.768
XT2 VSS
R
XT1
Note 1
(fXT)
C3
C4
Oscillation settling
VDD = 4.5 to 5.5 V
1.2
2
s
Note 2
time
10
External
XT1 input frequency
32
5
100
kHz
ms
XT1
XT2
Note 1
(fXT)
XT1 input high, low-
level width (tXTH, tXTL)
15
Notes 1. It indicates only the oscillator characteristics. For the instruction execution time, see the AC Charac-
teristics.
2. Time required until oscillation becomes stable after VDD reaching MIN. of oscillation voltage range.
Cautions 1. If the subsystem clock oscillator is to be used, wire the area inside the broken line square as
follows to avoid influence of wiring capacitance:
• Make wiring as short as possible.
• Do not cross other signal lines.
• Do not get close to lines with fluctuating large current.
• Make sure that the connecting points of the capacitor of the oscillator always have the same
electric potential as VSS.
• Do not connect the oscillator to a ground pattern that conducts a large current.
• Do not take out signal from the oscillator.
2. The subsystem clock oscillator is more likely to have malfunctions due to noise than the main
system clock oscillator because gain for the subsystem clock oscillator is made lower to
reduce current consumption. When using the subsystem clock, be careful about how to
connect wires.
3 9
mPD78042F, 78043F, 78044F, 78045F
RECOMMENDED OSCILLATOR CONSTANT
MAIN SYSTEM CLOCK: CERAMIC RESONATOR (TA = –40 to +85 °C)
Manufacturer
Product name
Frequency
(MHz)
Recommended
circuit constant
Oscillator voltage range
Remark
C1 (pF)
100
100
—
C2 (pF) MIN. (V) MAX. (V)
Note
Murata Mfg. Co., Ltd.
CSB1000J
1.00
2.00
2.00
4.00
4.00
5.00
5.00
1.00
2.00
100
100
—
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
2.7
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
Rd = 4.7 kΩ
CSA2.00MG040
CST2.00MG040
CSA4.00MG
CST4.00MGW
CSA5.00MG
CST5.00MGW
CCR1000K2
CCR2.0MC3
Built-in capacitor
Built-in capacitor
30
30
—
—
30
30
—
—
Built-in capacitor
Surface-mount type
TDK Corp.
150
—
150
—
Built-in capacitor,
surface-mount type
CCR4.0MC3
4.00
—
—
2.7
5.5
Built-in capacitor,
surface-mount type
FCR4.0MC5
CCR5.0MC3
4.00
5.00
—
—
—
—
2.7
2.7
5.5
5.5
Built-in capacitor
Built-in capacitor,
surface-mount type
FCR5.0MC5
5.00
2.00
2.00
—
33
33
—
33
33
2.7
2.7
2.7
5.5
5.5
5.5
Built-in capacitor
Built-in capacitor
Matsushita Electronics
Components Co., Ltd.
EFOEC2004A4
EFOS2004B5
Built-in capacitor,
surface-mount type
EFOEC3584A4
EFOS3584B5
3.58
3.58
33
33
33
33
2.7
2.7
5.5
5.5
Built-in capacitor
Built-in capacitor,
surface-mount type
EFOEC4004A4
EFOS4004B5
4.00
4.00
33
33
33
33
2.7
2.7
5.5
5.5
Built-in capacitor
Built-in capacitor,
surface-mount type
EFOEC5004A4
EFOS5004B5
5.00
5.00
33
33
33
33
2.7
2.7
5.5
5.5
Built-in capacitor
Built-in capacitor,
surface-mount type
Note When the CSB1000J (1.00 MHz) manufactured by Murata Mfg. is used, a limiting resistor (4.7 kΩ) is
necessary (see the figure in the next page). When one of other resonators is used, no limiting resistor is
required.
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable
oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit
requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency
of the resonator in the application circuit. For this, it is necessary to directly contact the
manufacturer of the resonator that being used.
4 0
mPD78042F, 78043F, 78044F, 78045F
Recommended sample circuit for the main system clock when the CSB1000J manufactured by Murata Mfg.
is used
VSS
X1
X2
CSB1000J
Rd
C2
C1
VDD
4 1
mPD78042F, 78043F, 78044F, 78045F
CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
Input
CIN
f = 1 MHz Unmeasured pins returned to 0 V
capacitance
Output
COUT
f = 1 MHz Unmeasured pins returned to 0 V
35
15
pF
pF
capacitance
Input/output
capacitance
CIO
f = 1 MHz
P01-P03, P10-P17,
Unmeasured pins returned to 0 V P20-P27, P30-P37
P70-P74
20
35
pF
pF
P110-P117, P120-P127
Remark Unless otherwise specified, the characteristics of the shared pin are the same as the characteristics of
the port pin.
POWER SUPPLY VOLTAGE (TA = –40 to +85 °C)
Parameter
Conditions
MIN.
2.7Note 2
4.5
TYP.
MAX.
5.5
Unit
V
Note 1
CPU
Display controller/driver
5.5
V
PWM mode of 16-bit
timer/event counter
(TM0)
4.5
5.5
V
A/D converter
4.0
2.7
5.5
5.5
V
V
Other hardware
Notes 1. Except for system clock oscillator, display controller/driver, and PWM.
2. Operating power supply voltage differs depending on the cycle time. See the AC Characteristics.
4 2
mPD78042F, 78043F, 78044F, 78045F
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
Symbol
VIH1
MIN.
0.7VDD
0.8VDD
0.7VDD
VDD – 0.5
VDD – 0.5
VDD – 0.3
0.65VDD
0.7VDD
0.7VDD
VDD – 0.5
0
MAX.
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Parameter
Conditions
TYP.
High-level
VDD
P21, P23
P00-P03, P20, P22, P24-P27, P33, P34, RESET
P70-P74 N-ch open drain
input voltage
VDD
VIH2
VIH3
VIH4
VIH5
Note 1
15
Note 2
VDD
VDD
X1, X2
Note 2
XT1/P04, XT2
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD
VDD
VIH6
VIH7
P10-P17, P30-P32, P35-P37
P110-P117, P120-P127
P21, P23
VDD
VDD
VDD
0.3VDD
0.2VDD
0.3VDD
0.2VDD
0.4
Low-level
VIL1
VIL2
VIL3
input voltage
0
P00-P03, P20, P22, P24-P27, P33, P34, RESET
P70-P74 VDD = 4.5 to 5.5 V
0
0
Note 2
X1, X2
VIL4
VIL5
0
Note 2
0.4
0
XT1/P04, XT2
VDD = 4.5 to 5.5 V
0.3
0
0.3VDD
0.3VDD
VIL6
VIL7
VOH
0
P10-P17, P30-P32, P35-P37
P110-P117, P120-P127
VDD – 35
VDD – 1.0
High-level
output
P01-P03, P10-P17, P20-P27,
P30-P37, P80, P81, P90-P97,
P100-P107, P110-P117,
P120-P127
VDD = 4.5 to 5.5 V
IOH = –1 mA
voltage
VDD – 0.5
IOH = –100 mA
V
V
0.4
VOL1
2.0
0.4
Low-level
output
P30-P37, P70-P74
VDD = 4.5 to 5.5 V,
IOL = 15 mA
voltage
P01-P03, P10-P17, P20-P27
SB0, SB1, SCK0
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
V
V
V
VOL2
VOL3
VDD = 4.5 to 5.5 V,
With open-drain and
pull-up (R = 1 kW)
0.2VDD
0.5
P01-P03, P10-P17, P20-P27,
P30-P37, P70-P74
IOL = 400 mA
Notes 1. Pins to which pull-up resistors are connected by the mask option become VDD.
2. If the X1 pin is used for high-level voltage input, the X2 pin is used for low-level voltage input, or vice
versa. This is also true for the XT1/P04 pin and XT2 pin.
Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
4 3
mPD78042F, 78043F, 78044F, 78045F
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
Symbol
MIN.
TYP.
MAX.
3
Unit
Parameter
Conditions
P00-P03, P10-P17,
mA
ILIH1
VIN = VDD
High-level
input leakage
current
P20-P27, P30-P37, RESET
X1, X2, XT1/P04, XT2
P70-P74
mA
mA
mA
mA
mA
ILIH2
ILIH3
ILIH4
20
VIN = 15 V
20
Note 1
VDD = 4.5 to 5.5 V
3
P110-P117, P120-P127,
VIN = VDD
Note 2
3
P00-P03, P10-P17,
–3
ILIL1
VIN = 0 V
Low-level
input leakage
current
P20-P27, P30-P37, RESET
mA
mA
mA
mA
X1, X2, XT1/P04, XT2
P70-P74
–20
ILIL2
ILIL3
ILIL4
ILOH1
Note 3
–3
P110-P117, P120-P127
–10
P01-P03, P10-P17, P20-P27,
P30-P37, P80, P81, P90-P97,
P100-P107, P110-P117, P120-P127
3
VOUT = VDD
High-level
output
leakage
Note 4
current
mA
mA
P70-74, N-ch open drain
20
–3
VOUT = 15 V
VOUT = 0 V
ILOH2
ILOL1
P01-P03, P10-P17, P20-P27,
P30-P37, P70-P74
Low-level
output
leakage
P80, P81, P90-P97, P100-P107,
P110-P117, P120-P127
–10
VOUT = VLOAD = VDD – 35 V
mA
mA
k Ω
k Ω
ILOL2
IOD
R1
Note 4
current
–15
20
–25
40
VDD = 4.5 to 5.5 V, VO3 = VDD – 2 V
Display output
current
90
90
VIN = 0 V, P70-P74
Mask option
pull-up resistor
VDD = 4.5 to 5.5 V
15
40
R2
VIN = 0 V,
Software pull-
up resistor
P01-P03, P10-P17,
P20-P27, P30-P37
20
25
500
135
k Ω
k Ω
VO3 – VLOAD = 35 V
VO3 – VSS = 5 V
P80, P81, P90-P97,
P100-P107, P110-P117,
P120-P127
65
R3
R4
Mask option
pull-down
resistor
15
40
90
k Ω
k Ω
40
80
150
P30-P37, VIN = VDD
Notes 1. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the
specification of the mask option), a high-level input leakage current of 150 mA (MAX.) flows only during
1.5 clocks after a read instruction has been executed to read out port 11 or 12 (P11 or P12) or port mode
register 11 or 12 (PM11 or PM12). Outside the 1.5 clocks after a read instruction, the current is 3 mA
(MAX.).
2. When P110 to P117 and P120 to P127 do not contain the pull-down resistors (according to the
specification of the mask option), a high-level input leakage current of 90 mA (MAX.) flows only during
1.5 clocks after a read instruction has been executed to read out P11, P12, PM11, or PM12. Outside
the 1.5 clocks after a read instruction, the current is 3 mA (MAX.).
3. When P70 to P74 do not contain the pull-down resistors (according to the specification of the mask
option), a low-level input leakage current of –150 mA (MAX.) flows only during 1.5 clocks after a read
instruction has been executed to read out port 7 (P7) or port mode register 7 (PM7). Outside the 1.5
clocks after a read out instruction, the current is –3 mA (MAX.).
4. Current which flows in the built-in pull-up or pull-down resistor is not included.
Remark Unless otherwise specified, the characteristics of a shared pin are the same as those of a port pin.
4 4
mPD78042F, 78043F, 78044F, 78045F
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
Parameter Symbol Conditions
5.0 MHz crystal oscillation
MIN.
TYP.
7.2
0.9
1.3
550
60
MAX.
21.6
2.7
Unit
mA
mA
mA
mA
Power supply IDD1
VDD = 5.0 V ±10 %Note 2
VDD = 3.0 V ±10 %Note 3
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
Note 1
current
Operating mode
IDD2
IDD3
IDD4
IDD5
5.0 MHz crystal oscillation
HALT mode
3.9
1650
120
70
32.768 kHz crystal oscillation
mA
Note 4
Operating mode
35
mA
32.768 kHz crystal oscillation
25
50
mA
Note 4
HALT mode
5
10
mA
XT1 = 0 V
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
1
20
10
mA
mA
STOP mode
0.5
Feedback resistor connected
IDD6
XT1 = 0 V
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
0.1
20
10
mA
mA
STOP mode
0.05
Feedback resistor not connected
Notes 1. This current excludes the AVREF current, port current, and current which flows in the built-in pull-down
resistor (mask option).
2. When operating at high-speed mode (when the processor clock control register (PCC) is set to 00H)
3. When operating at low-speed mode (when the PCC is set to 04H)
4. When the main system clock is stopped
4 5
mPD78042F, 78043F, 78044F, 78045F
AC CHARACTERISTICS
(1) Basic operation (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
TYP.
122
Parameter
Symbol
TCY
Conditions
MIN.
0.4
MAX.
Unit
Cycle time
(minimum
instruction
execution
time)
Operated with main system clock
VDD = 4.5 to 5.5 V
ms
ms
ms
32
32
0.8
Note 1
Operated with subsystem clock
VDD = 4.5 to 5.5 V
40
125
TI1, 2 input
frequency
MHz
kHz
ns
fTI
0
0
2
138
TI1, 2 input
high, low-level
width
tTIH
tTIL
VDD = 4.5 to 5.5 V
250
3.6
ms
tINTH
Interrupt
input high,
low-level
width
8/fsamNote 2
INTP0
ms
tINTL
tRSL
INTP1-INTP3
ms
ms
10
10
RESET low-
level width
Notes 1. Value when external clock input is used as subsystem clock. When crystal is used, the value becomes
114 ms.
2. Selection of fsam = fX/2N+1, fX/64, fX/128 is available (N = 0 to 4) by bits 0 and 1 (SCS0, SCS1) of sampling
clock select register (SCS).
TCY vs. VDD (with main system clock operated)
60
30
Operation guarantee
range
10
µ
2.0
1.0
0.5
0.4
0
1
2
3
4
5
6
Power supply voltage VDD [V]
4 6
mPD78042F, 78043F, 78044F, 78045F
(2) Serial interface (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V)
(a) Serial interface channel 0
(i) Three-wire serial I/O mode (SCK0: Internal clock output)
Parameter
SCK0 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tKCY1
3200
SCK0 high, low-level width
tKH1
tKL1
VDD = 4.5 to 5.5 V
tKCY1/2
KCY1/2
–
50
t
–
150
SI0 setup time to SCK0↑
SI0 hold time from SCK0↑
tSIK1
tKSI1
tKSO1
100
400
Note
SCK0ØÆ SO0 output
delay time
C = 100 pF
VDD = 4.5 to 5.5 V
300
1000
Note C is a load capacitance of the SCK0 or SO0 output line.
(ii) Three-wire serial I/O mode (SCK0: External clock input)
Parameter
SCK0 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY2
3200
400
SCK0 high, low-level width
tKH2
tKL2
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
1600
100
SI0 setup time to SCK0↑
SI0 hold time from SCK0↑
tSIK2
tKSI2
tKSO2
400
Note
SCK0ØÆ SO0 output
delay time
C = 100 pF
VDD = 4.5 to 5.5 V
300
1000
160
SCK0 rise time and fall time
tR2
tF2
Note C is a load capacitance of the SO0 output line.
4 7
mPD78042F, 78043F, 78044F, 78045F
(iii) SBI mode (SCK0: Internal clock output)
Parameter
SCK0 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tKCY3
3200
SCK0 high, low-level width
tKH3
tKL3
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
tKCY3/2 – 50
t
KCY3/2 – 150
100
SB0, SB1 setup time to SCK0↑ tSIK3
300
SB0, SB1 hold time from
tKSI3
tKCY3/2
SCK0↑
SCK0ØÆSB0, SB1 output
delay time
tKSO3
R = 1 kW,
C = 100 pF
VDD = 4.5 to 5.5 V
0
250
ns
ns
ns
ns
ns
ns
Note
0
1000
SCK0↑ÆSB0, SB1Ø
tKSB
tSBK
tSBH
tSBL
tKCY3
tKCY3
tKCY3
tKCY3
SB0, SB1ØÆ SCK0Ø
SB0, SB1 high-level width
SB0, SB1 low-level width
Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance.
(iv) SBI mode (SCK0: External clock input)
Parameter
SCK0 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tKCY4
3200
400
SCK0 high, low-level width
tKH4
tKL4
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
1600
100
SB0, SB1 setup time to SCK0↑ tSIK4
300
SB0, SB1 hold time from
tKSI4
tKCY4/2
SCK0↑
SCK0ØÆSB0, SB1 output
delay time
tKSO4
R = 1 kW,
C = 100 pF
VDD = 4.5 to 5.5 V
0
300
ns
ns
ns
ns
ns
ns
ns
Note
0
1000
SCK0↑ÆSB0, SB1Ø
tKSB
tSBK
tSBH
tSBL
tKCY4
tKCY4
tKCY4
tKCY4
SB0, SB1ØÆSCK0Ø
SB0, SB1 high-level witdh
SB0, SB1 low-level width
SCK0 rise time and fall time
tR4
tF4
160
Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance.
4 8
mPD78042F, 78043F, 78044F, 78045F
(v) Two-wire serial I/O mode (SCK0: Internal clock output)
Parameter
SCK0 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
1600
3800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY5
R = 1 kW,
C = 100 pF
Note
SCK0 high-level width
SCK0 low-level width
tKH5
tKL5
tKCY5/2
tKCY5/2
–
160
50
–
SB0, SB1 setup time to SCK0↑ tSIK5
300
600
SB0, SB1 hold time from
tKSI5
SCK0↑
SCK0ØÆ SB0, SB1 output
delay time
tKSO5
VDD = 4.5 to 5.5 V
0
0
250
ns
ns
1000
Note R is a load resistance of the SCK0, SB0, or SB1 output line, and C is its load capacitance.
(vi) Two-wire serial I/O mode (SCK0: External clock input)
Parameter
SCK0 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
1600
3800
650
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
tKCY6
SCK0 high-level width
SCK0 low-level width
tKH6
tKL6
800
SB0, SB1 setup time to SCK0↑ tSIK6
100
SB0, SB1 hold time from
tKSI6
tKCY6/2
SCK0↑
SCK0ØÆ SB0, SB1 output
delay time
tKSO6
R = 1 kW,
C = 100 pF
VDD = 4.5 to 5.5 V
0
0
300
1000
160
ns
ns
ns
Note
SCK0 rise time and fall time
tR6
tF6
Note R is a load resistance of the SB0 or SB1 output line, and C is its load capacitance.
4 9
mPD78042F, 78043F, 78044F, 78045F
(b) Serial interface channel 1
(i) Three-wire serial I/O mode (SCK1: Internal clock output)
Parameter
SCK1 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
tKCY7
3200
SCK1 high, low-level width
tKH7
tKL7
VDD = 4.5 to 5.5 V
tKCY7/2
KCY7/2
–
50
t
–
150
SI1 setup time to SCK1↑
SI1 hold time from SCK1↑
tSIK7
tKSI7
tKSO7
100
400
Note
SCK1ØÆ SO1 output delay
time
C = 100 pF
VDD = 4.5 to 5.5 V
300
1000
Note C is a load capacitance of the SCK1 or SO1 output line.
(ii) Three-wire serial I/O mode (SCK1: External clock input)
Parameter
SCK1 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY8
3200
400
SCK1 high, low-level width
tKH8
tKL8
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
1600
100
SI1 setup time to SCK1↑
SI1 hold time from SCK1↑
tSIK8
tKSI8
tKSO8
400
Note
SCK1ØÆ SO1 output delay
time
C = 100 pF
VDD = 4.5 to 5.5 V
300
1000
160
SCK1 rise time and fall time
tR8
tF8
Note C is a load capacitance of the SO1 output line.
5 0
mPD78042F, 78043F, 78044F, 78045F
(iii) 3-wire serial I/O mode with automatic transmission/reception function (SCK1: internal clock
output)
Parameter
SCK1 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY9
3200
SCK1 high, low-level width
tKH9
tKL9
VDD = 4.5 to 5.5 V
tKCY9/2
KCY9/2
– 50
t
–
150
SI1 setup time to SCK1↑
SI1 hold time from SCK1↑
tSIK9
tKSI9
100
400
Note
SCK1ØÆSO1 output delay time tKSO9
C = 100 pF
VDD = 4.5 to 5.5 V
300
1000
SCK1↑ÆSTB•
tSBD
tSBW
t
KCY9/2
tKCY9
–
–
100
30
tKCY9/2 + 100
Strobe signal high level width
tKCY9 + 30
Busy signal setup time (to busy tBYS
signal detection timing)
100
Busy signal hold time (to busy
signal detection timing)
tBYH
100
ns
ns
Busy inactive Æ SCK1Ø
tSPS
2tKCY9
Note C is a load capacitance of the SCK1 or SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmission/reception function (SCK1: external clock
input)
Parameter
SCK1 cycle time
Symbol
Conditions
VDD = 4.5 to 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY10
3200
400
SCK1 high, low-level width
tKH10
tKL10
VDD = 4.5 to 5.5 V
1600
100
SI1 setup time to SCK1↑
SI1 hold time from SCK1↑
tSIK10
tKSI10
tKSO10
400
Note
SCK1ØÆ SO1 output delay
time
C = 100 pF
VDD = 4.5 to 5.5 V
300
1000
160
SCK1 rise time and fall time
tR10
tF10
Note C is a load capacitance of the SO1 output line.
5 1
mPD78042F, 78043F, 78044F, 78045F
AC timing test points (except X1, XT1 input)
0.8VDD
0.2VDD
0.8VDD
Test points
0.2VDD
Clock timing
1/fX
tXH
tXL
VDD – 0.5 V
0.4 V
X1 input
1/fXT
t
XTH
t
XTL
VDD – 0.5 V
XT1 input
0.4 V
TI timing
1/fTI
t
TIH
t
TIL
TI1, TI2
5 2
mPD78042F, 78043F, 78044F, 78045F
Serial transfer timing
3-wire serial I/O mode:
t
KCY1, 2, 7, 8
t
KL1, 2, 7, 8
t
KH1, 2, 7, 8
t
R2, 8
t
F2, 8
SCK0, SCK1
t
SIK1, 2, 7, 8
t
KSI1, 2, 7, 8
Input data
SI0, SI1
t
KSO1, 2, 7, 8
SO0, SO1
Output data
SBI mode (bus release signal transfer):
t
KCY3, 4
t
KL3, 4
R4
t
KH3, 4
t
t
F4
SCK0
t
SIK3, 4
t
KSB
t
SBL
t
SBH
t
SBK
t
KSI3, 4
SB0, SB1
t
KSO3, 4
SBI mode (command signal transfer):
t
KCY3, 4
t
KL3, 4
t
KH3, 4
SCK0
t
SIK3, 4
t
KSB
t
SBK
t
KSI3, 4
SB0, SB1
t
KSO3, 4
5 3
mPD78042F, 78043F, 78044F, 78045F
2-wire serial I/O mode:
t
KCY5, 6
t
KH5, 6
t
KL5, 6
R6
t
t
F6
SCK0
t
SIK5, 6
t
KSO5, 6
t
KSI5, 6
SB0, SB1
3-wire serial I/O mode with automatic transmission/reception function:
SO1
SI1
D2
D1
D0
D7
D2
D1
D0
D7
t
KSI9, 10
t
SIK9, 10
t
KH9, 10
t
KSO9, 10
t
F10
SCK1
STB
t
R10
t
KL9, 10
KCY9, 10
t
t
SBD
t
SBW
3-wire serial I/O mode with automatic transmission/reception function (busy processing):
Note
9Note
10Note
1
10 + n
SCK1
7
8
t
BYH
t
SPS
t
BYS
BUSY
(Active high)
Note SCK does not become low actually at this point, but is indicated so to conform to the timing specification.
5 4
mPD78042F, 78043F, 78044F, 78045F
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVDD = VDD = 4.0 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
%
Note 1
Total error
Conversion time
0.8
Note 2
tCONV
1 MHz - fX - 5.0 MHz
19.1
2.86
AVSS
200
30
ms
ms
V
Note 3
Sampling time
tSAMP
VIAN
Analog signal input
voltage
AVREF
Reference voltage
AVREF resistor
AVDD current
AVREF
RAVREF
AIDD
4.0
4
AVDD
V
14
k Ω
mA
200
400
Notes 1. Quantization error (±1/2LSB) is not included. This parameter is indicated as the ratio to the full-scale
value.
2. Set the A/D conversion time to 19.1 ms or more.
3. Sampling time depends on the conversion time.
5 5
mPD78042F, 78043F, 78044F, 78045F
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(TA = –40 to +85 °C)
Parameter
Symbol
VDDDR
Conditions
MIN.
2.0
TYP.
0.1
MAX.
5.5
Unit
V
Data retention supply
voltage
Data retention supply
current
IDDDR
VDDDR = 2.0 V
10
mA
Subsystem clock stopped
Feedback resistor not connected
Release signal set time tSREL
0
ms
ms
ms
17
Oscillation stabilization
wait time
tWAIT
Release by RESET
Release by interrupt
2 /fX
Note
Note Selection of 212/fX, 214/fX to 217/fX is available by bits 0 to 2 (OSTS0 to OSTS2) of oscillation settling time
select register (OSTS).
Data retention timing (STOP mode release by RESET)
Internal reset operation
HALT mode
Operating mode
STOP mode
Data retention mode
V
DD
VDDDR
t
SREL
STOP instruction execution
RESET
t
WAIT
Data retention timing (standby release signal: STOP mode release by interrupt signal)
HALT mode
Operating mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
5 6
mPD78042F, 78043F, 78044F, 78045F
Interrupt input timing
t
INTL
tINTH
INTP0-INTP2
t
INTL
INTP3
RESET input timing
t
RSL
RESET
5 7
mPD78042F, 78043F, 78044F, 78045F
★
11. CHARACTERISTIC CURVE (REFERENCE VALUE)
I
DD vs. VDD (Main system clock: 5.0 MHz)
(TA = 25 °C)
10.0
5.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 and XT1 oscillate)
1.0
0.5
f
f
X
= 5.0 MHz
XT = 32.768 kHz
0.1
PCC = B0H
0.05
HALT (X1 stops but XT1 oscillates)
(X1 stops but XT1 oscillates)
STOP
0.01
0.005
0.001
0
2
3
4
5
6
7
8
Supply voltage VDD [V]
5 8
mPD78042F, 78043F, 78044F, 78045F
I
DD vs. f
X
(VDD = 3 V, T
A
= 25 °C)
4
3
2
1
0
PCC
=
00H
PCC
PCC
=
=
01H
02H
PCC
PCC
=
=
03H
04H
HALT
(X1 oscil-
lates)
0
1
2
3
4
5
6
Clock oscillation frequency f
X
[MHz]
I
DD vs. f
X
(VDD = 5 V, T
A
= 25 °C)
7
6
5
4
PCC
=
00H
PCC
PCC
=
=
01H
02H
3
2
PCC
PCC
=
=
03H
04H
HALT
(X1 oscil-
lates)
1
0
0
1
2
3
4
5
6
Clock oscillation frequency f
X
[MHz]
5 9
mPD78042F, 78043F, 78044F, 78045F
VOL vs. IOL (Port 1)
(TA = 25 °C)
VDD = 6 V
VDD = 5 V
30
20
VDD = 4 V
VDD = 3 V
10
0
0
0.5
1.0
1.5
Low-level output voltage VOL [V]
VOL vs. IOL (Ports 0, 2, and 3)
(TA = 25 °C)
V
DD = 6 V VDD = 5 V
30
20
V
DD = 4 V
V
DD = 3 V
10
0
0
0.5
1.0
1.5
Low-level output voltage VOL [V]
6 0
mPD78042F, 78043F, 78044F, 78045F
V
OL vs. IOL (Port 7)
(TA = 25 °C)
VDD = 6 V
V
DD = 5 V
VDD = 4 V
30
20
VDD = 3 V
10
0
0
0.5
1.0
1.5
Low-level output voltage VOL [V]
6 1
mPD78042F, 78043F, 78044F, 78045F
V
DD – VOH vs. IOH (Port 0 - Port 3)
(T
A
= 25 °C)
V
DD = 5 V
VDD = 6 V
VDD = 4 V
–10
V
DD = 3 V
–5
0
0
0.5
1.0
1.5
High-level output voltage VDD – VOH [V]
V
DD – VOH vs. IOH (Port 8 - Port 12)
(TA
= 25 °C)
V
DD = 6 V VDD = 5 V
–30
V
DD = 4 V
VDD = 3 V
–20
–10
0
0
1.0
2.0
3.0
High-level output voltage
VDD – VOH [V]
6 2
mPD78042F, 78043F, 78044F, 78045F
12. PACKAGE DRAWING
★
80 PIN PLASTIC QFP (14 20)
A
B
41
40
64
65
detail of lead end
S
C D
R
Q
25
24
80
1
F
G
J
M
H
I
K
P
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
A
23.6±0.4
0.929±0.016
+0.009
0.795
B
20.0±0.2
–0.008
+0.009
0.551
C
14.0±0.2
–0.008
D
F
17.6±0.4
1.0
0.693±0.016
0.039
G
0.8
0.031
+0.004
0.014
H
0.35±0.10
–0.005
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P.)
+0.008
0.071
K
L
1.8±0.2
0.8±0.2
–0.009
+0.009
0.031
–0.008
+0.10
0.15
+0.004
0.006
M
–0.05
–0.003
N
P
Q
R
S
0.10
0.004
2.7
0.106
0.1±0.1
5°±5°
3.0 MAX.
0.004±0.004
5°±5°
0.119 MAX.
P80GF-80-3B9-3
Remark The shape and material of the ES version are the same as those of the corresponding mass-produced
product.
6 3
mPD78042F, 78043F, 78044F, 78045F
★
13. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the mPD78042F, mPD78043F, mPD78044F, or
mPD78045F.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 13-1 Soldering Conditions for Surface-Mount Devices
mPD78042FGF-¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm)
mPD78043FGF-¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm)
mPD78044FGF-¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm)
mPD78045FGF-¥¥¥-3B9: 80-pin plastic QFP (14 ¥ 20 mm)
Soldering process
Infrared ray reflow
Soldering conditions
Recommended conditions
IR35-00-3
Peak package's surface temperature: 235 °C
Reflow time: 30 seconds or less (210 °C or more)
Maximum allowable number of reflow processes: 3
VPS
Peak package's surface temperature: 215 °C
Reflow time: 40 seconds or less (200 °C or more)
Maximum allowable number of reflow processes: 3
VP15-00-3
WS60-00-1
Wave soldering
Solder temperature: 260 °C or less
Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature : 120 °C max.
(measured on the package surface)
Partial heating method
Terminal temperature: 300 °C or less
—
Heat time: 3 seconds or less (for one side of a device)
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
6 4
mPD78042F, 78043F, 78044F, 78045F
APPENDIX A DEVELOPMENT TOOLS
The following tools are available for development of systems using the mPD78042F, mPD78043F, mPD78044F,
or mPD78045F.
Language processing software
Notes 1, 2, 3, 4
RA78K/0
CC78K/0
DF78044
Assembler package common to 78K/0 series
C compiler package common to 78K/0 series
Device file for mPD78044A subseries
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4
CC78K/0-L
C compiler library source file common to 78K/0 series
PROM writing tools
PG-1500
PROM programmer
PA-78P048GF
Programmer adapter connected to PG-1500
PA-78P048KL-S
Notes 1, 2
PG-1500 controller
Control program for PG-1500
Debugging tools
IE-78000-R
In-circuit emulator common to 78K/0 series
In-circuit emulator common to 78K/0 series (for integrated debugger)
Break board common to 78K/0 series
Note 8
IE-78000-R-A
★
IE-78000-R-BK
IE-78044-R-EM
EP-78130GF-R
EV-9200G-80
Emulation board for evaluating mPD78044A subseries
Emulation probe common to mPD78134
Socket mounted on target system created for 80-pin plastic QFP
System simulator common to 78K/0 series
Integrated debugger for IE-78000-R-A
Notes 5, 6, 7
SM78K0
Notes 4, 5, 6, 7, 8
★
ID78K0
Notes 1, 2
SD78K/0
Screen debugger for IE-78000-R
Notes 1, 2, 5, 6, 7
DF78044
Device file common to mPD78044A subseries
Real-time OS
Notes 1, 2, 3, 4
RX78K/0
Real-time OS for 78K/0 series
OS for 78K/0 series
Notes 1, 2, 3, 4
MX78K0
Notes 1. PC-9800 series (MS-DOSTM) based
2. IBM PC/ATTM and compatible (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 series 300TM (HP-UXTM) based
4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (SunOSTM) based, EWS-4800 series (EWS-
UX/V) based
5. PC-9800 series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
★
8. Under development
6 5
mPD78042F, 78043F, 78044F, 78045F
Fuzzy inference development support system
Note 1
Note 3
FE9000
FT9080
/FE9200
/FT9085
Fuzzy knowledge data creation tool
Note 1
Note 2
Translator
Notes 1, 2
FI78K0
Fuzzy inference module
Fuzzy inference debugger
Notes 1, 2
FD78K0
Notes 1. PC-9800 series (MS-DOS) based
2. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS) based
3. IBM PC/AT and compatible (PC DOS/IBM DOS/MS-DOS + Windows) based
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on third party develop-
ment tools.
2. RA78K/0, CC78K/0, SM78K/0, ID78K0, SD78K/0, and RX78K/0 are used in combination with
DF78044.
6 6
mPD78042F, 78043F, 78044F, 78045F
APPENDIX B RELATED DOCUMENTS
• Documents Related to Devices
Document No.
Document name
Japanese
U10908J
English
U10908E
This manual
U10611E
—
mPD78044F Sub-Series User’s Manual
mPD78042F, 78043F, 78044F, 78045F Data Sheet
mPD78P048A Data Sheet
U10700J
U10611J
U10701J
IEU-849
U10903J
U10904J
mPD78044A, 78044F Sub-Series Special Function Registers
78K/0 Series User’s Manual, Instruction
78K/0 Series Instruction Summary Sheet
78K/0 Series Instruction Set
IEU-1372
—
—
• Documents Related to Development Tools (User’s Manual)
Document No.
Japanese
Document name
English
EEU-1399
EEU-1404
EEU-1402
EEU-1280
EEU-1284
EEA-1208
—
RA78K Series Assembler Package
Operation
Language
EEU-809
EEU-815
EEU-817
EEU-656
EEU-655
EEA-618
EEU-777
EEU-651
EEU-704
EEU-5008
EEU-810
U10057J
EEU-867
EEU-833
EEU-943
EEU-5002
U10092J
RA78K Series Structured Assembler Preprocessor
CC78K Series C Compiler
Operation
Language
CC78K/0 Compiler Application Note
CC78K Series Library Source File
PG-1500 PROM Programmer
PG-1500 Controller PC-9800 Series (MS-DOS) Base
PG-1500 Controller IBM PC Series (PC DOS) Base
IE-78000-R
Programming Know-How
EEU-1335
EEU-1291
U10540E
U11376E
U10057E
EEU-1427
EEU-1424
EEU-1470
U10181E
U10092E
IE-78000-R-A
★
IE-78000-R-BK
IE-78044-R-EM
EP-78130GF-R
SM78K0 System Simulator
SM78K Series System Simulator
Reference
External Parts User Open
Interface Specifications
★
ID78K0 Integrated Debugger
SD78K/0 Screen Debugger
PC-9800 Series (MS-DOS) Base
SD78K/0 Screen Debugger
IBM PC/AT (PC DOS) Base
Reference
Tutorial
U11151J
EEU-852
EEU-816
EEU-5024
U11279J
—
U10539E
—
Reference
Tutorial
EEU-1414
EEU-1413
Reference
Caution The above documents may be revised without notice. Use the latest versions when you design
an application system.
6 7
mPD78042F, 78043F, 78044F, 78045F
• Documents Related to Software to Be Incorporated into the Product (User’s Manual)
Document No.
Document name
Japanese
EEU-912
English
78K/0 Series Real-Time OS
OS for 78K/0 Series MX78K0
Basic
—
—
Installation
Technical
Basic
EEU-911
EEU-913
EEU-5010
EEU-829
EEU-829
—
—
Tool for Creating Fuzzy Knowledge Data
EEU-1438
EEU-1444
78K/0, 78K/II, and 87AD Series Fuzzy Inference Development
Support System, Translator
78K/0 Series Fuzzy Inference Development Support System,
Fuzzy Inference Module
EEU-858
EEU-921
EEU-1441
EEU-1458
78K/0 Series Fuzzy Inference Development Support System,
Fuzzy Inference Debugger
• Other Documents
Document No.
Document name
Japanese
English
IC PACKAGE MANUAL
C10943X
C10535J
IEI-620
★
SMD Surface Mount Technology Manual
C10535E
IEI-1209
C10983E
—
Quality Grades on NEC Semiconductor Device
NEC Semiconductor Device Reliability/Quality Control System
Electrostatic Discharge (ESD) Test
C10983J
MEM-539
MEI-603
MEI-604
Guide to Quality Assurance for Semiconductor Device
Guide for Products Related to Micro-Computer: Other Companies
MEI-1202
—
Caution The above documents may be revised without notice. Use the latest versions when you design
an application system.
6 8
mPD78042F, 78043F, 78044F, 78045F
[MEMO]
6 9
mPD78042F, 78043F, 78044F, 78045F
Cautions on CMOS Devices
Countermeasures against static electricity for all MOSs
Caution When handling MOS devices, take care so that they are not electrostatically charged.
Strong static electricity may cause dielectric breakdown in gates. When transporting or storing
MOS devices, use conductive trays, magazine cases, shock absorbers, or metal cases that NEC
uses for packaging and shipping. Be sure to ground MOS devices during assembling. Do not
allow MOS devices to stand on plastic plates or do not touch pins.
Also handle boards on which MOS devices are mounted in the same way.
CMOS-specific handling of unused input pins
Caution Hold CMOS devices at a fixed input level.
Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an intermediate-
level input may be caused by noise. This allows current to flow in the CMOS device, resulting
in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input level. Since unused
pins may function as output pins at unexpected times, each unused pin should be separately
connected to the VDD or GND pin through a resistor.
If handling of unused pins is documented, follow the instructions in the document.
Statuses of all MOS devices at initialization
Caution The initial status of a MOS device is unpredictable when power is turned on.
Since characteristics of a MOS device are determined by the amount of ions implanted in
molecules, the initial status cannot be determined in the manufacture process. NEC has no
responsibility for the output statuses of pins, input and output settings, and the contents of
registers at power on. However, NEC assures operation after reset and items for mode setting
if they are defined.
When you turn on a device having a reset function, be sure to reset the device first.
FIP is a trademark of NEC Corporation.
IEBus is trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
7 0
mPD78042F, 78043F, 78044F, 78045F
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Mountain View, California
Tel: 800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 800-729-9288
Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
NEC Electronics (France) S.A.
France
Fax: 0211-65 03 490
Tel: 02-528-0303
Fax: 02-528-4411
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Fax: 01908-670-290
Fax: 250-3583
Tel: 01-504-2787
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby Sweden
Fax: 02-66 75 42 99
Fax: 02-719-5951
Tel: 8-63 80 820
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
Fax: 8-63 80 388
J96. 3
7 1
mPD78042F, 78043F, 78044F, 78045F
Note that “prelim inary” is not indicated in this docum ent, even though the related docum ents m ay be
prelim inary versions.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94. 11
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