2SJ605 [NEC]
MOS FIELD EFFECT TRANSISTOR; MOS场效应
| 型号： | 2SJ605 |
| 厂家： | 
NEC |
| 描述： | MOS FIELD EFFECT TRANSISTOR |
| 文件： | 总8页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SJ605
SWITCHING
P-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
The 2SJ605 is P-channel MOS Field Effect Transistor designed
for high current switching applications.
ORDERING INFORMATION
PART NUMBER
2SJ605
PACKAGE
TO-220AB
TO-262
2SJ605-S
FEATURES
2SJ605-ZJ
TO-263
• Super low on-state resistance:
RDS(on)1 = 20 mΩ MAX. (VGS = –10 V, ID = –33 A)
RDS(on)2 = 31 mΩ MAX. (VGS = –4.0 V, ID = –33 A)
• Low input capacitance
2SJ605-Z
TO-220SMDNote
Note TO-220SMD package is produced only
in Japan.
!
Ciss = 4600 pF TYP. (VDS = –10 V, VGS = 0 A)
• Built-in gate protection diode
(TO-220AB)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT
–60
m 20
m 65
m 200
100
V
V
A
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
W
(TO-262)
W
PT
1.5
Tch
150
°C
Storage Temperature
Tstg
–55 to +150 °C
Single Avalanche Current Note2
Single Avalanche Energy Note2
IAS
–45
203
A
EAS
mJ
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2. Starting Tch = 25°C, VDD = –30 V, RG = 25 Ω, VGS = –20 →0 V
!
(TO-263, TO-220SMD)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. D14650EJ2V0DS00 (2nd edition)
Date Published May 2001 NS CP(K)
Printed in Japan
The mark ! shows major revised points.
2000
©
2SJ605
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
VDS = –60 V, VGS = 0 V
MIN. TYP. MAX. UNIT
–10
m 10
–2.5
µA
µA
V
VGS = m 20 V, VDS = 0 V
VDS = –10 V, ID = –1 mA
VDS = –10 V, ID = –33 A
VGS = –10 V, ID = –33 A
VGS = –4.0 V, ID = –33 A
VDS = –10 V
IGSS
!
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
–1.5
30
–2.0
59
Forward Transfer Admittance
Drain to Source On-state Resistance
S
17
20
31
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
22
Input Capacitance
4600
820
330
15
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
VGS = 0 V
f = 1 MHz
!
td(on)
tr
td(off)
tf
VDD = –30 V, ID = –33 A
VGS = –10 V
14
Turn-off Delay Time
Fall Time
RG = 0 Ω
100
58
Total Gate Charge
QG
VDD= –48 V
87
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QGS
QGD
VF(S-D)
trr
VGS = –10 V
15
ID = –65 A
22
IF = 65 A, VGS = 0 V
IF = 65 A, VGS = 0 V
di/dt = 100 A/µs
1.0
53
!
!
!
ns
nC
Qrr
110
!
TEST CIRCUIT 2 SWITCHING TIME
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
D.U.T.
L
RG
= 25 Ω
V
GS (−)
R
L
90%
PG
V
GS
10%
VDD
50 Ω
Wave Form
0
RG
V
GS = –20 V → 0 V
PG.
VDD
VDS (−)
90%
90%
−
BVDSS
V
DS
I
AS
V
GS (−)
10% 10%
V
DS
0
VDS
0
Wave Form
I
D
t
d(on)
td(off)
t
f
t
r
VDD
τ
t
on
t
off
µ
τ = 1
s
Starting Tch
Duty Cycle ≤ 1%
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= −2 mA
RL
PG.
VDD
50 Ω
2
Data Sheet D14650EJ2V0DS
2SJ605
TYPICAL CHARACTERISTICS (TA = 25°C)
!
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
120
100
80
60
40
20
0
100
80
60
40
20
0
0
20
40 60
80 100 120 140 160
20 40
60
80 100 120 140 160
0
T
ch - Channel Temperature - ˚C
T
C
- Case Temperature - ˚C
FORWARD BIAS SAFE OPERATING AREA
–1000
I
D(pulse)
100
–100
–10
µ
s
I
D(DC)
Power Dissipation
Limited
–1
T
C
= 25˚C
Single Pulse
–0.1
–0.1
–1
–10
–100
V
DS - Drain to Source Voltage - V
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
Rth(ch-A) = 83.3˚C/W
Rth(ch-C) = 1.25˚C/W
1
0.1
0.01
Single Pulse
100 1000
µ
10
1 m
10 m
100 m
1
10
100
µ
PW - Pulse Width - s
3
Data Sheet D14650EJ2V0DS
2SJ605
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
–1000
–100
–10
–200
–150
–100
–50
0
V
GS = –10 V
–4.5 V
T
A
= −55˚C
25˚C
75˚C
125˚C
–1
–4.0 V
–2
V
DS = –10 V
Pulsed
–4
–5
Pulsed
–4
GS - Gate to Source Voltage - V
–0.1
0
–1
–3
–5
–1
–2
–3
V
VDS - Drain to Source Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
40
30
20
10
0
1000
100
10
Pulsed
I = –65 A
D
T
A
= 125˚C
75˚C
I = –13 A
I = –33 A
D
25˚C
D
−50˚C
1
V
DS = –10 V
Pulsed
0.1
0
–5
–10
–15
–20
–0.01
–0.1
–1
–10
–100
V
GS - Gate to Source Voltage - V
I
D - Drain Current - A
DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
GATE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
–4.0
–3.0
100
80
60
40
20
Pulsed
VDS = –10 V
I
D
= –1 mA
V
GS = –4.0 V
–4.5 V
–10 V
–2.0
–1.0
0
0
–50
0
50
100
150
–1
–10
–100
–1000
T
ch - Channel Temperature - ˚C
I
D - Drain Current - A
4
Data Sheet D14650EJ2V0DS
2SJ605
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
SOURCE TO DRAIN DIODE
FORWARD VOLTAGE
50
–1000
–100
–10
Pulsed
Pulsed
40
30
20
10
0
V
GS = –4.0 V
–4.5 V
V
GS = –10 V
–4 V
–10 V
0 V
–1
I
D
= –33A
–0.1
100
150
0
50
−50
0
–2.0
–1.5
–1.0
–0.5
T
ch - Channel Temperature - ˚C
V
SD
- Source to Drain Voltage - V
CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
SWITCHING CHARACTERISTICS
1000
100000
10000
V
DD = –30V
V
GS = 0 V
RG
= 0 Ω
f = 1 MHz
V
GS = –10 V
t
d(off)
100
10
1
Ciss
t
f
t
d(on)
1000
100
t
r
Coss
Crss
–0.1
–1
–10
–100
–0.1
–1
–10
–100
I
D
- Drain Current - A
V
DS - Drain to Source Voltage - V
SINGLE AVALANCHE CURRENT vs.
INDUCTIVE LOAD
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
–60
–50
–40
–30
–20
–10
0
–1000
–12
–10
–8
–6
–4
–2
0
I = –65 A
D
V
DD = –48 V
–30 V
V
GS
–12 V
–100
I
AS = –45A
EAS
=
203 mJ
–10
–1
VDS
V
DD = –30V
= 25 Ω
GS = –20→0 V
RG
V
0
20
40
60
80
100
10
µ
100
µ
1m
10m
Q
G
- Gate Charge - nC
L - Inductive Load - H
5
Data Sheet D14650EJ2V0DS
2SJ605
SINGLE AVALANCHE ENERGY
DERATING FACTOR
160
140
120
100
80
V
R
V
DD = –30 V
= 25 Ω
GS = –20 → 0 V
G
I
AS ≤ –45 A
60
40
20
0
25
50
75
100
125
150
Starting Tch - Starting Channel Temperature - ˚C
6
Data Sheet D14650EJ2V0DS
2SJ605
!
PACKAGE DRAWINGS(Unit: mm)
1) TO-220AB(MP-25)
2) TO-262(MP-25 Fin Cut)
4.8 MAX.
1.3±0.2
4.8 MAX.
10.6 MAX.
10 TYP.
φ
3.6±0.2
1.3±0.2
10.0 TYP.
4
1
2
3
4
1
2 3
1.3±0.2
1.3±0.2
2.8±0.2
0.5±0.2
0.75±0.3
2.54 TYP.
2.54 TYP.
0.75±0.1
2.54 TYP.
0.5±0.2
1.Gate
2.8±0.2
1.Gate
2.Drain
3.Source
2.54 TYP.
4.Fin (Drain)
2.Drain
3.Source
4.Fin (Drain)
3) TO-263 (MP-25ZJ)
4) TO-220SMD(MP-25Z)Note
4.8 MAX.
4.8 MAX.
10 TYP.
4
10 TYP.
4
1.3±0.2
1.3±0.2
1
2
3
1
2
3
1.4±0.2
1.4±0.2
0.7±0.2
0.75±0.3
2.54 TYP.
0.5±0.2
0.5±0.2
2.54 TYP.
2.54 TYP.
2.54 TYP.
1.Gate
1.Gate
2.Drain
3.Source
2.Drain
3.Source
4.Fin (Drain)
4.Fin (Drain)
Note This package is produced only in Japan.
EQUIVALENT CIRCUIT
Drain
Remark The diode connected between the gate and source of the transistor
serves as a protector against ESD. When this device actually used,
an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
Body
Diode
Gate
Gate
Protection
Diode
Source
7
Data Sheet D14650EJ2V0DS
2SJ605
•
The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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redundancy, fire-containment, and anti-failure features.
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
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M8E 00. 4
相关型号：
2SJ605(0)-Z-E1-AY
Pch Single Power Mosfet -60V -65A 20Mohm Mp-25Z/To-220Smd, MP-25Z, /Embossed Tape
RENESAS
2SJ605-S-AZ
65A, 60V, 0.031ohm, P-CHANNEL, Si, POWER, MOSFET, TO-262AA, MP-25 FIN CUT, TO-262, 3 PIN
RENESAS
2SJ605-Z-AZ
Power Field-Effect Transistor, 65A I(D), 60V, 0.031ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, MP-25Z, TO-220SMD, 3 PIN
NEC
2SJ605-ZJ-AZ
Power Field-Effect Transistor, 65A I(D), 60V, 0.031ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, MP-25ZJ, TO-263, 3 PIN
NEC
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