2SJ600-AZ [NEC]
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NEC 
PRELIMINARY DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SJ600
SWITCHING
P-CHANNEL POWER MOS FET
INDUSTRIAL USE
DESCRIPTION
ORDERING INFORMATION
The 2SJ600 is P-channel MOS Field Effect Transistor designed
for solenoid, motor and lamp driver.
PART NUMBER
2SJ600
PACKAGE
TO-251
2SJ600-Z
TO-252
FEATURES
• Low on-state resistance:
RDS(on)1 = 50 mΩ MAX. (VGS = –10 V, ID = –13 A)
RDS(on)2 = 79 mΩ MAX. (VGS = –4.0 V, ID = –13 A)
• Low Ciss: Ciss = 1900 pF TYP.
• Built-in gate protection diode
• TO-251/TO-252 package
(TO-251)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
VDSS
VGSS
ID(DC)
ID(pulse)
PT
–60
V
V
+
+
+
20
25
70
A
A
Total Power Dissipation (TC = 25°C)
Total Power Dissipation (TA = 25°C)
Channel Temperature
45
W
W
°C
(TO-252)
PT
1.0
Tch
150
Storage Temperature
Tstg
–55 to +150 °C
Single Avalanche Current Note2
IAS
–25
A
Single Avalanche Energy Note2
EAS
62.5
mJ
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
2. Starting Tch = 25°C, RG = 25 Ω, VGS = –20 V → 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published November 2000 NS CP(K)
Printed in Japan
D14645EJ1V0DS00 (1st edition)
2000
©
2SJ600
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
VDS = –60 V, VGS = 0 V
MIN. TYP. MAX.
UNIT
µA
µA
V
–10
+
+
10
VGS = 20 V, VDS = 0 V
IGSS
Gate Cut-off Voltage
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
VDS = –10 V, ID = –1 mA
VDS = –10 V, ID = –13 A
VGS = –10 V, ID = –13 A
VGS = –4.0 V, ID = –13 A
VDS = –10 V,
1.5
10
2.0
20
2.5
Forward Transfer Admittance
Drain to Source On-state Resistance
S
41
50
79
mΩ
mΩ
pF
pF
pF
ns
55
Input Capacitance
1900
350
140
9
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
VGS = 0 V,
f = 1 MHz
td(on)
tr
td(off)
tf
ID = –13 A,
VGS(on) = –10 V,
VDD = –30 V,
10
ns
Turn-off Delay Time
Fall Time
67
ns
RG = 0 Ω
19
ns
Total Gate Charge
QG
ID = –25 A,
38
nC
nC
nC
V
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QGS
QGD
VF(S-D)
trr
VDD= –48 V,
7
VGS = –10 V
10
IF = –25 A, VGS = 0 V
IF = –25 A, VGS = 0 V
di/dt = –100 A/µs
1.0
49
ns
Qrr
100
nC
TEST CIRCUIT 2 SWITCHING TIME
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
D.U.T.
L
RG
= 25 Ω
V
GS (−)
R
L
90%
PG
V
GS
VGS(on)
10%
VDD
50 Ω
Wave Form
0
RG
V
GS = –20 V → 0 V
PG.
VDD
VDS (−)
90%
90%
−
BVDSS
V
DS
I
AS
V
GS (−)
10% 10%
d(off)
V
DS
0
VDS
0
Wave Form
I
D
t
d(on)
t
t
f
t
r
V
DD
τ
t
on
t
off
µ
τ = 1 s
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
I
G
= −2 mA
RL
PG.
VDD
50 Ω
2
Preliminary Data Sheet D14645EJ1V0DS
2SJ600
PACKAGE DRAWINGS (Unit : mm)
1) TO-251 (MP-3)
2) TO-252 (MP-3Z)
2.3±0.2
0.5±0.1
6.5±0.2
6.5±0.2
2.3±0.2
5.0±0.2
4
5.0±0.2
0.5±0.1
4
1
2
3
1
2
3
1.1±0.2
0.9
0.8
1.1±0.2
MAX. MAX.
2.3 2.3
+0.2
0.5-0.1
+0.2
0.5-0.1
0.8
1. Gate
2.3 2.3
2. Drain
3. Source
4. Fin (Drain)
1.Gate
2.Drain
3.Source
4.Fin (Drain)
EQUIVALENT CIRCUIT
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
Remark The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
3
Preliminary Data Sheet D14645EJ1V0DS
2SJ600
•
The information in this document is current as of November, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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M8E 00. 4
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