NT5CC256M16CN-FLH_技术文档

Nanya Technology Corp.

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Commercial, Industrial and Automotive DDR3(L) 4Gb SDRAM

Features



Signal Integrity



JEDEC DDR3 Compliant

- Configurable DS for system compatibility

- Configurable On-Die Termination

- 8n Prefetch Architecture

- Differential Clock(CK/) and Data Strobe(DQS/)

- Double-data rate on DQs, DQS and DM

Data Integrity

- ZQ Calibration for DS/ODT impedance accuracy via

external ZQ pad (240 ohm ± 1%)



Signal Synchronization

- Write Leveling via MR settings ⁷

- Auto Self Refresh (ASR) by DRAM built-in TS

- Auto Refresh and Self Refresh Modes

Power Saving Mode

- Read Leveling via MPR

Interface and Power Supply

- Partial Array Self Refresh (PASR)¹

- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)

- SSTL_135⁴for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)

- Power Down Mode

Options

 Speed Grade (CL-TRCD-TRP) ^2,3

 Temperature Range (T_c) ⁵

- Commercial Grade = 0℃~95℃

- 2133 Mbps / 14-14-14

- 1866 Mbps / 13-13-13

- 1600 Mbps / 11-11-11

- Industrial Grade (-I) = -40℃~95℃

- Automotive Grade 2 (-H) = -40℃~105℃

- Automotive Grade 3 (-A) = -40℃~95℃

Programmable Functions



Self RefreshTemperature Range(Normal/Extended)

Output Driver Impedance (34/40)



CAS Latency (5/6/7/8/9/10/11/12/13/14)

CAS Write Latency (5/6/7/8/9/10)

On-Die Termination of Rtt_Nom(20/30/40/60/120)

On-Die Termination of Rtt_WR(60/120)

Precharge Power Down (slow/fast)

Additive Latency (0/CL-1/CL-2)

Write Recovery Time (5/6/7/8/10/12/14/16)

Burst Type (Sequential/Interleaved)

Burst Length (BL8/BC4/BC4 or 8 on the fly)

Packages / Density Information

Density and Addressing

512Mb x 8

Lead-free RoHS compliance and Halogen-free

Organization

256Mb x 16

4Gb

Length x Width

(mm)

Ball pitch

(mm)

Bank Address

Auto precharge

BL switch on the fly

Row Address

Column Address

Page Size

BA0 – BA2

A10 / AP

A12 / 

A0 – A15

A0 – A9

1KB

BA0 – BA2

A10 / AP

A12 / 

A0 – A14

A0 – A9

2KB

(Org. / Package)

78-ball

512Mbx8

9.00 x 10.50

9.00 x 13.00

0.80

TFBGA

96-ball

tREFI(us) ⁵

tRFC(ns) ⁶

Tc<=85℃:7.8, Tc>85℃:3.9

260ns

256Mbx16

TFBGA

NOTE 1 Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.

NOTE 2 The timing specification of high speed bin is backward compatible with low speed bin.

NOTE 3 Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).

NOTE 4 SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional

and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.

NOTE 5 If T_Cexceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.

NOTE 6 Violating tRFC specification will induce malfunction.

NOTE 7 Only Support prime DQ’s feedback for each byte lane.

Version 1.7

04/2015

1

Nanya Technology Cooperation ©

NTC has the rights to change any specifications or product without notification.

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Fundamental AC Specifications – Core Timing

DDR3-2133, DDR3(L)-1866, DDR3(L)-1600 and DDR3(L)-1333

DDR3-2133

DDR3(L)-1866 DDR3(L)-1600

DDR3(L)-1333

Speed Bins

Parameter

14-14-14

13-13-13 11-11-11

9-9-9 10-10-10

Unit

Min

13.09

46.09

33

Max

Min

Max

Min

Max

Min

13.5

49.5

36

Max

Min

Max

20

13.91

47.91

34

20

13.75

48.75

35

20

-

15

51

36

20

-

ns

tAA

tRCD

tRP

-

tRC

9*tREFI

9*tREFI ns

tRAS

DDR3(L)-1066 and DDR3(L)-800

DDR3(L)-1066

DDR3(L)-800

Speed Bins

Parameter

7-7-7 8-8-8

5-5-5 6-6-6

Unit

Min

Max

Min

15

Max

Min

Max

Min

15

Max

13.125

50.625

37.5

20

12.5

50

20

-

ns

tAA

tRCD

tRP

-

15

-

15

-

15

-

15

-

52.5

37.5

-

52.5

37.5

-

tRC

9*tREFI

37.5

9*tREFI

9*tREFI ns

tRAS

Version 1.7

04/2015

2

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Descriptions

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits.

It is internally configured as an octal-bank DRAM.

The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These synchronous

devices achieve high speed double-data-rate transfer rates of up to 2133 Mb/sec/pin for general applications.

The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address

inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross

point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or

differential DQS pair in a source synchronous fashion.

These devices operate with a single 1.5V ± 0.075V or 1.35V -0.067V/+0.1V power supply and are available in

BGA packages.

Version 1.7

04/2015

3

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Ordering Information

Speed³

Organization

Part Number

Package

Clock

(MHz)

Data Rate

CL-TRCD-TRP

(Mb/s)

DDR3 Commercial Grade

NT5CB512M8CN-DI

800

933

DDR3-1600

DDR3-1866

DDR3-2133

DDR3-1600

DDR3-1866

DDR3-2133

11-11-11

13-13-13

14-14-14

11-11-11

13-13-13

14-14-14

512M x 8

NT5CB512M8CN-EK

NT5CB512M8CN-FL

NT5CB256M16CP-DI

NT5CB256M16CP-EK

NT5CB256M16CP-FL

78-Ball

96-Ball

1066

800

256M x 16

933

1066

DDR3L Commercial Grade

Speed³

Organization

Part Number

Package

Clock

(MHz)

Data Rate

(Mb/s)

CL-TRCD-TRP

NT5CC512M8CN-DI

NT5CC512M8CN-DIB¹

NT5CC512M8CN-EK

NT5CC256M16CP-DI

NT5CC256M16CP-DIB¹

NT5CC256M16CP-EK

800

933

800

933

DDR3L-1600 ⁴

DDR3L RS-1600

DDR3L-1866 ⁴

DDR3L-1600 ⁴

DDR3L RS-1600

DDR3L-1866 ⁴

11-11-11

13-13-13

11-11-11

13-13-13

512M x 8

78-Ball

256M x 16

96-Ball

DDR3(L) Industrial Grade

NT5CB512M8CN-DII

800

DDR3-1600

11-11-11

512M x 8

78-Ball

NT5CC512M8CN-DII

NT5CB256M16CP-DII

NT5CC256M16CP-DII

DDR3L-1600 ⁴

DDR3-1600

256M x 16

96-Ball

DDR3L-1600 ⁴

DDR3 Automotive Grade 2 ²

NT5CB256M16CP-DIH 96-Ball 800

DDR3 Automotive Grade 3 ²

NT5CB256M16CP-DIA 96-Ball 800

256M x 16

DDR3-1600

11-11-11

NOTE 1 Reduced Standby

NOTE 2 Please confirm with NTC for the available schedule.

NOTE 3 The timing specification of high speed bin is backward compatible with low speed bin.

NOTE 4 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional and

unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.

Version 1.7

04/2015

4

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

NANYA Component Part Numbering Guide

NT

5C

B

512M8

C

N

DI

Special Type Option

NA = Commercial Grade

I = Industrial Grade

NANYA

Technology

H = Automotive Grade2

A = Automotive Grade3

B = Reduced Standby

Product Family

5C = DDR3 SDRAM

Speed

DDR3 SDRAM

DI = DDR3- 1600 11-11-11

EK = DDR3- 1866 13-13-13

Interface & Power ( VDD & VDDQ)

B = SSTL_ 15 (1.5V,1.5V)

C = SSTL_135 (1.35V,1.35V)

FL = DDR3- 2133 14-14-14

Organization (Depth , Width)

256M 16 = 512M8 = 4Gb

Note:M=Mono

Package Code

RoHS + Halogen Free

N=78 -Ball BGA

Device Version

C =3^rdVersion

P=96 -Ball BGA

Version 1.7

04/2015

5

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Ball Configuration – 78 Ball BGA Package (X8)

See the balls through the package

1

VSS

VDDQ

VSSQ

VREFDQ

NC

2

VDD

VSSQ

DQ2

DQ6

VDDQ

VSS

VDD



3

4

5

6

7

NU,T

DM,TDQS

DQ1

8

VSS

VSSQ

DQ3

VSS

DQ5

VSS

VDD

ZQ

9

A

B

C

D

E

F

NC

VDD

VDDQ

VSSQ

VDDQ

NC

A

B

C

D

E

DQ0

DQS



DQ4

RA

A

WE

BA2

A0

VDD

DQ7

CK

F

G

H

J

ODT

NC



CKE

NC

G

H

J

A10/AP

A15

VSS

VDD

VSS

VDD

VSS

1

BA0

A3

VREFCA

BA1

A4

VSS

VDD

VSS

VDD

VSS

9

K

L

M

N

A12/

A1

K

L

A5

A2

A7

A9

A11

A6

M

N

REET

2

A13

3

A14

A8

4

5

6

7

8

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.7

04/2015

6

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Ball Configuration – 96 Ball BGA Package (X16)

See the balls through the package

1

VDDQ

VSSQ

VDDQ

VSSQ

VSS

2

3

4

5

6

7

DQU4

U

DQSU

DQU0

DML

DQL1

VDD

DQL7

CK

8

VDDQ

DQU6

DQU2

VSSQ

DQL3

VSS

DQL5

VSS

VDD

ZQ

9

A

B

C

D

E

F

DQU5

VDD

DQU3

VDDQ

VSSQ

DQL2

DQL6

VDDQ

VSS

VDD



DQU7

VSS

DQU1

DMU

DQL0

DQSL

L

DQL4

RA

A

WE

VSS

VSSQ

VDDQ

VDD

VDDQ

VSSQ

VDDQ

NC

A

B

C

D

E

F

VDDQ

VSSQ

VREFDQ

NC

G

H

J

G

H

J

K

L

M

N

P

ODT



CKE

NC

K

L

M

N

P

NC

A10/AP

NC

VSS

BA0

A3

BA2

A0

VREFCA

BA1

VSS

VDD

VSS

VDD

VSS

9

VDD

VSS

A12/

A1

A5

A2

A4

R

T

VDD

VSS

A7

A9

A11

A6

R

T

REET

2

A13

3

A14

A8

1

4

5

6

7

8

Unit: mm

* BSC (Basic Spacing between Center)

Version 1.7

04/2015

7

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Ball Descriptions

Symbol

Type

Function

Clock: CK and  are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of .



Input

Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device

input buffers and output drivers. Taking CKE low provides Precharge Power-Down and

Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is

synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for

Self-Refresh exit. After VREF has become stable during the power on and initialization sequence,

it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and

exit, VREF must maintain to this input. CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input

buffers, excluding CKE, are disabled during Self-Refresh.

CKE

Input

Chip Select: All commands are masked when  is registered high.  provides for external

rank selection on systems with multiple memory ranks.  is considered part of the command

code.

Input



RA, A, WE

Command Inputs: RA, A and WE (along with ) define the command being entered.

For x8,

DM

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled HIGH coincident with that input data during a Write access. DM is sampled on both

edges of DQS. For x8 device, the function of DM or TDQS/T is enabled by Mode Register

A11 setting in MR1.

Input

For x16,

DMU, DML

Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or

Precharge command is being applied. Bank address also determines which mode register is to be

accessed during a MRS cycle.

BA0 - BA2

Auto-Precharge: A10 is sampled during Read/Write commands to determine whether

Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:

Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to

determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only

one bank is to be precharged, the bank is selected by bank addresses.

A10 / AP

Input

For x8,

A0 – A15

For x16,

A0 – A14

Address Inputs: Provide the row address for Activate commands and the column address for

Read/Write commands to select one location out of the memory array in the respective bank.

(A10/AP and A12/ have additional function as below.) The address inputs also provide the

op-code during Mode Register Set commands.

Burst Chop: A12/is sampled during Read and Write commands to determine if burst chop

A12/

Input

(on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).

On Die Termination: ODT (registered HIGH) enables termination resistance internal to the

DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, and DM/TDQS, NU/T

(when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT

pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.

ODT

Version 1.7

04/2015

8

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Symbol

Type

Function

Active Low Asynchronous Reset: Reset is active when REET is LOW, and inactive when

REET is HIGH. REET must be HIGH during normal operation. REET is a CMOS rail to rail

signal with DC high and low at 80% and 20% of VDD, i.e. 1.20V for DC high and 0.30V.

Data Inputs/Output: Bi-directional data bus. DQ0 is the prime DQ in a low byte lane of

x4/x8/x16 configuration and DQ8 is the prime DQ in a high byte lane of x16 configuration for write

leveling.

Input

REET

DQ

Input/output

Data Strobe: output with read data, input with write data. Edge aligned with read data, centered

with write data. The data strobes DQS, DQSL, DQSU are paired with differential signals ,

L, U, respectively, to provide differential pair signaling to the system during both reads

and writes. DDR3 SDRAM supports differential data strobe only and does not support

single-ended.

For x8,

DQS, ()

For x16,

DQSL,(L),

DQSU,(U)

Termination Data Strobe: TDQS/T is applicable for X8 DRAMs only. When enabled via

Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on

TDQS/T that is applied to DQS/. When disabled via mode register A11=0 in MR1,

DM/T will provide the data mask function and T is not used. x16 DRAMs must disable the

TDQS function via mode register A11=0 in MR1.

For x8,

Output

TDQS, (T)

NC

-

No Connect: No internal electrical connection is present.

V_DDQ

V_DD

Supply

DQ Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V

Power Supply: 1.35V -0.067V/+0.1V or 1.5V ± 0.075V

DQ Ground

V_SSQ

V_SS

Ground

V_REFCA

V_REFDQ

ZQ

Reference voltage for CA

Reference voltage for DQ

Reference pin for ZQ calibration.

Notes:

1. Input only pins (BA0-BA2, A0-A15, RA, A, WE, , CKE, ODT, and REET) do not supply termination.

2. The signal may show up in a different symbol but it indicates the same thing. e.g., /CK = CK# =  = CKb, /DQS = DQS# =

 = DQSb, /CS = CS# =  = CSb.

Version 1.7

04/2015

9

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Simplified State Diagram

Power

Applied

MRS, MPR,

Write

Levelizing

Power

ON

Reset

Procedure

Initialization

Self Refresh

SRE

ZQCL

MRS

From any

State

SRX

RESET

ZQCL

ZQCS

ZQ Calibration

Idle

Refreshing

REF

PDX

ACT

PDE

Precharge

Power

Activating

Down

Active

Power

Down

PDE

PDX

Bank

Active

Write

Read

Write

Read

Write

Writing

Write A

Writing

Reading

Read A

Reading

Write A

Read A

Automatic

Sequence

Read A

Command

Sequence

PRE,

PREA

PRE,

PREA

PRE,

PREA

Precharging

State Diagram Command Definitions

Abbr.

Function

Abbr.

Function

Abbr.

Function

ACT

Active

Read

RD, RDS4, RDS8

PDE

PDX

SRE

SRX

MPR

-

Enter Power-down

Exit Power-down

Self-Refresh entry

Self-Refresh exit

Multi-Purpose Register

-

PRE

Precharge

Read A

Write

RDA, RDAS4, RDAS8

WR, WRS4, WRS8

PREA

MRS

REF

Precharge All

Mode Register Set

Refresh

Write A

RESET

ZQCS

WRA, WRAS4, WRAS8

Start RESET Procedure

ZQ Calibration Short

ZQCL

ZQ Calibration Long

Version 1.7

04/2015

10

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Basic Functionality

The DDR3(L) SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank DRAM.

The DDR3(L) SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n prefetch architecture is

combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write

operation for the DDR3(L) SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and

two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write operation to the DDR3(L) SDRAM are burst oriented, start at a selected location, and continue for a burst

length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Active

command, which is then followed by a Read or Write command. The address bits registered coincident with the Active

command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A15 select the row). The

address bit registered coincident with the Read or Write command are used to select the starting column location for the

burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode ‘on the

fly’ (via A12) if enabled in the mode register.

Prior to normal operation, the DDR3(L) SDRAM must be powered up and initialized in a predefined manner. The following

sections provide detailed information covering device reset and initialization, register definition, command descriptions

and device operation.

RESET and Initialization Procedure

Power-up Initialization sequence

The Following sequence is required for POWER UP and Initialization

1. Apply power (REET is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined). REET

needs to be maintained for minimum 200μs with stable power. CKE is pulled “Low” anytime before REETbeing

de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDD_minmust be no greater than 200ms;

and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.

- VDD and VDDQ are driven from a single power converter output, AND

- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one

side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once

power ramp is finished, AND

- V_reftracks VDDQ/2.

OR

- Apply VDD without any slope reversal before or at the same time as VDDQ.

- Apply VDDQ without any slope reversal before or at the same time as VTT & V_ref.

- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one

side and must be larger than or equal to VSSQ and VSS on the other side.

2. After REETis de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will start

internal state initialization; this will be done independently of external clocks.

3. Clock (CK, ) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active.

Since CKE is a synchronous signal, the corresponding set up time to clock (t_IS) must be meeting. Also a NOP or

Version 1.7

04/2015

11

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Deselect command must be registered (with t_ISset up time to clock) before CKE goes active. Once the CKE registered

“High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence is finished,

including expiration of t_DLLKand t_ZQinit

.

4. The DDR3(L) DRAM will keep its on-die termination in high impedance state as long as REETis asserted. Further,

the DRAM keeps its on-die termination in high impedance state after REET de-assertion until CKE is registered HIGH.

The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When CKE is registered

HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be enabled in MR1, the

ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power up

initialization sequence is finished, including the expiration of tDLLK and tZQinit.

5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS command

to load mode register. [TXPR=max (tXS, 5tCK)]

6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low” to

BA0 and BA2, “High” to BA1)

7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low” to

BA2, “High” to BA0 and BA1)

8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable” command,

provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)

9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command,

provide “High” to A8 and “Low” to BA0-BA2)

10. Issue ZQCL command to starting ZQ calibration.

11. Wait for both t_DLLKand t_ZQinitcompleted.

12. The DDR3 (L) SDRAM is now ready for normal operation.

Version 1.7

04/2015

12

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Reset and Initialization Sequence at Power- on Ramping (Cont’d)

Ta

Tb

Tc

Td

Te

Tf

Tg

Th

Ti

Tj

Tk

tCKSRX

CK

RESET

CKE

10ns

tIS

Valid

Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

ODT

NOP*

MRS

MR2

MRS

MR3

MRS

MR1

MRS

MR0

ZQCL

NOP*

Command

BA0-BA2

VDD,

VDDQ

tDLLK

tMRD

T=200us

tXPR

tMRD

tMOD

T=500us

tZQinit.

Do Not

Care

Time break

* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.

Reset Procedure at Stable Power (Cont’d)

The following sequence is required for RESET at no power interruption initialization.

1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be

maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns).

2. Follow Power-up Initialization Sequence step 2 to 11.

3. The Reset sequence is now completed. DDR3 (L) SDRAM is ready for normal operation.

Reset Procedure at Power Stable Condition

Ta

Tb

Tc

Td

Te

Tf

Tg

Th

Ti

Tj

Tk

tCKSRX

CK

RESET

CKE

10ns

tIS

Valid

Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW

ODT

NOP*

MRS

MR2

MRS

MR3

MRS

MR1

MRS

MR0

ZQCL

NOP*

Command

BA0-BA2

VDD,

VDDQ

tDLLK

tMRD

T=100ns

tXPR

tMRD

tMOD

T=500us

tZQinit.

Do Not

Care

Time break

* From time point Td until Tk. NOP or DES commands must be applied between MRS and ZQcal commnads.

Version 1.7

04/2015

13

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

VDDQ/VDDQ Voltage Switch Between DDR3L and DDR3

Version 1.7

04/2015

14

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Register Definition

Programming the Mode Registers

For application flexibility, various functions, features, and modes are programmable in four Mode Registers, provided by the

DDR3 (L) SDRAM, as user defined variables and they must be programmed via a Mode Register Set (MRS) command. As

the default values of the Mode Registers (R) are not defined, contents of Mode Registers must be fully initialized and/or

re-initialized, i.e. written, after power up and/or reset for proper operation. Also the contents of the Mode Registers can be

altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the

user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be

redefined when the MRS command is issued. MRS command and DLL Reset do not affect array contents, which mean

these commands can be executed any time after power-up without affecting the array contents.

The mode register set command cycle time, t_MRDis required to complete the write operation to the mode register and is the

minimum time required between two MRS commands shown as below.

t_MRDTiming

CK

CMD

ADDR

CKE

MRS

VAL

NOP

MRS

VAL

tMRD

Do not

Care

Time break

The MRS command to Non-MRS command delay, t_MOD, is require for the DRAM to update the features except DLL reset,

and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DES shown as the

following figure.

Version 1.7

04/2015

15

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

t_MODTiming

CK

Non

MRS

CMD

ADDR

CKE

MRS

VAL

NOP

tMOD

VAL

Old Setting

New Setting

Updating Setting

Programming the Mode Registers (Cont’d)

The mode register contents can be changed using the same command and timing requirements during normal operation as

long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed

and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the

functionality and/or modes.

Mode Register MR0

The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include

various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by

asserting low on , RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the

following figure.

Version 1.7

04/2015

16

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

MR0 Definition

BA2 BA1 BA0

A15-A13

A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

↓

MR select

WR

CAS Latency

BL

0

PPD

DLL TM

RBT CL

PPD

Slow exit(DLL off)

Fast exit(DLL on)

DLL Reset

No

Read Burst Type

Nibble Sequential

Interleave

A12

0

1

A8

0

1

A3

0

1

Yes

mode

Normal

Test

BA1 BA0 MR select

A7

0

1

0

1

0

1

0

1

MR0

MR1

MR2

MR3

BL

8(Fixed)

A1

0

A0

0

BC4 or 8 (on the fly)

BC4(Fixed)

0

1

0

WR

16

5

6

7

Reserved

A11 A10 A9

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

8

10

12

14

CAS Latency

Reserved

A6

0

1

0

1

A5

0

1

0

1

0

1

0

1

A4

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

A2

0

1

5

6

7

8

9

10

11

12

13

14

Reserved

*1: BA2 and A13~A15 are RFU and must be programmed to 0 during MRS.

*2: WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next

integer: WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than

WRmin. The programmed WR value is used with tRP to determine tDAL.

*3: The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each frequency

*4: The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timingtable.

Version 1.7

04/2015

17

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Burst Length, Type, and Order

Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3

as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,

burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,

fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write

command via A12/.

Burst Type and Burst Order

Starting

Column

Address

(A2,A1,A0)

Burst type:

Sequential

(decimal)

A3 = 0

Burst type:

Interleaved

(decimal)

A3 = 1

Burst

Length

Read

Write

Note

0,0,0

0,0,1

0,1,0

0,1,1

1,0,0

1,0,1

1,1,0

1,1,1

0,V,V

1,V,V

0,0,0

0,0,1

0,1,0

0,1,1

1,0,0

1,0,1

1,1,0

1,1,1

V,V,V

0,1,2,3,T,T,T,T

1,2,3,0,T,T,T,T

2,3,0,1,T,T,T,T

3,0,1,2,T,T,T,T

4,5,6,7,T,T,T,T

5,6,7,4,T,T,T,T

6,7,4,5,T,T,T,T

7,4,5,6,T,T,T,T

0,1,2,3,X,X,X,X

4,5,6,7,X,X,X,X

0,1,2,3,4,5,6,7

1,2,3,0,5,6,7,4

2,3,0,1,6,7,4,5

3,0,1,2,7,4,5,6

4,5,6,7,0,1,2,3

5,6,7,4,1,2,3,0

6,7,4,5,2,3,0,1

7,4,5,6,3,0,1,2

0,1,2,3,4,5,6,7

0,1,2,3,T,T,T,T

1,0,3,2,T,T,T,T

2,3,0,1,T,T,T,T

3,2,1,0,T,T,T,T

4,5,6,7,T,T,T,T

5,4,7,6,T,T,T,T

6,7,4,5,T,T,T,T

7,6,5,4,T,T,T,T

0,1,2,3,X,X,X,X

4,5,6,7,X,X,X,X

0,1,2,3,4,5,6,7

1,0,3,2,5,4,7,6

2,3,0,1,6,7,4,5

3,2,1,0,7,6,5,4

4,5,6,7,0,1,2,3

5,4,7,6,1,0,3,2

6,7,4,5,2,3,0,1

7,6,5,4,3,2,1,0

0,1,2,3,4,5,6,7

Read

Write

1,2,3

4

Chop

1,2,4,5

Read

Write

2

8

2,4

Note:

1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8

mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected

on-the-fly via A12/, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that

during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.

2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.

3. T: Output driver for data and strobes are in high impedance.

4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.

5. X: Do not Care.

Version 1.7

04/2015

18

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

CAS Latency

The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the delay, in

clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3(L) SDRAM does

not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency

(CL); RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0

definition figure. Programming bit A7 to a ‘1’ places the DDR3(L) SDRAM into a test mode that is only used by the DRAM

manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.

DLL Reset

The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued.

Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK

must be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous

operations.)

Write Recovery

The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to

determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns)

and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be

equal or larger than tWR (min).

Precharge PD DLL

MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’,

the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be

met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge

power-down and upon exiting power-down requires tXP to be met prior to the next valid command.

Version 1.7

04/2015

19

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Mode Register MR1

The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance, additive

latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on , RA, A, WE high on

BA0 and low on BA1 and BA2, while controlling the states of address pins according to the following figure.

MR1 Definition

BA2 BA1 BA0

A15-A13

A12 A11 A10 A9

A8

↓

0

A7

↓

A6

A5

↓

A4

A3

A2

A1

A0

↓

Rtt_Nom

↓

Rtt_Nom

↓

Rtt_Nom

↓

MR select

AL

0

Qoff TDQS

0

Level

D.I.C

D.I.C DLL

Rtt_Nom

Disabled

RZQ/4

AL

Disabled

CL-1

A11

0

1

TDQS

Disabled

Enabled

A9

0

A6

0

A2

0

1

A4

0

A3

0

1

RZQ/2

CL-2

0

1

0

1

0

RZQ/6

Reserved

BA1 BA0 MR select

0

1

RZQ/12

RZQ/8

Reserved

0

1

0

1

0

1

MR0

MR1

MR2

MR3

1

0

1

0

1

0

1

DLL Enable

Enable

Disable

A0

0

1

Write Leveling enable

Disabled

Output Driver Impedance

RZQ/6

A7

0

A5

0

A1

0

Enabled

RZQ/7

1

0

1

Reserved

1

0

Reserved

1

Qoff

A12

Output buffer enabled

Output buffer disabled

0

1

* 1 : BA2 and A8, A10, and A13 ~ A15 are RFU and must be programmed to 0 during MRS.

*2: Outputs disabled - DQs, DQSs, s.

*3: RZQ = 240

*4: In Write leveling Mode (MR1[bit7] = 1) with MR1[bit12]=1, all RTT_Nom settings are allowed; in Write Leveling Mode (MR1[bit7] = 1) with

MR1[bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.

*5: If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.

Version 1.7

04/2015

20

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to

normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the DLL is

automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-Refresh

operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a Read or

synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock.

Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF parameters. During

tDLLK, CKE must continuously be registered high. DDR3(L) SDRAM does not require DLL for any Write operation, expect

when RTT_WR is enabled and the DLL is required for proper ODT operation. For more detailed information on DLL Disable

operation in DLL-off Mode.

The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continu-

ously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register

set command during DLL-off mode.

The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2 {A10, A9}

= {0, 0}, to disable Dynamic ODT externally.

Output Driver Impedance Control

The output driver impedance of the DDR3(L) SDRAM device is selected by MR1 (bit A1 and A5) as shown in MR1 definition

figure.

ODT Rtt Values

DDR3(L) SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal termination

value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to enable a unique Rtt

value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.

Version 1.7

04/2015

21

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Additive Latency (AL)

Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3(L)

SDRAM. In this operation, the DDR3(L) SDRAM allows a read or write command (either with or without auto-precharge) to

be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is

issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings.

Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL

register options are shown as the following table.

Additive Latency (AL) Settings

A4

A3

AL

0, (AL Disable)

CL-1

0

1

0

CL-2

1

Reserved

Version 1.7

04/2015

22

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Write leveling

For better signal integrity, DDR3(L) memory module adopted fly by topology for the commands, addresses, control signals,

and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes

flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the Controller to maintain tDQSS,

tDSS, and tDSH specification. Therefore, the controller should support ‘write leveling’ in DDR3(L) SDRAM to compensate

for skew.

Output Disable

The DDR3(L) SDRAM outputs maybe enable/disabled by MR1 (bit12) as shown in MR1 definition. When this feature is

enabled (A12=1) all output pins (DQs, DQS, , etc.) are disconnected from the device removing any loading of the

output drivers. This feature may be useful when measuring modules power for example. For normal operation A12 should

be set to ‘0’.

TDQS, T

TDQS (Termination Data Strobe) is a feature of x8 DDR3(L) SDRAM that provides additional termination resistance outputs

that may be useful in some system configurations.

When enabled via the mode register, the same termination resistance function is applied to be TDQS/T pins that are

applied to the DQS/ pins.

In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data

strobe function of RDQS is not provided by TDQS.

The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM

function is not supported. When the TDQS function is disabled, the DM function is provided and the T pin is not used.

The TDQS function is available in x8 DDR3(L) SDRAM only and must be disabled via the mode register A11=0 in MR1 for

x16 configurations.

TDQS, T Function Matrix

MR1 (A11)

DM / TDQS

DM

NU / TDQS

Hi-Z

0 (TDQS Disabled)

1 (TDQS Enabled)

TDQS

T

Note:

1. If TDQS is enabled, the DM function is disabled.

2. When not used, TDQS function can be disabled to save termination power.

3. TDQS function is only available for x8 DRAM and must be disabled for x16.

Version 1.7

04/2015

23

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Mode Register MR2

The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency.

The Mode Register 2 is written by asserting low on , RA, A, WE high on BA1 and low on BA0 and BA2, while

controlling the states of address pins according to the table below.

MR2 Definition

BA2 BA1 BA0

A15-A13

A12 A11 A10 A9

A8

↓

0

A7

A6

A5

A4

A3

A2

A1

A0

↓

CWL

↓

PASR

↓

MR select

0

Rtt_WR

0

SRT ASR

ASR

PASR

Full Array

A6

0

1

A2

0

A1

0

1

A0

0

1

0

1

Manual SR Reference (SRT)

ASR enable

HalfArray (BA[2:0]=000,001,010, &011)

Quarter Array (BA[2:0]=000, & 001)

1/8th Array (BA[2:0] = 000)

3/4 Array (BA[2:0] = 010,011,100,101,110, & 111)

HalfArray (BA[2:0] = 100, 101, 110, &111)

Quarter Array (BA[2:0]=110, &111)

1/8th Array (BA[2:0]=111)

1

0

1

0

1

0

1

Rtt_WR

Dynamic ODT off

RZQ/4

A10 A9

0

1

0

1

0

1

RZQ/2

Reserved

CWL

A5

0

A4

0

A3

0

5 (tCK(avg)>=2.5ns)

SRT

6 (2.5ns>=tCK(avg)>=1.875ns)

7 (1.875ns>=tCK(avg)>=1.5ns)

8 (1.5ns>=tCK(avg)>=1.25ns)

9 (1.25ns>=tCK(avg)>=1.07ns)

10 (1.07ns>=tCK(avg)>=0.935ns)

RFU

A7

0

1

0

1

0

1

0

1

0

1

0

Normal operating

temperature range

Extended operating

temperature range

1

MR select

MR0

RFU

BA1 BA0

1

0

1

0

1

0

1

MR1

MR2

MR3

* 1 : Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.

* 2 : BA2, A5, A8, A11 ~ A15 are RFU and must be programmed to 0 during MRS.

* 3 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available.

Version 1.7

04/2015

24

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

CAS Write Latency (CWL)

The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock cycles,

between the internal Write command and the availability of the first bit of input data. DDR3(L) DRAM does not support any

half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write Latency (CWL);

WL=AL+CWL.

Auto Self-Refresh (ASR) and Self-Refresh Temperature (SRT)

DDR3(L) SDRAM must support Self-Refresh operation at all supported temperatures. Applications requiring Self-Refresh

operation in the Extended Temperature Range must use the ASR function or program the SRT bit appropriately.

Optional in DDR3(L) SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if

DDR3(L) SDRAM devices support the following options or requirements referred to in this material. For more details refer to

“Extended Temperature Usage”. DDR3(L) SDRAMs must support Self-Refresh operation at all supported temperatures.

Applications requiring Self-Refresh operation in the Extended Temperature Range must use the optional ASR function or

program the SRT bit appropriately.

Dynamic ODT (Rtt_WR)

DDR3(L) SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal

integrity on the data bus, it is desirable that the termination strength of the DDR3(L) SDRAM can be changed without

issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write leveling

mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.

Version 1.7

04/2015

25

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Mode Register MR3

The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on , RA, A,

WE high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below.

MR3 Definition

BA2 BA1 BA0

A15-A13

A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

↓

A1

A0

↓

MR select

0

MPR Loc

0

MPR

MPR Loc

Predefined pattern

Reserved

A2

0

1

A1

0

A0

0

1

Normal operation

Dataflow from MPR

Reserved

1

0

Reserved

BA1 BA0 MR select

1

0

1

0

1

0

1

MR0

MR1

MR2

MR3

* 1 : BA2, A3 - A15 are RFU and must be programmed to 0 during MRS.

* 2 : The predefined pattern will be used for read synchronization.

* 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.

Version 1.7

04/2015

26

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Multi-Purpose Register (MPR)

The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence. To

enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2=1. Prior to issuing the

MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any

subsequent RD or RDA commands will be redirected to the Multi Purpose Register. When the MPR is enabled, only RD or

RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power

down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable mode. The RESET

function is supported during MPR enable mode.

The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence.

Fig. 1: MPR Block Diagram

To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1, prior to issuing

the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is enabled, any

subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting operation, when a RD or

RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown. When the MPR is enabled,

only RD or RDA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2 =

0). Note that in MPR mode RDA has the same functionality as a READ command which means the auto precharge part of

RDA is ignored. Power-Down mode, Self-Refresh and any other non-RD/RDA command is not allowed during MPR enable

mode. The RESET function is supported during MPR enable mode.

Version 1.7

04/2015

27

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

MPR MR3 Register Definition

MR3 A[2]

MR3 A[1:0]

Function

MPR

MPR-Loc

Normal operation, no MPR transaction.

0b

1b

don't care (0b or 1b)

See MR3 Table

All subsequent Reads will come from DRAM array.

All subsequent Write will go to DRAM array.

Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].

MPR Functional Description

• One bit wide logical interface via all DQ pins during READ operation.

• Register Read on x8:

• DQ[0] drives information from MPR.

• DQ[7:1] either drive the same information as DQ [0], or they drive 0b.

• Register Read on x16:

• DQL[0] and DQU[0] drive information from MPR.

• DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b.

• Addressing during for Multi Purpose Register reads for all MPR agents:

• BA [2:0]: don’t care

• A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed

• A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the burst

order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *)

A[2]=1b, Burst order: 4,5,6,7 *)

• A[9:3]: don’t care

• A10/AP: don’t care

• A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.

• A11, A13... (if available): don’t care

• Regular interface functionality during register reads:

• Support two Burst Ordering which are switched with A2 and A[1:0]=00b.

• Support of read burst chop (MRS and on-the-fly via A12/BC)

• All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3(L)

SDRAM.

• Regular read latencies and AC timings apply.

• DLL must be locked prior to MPR Reads.

NOTE: *Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.

Version 1.7

04/2015

28

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

MPR MR3 Register Definition

Read Address

A[2:0]

Burst Order

MR3 A[2]

MR3 A[1:0]

Function

Burst Length

and Data Pattern

Burst order 0,1,2,3,4,5,6,7

Pre-defined Data Pattern [0,1,0,1,0,1,0,1]

Burst order 0,1,2,3

BL8

BC4

000b

100b

Read Predefined

Pattern for System

Calibration

1b

00b

Pre-defined Data Pattern [0,1,0,1]

Burst order 4,5,6,7

Pre-defined Data Pattern [0,1,0,1]

BL8

BC4

BL8

000b

100b

000b

Burst order 0,1,2,3,4,5,6,7

Burst order 0,1,2,3

1b

01b

10b

11b

RFU

Burst order 4,5,6,7

Burst order 0,1,2,3,4,5,6,7

BC4

000b

Burst order 0,1,2,3

BC4

BL8

BC4

100b

000b

100b

Burst order 4,5,6,7

Burst order 0,1,2,3,4,5,6,7

Burst order 0,1,2,3

Burst order 4,5,6,7

NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.

Version 1.7

04/2015

29

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3(L) SDRAM Command Description and Operation

Command Truth Table

CKE

A0-

BA0- A13- A12- A10-

Function

Abbr.

 RA A WE

A9, NOTES

A11

Previous Current

BA2

A15  AP

Cycle

Mode Register Set

Refresh

MRS

REF

SRE

H

L

H

L

H

L

H

L

H

L

H

X

BA

V

OP Code

V

X

V

X

V

X

V

L

H

V

H

L

V

X

V

Self Refresh Entry

L

7,9,12

X

H

L

X

Self Refresh Exit

SRX

L

H

7,8,9,12

V

H

L

H

L

Single Bank Precharge

PRE

PREA

ACT

H

BA

V

Precharge all Banks

L

Bank Activate

L

H

L

BA

V

Row Address (RA)

RFU

V

L

H

V

L

H

V

L

H

V

L

H

V

X

V

X

V

X

Write (Fixed BL8 or BC4)

WR

H

X

L

CA

V

Write (BC4, on the Fly)

WRS4

WRS8

WRA

WRAS4

WRAS8

RD

L

Write (BL8, on the Fly)

L

Write with Auto Precharge (Fixed BL8 or BC4)

Write with Auto Precharge (BC4, on the Fly)

Write with Auto Precharge (BL8, on the Fly)

Read (Fixed BL8 or BC4)

L

H

L

H

X

Read (BC4, on the Fly

RDS4

RDS8

RDA

L

Read (BL8, on the Fly)

L

Read with Auto Precharge (Fixed BL8 or BC4)

Read with Auto Precharge (BC4, on the Fly)

Read with Auto Precharge (BL8, on the Fly)

No Operation

L

H

V

X

V

X

V

X

H

L

RDAS4

RDAS8

NOP

L

H

X

H

X

H

X

H

10

11

X

Device Deselected

DES

V

H

X

H

X

Power Down Entry

Power Down Exit

PDE

PDX

H

L

6,12

X

V

H

X

H

X

H

X

ZQ Calibration Long

ZQ Calibration Short

ZQCL

ZQCS

H

L

X

L

Version 1.7

04/2015

30

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3(L) SDRAM Command Description and Operation

Command Truth Table (Conti.)

NOTE1. All DDR3(L) SDRAM commands are defined by states of , RA, A, WEand CKE at the rising edge of the clock. The MSB of

BA, RA and CA are device density and configuration dependant.

NOTE2. REET is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any function.

NOTE3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.

NOTE4. “V” means “H or L (but a defined logic level)” and “X” means either “defined or undefined (like floating) logic level”.

NOTE5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-Fly BL will be defined by MRS.

NOTE6. The Power-Down Mode does not perform any refresh operation.

NOTE7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.

NOTE8. Self Refresh Exit is asynchronous.

NOTE9. VREF (Both VrefDQ and VrefCA) must be maintained during Self Refresh operation.

NOTE10. The No Operation command should be used in cases when the DDR3(L) SDRAM is in an idle or wait state. The purpose of the

No Operation command (NOP) is to prevent the DDR3(L) SDRAM from registering any unwanted commands between operations.

A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or write cycle.

NOTE11. The Deselect command performs the same function as No Operation command.

NOTE12. Refer to the CKE Truth Table for more detail with CKE transition.

Version 1.7

04/2015

31

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

CKE Truth Table

CKE

Command (N)

Current State

Action (N)

Notes

Previous Cycle Current Cycle

RA, A,WE, 

(N-1)

(N)

X

L

Maintain Power-Down

Power-Down Exit

14,15

11,14

Power-Down

Self-Refresh

L

H

L

DESELECT or NOP

X

L

Maintain Self-Refresh

Self-Refresh Exit

15,16

L

H

L

DESELECT or NOP

REFRESH

8,12,16

Bank(s) Active

Reading

H

Active Power-Down Entry

Power-Down Entry

11,13,14

11,13,14,17

11

H

L

Writing

H

L

Power-Down Entry

Precharging

Refreshing

H

L

Power-Down Entry

H

L

Precharge Power-Down Entry

Self-Refresh

H

L

11,13,14,18

9,13,18

All Banks Idle

H

L

NOTE 1 CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.

NOTE 2 Current state is defined as the state of the DDR3(L) SDRAM immediately prior to clock edge N.

NOTE 3 COMMAND (N) is the command registered at clock edge N, and ACTION (N) is a result of COMMAND (N), ODT is not

included here.

NOTE 4 All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.

NOTE 5 The state of ODT does not affect the states described in this table. The ODT function is not available during Self-Refresh.

NOTE 6 CKE must be registered with the same value on tCKEmin consecutive positive clock edges. CKE must remain at the valid

input level the entire time it takes to achieve the tCKEmin clocks of registrations. Thus, after any CKE transition, CKE may

not transition from its valid level during the time period of tIS + tCKEmin + tIH.

NOTE 7 DESELECT and NOP are defined in the Command Truth Table.

NOTE 8 On Self-Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXS period.

Read or ODT commands may be issued only after tXSDLL is satisfied.

NOTE 9 Self-Refresh modes can only be entered from the All Banks Idle state.

NOTE 10 Must be a legal command as defined in the Command Truth Table.

NOTE 11 Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.

NOTE 12 Valid commands for Self-Refresh Exit are NOP and DESELECT only.

NOTE 13 Self-Refresh cannot be entered during Read or Write operations.

NOTE 14 The Power-Down does not perform any refresh operations.

NOTE 15 “X” means “don’t care“(including floating around VREF) in Self-Refresh and Power-Down. It also applies to Address pins.

NOTE 16 VREF (Both Vref_DQ and Vref_CA) must be maintained during Self-Refresh operation.

NOTE 17 If all banks are closed at the conclusion of the read, write or precharge command, then Precharge Power-Down is entered,

otherwise Active Power-Down is entered.

NOTE 18 ‘Idle state’ is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all

timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all

Self-Refresh exit and Power-Down Exit parameters are satisfied (tXS, tXP, tXPDLL, etc).

Version 1.7

04/2015

32

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

No Operation (NOP) Command

The No operation (NOP) command is used to instruct the selected DDR3(L) SDRAM to perform a NOP (low and RA,

A, and WE high). This prevents unwanted commands from being registered during idle or wait states. Operations

already in progress are not affected.

Deselect Command

The Deselect function (HIGH) prevents new commands from being executed by the DDR3(L) SDRAM. The DDR3(L)

SDRAM is effectively deselected. Operations already in progress are not affected.

DLL- Off Mode

DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0

bit set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.

The DLL-off Mode operations listed below are an optional feature for DDR3(L). The maximum clock frequency for DLL-off

Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the

refresh interval, tREFI.

Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL)

in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6.

DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data

relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain.

Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command,

the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be

small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is

significantly larger than in DLL-on mode.

The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)

Version 1.7

04/2015

33

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DLL-off mode READ Timing Operation

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK

CMD

Address

READ

Bank, Col b

RL = AL+CL = 6 (CL=6, AL=0)

DQSdiff_DLL_on

DQ_DLL_on

Din

b

Din

b+1

Din

b+2

Din

b+3

Din

b+4

Din

b+5

Din

b+6

Din

b+7

RL(DLL_off) = AL+(CL-1) = 5

tDQSCKDLL_diff_min

DQSdiff_DLL_off

Din

b+4

Din

b

Din

b+1

Din

b+2

Din

b+3

Din

b+5

Din

b+6

Din

b+7

DQ_DLL_off

DQSdiff_DLL_off

tDQSCKDLL_diff_max

Din

b+4

Din

b

Din

b+1

Din

b+2

Din

b+3

Din

b+5

Din

b+6

Din

b+7

DQ_DLL_off

Note: The tDQSCK is used here for DQS, DQS, and DQ to have a simplified diagram; the DLL_off shift will affect both timings in the same

way and the skew between all DQ, DQS, and signals will still be tDQSQ.

Version 1.7

04/2015

34

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DLL on/off switching procedure

DDR3(L) DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit

set back to “0”.

DLL “on” to DLL “off” Procedure

To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following

procedure:

1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT, must

be in high impedance state before MRS to MR1 to disable the DLL).

2. Set MR1 Bit A0 to “1” to disable the DLL.

3. Wait tMOD.

4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.

5. Change frequency, in guidance with “Input Clock Frequency Change” section.

6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from any

MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self Refresh

mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any MRS

command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was entered,

ODT signal can be registered LOW or HIGH.

8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be

necessary. A ZQCL command may also be issued after tXS).

9. Wait for tMOD, and then DRAM is ready for next command.

Version 1.7

04/2015

35

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DLL Switch Sequence from DLL-on to DLL-off

T

a

T

a

T

b

T

c

T

d

T

d

T

e

T

e

T

f

T0

T1

0

1

0

1

0

1

0

CK

tMOD

NOP

tCKSRE

NOP

4)

tCKSRX 5)

SRX 6)

tXS

tMOD

NOP

Vali

d

CMD

CKE

MRS 2)

SRE 3)

MRS 7)

8)

1)

NOP

tCKESR

Vali

d

Vali

d

ODT

8)

Do

Tim

not

Car

e

break

Note:

ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High

1) Starting with Idle State, RTT in Hi-Z State.

2) Disable DLL by setting MR1 Bit A0 to 1.

3) Enter SR.

4) Change Frequency.

5) Clock must be stable at least tCKSRX.

6) Exit SR.

7) Update Mode registers with DLL off parameters setting.

8) Any valid command.

Version 1.7

04/2015

36

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DLL “off” to DLL “on” Procedure

To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:

1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must

be in high impedance state before Self-Refresh mode is entered).

2. Enter Self Refresh Mode, wait until tCKSRE satisfied.

3. Change frequency, in guidance with “Input clock frequency change” section.

4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs.

5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subse-

quent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self

Refresh mode was entered. The ODT signal must continuously be registered LOW until tDLLK timings from subsequent

DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was

entered, ODT signal can be registered LOW or HIGH.

6. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.

7. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.

8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be

necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or

after tDLLK).

9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying

command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.

Version 1.7

04/2015

37

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DLL Switch Sequence from DLL-off to DLL-on

T0

Ta0

Ta1

Tb0

Tc0

Tc1

Td0

Te0

Tf1

Th0

Tg0

CK

CMD

CKE

1)

NOP

SRE 2)

NOP

SRX 5)

MRS 6)

MRS 7)

MRS 8)

tDLLK

Valid

ODTLoff

+ 1tck

tCKSRE

3)

tCKSRX 4)

tXS

tMRD

tCKESR

ODT

Do not

Care

Time

break

Note:

ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High

1) Starting from Idle State.

2) Enter SR.

3) Change Frequency.

4) Clock must be stable at least tCKSRX.

5) Exit SR.

6) Set DLL-on by MR1 A0="0"

7) Start DLL Reset

8) Any valid command

Version 1.7

04/2015

38

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Input Clock frequency change

Once the DDR3(L) SDRAM is initialized, the DDR3(L) SDRAM requires the clock to be “stable” during almost all states of

normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock period is

not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking) specification.

The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1)

Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to change the clock

frequency.

For the first condition, once the DDR3(L) SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE has

been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is permissible,

provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode of the sole

purpose of changing the clock frequency. The DDR3(L) SDRAM input clock frequency is allowed to change only within the

minimum and maximum operating frequency specified for the particular speed grade.

The second condition is when the DDR3(L) SDRAM is in Precharge Power-Down mode (either fast exit mode or slow exit

mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode, the ODT

signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was disabled in the

mode register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be

registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes LOW before the clock

frequency may change. The DDR3(L) SDRAM input clock frequency is allowed to change only within the minimum and

maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and

CKE must be held at stable LOW levels. Once the input clock frequency is changed, stable new clocks must be provided to

the DRAM tCKSRX before precharge Power Down may be exited; after Precharge Power Down is exited and tXP has

expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to

be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL re-lock period,

ODT must remain LOW and CKE must remain HIGH. After the DLL lock time, the DRAM is ready to operate with new clock

frequency.

Version 1.7

04/2015

39

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Change Frequency during Precharge Power-down

Previous Clock Frequency

New Clock Frequency

Te1

T0

T1

T2

Ta0

Tb0

Tc0

Tc1

Td0

Td1

Te0

tCKb

tCHb tCLb

tCK

CK

tCH

tCL

tCKSRE

tCKSRX

CKE

tIH

tIS

tIH

tCPDED

tCKE

Command

Valid

MRS

NOP

tXP

DLL

Reset

Address

ODT

tAOFPD/tAOF

tIS

tIH

DQS,

DQS

High-Z

tDLLK

DQ

High-Z

DM

Enter Precharge

Power-Down mode

Exit Precharge

Power-Down mode

Frequency

Change

NOTES:

1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down

2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1; refer to ODT timing section for exact requirements

3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT signal must

continuously be registered LOW ensuring RTT is in an off state. If the RTT_NOM feature was disabled in the mode register prior to entering

Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.

Version 1.7

04/2015

40

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Write Leveling

For better signal integrity, DDR3(L) memory adopted fly by topology for the commands, addresses, control signals, and

clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect, causes flight

time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to maintain tDQSS,

tDSS, and tDSH specification. Therefore, the controller should support “write leveling” in DDR3(L) SDRAM to compensate

the skew.

The memory controller can use the “write leveling” feature and feedback from the DDR3(L) SDRAM to adjust the DQS -

 to CK -  relationship. The memory controller involved in the leveling must have adjustable delay setting on DQS -

 to align the rising edge of DQS -  with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK -

, sampled with the rising edge of DQS - , through the DQ bus. The controller repeatedly delays DQS - until a

transition from 0 to 1 is detected. The DQS -  delay established though this exercise would ensure tDQSS specification.

Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the actual

tDQSS in the application with an appropriate duty cycle and jitter on the DQS- signals. Depending on the actual

tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute limits provided in

“AC Timing Parameters” section in order to satisfy tDSS and tDSH specification. A conceptual timing of this scheme is

show as below figure.

Write Leveling Concept

Diff _CK

Source

Diff _DQS

Diff _CK

Destination

Diff _ DQS

DQ

0 or 1

0

Push DQS to capture

0 -1 transition

DQ

0 or 1

1

DQS/ driven by the controller during leveling mode must be determined by the DRAM based on ranks populated.

Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.

A separated feedback mechanism should be able for each byte lane. The low byte lane’s prime DQ, DQ0, carries the

leveling feedback to the controller across the DRAM configurations x4/x8 whereas DQ0 indicates the lower diff_DQS

(diff_LDQS) to clock relationship. The high byte lane’s prime DQ, DQ8, provides the feedback of the upper diff_DQS

(diff_UDQS) to clock relationship.

Version 1.7

04/2015

41

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DRAM setting for write leveling and DRAM termination unction in that mode

DRAM enters into Write leveling mode if A7 in MR1 set “High” and after finishing leveling, DRAM exits from write leveling

mode if A7 in MR1 set “Low”. Note that in write leveling mode, only DQS/ terminations are activated and deactivated

via ODT pin not like normal operation.

MR setting involved in the leveling procedure

Function

MR1

Enable

Disable

Write leveling enable

Output buffer mode (Qoff)

A7

1

0

1

A12

DRAM termination function in the leveling mode

ODT pin at DRAM

DQS/ termination

DQs termination

De-asserted

off

on

off

Asserted

Note: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed; in Write

Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2, RZQ/4, and RZQ/6 are

allowed.

Procedure Description

Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling mode, the

DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are allowed. As well

as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the output of other rank

must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to

accept the ODT signal.

Controller may drive DQS low and  high after a delay of tWLDQSEN, at which time DRAM has applied on-die

termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, edge which is used by the

DRAM to sample CK –  driven from controller. tWLMRD (max) timing is controller dependent.

DRAM samples CK -  status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after

tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes

(DQS/DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS – 

delay setting and launches the next DQS/ pulse after some time, which is controller dependent. Once a 0 to 1

transition is detected, the controller locks DQS – delay setting and write leveling is achieved for the device. The

following figure describes the timing diagram and parameters for the overall Write leveling procedure.

Version 1.7

04/2015

42

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Timing details of Write leveling sequence (For Information. Only Support prime DQ)

DQS -  is capturing CK -  low at T1 and CK -  high at T2

T1

tWLH

T2

tWLH

tWLS

CK

CMD

MRS

NOP

tMOD

ODT

tDQSL

tDQSH

tDQSL

tDQSH

tWLDQSEN

Diff_DQS

tWLMRD

tWLO

One Prime DQ:

Prime DQ

tWLO

Late

Re ma ining

DQs

Early

Re ma ining

DQs

tWLO

tWLOE

All DQs are Prime:

tWLMRD

tWLO

Late

Re ma ining

DQs

tWLOE

Early

Re ma ining

DQs

tWLOE

tWLO

Undefined

Driving Mode

Do not

Care

Time

break

Note:

1. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on

one DQ, the remaining DQs must be driven low as shown in above Figure, and maintained at this state

through out the leveling procedure.

2. MRS: Load MR1 to enter write leveling mode

3. NOP: NOP or deselect

4. diff_DQS is the differential data strobe (DQS, ). Timing reference points are the zero crossings. DQS

is shown with solid line,  is shown with dotted line.

6. DQS/ needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for

regular Writes; the max pulse width is system dependent.

Write Leveling Mode Exit

The following sequence describes how Write Leveling Mode should be exited:

1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins are in

undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1).

2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).

3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).

4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD (Td1).

Version 1.7

04/2015

43

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Timing detail of Write Leveling exit

T0

T1

T2

Ta0

Tb0

Tc0

Tc1

Tc2

Td0

Td1

Te0

Te1

CK

CMD

NOP

MRS

MR1

NOP

tMRD

Valid

tMOD

Valid

NOP

Valid

BA

ODT

tAOFmin

tIS

tODTLoff

tWLO

RTT_DQS_DQS

RTT_Nom

tAOFmax

DQS_DQS

DQ

Result = 1

Undefined

Driving Mode

Time Break

Transitioning

Do not Care

Extended Temperature Usage

Nanya’s DDR3(L) SDRAM supports the optional extended temperature range of 0°C to +95°C, TC. Thus, the SRT and ASR

options must be used at a minimum. The extended temperature range DRAM must be refreshed externally at 2X (double

refresh) anytime the case temperature is above +85°C (in supporting temperature range). The external refreshing

requirement is accomplished by reducing the refresh period from 64ms to 32ms. However, self refresh mode requires either

ASR or SRT to support the extended temperature. Thus either ASR or SRT must be enabled when TC is above +85°C or

self refresh cannot be used until the case temperature is at or below +85°C.

Mode Register Description

Field

Bits

Description

Auto Self-Refresh (ASR)

When enabled, DDR3(L) SDRAM automatically provides Self-Refresh power management functions for all

supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate T_OPER

during subsequent Self-Refresh operation.

ASR

MR2(A6)

0 = Manual SR Reference (SRT)

1 = ASR enable

Self-Refresh Temperature (SRT) Range

If ASR = 0, the SRT bit must be programmed to indicate T_OPERduring subsequent Self-Refresh operation. If

ASR = 1, SRT bit must be set to 0.

SRT

MR2(A7)

0 = Normal operating temperature range

1 = Extended operating temperature range

Version 1.7

04/2015

44

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Auto Self-Refresh mode - ASR mode

DDR3(L) SDRAM provides an Auto-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit

A6=1 and MR2 bit A7=0. The DRAM will manage Self-Refresh entry in either the Normal or Extended Temperature Ranges.

In this mode, the DRAM will also manage Self-Refresh power consumption when the DRAM operating temperature

changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by DRAM, MR2 bit

A6 must set to 0. If the ASR option is not enabled (MR2 bit A6=0), the SRT bit (MR2 bit A7) must be manually programmed

with the operating temperature range required during Self-Refresh operation. Support of the ASR option does not

automatically imply support of the Extended Temperature Range.

Self-Refresh Temperature Range - SRT

SRT applies to devices supporting Extended Temperature Range only. If ASR=0, the Self-Refresh Temperature (SRT)

Range bit must be programmed to guarantee proper self-refresh operation. If SRT=0, then the DRAM will set an

appropriate refresh rate for Self-Refresh operation in the Normal Temperature Range. If SRT=1, then the DRAM will set an

appropriate, potentially different, refresh rate to allow Self-Refresh operation in either the Normal or Extended Temperature

Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to IDD table for details.

Self-Refresh mode summary

Allowed Operating

MR2

A[6]

MR2

A[7]

Self-Refresh operation

Temperature Range for

Self-Refresh mode

Normal ¹

0

1

Self-Refresh rate appropriate for the Normal Temperature Range

Self-Refresh appropriate for either the Normal or Extended Temperature Ranges.

The DRAM must support Extended Temperature Range. The value of the SRT bit can

effect self-refresh power consumption, please refer to the IDD table for details.

Normal and Extended ²

ASR enabled (for devices supporting ASR and Normal Temperature Range).

Self-Refresh power consumption is temperature dependent.

Normal ¹

1

0

ASR enabled (for devices supporting ASR and Extended Temperature Range).

Self-Refresh power consumption is temperature dependent.

Normal and Extended ²

0

1

Illegal

NOTES:

1. The Normal range depends on product’s grade.

- Commercial Grade = 0℃~85℃

- Industrial Grade (-I) = -40℃~85℃

- Automotive Grade 2 (-H) = -40℃~85℃

- Automotive Grade 3 (-A) = -40℃~85℃

2. The Normal and Extended range depends on product’s grade.

- Commercial Grade = 0℃~95℃

- Industrial Grade (-I) = -40℃~95℃

- Automotive Grade 2 (-H) = -40℃~105℃

- Automotive Grade 3 (-A) = -40℃~95℃

Version 1.7

04/2015

45

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

MPR MR3 Register Definition

MR3 A[2]

MR3 A[1:0]

Function

Normal operation, no MPR transaction.

don't care

(0 or 1)

0

1

All subsequent Reads will come from DRAM array.

All subsequent Writes will go to DRAM array.

Enable MPR mode, subsequent RD/RDA commands defined by MR3 A[1:0].

See the following table

MPR Functional Description

 One bit wide logical interface via all DQ pins during READ operation.

 Register Read on x8:

 DQ [0] drives information from MPR.

 DQ [7:1] either drive the same information as DQ [0], or they drive 0.

 Addressing during for Multi Purpose Register reads for all MPR agents:

 BA [2:0]: don’t care.

 A [1:0]: A [1:0] must be equal to “00”. Data read burst order in nibble is fixed.

 A[2]: For BL=8, A[2] must be equal to 0, burst order is fixed to [0,1,2,3,4,5,6,7]; For Burst chop 4 cases, the burst order is

switched on nibble base, A[2]=0, burst order: 0,1,2,3, A[2]=1, burst order: 4,5,6,7. *)

 A [9:3]: don’t care.

 A10/AP: don’t care.

 A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0

 A11, A13: don’t care.

 Regular interface functionality during register reads:

 Support two Burst Ordering which are switched with A2 and A[1:0]=00.

 Support of read burst chop (MRS and on-the-fly via A12/BC).

 All other address bits (remaining column addresses bits including A10, all bank address bits) will be ignored by the

DDR3(L) SDRAM.

 Regular read latencies and AC timings apply.

 DLL must be locked prior to MPR READs.

Note: Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.

Version 1.7

04/2015

46

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

MPR Register Address Definition

The following table provide an overview of the available data location, how they are addressed by MR3 A[1:0] during a MRS

to MR3, and how their individual bits are mapped into the burst order bits during a Multi Purpose Register Read.

MPR MR3 Register Definition

Burst

Length

Read Address

A[2:0]

MR3 A[2]

MR3 A[1:0]

Function

Burst Order and Data Pattern

Burst order 0,1,2,3,4,5,6,7

Pre-defined Data Pattern [0,1,0,1,0,1,0,1]

Burst order 0,1,2,3

BL8

BC4

000

100

Read

Predefined

Pattern for

System

1

00

Pre-defined Data Pattern [0,1,0,1]

Burst order 4,5,6,7

Calibration

Pre-defined Data Pattern [0,1,0,1]

Burst order 0,1,2,3,4,5,6,7

BL8

BC4

BL8

BC4

BL8

BC4

000

100

000

100

000

100

1

01

10

11

RFU

Burst order 0,1,2,3

Burst order 4,5,6,7

Burst order 0,1,2,3,4,5,6,7

Burst order 0,1,2,3

Burst order 4,5,6,7

Burst order 0,1,2,3,4,5,6,7

Burst order 0,1,2,3

Burst order 4,5,6,7

Note: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent.

ACTIVE Command

The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on the

BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A15 selects the row. These rows remain active

(or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before

opening a different row in the same bank.

Version 1.7

04/2015

47

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

PRECHARGE Command

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The

bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE command is issued,

except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long

as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Once a bank

has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to

that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle bank) or if the previously open row

is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE

command issued to the bank.

Version 1.7

04/2015

48

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

READ Operation

Read Burst Operation

During a READ or WRITE command DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or

WRITE (AUTO PRECHARGE can be enabled or disabled).

A12=0, BC4 (BC4 = burst chop, tCCD=4)

A12=1, BL8

A12 will be used only for burst length control, not a column address.

Read Burst Operation RL=5 (AL=0, CL=5, BL=8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

CK

CMD

READ

NOP

Bank

Col n

Address

tRPRE

tRPST

DQS, DQS

DQ

Dout

n

Dout

n +1

Dout

n +2

Dout

n +3

Dout

n +4

Dout

n +5

Dout

n +6

Dout

n +7

CL=5

RL = AL + CL

READ Burst Operation RL = 9 (AL=4, CL=5, BL=8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

CK

CMD

READ

NOP

Bank

Col n

Address

AL = 4

tRPRE

DQS, DQS

DQ

CL=5

Dout

n

Dout

n +1

Dout

n +2

RL = AL + CL

Version 1.7

04/2015

49

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

READ Timing Definitions

Read timing is shown in the following figure and is applied when the DLL is enabled and locked.

Rising data strobe edge parameters:

• tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, .

• tDQSCK is the actual position of a rising strobe edge relative to CK, .

• tQSH describes the DQS,  differential output high time.

• tDQSQ describes the latest valid transition of the associated DQ pins.

• tQH describes the earliest invalid transition of the associated DQ pins.

Falling data strobe edge parameters:

• tQSL describes the DQS,  differential output low time.

• tDQSQ describes the latest valid transition of the associated DQ pins.

• tQH describes the earliest invalid transition of the associated DQ pins.

Version 1.7

04/2015

50

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Read Timing; Clock to Data Strobe relationship

Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked.

Rising data strobe edge parameters:

• tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and .

• tDQSCK is the actual position of a rising strobe edge relative to CK and .

• tQSH describes the data strobe high pulse width.

Falling data strobe edge parameters:

• tQSL describes the data strobe low pulse width.

Clock to Data Strobe Relationship

RL Measured

to this point

CK

tLZ(DQS)min

tDQSCKmin

tHZ(DQS)min

tRPRE

tQSH tQSL

tRPST

DQS, DQS

Early Strobe

tHZ(DQS)max

tDQSCKmax

tRPST

tLZ(DQS)max

DQS, DQS

Late Strobe

tRPRE

NOTES:

1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe edge

can vary between tDQSCK(min) and tDQSCK(max).

2. The DQS,  differential output high time is defined by tQSH and the DQS,  differential output low time is defined by tQSL.

3. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max are not

tied to tDQSCKmax (late strobe case).

4. The minimum pulse width of read preamble is defined by tRPRE(min).

5. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.

6. The minimum pulse width of read postamble is defined by tRPST(min).

7. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.

Version 1.7

04/2015

51

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Read Timing; Data Strobe to Data Relationship

The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and locked.

Rising data strobe edge parameters:

• tDQSQ describes the latest valid transition of the associated DQ pins.

• tQH describes the earliest invalid transition of the associated DQ pins.

Falling data strobe edge parameters:

• tDQSQ describes the latest valid transition of the associated DQ pins.

• tQH describes the earliest invalid transition of the associated DQ pins.

• tDQSQ; both rising/falling edges of DQS, no tAC defined

Data Strobe to Data Relationship

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CK

CMD

READ

NOP

Bank

Col n

Address

DQS, DQS

tDQSQmax

tRPRE

tQH

tRPST

tHZ(DQ)min

tLZ(DQ)min

tDQSQmin

tQH

RL = AL + CL

Dout

n

Dout

n +1

Dout

n +2

Dout

n +3

Dout

n +4

Dout

n +5

Dout

n +6

Dout

n +7

DQ (Last data valid)

DQ (First data no

longer valid)

Dout

n

Dout

n +1

Dout

n +2

Dout

n +3

Dout

n +4

Dout

n +5

Dout

n +6

Dout

n +7

All DQ collectively

Valid data

Version 1.7

04/2015

52

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Read to Read (CL=5, AL=0)

Version 1.7

04/2015

53

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

READ to WRITE (CL=5, AL=0; CWL=5, AL=0)

Version 1.7

04/2015

54

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

READ to READ (CL=5, AL=0)

Version 1.7

04/2015

55

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

READ to WRITE (CL=5, AL=0; CWL=5, AL=0)

Version 1.7

04/2015

56

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Write Operation

DDR3(L) Burst Operation

During a READ or WRITE command, DDR3(L) will support BC4 and BL8 on the fly using address A12 during the READ or

WRITE (Auto Precharge can be enabled or disabled).

A12=0, BC4 (BC4 = Burst Chop, tCCD=4)

A12=1, BL8

A12 is used only for burst length control, not as a column address.

WRITE Timing Violations

Motivation

Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the

DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to “hang up”

and errors be limited to that particular operation.

For the following, it will be assumed that there are no timing violations with regard to the Write command itself (including

ODT, etc.) and that it does satisfy all timing requirements not mentioned below.

Data Setup and Hold Violations

Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then

wrong data might be written to the memory location addressed with the offending WRITE command.

Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly

otherwise.

Strobe to Strobe and Strobe to Clock Violations

Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS,

tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might be written to

the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in

unpredictable read data, however the DRAM will work properly otherwise.

Write Timing Parameters

This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing violations

are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not only for one edge -

as shown).

Version 1.7

04/2015

57

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Write Timing Definition

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

Tn

CK

CMD

Write

NOP

tDSH

NOP

tDSH

NOP

Bank

Col n

Address

tWPST(min)

tDSH

tDQSS tDSH

tDSS

tWPRE(min)

DQS, DQS

(tDQSS min)

tDQSL(min)

tDSS

tDQSH

tDSS

Din

tDQSH tDQSL tDQSH

tDSS

Din

n

Din

n +1

Din

n +3

Din

n +5

Din

DQ

n +2

n +4

n +6

n +7

tDSS

WL = AL + CWL

tWPST(min)

tDSH

tDSS

tWPRE(min)

DQS, DQS

(tDQSS nominal)

tDQSL(min)

tDSS

tDQSH

tDSS

tDQSH tDQSL tDQSH

tDSS

Din

n

Din

n +1

Din

n +2

Din

n +3

Din

n +4

Din

n +5

Din

n +6

Din

DQ

n +7

tDSS

tDSH

tDQSS

tWPST(min)

tDQSL(min)

tDSH

tWPRE(min)

DQS, DQS

(tDQSS max)

tDSS

tDQSH

tDQSH tDQSL tDQSH

Din

n

Din

n +1

Din

n +2

Din

n +3

Din

n +4

Din

n +5

Din

n +6

Din

n +7

tDSS

DQ

tDSS

Note:

1. BL=8, WL=5 (AL=0, CWL=5).

2. Din n = data in from column n.

3. NOP commands are shown for ease of illustration; other command may be valid at these times.

4. BL8 setting activated by either MR0 [A1:0=00] or MR0 [A1:0=01] and A12 = 1 during WRITE command at T0.

5. tDQSS must be met at each rising clock edge.

Version 1.7

04/2015

58

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

WRITE to WRITE (WL=5; CWL=5, AL=0)

Version 1.7

04/2015

59

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

WRITE to READ (RL=5, CL=5, AL=0; WL=5, CWL=5, AL=0; BL=4)

Version 1.7

04/2015

60

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

WRITE to WRITE (WL=5, CWL=5, AL=0)

Version 1.7

04/2015

61

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Refresh Command

The Refresh command (REF) is used during normal operation of the DDR3(L) SDRAMs. This command is not persistent,

so it must be issued each time a refresh is required. The DDR3(L) SDRAM requires Refresh cycles at an average periodic

interval of tREFI. When , RA, and A are held Low and WE High at the rising edge of the clock, the chip enters a

Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before

the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes

the address bits “Don’t Care” during a Refresh command. An internal address counter suppliers the address during the

refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has

completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the

next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as

shown in the following figure.

In general, a Refresh command needs to be issued to the DDR3(L) SDRAM regularly every tREFI interval. To allow for

improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.

A maximum of 8 Refresh commands can be postponed during operation of the DDR3(L) SDRAM, meaning that at no point

in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are

postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A

maximum of 8 additional Refresh commands can be issued in advance (“pulled in”), with each one reducing the number of

regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not

further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two

surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh

commands must be executed.

Self-Refresh Entry/Exit Timing

T0

T1

Ta0

Ta1

Tb0

Tb1

Tb2

Tb3

Tc0

Tc1

CK

CMD

REF

NOP

REF

NOP

Valid

REF

Valid

tRFC

tRFC(min)

DRAM must be idle

tREFI (max, 9 x tREFI)

DRAM must be idle

Time Break

Postponing Refresh Commands (Example)

tREFI

9 x tREFI

t

tREFI

8 REF-Command postponed

Version 1.7

04/2015

62

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Pulled-in Refresh Commands (Example)

tREFI

9 x tREFI

t

tREFI

8 REF-Commands pulled-in

Self-Refresh Operation

The Self-Refresh command can be used to retain data in the DDR3(L) SDRAM, even if the reset of the system is powered

down. When in the Self-Refresh mode, the DDR3(L) SDRAM retains data without external clocking. The DDR3(L) SDRAM

device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE) Command is defined by

having , RA, A, and E held low with WE high at the rising edge of the clock.

Before issuing the Self-Refreshing-Entry command, the DDR3(L) SDRAM must be idle with all bank precharge state with

tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either registering

ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command. Once the

Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode. During normal

operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self-Refresh and is automatically

enabled (including a DLL-RESET) upon exiting Self-Refresh.

When the DDR3(L) SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and REET,

are “don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ,

VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh command internally within

tCKE period once it enters Self-Refresh mode.

The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3(L) SDRAM

must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the external clock

tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable tCKSRX before the device

can exit Self-Refresh mode.

The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE going

back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or Deselect on

command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL

can be issued to the device to allow for any internal refresh in progress. Before a command which requires a locked DLL

can be applied, a delay of at least tXSDLL and applicable ZQCAL function requirements must be satisfied.

Version 1.7

04/2015

63

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on

the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to

compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To issue ZQ calibration

commands, applicable timing requirements must be satisfied.

CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry.

Upon exit from Self-Refresh, the DDR3(L) SDRAM can be put back into Self-Refresh mode after waiting at least tXS period

and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each

positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL.

The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is

raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3(L) SDRAM requires a minimum of one extra

refresh command before it is put back into Self-Refresh mode.

Self-Refresh Entry/Exit Timing

T0

T1

T2

Ta0

Tb0

Tc0

Tc1

Td0

Te0

Tf

CK, CK

tCKSRE

tCKS

RX

tCPDED

CKE

ODT

CMD

Valid

tCKESR

ODTL

NOP

SRE

NOP

SRX

NOP 1)

tXS

Valid 2) Valid 3)

Valid

tRF

tXSDLL

Enter Self Refresh

Note:

1. Only NOP or DES commands

Exit Self Refresh

Do Not

Care

Time

Break

2. Valid commands not requiring a locked DLL

3. Valid commands requiring a locked DLL

Version 1.7

04/2015

64

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Power-Down Modes

Power-Down Entry and Exit

Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is not

allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write

operation are in progress. CKE is allowed to go low while any of other operation such as row activation, precharge or auto

precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operation.

The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not

locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and

synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL

operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications.

During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in precharge

Power-Down mode; if any bank is open after in progress commands are completed, the device will be in active

Power-Down mode.

Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, E, and REET. To protect

DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed during the

CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in deactivation of

command and address receivers after tCPDED has expired.

Power-Down Entry Definitions

Status of DRAM

MRS bit A12

DLL

PD Exit

Relevant Parameters

Active

Don't Care

On

Fast

tXP to any valid command.

(A Bank or more open)

tXP to any valid command. Since it is in precharge state,

commands here will be ACT, AR, MRS/EMRS, PR, or PRA.

tXPDLL to commands who need DLL to operate, such as RD,

RDA, or ODT control line.

Precharged

0

1

Off

On

Slow

Fast

(All Banks Precharged)

Precharged

tXP to any valid command.

(All Banks Precharged)

Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during

precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, REET high, and a stable

clock signal must be maintained at the inputs of the DDR3(L) SDRAM, and ODT should be in a valid state but all other input

signals are “Don’t care” (If REET goes low during Power-Down, the DRAM will be out of PD mode and into reset state).

CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the device.

Version 1.7

04/2015

65

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect command).

CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down

exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC spec table of this datasheet.

Active Power-Down Entry and Exit timing diagram

T0

T1

T2

Ta0

Ta1

Tb0

Tb1

Tc0

CK

CMD

Valid

NOP

tIS

tPD

tIH

CKE

Valid

tIH

tIS

tCKE

Address

Valid

tCPDED

tXP

Enter

Power-Down

Exit

Power-Down

Do not

care

Time

Break

Timing Diagrams for CKE with PD Entry, PD Exit with Read, READ with Auto Precharge, Write and Write with Auto Precharge, Activate,

Precharge, Refresh, MRS:

Power-Down Entry after Read and Read with Auto Precharge

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

Tb2

Tb3

Tc0

CK

WRITE

CMD

NOP

Valid

tIS

tCPDED

CKE

Bank,

Col n

Address

DQS

WL=AL+CWL

WR (1)

tPD

Start Internal

Precharge

Din

b

Din

b+1

Din

b+2

Din

b+3

Din

b+4

Din

b+5

Din

b+6

Din

b+7

BL8

BC4

Din

b

Din

b+1

Din

b+2

Din

b+3

tWRAPDEN

Power-Down

Entry

Do not

care

Time

Break

Version 1.7

04/2015

66

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Power-Down Entry after Write with Auto Precharge

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Ta8

Tb0

Tb1

CK

RD or

RDA

CMD

NOP

Valid

tIS

tCPDED

CKE

tPD

Address

DQS

Valid

RL = AL + CL

Din

b

Din

b+1

Din

b+2

Din

b+3

Din

b+4

Din

b+5

Din

b+6

Din

b+7

BL8

BC4

Din

b

Din

b+1

Din

b+2

Din

b+3

tRDPDEN

Power-Down

Entry

Do not

care

Time

Break

Version 1.7

04/2015

67

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Power-Down Entry after Write

T0

T1

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Ta7

Tb0

Tb1

Tb2

Tc0

CK

WRITE

CMD

NOP

tIS

tCPDED

CKE

Bank,

Col n

Address

DQS

WL=AL+CWL

WR

tPD

Din

b

Din

b+1

Din

b+2

Din

b+3

Din

b+4

Din

b+5

Din

b+6

Din

b+7

BL8

BC4

Din

b

Din

b+1

Din

b+2

Din

b+3

tWRPDEN

Power-Down

Entry

Do not

care

Time

Break

Precharge Power-Down (Fast Exit Mode) Entry and Exit

T0

T1

T2

Ta0

Ta1

Tb0

Tb1

NOP

Tc0

CK

WRITE

CMD

NOP

tCKE

NOP

tCPDED

tIS

tIH

CKE

Valid

tIS

tPD

tXP

Enter

Power-Down

Mode

Exit

Power-Down

Mode

Do not

care

Time

Break

Precharge Power-Down (Slow Exit Mode) Entry and Exit

T0

T1

T2

Ta0

Ta1

Tb0

Tb1

Tc0

Td0

CK

WRITE

CMD

NOP

Valid

tCPDED

tCKE

tIS

tIH

CKE

Valid

tIS

tXP

tPD

tXPDLL

Enter

Power-Down

Mode

Exit

Power-Down

Mode

Time

Break

Do not

care

Version 1.7

04/2015

68

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Refresh Command to Power-Down Entry

T0

T1

T2

T3

Ta0

Ta1

CK

CMD

REF

NOP

Valid

Address

Valid

tCPDED

tIS

tPD

CKE

Valid

tREFPDEN

Do not

care

Time

Break

Version 1.7

04/2015

69

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Active Command to Power-Down Entry

T0

T1

T2

T3

Ta0

Ta1

CK

CMD

Active

Valid

NOP

Valid

Address

tCPDED

tIS

tPD

CKE

Valid

tACTPDEN

Do not

care

Time

Break

Precharge/Precharge all Command to Power-Down Entry

T0

T1

T2

T3

Ta0

Ta1

CK

PRE

PREA

CMD

NOP

Valid

Address

Valid

tCPDED

tIS

tPD

CKE

Valid

tPREPDEN

Do not

care

Time

Break

MRS Command to Power-Down Entry

T0

T1

Ta0

Ta1

Tb0

Tb1

CK

CMD

MRS

Valid

NOP

Valid

Address

tCPDED

tIS

tPD

CKE

Valid

tMRSPDEN

Do not

care

Time

Break

Version 1.7

04/2015

70

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

On-Die Termination (ODT)

ODT (On-Die Termination) is a feature of the DDR3(L) SDRAM that allows the DRAM to turn on/off termination resistance

for each DQ, DQS, , and DM for x8 configuration and TDQS, T for x8 configuration, when enabled via A11=1 in

MR1) via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing

the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.

The ODT feature is turned off and not supported in Self-Refresh mode.

A simple functional representation of the DRAM ODT feature is shown as below.

Functional Representation of ODT

ODT

/ 2

VDDQ

To other

circuitry

like

RTT

Switch

RCV, ...

DQ , DQS, DM, TDQS

The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The

value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the Mode Register MR1

and MR2 are programmed to disable ODT and in self-refresh mode.

ODT Mode Register and ODT Truth Table

The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of RTT is

determined by the settings of those bits.

Application: Controller sends WR command together with ODT asserted.

One possible application: The rank that is being written to provides termination.

DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)

DRAM does not use any write or read command decode information.

Termination Truth Table

ODT pin

DRAM Termination State

OFF

0

1

ON, (OFF, if disabled by MR1 {A2, A6, A9} and MR2{A9, A10} in general)

Version 1.7

04/2015

71

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Synchronous ODT Mode

Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these

modes are:



Any bank active with CKE high

Refresh with CKE high

Idle mode with CKE high

Active power down mode (regardless of MR0 bit A12)

Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12

The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by continu-

ously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register

set command during DLL-off mode.

In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock edge

and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write

latency (WL) by: ODTLonn = WL - 2; ODTLoff = WL-2.

ODT Latency and Posted ODT

In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT

signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative

to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3(L) SDRAM

latency definitions.

ODT Latency

Symbol

ODTLon

ODTLoff

Parameter

DDR3-1600

Unit

tCK

ODT turn on Latency

ODT turn off Latency

WL - 2 = CWL + AL - 2

tCK

Version 1.7

04/2015

72

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Timing Parameters

In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max.

Minimum RTT turn-on time (t_AONmin) is the point in time when the device leaves high impedance and ODT resistance

begins to turn on. Maximum RTT turn-on time (t_AONmax) is the point in time when the ODT resistance is fully on. Both are

measured from ODTLon.

Minimum RTT turn-off time (t_AOFmin) is the point in time when the device starts to turn off the ODT resistance. Maximum

RTT turn off time (t_AOFmax) is the point in time when the on-die termination has reached high impedance. Both are

measured from ODTLoff.

When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with

ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and

ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until

ODT is registered low.

Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6;

ODTLoff=AL+CWL-2=6

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

CK

CKE

ODT

tAONmax

tAONmin

AL=3

ODTH4, min

AL=3

CWL - 2

tAONmax

ODTLon = CWL + AL -2

tAONmin

ODTLoff = CWL + AL -2

RTT_NOM

DRAM_RTT

Transitioning

Do not care

Synchronous ODT example with BL=4, WL=7

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

T18

CK

NOP

WRS4

NOP

ODTH4

ODT

ODTH4min

ODTLoff = WL - 2

ODTLoff = CWL -2

tAOFmax

tAONmax

tAONmin

tAOFmax

tAOFmin

tAONmin

tAONmax

tAOFmin

DRAM_RTT

RTT_NOM

ODTLon = CWL -2

Transitioning

Do not care

ODT must be held for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8 (BL=8) after

Write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of

Write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered at T6

ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the Write command at T7.

Version 1.7

04/2015

73

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ODT during Reads:

As the DDR3(L) SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle

before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble

as shown in the following figure. DRAM turns on the termination when it stops driving which is determined by tHZ. If DRAM

stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops driving late (i.e. tHZ is late), then DRAM

complies with tAONmax timing. Note that ODT may be disabled earlier before the Read and enabled later after the Read

than shown in this example.

ODT must be disabled externally during Reads by driving ODT low. (Example: CL=6;

AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

CK

CMD

Read

Valid

NOP

Address

ODT

RL = AL + CL

ODTLon = CWL + AL - 2

ODTLoff = CWL + AL - 2

RTTR_TNTOM

tAONmax

tAOFmin

DRAM

ODT

RTT_NOM

tAOFmax

DQSdiff

Din

b

Din

b+1

Din

b+2

Din

b+3

Din

b+4

Din

b+5

Din

b+6

Din

b+7

DQ

Version 1.7

04/2015

74

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Dynamic ODT

In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination

strength of the DDR3(L) SDRAM can be changed without issuing an MRS command. This requirement is supported by the

“Dynamic ODT” feature as described as follows:

Functional Description

The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described as follows:

Two RTT values are available: RTT_Nom and RTT_WR.

 The value for RTT_Nom is preselected via bits A[9,6,2] in MR1.

 The value for RTT_WR is preselected via bits A[10,9] in MR2.

During operation without write commands, the termination is controlled as follows:

 Nominal termination strength RTT_Nom is selected.

 Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.

When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the

termination is controlled as follows:

 A latency ODTLcnw after the write command, termination strength RTT_WR is selected.

 A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the

write command, termination strength RTT_Nom is selected.

 Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.

The following table shows latencies and timing parameters which are relevant for the on-die termination control in Dynamic

ODT mode.

The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2[A10,A9

= [0,0], to disable Dynamic ODT externally.

When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with

ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write command. ODTH4 and

ODTH8 are measured from ODT registered high to ODT registered low or from the registration of Write command until ODT

is register low.

Version 1.7

04/2015

75

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Latencies and timing parameters relevant for Dynamic ODT

Definition for all

DDR3(L) speed pin

Name and Description

Abbr.

Defined from

Defined to

Unit

tCK

registering external

ODT signal high

ODT turn-on Latency

ODTLon

turning termination on

ODTLon=WL-2

ODTLoff=WL-2

ODTLcnw=WL-2

ODTLcwn4=4+ODTLoff

ODTLcwn8=6+ODTLoff

ODTH4=4

registering external

ODT signal low

ODT turn-off Latency

ODTLoff

ODTLcnw

ODTLcwn4

ODTLcwn8

ODTH4

turning termination off

tCK

ODT Latency for changing from

RTT_Nom to RTT_WR

registering external

write command

change RTT strength from

RTT_Nom to RTT_WR

tCK

ODT Latency for change from

RTT_WR to RTT_Nom (BL=4)

registering external

write command

change RTT strength from

RTT_WR to RTT_Nom

tCK

ODT Latency for change from

RTT_WR to RTT_Nom (BL=8)

registering external

write command

change RTT strength from

RTT_WR to RTT_Nom

tCK(avg)

Minimum ODT high time

after ODT assertion

registering ODT high ODT registered low

Minimum ODT high time

after Write (BL=4)

registering write with

ODT registered low

ODT high

ODTH4

ODTH4=4

Minimum ODT high time

after Write (BL=8)

registering write with

ODT register low

ODT high

ODTH8

ODTH8=6

ODTLcnw

RTT valid

ODTLcwn

tADC(min)=0.3tCK(avg)

tADC(max)=0.7tCK(avg)

RTT change skew

tADC

Note: tAOF,nom and tADC,nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)

Version 1.7

04/2015

76

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ODT Timing Diagrams

Dynamic ODT: Behavior with ODT being asserted before and after the write

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

T16

T17

CK

CMD

NOP

WRS4

Valid

NOP

Address

ODT

ODTLoff

ODTH4

tAOFmin

ODTLcwn4

tADCmin

tAONmin

RTT_Nom

RTT_WR

RTT_Nom

RTT

tAOFmax

tAONmax

tADCmax

ODTLon

ODTLcnw

ODTH4

DQS/DQS

WL

Din

n

Din

n+1

Din

n+2

Din

n+3

DQ

Do not

care

Transitioning

Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write

command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command).

Dynamic ODT: Behavior without write command, AL=0, CWL=5

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK

CMD

Valid

Address

ODT

ODTLoff

ODTH4

tADCmin

tAONmin

RTT_Nom

RTT

tADCmax

tAONmax

ODTLon

DQS/DQS

DQ

Do not

care

Transitioning

Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5

would also be legal.

Version 1.7

04/2015

77

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Dynamic ODT: Behavior with ODT pin being asserted together with write command

for the duration of 6 clock cycles.

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK

CMD

NOP

WRS8

Valid

NOP

ODTLcnw

ODTLon

Address

ODT

ODTH8

ODTLoff

tAOFmin

tAONmin

RTT_WR

RTT

tAOFmax

tAONmax

ODTLcwn8

DQS/DQS

WL

Din

h

Din

h+1

Din

h+2

Din

h+3

Din

h+4

Din

h+5

Din

h+6

Din

h+7

DQ

Do not

care

Transitioning

Note: Example for BL8 (via MRS or OTF), AL=0, CWL=5. In this example ODTH8=6 is exactly satisfied.

Dynamic ODT: Behavior with ODT pin being asserted together with write

command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF),

AL=0, CWL=5.

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK

ODTLcnw

CMD

NOP

WRS4

Valid

NOP

Address

ODT

ODTH4

tAONmin

ODTLoff

tADCmin

tAOFmin

RTT_WR

RTT_Nom

tADCmax

RTT

tAOFmax

tAONmax

ODTLon

ODTLcwn4

DQS/DQS

WL

Din

n

Din

n+1

Din

n+2

Din

n+3

DQ

Do not

care

Transitioning

Version 1.7

04/2015

78

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Dynamic ODT: Behavior with ODT pin being asserted together with write command

for the duration of 4 clock cycles.

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

CK

CK#

ODTLcnw

CMD

NOP

WRS4

Valid

NOP

Address

ODT

ODTH4

tAONmin

ODTLoff

RTT_WR

tAOFmin

RTT

tAONmax

tAOFmax

ODTLon

ODTLcwn4

DQS/DQS

WL

Din

n

Din

n+1

Din

n+2

Din

n+3

DQ

Do not

care

Transitioning

Version 1.7

04/2015

79

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Asynchronous ODT Mode

Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen) in

precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge power

down mode if DLL is disabled during precharge power down by MR0 bit A12.

In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the

external ODT command.

In asynchronous ODT mode, the following timing parameters apply: t_AONPDmin/max, t_AOFPDmin/max.

Minimum RTT turn-on time (t_AONPDmin) is the point in time when the device termination circuit leaves high impedance state

and ODT resistance begins to turn on. Maximum RTT turn on time (t_AONPDmax) is the point in time when the ODT

resistance is fully on.

t_AONPDmin and t_AONPDmax are measured from ODT being sampled high.

Minimum RTT turn-off time (t_AOFPDmin) is the point in time when the devices termination circuit starts to turn off the ODT

resistance. Maximum ODT turn off time (t_AOFPDmax) is the point in time when the on-die termination has reached high

impedance. t_AOFPDmin and t_AOFPDmax are measured from ODT being sample low.

Asynchronous ODT Timings on DDR3(L) SDRAM with fast ODT transition: AL is

ignored.

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

T15

CK

CK#

CKE

ODT

tIS

tIH

tIS

tIH

tAONPDmax

tAOFPDmin

RTT

tAONPDmin

tAOFPDmax

Do not

care

Transitioning

In Precharge Power Down, ODT receiver remains active; however no Read or Write command can be issued, as the

respective ADD/CMD receivers may be disabled.

Asynchronous ODT Timing Parameters for all Speed Bins

Symbol

Description

Min.

Max.

8.5

Unit

ns

Asynchronous RTT turn-on delay (Power-Down with DLL frozen)

Asynchronous RTT turn-off delay (Power-Down with DLL frozen)

t_AONPD

2

t_AOFPD

8.5

ns

Version 1.7

04/2015

80

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ODT timing parameters for Power Down (with DLL frozen) entry and exit transition

period

Description

Min.

Max.

min{ ODTLon * tCK + tAONmin; tAONPDmin }

min{ (WL - 2) * tCK + tAONmin; tAONPDmin }

min{ ODTLoff * tCK + tAOFmin; tAOFPDmin }

min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin }

max{ ODTLon * tCK + tAONmax; tAONPDmax }

max{ (WL - 2) * tCK + tAONmax; tAONPFmax }

max{ ODTLoff * tCK + tAOFmax; tAOFPDmax }

max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax }

ODT to RTT turn-on delay

ODT to RTT turn-off delay

tANPD

WL-1

Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry

If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a transition

period around power down entry, where the DDR3(L) SDRAM may show either synchronous or asynchronous ODT

behavior.

The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is counted

backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock cycle where

CKE is first registered low. The transition period begins with the starting point of tANPD and terminates at the end point of

tCPDED(min). If there is a Refresh command in progress while CKE goes low, then the transition period ends at the later

one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please note that the actual starting point

at tANPD is excluded from the transition period, and the actual end point at tCPDED(min) and tRFC(min, respectively, are

included in the transition period.

ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and

(ODTLon*tCK + tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK + tAONmax). ODT de-assertion

during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and (ODTLoff*tCK +

tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK + tAOFmax). Note that, if AL has a large value, the

range where RTT is uncertain becomes quite large. Figure 85 shows the three different cases: ODT_A, synchronous

behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the

transition period.

Version 1.7

04/2015

81

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Synchronous to asynchronous transition during Precharge Power Down (with DLL

frozen) entry (AL=0; CWL=5; tANPD=WL-1=4)

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

CK

NOP

CMD

CKE

tCPDEDmin

tANPD

tCPDED

PD entry transition period

Last sync.

ODT

tAOFmin

RTT

tAOFmax

ODTLoff

Sync. Or

async. ODT

RTT

tAOFPDmin

tAOFPDmax

ODTLoff+tAOFPDmin

ODTLoff+tAOFPDmax

First async.

ODT

tAOFPDmax

RTT

tAOFPDmin

Do not

care

Time

Break

Transitioning

Version 1.7

04/2015

82

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Asynchronous to Synchronous ODT Mode transition during Power-Down Exit

If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a

transition period around power down exit, where either synchronous or asynchronous response to a change in ODT must

be expected from the DDR3(L) SDRAM.

This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high.

t_ANPDis equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high.

ODT assertion during the transition period may result in an RTT change as early as the smaller of t_AONPDmin and (ODT-

Lon*tCK+t_AONmin) and as late as the larger of t_AONPDmax and (ODTLon*tCK+t_AONmax). ODT de-assertion during the tran-

sition period may result in an RTT change as early as the smaller of t_AOFPDmin and (ODTLoff*tCK+t_AOFmin) and as late as

the larger of t_AOFPDmax and (ODToff*tCK+t_AOFmax). Note that if AL has a large value, the range where RTT is uncertain

becomes quite large. The following figure shows the three different cases: ODT_C, asynchronous response before t_ANPD

;

ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition

period with synchronous response.

Asynchronous to synchronous transition during Precharge Power Down (with DLL

frozen) exit (CL=6; AL=CL-1; CWL=5; tANPD=WL-1=9)

T0

T1

T2

Ta0

Ta1

Ta2

Ta3

Ta4

Ta5

Ta6

Tb0

Tb1

Tb2

Tc0

Tc1

Tc2

Td0

Td1

CK

CKE

CMD

NOP

tANPD

tXPDLL

PD exit transition period

ODT_C

_sync

tAOFPDmin

tAOFPDmax

DRAM

_RTT_

C_sync

RTT

ODT_B

_tran

tAOFPDmin

DRAM

_RTT_

B_tran

RTT

tAOFPDmax

ODTLoff + tAOFmin

ODTLoff + tAOFmax

ODTLoff

ODT_A

_async

tAOFmax

tAOFmin

DRAM_

RTT_A_

async

RTT

Do not

care

Time

Break

Transitioning

Version 1.7

04/2015

83

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low

periods

If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD exit

may overlap. In this case, the response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be

synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition period

(even if the entry ends later than the exit period).

If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case, the

response of the DDR3(L) SDRAMs RTT to a change in ODT state at the input may be synchronous or asynchronous from

the state of the PD exit transition period to the end of the PD entry transition period. Note that in the following figure, it is

assumed that there was no Refresh command in progress when Idle state was entered.

Transition period for short CKE cycles with entry and exit period overlapping

(AL=0; WL=5; tANPD=WL-1=4)

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

T10

T11

T12

T13

T14

CK

CMD

REF

NOP

CKE

tANPD

tXPDLL

PD exit transition period

PD entry transition period

tRFC(min)

CKE

Short CKE high transition period

tXPDLL

Do not

care

Transitioning

Version 1.7

04/2015

84

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ZQ Calibration Commands

ZQ Calibration Description

ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3(L) SDRAM needs longer time to calibrate

output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations.

ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be

issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine

inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO

which gets reflected as updated output driver and on-die termination values.

The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the

transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing

period of tZQoper.

ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing

window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS.

No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or

tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM

calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power.

All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.

ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh

exit, DDR3(L) SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible

time for ZQ Calibration command (short or long) after self refresh exit is tXS.

In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or

tZQCS between ranks.

Version 1.7

04/2015

85

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ZQ Calibration Timing

T0

T1

Ta0

Ta1

Ta2

Ta3

Tb0

Tb1

Tc0

Tc1

Tc2

CK

CMD

ZQCL

NOP

Valid

ZQCS

NOP

Valid

Address

A10

Valid

CKE

ODT

(1)

(2)

Valid

(1)

(2)

Valid

DQ Bus

Activities

(3)

Hi-Z

tZQCS

Activities

(3)

Hi-Z

tZQCS

Do not

care

Time

Break

Note:

1. CKE must be continuously registered high during the calibration procedure.

2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.

3. All devices connected to the DQ bus should be high impedance during the calibration procedure.

ZQ External Resistor Value, Tolerance, and Capacitive loading

In order to use the ZQ calibration function, a 240 ohm +/- 1% tolerance external resistor connected between the ZQ pin and

ground. The single resistor can be used for each SDRAM or one resistor can be shared between two SDRAMs if the ZQ

calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin must be limited.

Version 1.7

04/2015

86

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Absolute Maximum Ratings

Absolute Maximum DC Ratings

Symbol

Parameter

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

Rating

Unit

V

Note

1,3

1

VDD

-0.4 V ~ 1.80 V

-55 ~ 100

VDDQ

Vin, Vout

Tstg

V

1,2

C

Note:

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.

3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when VDD and

VDDQ are less than 500Mv; Vref may be equal to or less than 300mV.

Refresh parameters by device density

Parameter

1Gb

2Gb

4Gb

8Gb

Unit

Symbol

REF command to ACT or REF command time

tRFC

110

160

260

350

ns

Version 1.7

04/2015

87

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Temperature Range

Condition

Parameter

Value

Unit

C

Notes

Normal Operating Temperature Range

Extended Temperature Range

0 ≤Toper ≤ 85

1

1,2

1

Commercial

85 < Toper ≤ 95

-40 ≤ Toper ≤ 85

85 < Toper ≤ 95

-40 ≤ Toper ≤ 85

85 < Toper ≤ 105

-40 ≤ Toper ≤ 85

85 < Toper ≤ 95

C

Normal Operating Temperature Range

Extended Temperature Range

C

Industrial

1,2

1

C

Normal Operating Temperature Range

Extended Temperature Range

C

Automotive Grade 2

Automotive Grade 3

1,2

1

C

Normal Operating Temperature Range

Extended Temperature Range

C

1,2

C

Note:

1. Operating Temperature Toper is the case surface temperature on the center/top side of the DRAM.

2. Some applications require operation of the DRAM in the Extended Temperature Range.

Full specifications are guaranteed in this range, but the following additional apply.

a) Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. It is also possible to

specify a component with 1x refresh (tREFI to 7.8us) in the Extended Temperature Range.

b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual

Self-Refresh mode with Extended Temperature Range capability (MR2 A6=0 and MR2 A7=1) or enable the optional Auto

Self-Refresh mode (MR2 A6=1 and MR2 A7=0).

Version 1.7

04/2015

88

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

AC & DC Operating Conditions

Recommended DC Operating Conditions

Rating

Typ.

Symbol

Parameter

Unit

Note

Min.

1.425

1.283

Max.

1.575

1.45

DDR3

1.5

1,2

VDD

Supply Voltage

V

DDR3L

1.35

3,4,5,6

DDR3

1.425

1.283

1.5

1.575

1.45

1,2

VDDQ

Supply Voltage for Output

V

DDR3L

1.35

3,4,5,6

Note:

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.

3. Maximun DC value may not be great than 1.425V.The DC value is the linear average of VDD/ VDDQ(t) over a very long period of time

(e.g., 1 sec).

4. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.

5. Under these supply voltages, the device operates to this DDR3L specification.

6. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed

for DDR3L operation.

7. VDD= VDDQ= 1.35V (1.283–1.45V )

Backward compatible to VDD= VDDQ= 1.5V ±0.075V

Supports DDR3L devices to be backward com-patible in 1.5V applications

Version 1.7

04/2015

89

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

AC & DC Input Measurement Levels

DDR3 AC and DC Logic Input Levels for Command and Address

DDR3

Symbol

Parameter

800,1066,1333,1600

1866,2133

Unit

Notes

Min

Max

Min

Max

VIH.CA(DC100)

VIL.CA(DC100)

VIH.CA(AC175)

VIL.CA(AC175)

VIH.CA(AC150)

VIL.CA(AC150)

VIH.CA(AC135)

VIL.CA(AC135)

VIH.CA(AC125)

VIL.CA(AC125)

DC input logic high

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

Vref + 0.1

VDD

Vref + 0.1

VDD

V

1, 5

VSS

Vref - 0.1

VSS

Vref - 0.1

1, 6

Vref + 0.175

Note 2

-

1, 2, 7

1, 2, 8

1, 2, 7

1, 2, 8

1, 2, 7

1, 2, 8

1, 2, 7

1, 2, 8

Note 2

Vref - 0.175

-

Vref + 0.150

Note 2

-

Note 2

Vref - 0.150

-

Vref + 0.135

Note 2

-

Note 2

Vref - 0.135

Note 2

Vref - 0.125

Note 2

Reference Voltage for ADD,

CMD inputs

VRefCA(DC)

0.49 * VDD

0.51 * VDD

0.49 * VDD

0.51 * VDD

V

3, 4, 9

NOTE 1. For input only pins except REET. Vref = VrefCA(DC).

NOTE 2. See “Overshoot and Undershoot Specifications” .

NOTE 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).

NOTE 4. For reference: approx. VDD/2 +/- 15 mV.

NOTE 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)

NOTE 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)

NOTE 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and VIH.CA(AC125); VIH.CA(AC175)

value is used when Vref + 0.175V is referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value

is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is used when Vref + 0.125V is referenced.

NOTE 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC175) value

is used when Vref - 0.175V is referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used

when Vref - 0.135V is referenced, and VIL.CA(AC125) value is used when Vref - 0.125V is referenced.

NOTE 9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device

Version 1.7

04/2015

90

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3L AC and DC Logic Input Levels for Command and Address

DDR3L

Symbol

Parameter

800,1066

1333,1600

1866

Unit Notes

Min

Max

Min

Max

Min

Max

V

1

VIH.CA(DC90)

VIL.CA(DC90)

VIH.CA(AC160)

VIL.CA(AC160)

VIH.CA(AC135)

VIL.CA(AC135)

VIH.CA(AC125)

VIL.CA(AC125)

VRefCA(DC)

DC input logic high

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

Vref + 0.09

VSS

VDD

Vref + 0.09

VSS

VDD

Vref + 0.09

VDD

V

1

Vref - 0.09

Note 2

Vref - 0.09

Note 2

VSS

Vref - 0.09

-

V

-

Vref + 0.16

Note 2

Vref + 0.16

Note 2

1,2

V

1,2

-

Vref - 0.16

Note 2

Vref - 0.16

Note 2

Vref + 0.135

Note 2

1,2

Note 2

Vref - 0.135

Note 2

Vref - 0.135

Note 2

Vref - 0.135

Note 2

Vref + 0.125

-

1,2

Note 2

Vref - 0.125

Reference Voltage for

ADD, CMD inputs

0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD

V

3,4

NOTE 1 For input only pins except REET. Vref = VrefCA(DC).

NOTE 2 See “Overshoot and Undershoot Specifications”

NOTE 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).

NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV

Version 1.7

04/2015

91

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3 AC and DC Logic Input Levels for DQ and DM

DDR3

1333,1600

Symbol

Parameter

800,1066

1866,2133

Unit Notes

Min

Max

Min

Max

Min

Max

VIH.DQ(DC100) DC input logic high

VIL.DQ(DC100) DC input logic low

Vref + 0.1

VSS

VDD

Vref + 0.1

VSS

VDD

Vref + 0.1

VDD

V

1, 5

Vref - 0.1

Note 2

Vref - 0.1

-

VSS

Vref - 0.1

1, 6

VIH.DQ(AC175) AC input logic high Vref + 0.175

VIL.DQ(AC175) AC input logic low Note 2

VIH.DQ(AC150) AC input logic high Vref + 0.150

VIL.DQ(AC150) AC input logic low Note 2

VIH.DQ(AC135) AC input logic high Vref + 0.135

-

1, 2, 7

1, 2, 8

1, 2, 7

1, 2, 8

1, 2, 7

1, 2, 8

Vref - 0.175

Note 2

-

Vref + 0.150

Note 2

Vref + 0.135

Note 2

Vref - 0.150

Note 2

Vref - 0.135

-

Vref - 0.150

Note 2

Vref + 0.135

Note 2

Vref - 0.135

VIL.DQ(AC135)

VRefDQ(DC)

AC input logic low

Note 2

Vref - 0.135

Reference Voltage

for DQ, DM inputs

0.49 * VDD

0.51 * VDD 0.49 * VDD 0.51 * VDD

0.49 * VDD

0.51 * VDD

V

3, 4, 9

NOTE 1. Vref = VrefDQ(DC).

NOTE 2. See “Overshoot and Undershoot Specifications” .

NOTE 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:approx. +/- 15 mV).

NOTE 4. For reference: approx. VDD/2 +/- 15 mV.

NOTE 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)

NOTE 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)

NOTE 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135);VIH.DQ(AC175) value is used when

Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when

Vref + 0.135V is referenced.

NOTE 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135);VIL.DQ(AC175) value is used when

Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref -0.150V is referenced, and VIL.DQ(AC135) value is used when

Vref - 0.135V is referenced.

NOTE 9. VrefCA(DC) is measured relative to VDD at the same point in time on the same device

Version 1.7

04/2015

92

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3L AC and DC Logic Input Levels for DQ and DM

DDR3L

Symbol

Parameter

800,1066

1333,1600

1866

Unit Notes

Min

Max

Min

Max

Min

Max

V

VIH.DQ(DC90) DC input logic high Vref + 0.09

VIL.DQ(DC90) DC input logic low VSS

VIH.DQ(AC160) AC input logic high Vref + 0.16

VIL.DQ(AC160) AC input logic low Note 2

VIH.DQ(AC135) AC input logic high Vref + 0.135

VDD

Vref + 0.09

VSS

VDD

Vref + 0.09

VSS

VDD

1

Vref - 0.09

Note 2

Vref - 0.16

Note 2

Vref - 0.135

-

Vref - 0.09

Note 2

Vref - 0.16

Note 2

Vref - 0.135

-

Vref - 0.09

-

V

Vref + 0.16

Note 2

Vref + 0.135

Note 2

-

1,2

V

1,2

-

Vref + 0.135

Note 2

Vref + 0.13

Note 2

Vref - 0.135

Note 2

Vref - 0.13

1,2

VIL.DQ(AC135) AC input logic low

VIH.DQ(AC130) AC input logic high

VIL.DQ(AC130) AC input logic low

Note 2

-

1,2

-

Reference Voltage

VRefDQ(DC)

0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD

V

3,4

for DQ, DM inputs

NOTE 1 For input only pins except REET. Vref = VrefDQ(DC).

NOTE 2 See “Overshoot and Undershoot Specifications”.

NOTE 3 The AC peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).

NOTE 4 For reference: approx. VDD/2 +/- 13.5 mV.

Version 1.7

04/2015

93

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Vref Tolerances

The dc-tolerance limits and ac-moist limits for the reference voltages VrefCA and VrefDQ are illustrated in the following

figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise).

Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max

requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD.

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref.

“Vref” shall be understood as Vref(DC).

The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level

and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for

Vref(DC) deviations from the optimum position within the data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated

with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in

DRAM timing and their associated de-ratings.

Illustration of V_ref(DC)tolerance and V_refac-noise limits

Voltage

VDD

Vref ac-noise

Vref(DC)max

VDD/2

Vref(DC)

Vref(DC)min

VSS

time

Version 1.7

04/2015

94

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3 Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - )

DDR3-800, 1066, 1333, & 1600

Symbol

Parameter

Unit

Notes

Min

+ 0.200

Max

Note 3

1

2

VIHdiff

VILdiff

Differential input high

Differential input logic low

Differential input high ac

Differential input low ac

V

Note 3

- 0.200

VIHdiff(ac)

VILdiff(ac)

2 x (VIH(ac) - Vref)

Note 3

2 x (VIL(ac) - Vref)

NOTE 1. Used to define a differential signal slew-rate.

NOTE 2. For CK -  use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU ,U use VIH/VIL(ac) of

DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,then the reduced level applies also here.

NOTE 3. These values are not defined; however, the single-ended signals CK, , DQS, , DQSL, L, DQSU,

U need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for

overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications”

DDR3L Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - )

DDR3L-800, 1066, 1333, 1600 & 1866

Symbol

Parameter

Unit

Notes

Min

+ 0.180

Max

Note 3

1

2

VIHdiff

VILdiff

Differential input high

Differential input logic low

Differential input high ac

Differential input low ac

V

Note 3

- 0.180

VIHdiff(ac)

VILdiff(ac)

2 x (VIH(ac) - Vref)

Note 3

2 x (VIL(ac) - Vref)

NOTE 1 Used to define a differential signal slew-rate.

NOTE 2 For CK -  use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU , U use VIH/VIL(AC) of

DQs and VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.

NOTE 3 These values are not defined, however the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be

within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and

undershoot. Refer to “Overshoot and Undershoot Specifications”.

Version 1.7

04/2015

95

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Definition of differential ac-swing and “time above ac-level”

tDVAC

VIH.Diff.AC.min

VIH.Diff. DC min

0

Half cycle

VIL. Diff. DC max

VIL.Diff.AC.max

tDVAC

Time

Version 1.7

04/2015

96

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3 Allowed time before ringback (tDVAC) for CK -  and DQS - 

DDR3-800 / 1066 / 1333 / 1600

DDR3-1866 / 2133

Slew Rate

[V/ns]

tDVAC [ps]

@ |VIH/Ldiff(AC)| =

350mV

tDVAC [ ps ]

@ |VIH/Ldiff(AC)| =

300mV

tDVAC [ ps ]

@ |VIH/Ldiff(AC)| =

tDVAC [ ps ]

@ |VIH/Ldiff(AC)| =

300mV

tDVAC [ ps ]

@ |VIH/Ldiff(AC)| =

(CK - ) only

(DQS - ) only

Min

Max

Min

175

170

167

119

102

81

Max

Min

214

191

146

131

113

88

Max

Min

134

112

67

Max

Min

139

118

77

Max

> 4.0

4.0

75

-

57

3.0

50

2.0

38

1.8

34

52

63

1.6

29

33

45

1.4

22

54

9

23

1.2

note

19

56

note

1.0

note

11

< 1.0

note

NOTE 1. Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become

equal to or less than VILdiff(ac) level.

Version 1.7

04/2015

97

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3L Allowed time before ringback (tDVAC) for CK -  and DQS - 

DDR3L-800/1066/1333/1600

DDR3L-1866

tDVAC [ps]

Slew Rate

[V/ns]

tDVAC [ps]

@|VIH/Ldiff(AC)| =

320 mV

tDVAC [ps]

@|VIH/Ldiff(AC)| =

270 mV

tDVAC [ps]

@|VIH/Ldiff(AC)| =

270 mV

tDVAC [ps]

@|VIH/Ldiff(AC)| =

260 mV

@|VIH/Ldiff(AC)| =

250 mV

Min

189

162

109

91

Max

Min

201

179

134

119

100

76

Max

Min

163

140

95

Max

Min

168

147

105

91

Max

Min

176

154

111

97

Max

> 4.0

4.0

-

3.0

2.0

1.8

80

1.6

69

62

74

78

1.4

40

37

52

56

1.2

note

44

5

22

24

1.0

note

< 1.0

NOTE 1. Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become

equal to or less than VILdiff(ac) level.

Version 1.7

04/2015

98

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, , ,L, or U) has also to comply

with certain requirements for single-ended signals.

CK and have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH (ac) / VIL (ac)) for

ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, , L have to reach VSEHmin / VSELmax (approxi-

mately the ac-levels (VIH (ac) / VIL (ac)) for DQ signals) in every half-cycle proceeding and following a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH150

(ac)/VIL150(ac) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and 

Version 1.7

04/2015

99

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Single-ended levels for CK, DQS, DQSL, DQSU, , , L, or U

DDR3(L)-800, 1066, 1333, & 1600

Symbol

Parameter

Unit

Notes

Min.

(VDDQ/2) + 0.175

note3

Max.

note3

Single-ended high-level for strobes

Single-ended high-level for CK, 

Single-ended low-level for strobes

Single-ended Low-level for CK, 

1, 2

V

VSEH

note3

(VDDQ/2) - 0.175

VSEL

Note:

note3

1. For CK,  use VIH/VIL(ac) of ADD/CMD; for strobes (DQS, DQSL, DQSU, CK, , L, or U) use VIH/VIL(ac) of DQs.

2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low

level is used for a signal group, then the reduced level applies also there.

3. These values are not defined, however the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be within

the respective limits (VIH(dc)max, VIL(dc)min) for single-ended signals as well as limitations for overshoot and undershoot.

Version 1.7

04/2015

100

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross

point voltage of differential input signals (CK,  and DQS, ) must meet the requirements in the following table. The

differential input cross point voltage Vix is measured from the actual cross point of true and complete signal to the midlevel

between of VDD and VSS.

Vix Definition

VDD

,

V_IX

VDD/2

V_IX

CK,DQS

VSEL

VSS

Cross point voltage for differential input signals (CK, DQS)

DDR3

DDR3L

800/1066/1333/1600/

1866/2133

800/1066/1333/1600/

1866

Symbol

Parameter

Unit

Notes

Min

Max

Min

Max

Differential Input Cross Point

Voltage relative to

- 150

+ 150

mV

1

2

VIX(CK)

- 150

+ 150

- 175

- 150

- 175

VDD/2 for CK, 

Differential Input Cross Point

Voltage relative to

VIX(DQS)

+ 150

- 150

+ 150

mV

1

VDD/2 for DQS, 

Note 1 The relation between Vix Min/Max and VSEL/VSEH should satisfy following:

(VDD/2) + VIX (min) - VSEL >= 25 mV ;

VSEH - ((VDD/2) + VIX (max)) >= 25 mV;

Note 2 Extended range for Vix is only allowed for clock and if single-ended clock input signals CK and  are monotonic with a

single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -  is larger

than 3 V/ns.

Version 1.7

04/2015

101

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Slew Rate Definition for Differential Input Signals

Input slew rate for differential signals (CK,  and DQS, ) are defined and measured as shown below.

Differential Input Slew Rate Definition

Measured

Description

Defined by

From

To

Differential input slew rate for rising edge

(CK-& DQS-)

VILdiffmax

VIHdiffmin

[VIHdiffmin-VILdiffmax] / DeltaTRdiff

[VIHdiffmin-VILdiffmax] / DeltaTFdiff

Differential input slew rate for falling edge

(CK- & DQS-)

VIHdiffmin

VILdiffmax

The differential signal (i.e., CK-& DQS-) must be linear between these thresholds.

Version 1.7

04/2015

102

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Input Nominal Slew Rate Definition for single ended signals

Delta

TRdiff

VIHdiffMin

0

VILdiffMax

Delta

TFdiff

AC and DC Output Measurement Levels

Single Ended AC and DC Output Levels

Symbol

VOH(DC)

VOM(DC)

VOL(DC)

VOH(AC)

VOL(AC)

Parameter

DDR3(L)

0.8xVDDQ

Unit Notes

DC output high measurement level (for IV curve linearity)

DC output mid measurement level (for IV curve linearity)

DC output low measurement level (fro IV curve linearity)

AC output high measurement level (for output SR)

AC output low measurement level (for output SR)

V

0.5xVDDQ

0.2xVDDQ

VTT+0.1xVDDQ

VTT-0.1xVDDQ

V

1

Note:

1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver

impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.

Differential AC and DC Output Levels

Symbol

Parameter

DDR3(L)

+0.2 x VDDQ

-0.2 x VDDQ

Unit Notes

VOHdiff(AC) AC differential output high measurement level (for output SR)

VOLdiff(AC) AC differential output low measurement level (for output SR)

V

1

Note:

1. The swing of ± 0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with a driver

impedance of 40 Ω and an effective test load of 25 Ω to VTT=VDDQ/2 at each of the differential outputs.

Version 1.7

04/2015

103

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Single Ended Output Slew Rate

Measured

Description

Defined by

From

To

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

VOL(AC)

VOH(AC)

[VOH(AC)-VOL(AC)] / DeltaTRse

[VOH(AC)-VOL(AC)] / DeltaTFse

VOL(AC)

Note: Output slew rate is verified by design and characterization, and may not be subject to production test.

Single Ended Output Slew Rate Definition

Delta TFse

V_{OH (AC)}

V_TT

V_{OL (AC)}

Delta TFse

Version 1.7

04/2015

104

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Output Slew Rate (Single-ended)

800

1066

1333

1600

1866

2133

Parameter Symbol

-

Unit

Min Max Min Max Min Max Min Max Min Max Min Max

Single-ended

DDR3

2.5

5

2.5

5

2.5

5

2.5

5

2.5

5

2.5

5

V/ns

Output Slew

Rate

SRQse

DDR3L

1.75

Description: SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

se: Single-ended Signals

For Ron = RZQ/7 setting

Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high)

while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).

Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high)

while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low

respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

Version 1.7

04/2015

105

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Differential Output Slew Rate

Measured

From

Description

Defined by

To

Differential output slew rate for rising edge

Differential output slew rate for falling edge

VOLdiff(AC)

VOHdiff(AC)

VOLdiff(AC)

[VOHdiff(AC)-VOLdiff(AC)] / DeltaTRdiff

[VOHdiff(AC)-VOLdiff(AC)] / DeltaTFdiff

Note: Output slew rate is verified by design and characterization, and may not be subject to production test.

Differential Output Slew Rate Definition

Delta TFse

V_{Oh diff (AC)}

0

V_{OL diff (AC)}

Delta TFse

Output Slew Rate (Differential)

800

1066

1333

1600

1866

2133

Parameter Symbol

-

Unit

Min

Max

10

Min

Max

10

Min

Max

10

Min

Max

10

Min

Max

10

Min

Max

10

Differential

DDR3

5

V/ns

Output Slew

Rate

SRQdiff

DDR3L

3.5

12

3.5

12

3.5

12

3.5

12

3.5

12

3.5

12

Description:

SR: Slew Rate

Q: Query Output (like in DQ, which stands for Data-in, Query-Output)

diff: Differential Signals

For Ron = RZQ/7 setting

Version 1.7

04/2015

106

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Reference Load for AC Timing and Output Slew Rate

The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters

of the device as well as output slew rate measurements.

It is not intended as a precise representation of any particular system environment or a depiction of the actual load

presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing

reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more

coaxial transmission lines terminated at the tester electronics.

VDDQ

25 Ohm

DUT

CK , 

Vtt = VDDQ/2

DQ

DQS



Timing Reference Points

Version 1.7

04/2015

107

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Overshoot and Undershoot Specifications

AC Overshoot/Undershoot Specification for Address and Control Pins

-

800

1066

1333

1600

1866

2133

0.4

Unit

V

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area.

Maximum overshoot area above VDD

0.4

V

0.67

0.5

0.4

0.33

0.28

0.25

V-ns

Maximum undershoot area below VSS

0.5

0.4

NOTE 1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings

NOTE 2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings

Maximum Amplitude

Overshoot Area

VDD

VSS

Undershoot Area

Maximum Amplitude

Time (ns)

Version 1.7

04/2015

108

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Overshoot and Undershoot Specifications

AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask

800

1066

1333

1600

1866

2133

Unit

V

Maximum peak amplitude allowed for overshoot area

Maximum peak amplitude allowed for undershoot area.

Maximum overshoot area above VDD

0.4

V

0.25

0.19

0.15

0.13

0.11

0.10

V-ns

Maximum undershoot area below VSS

NOTE 1. The sum of the applied voltage (VDD) and peak amplitude overshoot voltage is not to exceed absolute maximum DC ratings

NOTE 2. The sum of applied voltage (VDD) and the peak amplitude undershoot voltage is not to exceed absolute maximum DC ratings

Maximum Amplitude

Overshoot Area

VDDQ

VSSQ

Undershoot Area

Maximum Amplitude

Time (ns)

Version 1.7

04/2015

109

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

34 Ohm Output Driver DC Electrical Characteristics

A Functional representation of the output buffer is shown as below. Output driver impedance RON is defined by the value of

the external reference resistor RZQ as follows:

RON₃₄= R_ZQ/ 7 (nominal 34.4ohms +/-10% with nominal R_ZQ=240ohms)

The individual pull-up and pull-down resistors (RON_Puand RON_Pd) are defined as follows:

VDDQ – V_Out

under the condition that RONPd is turned off

under the condition that RONPu is turned off

(1)

(2)

RON_Pu=

RON_Pd=

| I_Out

|

V_Out

| I_Out

|

Output Driver: Definition of Voltages and Currents

Version 1.7

04/2015

110

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Output Driver DC Electrical Characteristics, assuming R_ZQ= 240ohms; entire

operating temperature range; after proper ZQ calibration

RON_Nom

Resistor

RON34_Pd

RON34_Pu

RON40_Pd

RON40Pu

Vout

DDR3L

Min. Nom. Max.

Unit

Notes

VOLdc = 0.2 x VDDQ

VOMdc = 0.5 x VDDQ

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

VOMdc = 0.5 x VDDQ

VOHdc = 0.8 x VDDQ

1,2,3

0.6

0.9

0.6

1.0

1.15

1.45

1.15

R_ZQ/ 7

34 ohms

VOLdc = 0.2 × VDDQ

1,2,3

0.6

1.0

1.15

R_ZQ/ 6

VOMdc = 0.5 × VDDQ

VOHdc = 0.8 × VDDQ

VOLdc = 0.2 × VDDQ

VOMdc = 0.5 × VDDQ

VOHdc = 0.8 × VDDQ

1,2,3

0.9

0.6

1.0

1.15

1.45

1.15

R_ZQ/ 6

40 ohms

Mismatch between pull-up and pull-down,

MM_PuPd

VOMdc = 0.5 x VDDQ

1,2,4

-10

+10

%

DDR3

VOLdc = 0.2 x VDDQ

VOMdc = 0.5 x VDDQ

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

VOMdc = 0.5 x VDDQ

1,2,3

0.6

0.9

0.6

0.9

0.6

1.0

1.1

1.4

1.1

1.4

1.1

R_ZQ/ 7

R_ZQ/ 6

RON34_Pd

34 ohms

RON34_Pu

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 × VDDQ

VOMdc = 0.5 × VDDQ

VOHdc = 0.8 × VDDQ

VOLdc = 0.2 × VDDQ

VOMdc = 0.5 × VDDQ

VOHdc = 0.8 × VDDQ

1,2,3

RON40_Pd

40 ohms

RON40_Pu

Mismatch between pull-up and pull-down,

VOMdc = 0.5 x VDDQ

1,2,4

-10

+10

%

MM_PuPd

Version 1.7

04/2015

111

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

NOTE 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance

limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.

NOTE 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.

NOTE 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration

schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ.

NOTE 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd:

Measure RONPu and RONPd, both at 0.5 * VDDQ:

Ron_Pu– Ron_Pd

MM_PuPd

=

X 100

Ron_Nom

Version 1.7

04/2015

112

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Output Driver Temperature and Voltage sensitivity

If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.

Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ

Note: dR_ONdT and dR_ONdV are not subject to production test but are verified by design and characterization.

Output Driver Sensitivity Definition

Items

Min.

Max.

Unit

RONPU@VOHdc

0.6 - dR_ONdTH*lDelta Tl - dR_ONdVH*lDelta Vl

1.1 + dR_ONdTH*lDelta Tl - dR_ONdVH*lDelta Vl

R_ZQ/7

RON@VOMdc

0.9 - dR_ONdTM*lDelta Tl - dR_ONdVM*lDelta Vl

0.6 - dR_ONdTL*lDelta Tl - dR_ONdVL*lDelta Vl

1.1 + dR_ONdTM*lDelta Tl - dR_ONdVM*lDelta Vl

1.1 + dR_ONdTL*lDelta Tl - dR_ONdVL*lDelta Vl

R_ZQ/7

RONPD@VOLdc

Output Driver Voltage and Temperature Sensitivity

Speed Bin

DDR3(L)-800/1066/1333

DDR3(L)-1600

Unit

Items

Min.

Max.

1.5

Min.

Max.

1.5

dRONdTM

dRONdVM

dRONdTL

dRONdVL

dRONdTH

dRONdVH

0

%/C

%/mV

%/C

%/mV

%/C

%/mV

0.15

1.5

0.13

1.5

0.15

1.5

0.13

1.5

0.15

0.13

Note: These parameters may not be subject to production test. They are verified by design and characterization.

Version 1.7

04/2015

113

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

On-Die Termination (ODT) Levels and I-V Characteristics

On-Die Termination effective resistance RTT is defined by bits A9, A6, and A2 of the MR1 Register.

ODT is applied to the DQ, DM, DQS/, and TDQS/T (x8 devices only) pins.

A functional representation of the on-die termination is shown in the following figure. The individual pull-up and pull-down

resistors (RTT_Puand RTT_Pd) are defined as follows:

VDDQ – V_Out

under the condition that RTTPd is turned off

under the condition that RTTPu is turned off

(3)

(4)

RTT_Pu=

RTT_Pd=

| I_Out

|

V_Out

| I_Out

|

On-Die Termination: Definition of Voltages and Currents

Version 1.7

04/2015

114

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ODT DC Electrical Characteristics

The following table provides an overview of the ODT DC electrical characteristics. The values for RTT_60Pd120, RTT_60Pu120

RTT_120Pd240, RTT_120Pu240, RTT_40Pd80, RTT_40Pu80, RTT_30Pd60, RTT_30Pu60, RTT_20Pd40, RTT_20Pu40are not specification

requirements, but can be used as design guide lines:

,

ODT DC Electrical Characteristics, assuming R_ZQ= 240ohms +/- 1% entire operating

temperature range; after proper ZQ calibration(DDR3L)

MR1 A9,A6,A2

RTT

Resistor

Vout

Min.

Nom. Max.

Unit

Notes

DDR3L

VOLdc = 0.2 x VDDQ

0.6

1

1.15

R_ZQ

1,2,3,4

RTT120Pd240

0.5 x VDDQ

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

-5

1

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

1.15

1.45

1.15

1.65

+5

R_ZQ

1,2,3,4

1,2,5

0,1,0

120Ω

R_ZQ

RTT120Pu240

RTT120

R_ZQ

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

R_ZQ

R_ZQ/2

R_ZQ/4

R_ZQ/3

R_ZQ/6

R_ZQ/4

R_ZQ/8

R_ZQ/6

R_ZQ/12

%

1,2,3,4

1,2,5

RTT60Pd120

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

0, 0, 1

0, 1, 1

1, 0, 1

1, 0, 0

60Ω

40Ω

30Ω

20Ω

RTT60Pu120

RTT60

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

1,2,3,4

1,2,5

RTT40Pd80

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

RTT40Pu80

RTT40

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

1,2,3,4

1,2,5

RTT30Pd60

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

RTT30Pu60

RTT30

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

1,2,3,4

1,2,5

RTT20Pd40

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

RTT20Pu40

RTT20

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

Deviation of VM w.r.t. VDDQ/2, DVM

1,2,5,6

Version 1.7

04/2015

115

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ODT DC Electrical Characteristics, assuming R_ZQ= 240ohms +/- 1% entire operating

temperature range; after proper ZQ calibration (DDR3)

MR1 A9,A6,A2 RTT

Resistor

Vout

Min.

Nom. Max.

Unit

Notes

DDR3

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

0.6

0.9

-5

1

1.1

1.4

1,1

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

1.1

1.4

1.1

1.6

+5

R_ZQ

1,2,3,4

1,2,5

RTT120Pd240

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

R_ZQ

0,1,0

0, 0, 1

0, 1, 1

1, 0, 1

1, 0, 0

120Ω

60Ω

40Ω

30Ω

20Ω

R_ZQ

RTT120Pu240

RTT120

R_ZQ

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

R_ZQ

R_ZQ/2

R_ZQ/4

R_ZQ/3

R_ZQ/6

R_ZQ/4

R_ZQ/8

R_ZQ/6

R_ZQ/12

%

1,2,3,4

1,2,5

RTT60Pd120

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

RTT60Pu120

RTT60

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

1,2,3,4

1,2,5

RTT40Pd80

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

RTT40Pu80

RTT40

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

1,2,3,4

1,2,5

RTT30Pd60

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

RTT30Pu60

RTT30

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

1,2,3,4

1,2,5

RTT20Pd40

VOHdc = 0.8 x VDDQ

VOLdc = 0.2 x VDDQ

0.5 x VDDQ

RTT20Pu40

RTT20

VOHdc = 0.8 x VDDQ

VIL(ac) to VIH(ac)

Deviation of VM w.r.t. VDDQ/2, DVM

1,2,5,6

Version 1.7

04/2015

116

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

NOTE 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits

if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.

NOTE 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.

NOTE 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be

used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ.

NOTE 4. Not a specification requirement, but a design guide line.

NOTE 5. Measurement definition for RTT:

Apply VIH(ac) to pin under test and measure current I(VIH(ac)), then apply VIL(ac) to pin under test and measure current

I(VIL(ac)) respectively.

VIH(ac) – VIL(ac)

RTT =

I(VIH(ac)) – I(VIL(ac))

NOTE 6. Measurement definition for VM and DVM:

Measure voltage (VM) at test pin (midpoint) with no load:

2 x VM

△VM = (

– 1) x 100

VDDQ

Version 1.7

04/2015

117

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ODT Temperature and Voltage sensitivity

If temperature and/or voltage after calibration, the tolerance limits widen according to the following table.

Delta T = T - T(@calibration); Delta V = VDDQ - VDDQ(@calibration); VDD = VDDQ

ODT Sensitivity Definition

Min.

Max.

Unit

0.9 – dRTTdT * l△Tl – dRTTdV * l△Vl

1.6 + dRTTdT * l△Tl + dRTTdV * l△Vl

RZQ/2,4,6,8,12

RTT

ODT Voltage and Temperature Sensitivity

Min.

Max.

1.5

Unit

dRTTdT

dRTTdV

0

%/C

%/mV

0.15

Note: These parameters may not be subject to production test. They are verified by design and characterization.

Test Load for ODT Timings

Different than for timing measurements, the reference load for ODT timings is defined in the following figure.

VDDQ

RTT=

25 Ohm

DUT

CK ,



Vtt =

VSSQ

DQ , DM

DQS , 

TDQS , T

Timing Reference Points

VSSQ

ODT Timing Reference Load

Version 1.7

04/2015

118

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

ODT Timing Definitions

Definitions for t_AON, t_AONPD, t_AOF, t_AOFPD, and t_ADCare provided in the following table and subsequent figures.

Symbol

tAON

Begin Point Definition

End Point Definition

Extrapolated point at VSSQ

Rising edge of CK - CK defined by the end point of ODTLon

Rising edge of CK - CK with ODT being first registered high

Rising edge of CK - CK defined by the end point of ODTLoff

Rising edge of CK - CK with ODT being first registered low

Rising edge of CK - CK defined by the end point of ODTLcnw,

ODTLcwn4, or ODTLcwn8

Extrapolated point at VSSQ

tAONPD

tAOF

End point: Extrapolated point at VRTT_Nom

End point: Extrapolated point at VRTT_Wr and

VRTT_Nom respectively

tAOFPD

tADC

Reference Settings for ODT Timing Measurements

DDR3

DDR3L

Parameter

RTT_Nom

RTT_Wr

VSW1[V]

0.05

VSW2[V]

0.10

VSW1[V]

0.05

VSW2[V]

0.10

RZQ/4

RZQ/12

RZQ/4

NA

tAON

0.10

0.20

0.10

0.20

NA

0.05

0.10

0.05

0.10

tAONPD

tAOF

RZQ/12

RZQ/4

NA

0.10

0.20

0.10

0.20

NA

0.05

0.10

0.05

0.10

RZQ/12

RZQ/4

NA

0.10

0.20

0.10

0.20

NA

0.05

0.10

0.05

0.10

tAOFPD

tADC

RZQ/12

NA

0.10

0.20

0.10

0.20

0.30

0.20

0.25

RZQ/2

Definition of t_AON

Begin point: Rising edge of CK – CK#

Defined by the end point of ODTLon

CK

VTT

CK#

tAON

Tsw2

Tsw1

DQ, DM

DQS, DQS#

TDQS, TDQS#

Vsw2

Vsw1

VSSQ

End point: Extrapolated point at VSSQ

Version 1.7

04/2015

119

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Definition of t_AONPD

Begin point: Rising edge of CK – CK#

with ODT being first register high

CK

VTT

CK#

tAONPD

Tsw2

Tsw1

DQ, DM

DQS, DQS#

TDQS, TDQS#

Vsw2

Vsw1

VSSQ

End point: Extrapolated point at VSSQ

Definition of t_AOF

Begin point: Rising edge of CK – CK#

defined by the end point of ODTLoff

CK

VTT

CK#

tAOF

End point: Extrapolated point at VRTT_Nom

VRTT_Nom

Vsw2

Tsw2

Tsw1

DQ, DM

DQS, DQS#

TDQS, TDQS#

Vsw1

VSSQ

Version 1.7

04/2015

120

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Definition of t_AOFPD

Begin point: Rising edge of CK – CK#

with ODT being first registered low

CK

VTT

CK#

tAOFPD

End point: Extrapolated point at VRTT_Nom

VRTT_Nom

Vsw2

Tsw2

Tsw1

DQ, DM

DQS, DQS#

TDQS, TDQS#

Vsw1

VSSQ

Definition of t_ADC

Begin point: Rising edge of CK – CK#

Begin point: Rising edge of CK – CK# defined

defined by the end of ODTLcnw

by the end of ODTLcwn4 or ODTLcwn8

CK

VTT

CK#

tADC

VRTT_Nom

End point: Extrapolated point at VRTT_Nom

VRTT_Nom

Tsw22

Tsw21

DQ, DM

DQS, DQS#

TDQS, TDQS#

Tsw12

Tsw11

VRTT_Wr

End point: Extrapolated point at VRTT_Wr

Vsw2

Vsw1

VSSQ

Version 1.7

04/2015

121

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Input/Output Capacitance

800

1066

1333

1600

1866

2133

Unit

pF

Notes

1,2,3

Parameter

Symbol

Min Max Min Max Min Max Min Max Min Max Min Max

CIO

(DDR3)

CIO

1.4

3.0

2.5

1.4

2.7

2.5

1.4

2.5

2.3

1.4 2.3 1.4 2.2 1.4

2.1

-

Input/output capacitance

(DQ, DM, DQS, ,

TDQS,T)

1.4 2.2 1.4 2.1

-

pF

(DDR3L)

CCK

0.8

0

1.6

0.8

0

1.6

0.8

0

1.4

0.8 1.4 0.8 1.3 0.8

1.3

pF

2,3

Input capacitance, CK and 

Input capacitance delta, CK and 

Input/output capacitance delta

DQS and 

0.15

0

0.15

0

0.15

0

0.15

2,3,4

CDCK

0

0.15

1.4

0

0.15

0

0.15

pF

2,3,5

2,3,6

CDDQS

CI

(DDR3)

CI

0.75

-0.5

0.75 1.35 0.75 1.3 0.75 1.3 0.75 1.2 0.75 1.2

Input capacitance,

(CTRL, ADD,CMD input-only pins)

1.3

0.75

1.3 0.75 1.3 0.75 1.2 0.75 1.2

-

2,3,6

(DDR3L)

Input capacitance delta,

(All CTRL input-only pins

CDI_CTRL

0.3

0.5

-0.5 0.3 -0.4 0.2 -0.4 0.2 -0.4 0.2 -0.4 0.2

-0.5 0.5 -0.4 0.4 -0.4 0.4 -0.4 0.4 -0.4 0.4

-0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3

2,3,7,8

CDI_ADD_

CMD

2,3,9,

10

Input capacitance delta,

(All ADD/CMD input-only pins)

Input/output capacitance delta, DQ,

DM, DQS, , TDQS, T

Input/output capacitance of ZQ pin

-0.5

-

0.3

3

pF

2,3,11

2,3,12

CDIO

CZQ

-

3

-

3

-

3

-

3

-

3

NOTE 1. Although the DM, TDQS and T pins have different functions, the loading matches DQ and DQS

NOTE 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured

according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”)

with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, REET and ODT as necessary).

VDD=VDDQ=1.5V, VBIAS=VDD/2 and ondie termination off.

NOTE 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

NOTE 4. Absolute value of CCK-

NOTE 5. Absolute value of CIO(DQS)-CIO()

NOTE 6. CI applies to ODT, , CKE, A0-A15, BA0-BA2, RA, A, WE.

NOTE 7. CDI_CTRL applies to ODT,  and CKE

NOTE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(L))

NOTE 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RA, A and WE

NOTE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(L))

NOTE 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO())

NOTE 12. Maximum external load capacitance on ZQ pin: 5 pF.

Version 1.7

04/2015

122

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3L IDD Currents

DDR3L-1600

(-DI/DII) (11-11-11)

DDR3L-1866

(13-13-13)

Symbol

Parameter/Condition

Unit

X8

X16

X8

X16

Operating Current 0

IDD0

IDD1

50

60

56

66

84

mA

One Bank Activate-> Precharge

Operating Current 1

56

80

61

One Bank Activate-> Read-> Precharge

Precharge Power-Down Current

IDD2P0

IDD2P1

16

Slow Exit - MR0 bit A12 = 0

Precharge Power-Down Current

24

29

Fast Exit - MR0 bit A12 = 1

IDD2Q

IDD2N

Precharge Quiet Standby Current

Precharge Standby Current

24

27

mA

IDD2NT

Precharge Standby ODT Current

30

34

33

37

Active Power-Down Current

IDD3P

30

33

mA

Always Fast Exit

IDD3N

IDD4R

IDD4W

IDD5B

Active Standby Current

32

40

35

42

mA

Operating Current Burst Read

Operating Current Burst Write

Burst Refresh Current

132

108

210

150

123

230

170

175

185

IDD6TC ¹

Self-Refresh Current:

3.7

20

22

mA

(RS -DIB)

Room Temperature Range

Self-Refresh Current

IDD6 ²

Normal

Self-Refresh Current:

IDD6ET ³

Extended

IDD7

IDD8

All Bank Interleave Read Current

Reset Low Current

170

210

190

240

mA

18

NOTE 1 IDD6TC (RS-DIB):T_C≤ Room Temperature; SRT is disabled, ASR is enabled. Value is maximum.

NOTE 2 IDD6: SRT is ‘Normal’, ASR is disabled. Value is maximum.

- Commercial Grade = 0℃~85℃

- Industrial Grade (-I) = -40℃~85℃

- Automotive Grade 2 (-H) = -40℃~85℃

- Automotive Grade 3 (-A) = -40℃~85℃

NOTE 3 IDD6ET: SRT is ‘Extended’, ASR is disabled. Value is maximum.

- Commercial Grade = 0℃~95℃

- Industrial Grade (-I) = -40℃~95℃

- Automotive Grade 2 (-H) = -40℃~105℃

- Automotive Grade 3 (-A) = -40℃~95℃

Version 1.7

04/2015

123

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

DDR3 IDD Currents

DDR3-1600

(11-11-11)

DDR3-1866

(13-13-13)

DDR3-2133

(14-14-14)

Symbol

Parameter/Condition

Unit

X8

X16

X8

X16

X8

X16

Operating Current 0

IDD0

IDD1

52

63

58

70

67

79

mA

One Bank Activate -> Precharge

Operating Current 1

60

83

64

87

69

92

One Bank Activate-> Read-> Precharge

Precharge Power-Down Current

IDD2P0

IDD2P1

18

27

18

32

18

38

Slow Exit - MR0 bit A12 = 0

Precharge Power-Down Current

Fast Exit - MR0 bit A12 = 1

IDD2Q

IDD2N

Precharge Quiet Standby Current

Precharge Standby Current

27

30

32

mA

IDD2NT

Precharge Standby ODT Current

35

38

41

42

45

Active Power-Down Current

IDD3P

35

38

41

mA

Always Fast Exit

IDD3N

IDD4R

IDD4W

IDD5B

Active Standby Current

35

43

38

45

41

48

mA

Operating Current Burst Read

Operating Current Burst Write

Burst Refresh Current

140

115

220

160

155

130

240

180

173

150

270

190

180

190

22

200

Self-Refresh Current

IDD6 ¹

mA

Normal

Self-Refresh Current

IDD6ET ²

26

20

Extended

IDD7

IDD8

All Bank Interleave Read Current

Reset Low Current

175

220

200

250

235

280

mA

NOTE 1 IDD6: SRT is ‘Normal’, ASR is disabled. Value is maximum.

- Commercial Grade = 0℃~85℃

- Industrial Grade (-I) = -40℃~85℃

- Automotive Grade 2 (-H) = -40℃~85℃

- Automotive Grade 3 (-A) = -40℃~85℃

NOTE 2 IDD6ET: SRT is ‘Extended’, ASR is disabled. Value is maximum.

- Commercial Grade = 0℃~95℃

- Industrial Grade (-I) = -40℃~95℃

- Automotive Grade 2 (-H) = -40℃~105℃

- Automotive Grade 3 (-A) = -40℃~95℃

Version 1.7

04/2015

124

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

IDD Measurement Conditions

Symbol

Parameter/Condition

Operating One Bank Active-Precharge Current

CKE: High; External clock: On;

tCK, nRC, nRAS, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

:High between ACT and PRE;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: MID-LEVEL;

IDD0

DM:stable at 0;

Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Operating One Bank Active-Read-Precharge Current

CKE: High; External clock: On;

tCK, nRC, nRAS, nRCD, CL: see see the table of Timings used for IDD and IDDQ;

BL: 8(1,7); AL:0;

: High between ACT, RD and PRE;

Command, Address, Bank Address Inputs, Data IO: partially toggling;

Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

IDD1

Precharge Standby Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0; : stable at 1;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: MID-LEVEL;

IDD2N

DM:stable at 0;

Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Precharge Power-Down Current Slow Exit

CKE: Low; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

IDD2P(0)

: stable at 1;

Version 1.7

04/2015

125

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Command, Address, Bank Address Inputs: stable at 0;

Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Pecharge Power Down Mode: Slow Exit(3)

Precharge Power-Down Current Fast Exit

CKE: Low; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: stable at 1;

Command, Address, Bank Address Inputs: stable at 0;

IDD2P(1)

Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Pecharge Power Down Mode: Fast Exit(3)

Precharge Quiet Standby Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: stable at 1;

Command, Address, Bank Address Inputs: stable at 0;

Data IO: MID-LEVEL;

IDD2Q

DM:stable at 0;

Bank Activity: all banks closed;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0

Active Standby Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

IDD3N

: stable at 1;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: MID-LEVEL;

DM:stable at 0;

Version 1.7

04/2015

126

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Bank Activity: all banks open;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Active Power-Down Current

CKE: Low; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: stable at 1;

Command, Address, Bank Address Inputs: stable at 0;

Data IO: MID-LEVEL;

IDD3P

DM:stable at 0;

Bank Activity: all banks open;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0

Operating Burst Read Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1,7); AL: 0;

: High between RD;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: seamless read data burst with different data between one burst and the next one;

DM:stable at 0;

IDD4R

Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Operating Burst Write Current

CKE: High; External clock: On;

tCK, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: High between WR;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: seamless write data burst with different data between one burst and the next one ;

DM: stable at 0;

IDD4W

Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,...;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at HIGH;

Version 1.7

04/2015

127

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Burst Refresh Current

CKE: High; External clock: On;

tCK, CL, nRFC: see the table of Timings used for IDD and IDDQ;

BL: 8(1); AL: 0;

: High between REF;

Command, Address, Bank Address Inputs: partially toggling;

Data IO: MID-LEVEL;

IDD5B

DM:stable at 0;

Bank Activity: REF command every nRFC;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

Self Refresh Current: Normal Temperature Range

TCASE: 0 - 85°C;

Auto Self-Refresh (ASR): Disabled(4);

Self-Refresh Temperature Range (SRT):Normal(5);

CKE: Low; External clock: Off;

CK and : LOW; CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1);AL: 0;

IDD6

, Command, Address, Bank Address, Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity:Self-Refresh operation;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: MID-LEVEL

Self-Refresh Current: Extended Temperature Range (optional)(6)

TCASE: 0 - 95°C;

Auto Self-Refresh (ASR): Disabled(4);

Self-Refresh Temperature Range (SRT):Extended(5);

CKE: Low; External clock: Off; CK and : LOW; CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1);AL: 0;

IDD6ET

, Command, Address, Bank Address, Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity:Extended Temperature Self-Refresh operation;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: MID-LEVEL

Auto Self-Refresh Current (optional)(6)

TCASE: 0 - 95°C;

IDD6TC

Auto Self-Refresh (ASR): Enabled(4);

Version 1.7

04/2015

128

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Self-Refresh Temperature Range (SRT):Normal(5);

CKE: Low; External clock: Off; CK and : LOW; CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1);AL: 0;

, Command, Address, Bank Address, Data IO: MID-LEVEL;

DM:stable at 0;

Bank Activity:Auto Self-Refresh operation;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: MIDLEVEL

Operating Bank Interleave Read Current

CKE: High; External clock: On;

tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the table of Timings used for IDD and IDDQ;

BL: 8(1,7); AL: CL-1;

: High between ACT and RDA;

Command, Address, Bank Address Inputs:partially toggling;

Data IO: read data bursts with different data between one burst and the next one;

DM:stable at 0;

IDD7

Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing;

Output Buffer and RTT: Enabled in Mode Registers(2);

ODT Signal: stable at 0;

RESET Low Current

RESET: LOW; External clock: Off;

CK and : LOW; CKE: FLOATING;

IDD8

, Command, Address,Bank Address, Data IO: FLOATING;

ODT Signal: FLOATING

RESET Low current reading is valid once power is stable and RESET has been LOW for at least 1ms.

NOTE 1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

NOTE 2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr

enable: set MR2 A[10,9] = 10B

NOTE 3. Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

NOTE 4. Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

NOTE 5. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

NOTE 6. Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by

DDR3 SDRAM device

NOTE 7. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B

Version 1.7

04/2015

129

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

IDD0 Measurement-Loop Pattern

Version 1.7

04/2015

130

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

IDD1 Measurement-Loop Pattern

Version 1.7

04/2015

131

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

IDD2N and IDD3N Measurement-Loop Pattern

Version 1.7

04/2015

132

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

IDD4R and IDDQ4R Measurement-Loop Pattern

IDD4W Measurement-Loop Pattern

Version 1.7

04/2015

133

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

IDD5B Measurement-Loop Pattern

Version 1.7

04/2015

134

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

IDD7 Measurement-Loop Pattern

Version 1.7

04/2015

135

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Fundamental AC Specifications – Operating Frequency

DDR3-2133

Speed Bins

14-14-14

Unit

Parameter

Min

Max

CWL5

Reserved

ns

nCK

CL5

CWL6/7/8/9/10

CWL5

2.5

3.3

CL6

CWL6

Reserved

CWL7/8/9/10

CWL5

CWL6

1.875

1.5

< 2.5

CL7

CL8

CL9

CWL7

Reserved

CWL8/9/10

CWL5

CWL6

CWL7

Reserved

CWL8/9/10

CWL5/6

CWL7

tCK

(Avg)

< 1.875

CWL8

Reserved

CWL9/10

CWL5/6

CWL7

1.5

CL10

CWL8

Reserved

CWL9

CWL10

CWL5/6/7

CWL8

1.25

< 1.5

CL11

CL12

CWL9

Reserved

CWL10

CWL5/6/7/8

CWL9

CWL10

CWL5/6/7/8

CWL9

tCK

CL13

CL14

1.07

< 1.25

< 1.07

(Avg)

CWL10

CWL5/6/7/8/9

CWL10

Reserved

0.938

Supported CL

5,6,7,8,9,10,11,12,13,14

5,6,7,8,9,10

Supported CWL

Version 1.7

04/2015

136

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Fundamental AC Specifications – Operating Frequency

DDR3-1866 and DDR3L-1866

DDR3(L)-1866

Speed Bins

13-13-13

Unit

Parameter

Min

Max

CWL5

Reserved

ns

nCK

CL5

CWL6/7/8/9

CWL5

2.5

3.3

CL6

CWL6

Reserved

CWL7/8/9

CWL5

CL7

CL8

CWL6

1.875

< 2.5

CWL7/8/9

CWL5

Reserved

CWL6

CWL7

Reserved

CWL8/9

CWL5/6

CWL7

tCK

(Avg)

1.5

< 1.875

CL9

CWL8

Reserved

CWL9

CWL5/6

CWL7

CL10

CL11

1.5

< 1.875

< 1.5

CWL8

Reserved

CWL5/6/7

CWL8

1.25

CWL9

Reserved

CWL5/6/7/8

CWL9

CL12

CL13

CWL5/6/7/8

CWL9

1.07

< 1.25

Supported CL

Supported CWL

6,7,8,9,10,11,13

5, 6, 7, 8, 9

Version 1.7

04/2015

137

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Fundamental AC Specifications – Operating Frequency

DDR3-1600 and DDR3L-1600

DDR3(L)-1600

Speed Bins

Unit

11-11-11

Parameter

CWL5

Min

Max

3.0

3.3

ns

nCK

CL5

CWL6/7/8

CWL5

Reserved

2.5

3.3

CL6

CWL6

Reserved

CWL7/8

CWL5

CWL6

1.875

< 2.5

CL7

CWL7

Reserved

CWL8

CWL5

tCK

CWL6

< 2.5

(Avg)

CL8

CL9

CWL7

Reserved

CWL8

CWL5/6

CWL7

1.5

<1.875

< 1.875

<1.5

CWL8

Reserved

CWL5/6

CWL7

CL10

CL11

CWL8

Reserved

CWL5/6/7

CWL8

1.25

Supported CL

5, 6, 7, 8, 9, 10, 11

5, 6, 7, 8

Supported CWL

Version 1.7

04/2015

138

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Fundamental AC Specifications – Operating Frequency

DDR3-1333 and DDR3L-1333

DDR3(L)-1333

9-9-9

DDR3(L)-1333

10-10-10

Speed Bins

Parameter

Unit

Min

Max

Min

Max

CWL5

3.0

2.5

3.3

3.0

2.5

3.3

ns

CL5

CWL6/7

CWL5

CWL6

CWL7

CWL5

CWL6

CWL7

CWL5

CWL6

CWL7

CWL5/6

CWL7

CWL5/6

CWL7

Reserved

3.3

ns

CL6

Reserved

ns

CL7

CL8

1.875

< 2.5

ns

tCK

Reserved

ns

(Avg)

ns

1.875

< 2.5

ns

Reserved

ns

CL9

1.5

< 1.875

ns

Reserved

ns

CL10

1.5

< 1.875

ns

Supported CL

Supported CWL

5, 6, 7, 8, 9, 10

5, 6, 7

5, 6, 8, 10

5, 6, 7

nCK

Version 1.7

04/2015

139

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Fundamental AC Specifications – Operating Frequency

DDR3-1066 and DDR3L-1066

DDR3(L)-1066

7-7-7

DDR3(L)-1066

8-8-8

Speed Bins

Parameter

Unit

Min

Max

Min

Max

CWL5

3.0

2.5

3.3

3.0

2.5

3.3

ns

CL5

CL6

CL7

CL8

CWL6

CWL5

CWL6

CWL5

CWL6

CWL5

CWL6

Reserved

3.3

ns

Reserved

ns

tCK

(Avg)

ns

1.875

< 2.5

ns

Reserved

ns

1.875

< 2.5

ns

Supported CL

5, 6, 7, 8

5, 6

5, 6, 8

5, 6

nCK

Supported CWL

DDR3-800 and DDR3L-800

DDR3(L)-800

5-5-5

DDR3(L)-800

6-6-6

Speed Bins

Unit

Parameter

CL5

Min

Max

3.3

Min

Max

3.3

CWL5

2.5

3.0

2.5

ns

tCK

(Avg)

CL6

3.3

Supported CL

5, 6

5

5, 6

5

nCK

Supported CWL

Fundamental AC Specifications Notes

NOTE 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of

tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.

NOTE 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all

possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard

tCK(AVG) value (3.0, 2.5, 1.875, 1.5, 1.25, 1.07, or 0.938 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding

up to the next ‘Supported CL’, where tCK(AVG) = 3.0 ns should only be used for CL = 5 calculation.

NOTE 3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next

valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.5 ns or 1.25 ns or 1.07 ns or 0.938 ns). This result is tCK(AVG).MAX

corresponding to CL SELECTED.

NOTE 4. ‘Reserved’ settings are not allowed. User must program a different value.

NOTE 5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to

Version 1.7

04/2015

140

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

supplier’s data sheet and/or the DIMM SPD information if and how this setting is supported.

NOTE 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject

to Production Tests but verified by Design/Characterization.

NOTE 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject

to Production Tests but verified by Design/Characterization.

NOTE 8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject

to Production Tests but verified by Design/Characterization.

NOTE 9. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject

to Production Tests but verified by Design/Characterization.

NOTE 10.Any DDR3-2133 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject

to Production Tests but verified by Design/Characterization.

NOTE 11.For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRPmin must be 13.125 ns. SPD settings must be

programmed to match. For example, DDR3-1333(9-9-9) devices supporting down binning to DDR3-1066(7-7-7) should

program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600(11-11-11)

devices supporting down binning to DDR3-1333(9-9-9) or DDR3-1066(7-7-7) should program 13.125 ns in SPD bytes for

tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte

21,23) also should be programmed accodingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for

DDR3-1333(9-9-9) and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600(11-11-11).

NOTE 12.DDR3 800 AC timing apply if DRAM operates at lower than 800 MT/s data rate.

NOTE 13.For CL5 support, refer to DIMM SPD information. DRAM is required to support CL5. CL5 is not mandatory in SPD coding.

NOTE 14.For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting

must be programed to match. For example, DDR3-1866(13-13-13) devices supporting down binning to DDR3-1600(11-11-11)

or DDR3-1333(9-9-9) or 1066(7-7-7) should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and

tRPmin (byte20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed

accordingly. For example, 47.125ns (tRASmin + tRPmin = 34 ns+ 13.125 ns)

Version 1.7

04/2015

141

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Electrical Characteristics & AC Timing

Timing Parameters for DDR3(L)-800, DDR3(L)-1066, and DDR3(L)-1333

DDR3(L)-800

DDR3(L)-1066 DDR3(L)-1333

Parameter

Symbol

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK (DLL_off)

8

-

8

-

8

-

ns

Average Clock Period

Average high pulse width

Average low pulse width

tCK(avg)

tCH(avg)

tCL(avg)

Refer to “Fundamental AC Specifications”

ps

tCK(avg)

0.47

0.53

0.47

0.53

0.47

0.53

Min.: tCK(avg)min + tJIT(per)min

Max.: tCK(avg)max + tJIT (per)max

Absolute Clock Period

tCK(abs)

ps

Absolute clock HIGH pulse width

Absolute clock LOW pulse width

Clock Period Jitter

tCH(abs)

tCL(abs)

JIT(per)

0.43

-100

-90

-

0.43

-90

-

90

80

0.43

-80

-

80

70

tCK(avg)

ps

100

90

Clock Period Jitter during DLL locking period JIT(per, lck)

-80

-70

ps

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL

locking period

Duty Cycle Jitter

Cumulative error across n = 2, 14 . . . 49, 50

cycles

tJIT(cc)

200

180

160

140

ps

JIT(cc, lck)

tJIT(duty)

tERR(nper)

ps

-

tERR(nper) min = (1 + 0.68ln(n)) * tJIT(per)min

tERR (nper) max = (1 + 0.68ln(n)) * tJIT (per)max

Data Timing

DQS,  to DQ skew, per group, per

access

tDQSQ

-

200

-

150

-

125

ps

DQ output hold time from DQS, 

DQ low-impedance time from CK, 

DQ high impedance time from CK, 

tQH

tLZ(DQ)

tHZ(DQ)

tDS(base)

DDR3-AC175

tDS(base)

0.38

-800

-

0.38

-600

-

0.38

-500

-

tCK(avg)

400

300

250

ps

75

125

90

-

25

75

-

ps

30

-

Data setup time to DQS,  referenced to DDR3-AC150

Vih(ac) / Vil(ac) levels

tDS(base)

DDR3L-AC160

tDS(base)

DDR3L-AC135

tDH(base)

DDR3-DC100

tDH(base)

DDR3L-DC90

40

140

150

90

45

65

Data hold time from DQS,  referenced

to

Vih(dc) / Vil(dc) levels

100

160

600

-

110

490

-

75

-

ps

DQ and DM Input pulse width for each input tDIPW

400

Data Strobe Timing

DQS, differential READ Preamble

DQS,  differential READ Postamble

DQS,  differential output high time

DQS,  differential output low time

DQS,  differential WRITE Preamble

DQS,  differential WRITE Postamble

DQS,  rising edge output access time

from rising CK, 

DQS and  low-impedance time

(Referenced from RL – 1)

DQS and  high-impedance time

(Referenced from RL + BL/2)

tRPRE

tRPST

tQSH

tQSL

tWPRE

tWPST

0.9

0.3

0.38

0.9

Note 19

Note 11

0.9

0.3

0.38

0.9

Note 19

Note 11

0.9

0.3

0.4

0.9

0.3

Note 19 tCK(avg)

Note 11 tCK(avg)

-

tCK(avg)

0.3

tDQSCK

tLZ(DQS)

tHZ(DQS)

-400

-800

-

400

-300

-600

-

300

-255

-500

-

255

250

ps

DQS,  differential input low pulse width tDQSL

DQS,  differential input high pulse width tDQSH

DQS,  rising edge to CK,  rising edge tDQSS

0.45

-0.25

0.55

0.25

0.45

-0.25

0.55

0.25

0.45

-0.25

0.55

0.25

tCK(avg)

DQS,  falling edge setup time to

tDSS

0.2

-

0.2

-

0.2

-

tCK(avg)

CK,  rising edge

DQS,  falling edge hold time from

tDSH

CK,  rising edge

Version 1.7

04/2015

142

Nanya Technology Cooperation ©

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Command and Address Timing

DLL locking time

tDLLK

512

-

512

-

512

-

nCK

Internal READ Command to

PRECHARGE Command delay

tRTPmin.: max(4tCK, 7.5ns)

tRTPmax.: -

tRTP

Delay from start of internal write

transaction to internal read command

WRITE recovery time

tWTRmin.: max(4tCK, 7.5ns)

tWTRmax.: -

tWTR

tWR

tMRD

15

4

-

15

4

-

15

4

-

ns

nCK

Mode Register Set command cycle time

tMODmin.: max(12tCK, 15ns)

tMODmax.:

Mode Register Set command update delay tMOD

ACT to internal read or write delay time

PRE command period

ACT to ACT or REF command period

tRCD

tRP

tRC

Refer to “Fundamental AC Specifications”

ACTIVE to PRECHARGE command period tRAS

A to A command delay

Auto precharge write recovery + precharge

time

tCCD

4

-

4

-

4

1

-

nCK

tDAL(MIN)

tMPRR

WR + roundup(tRP / tCK(avg))

Multi-Purpose Register Recovery Time

1

-

1

-

max(4t

CK,7.5n

s)

max(4tCK,1

0ns)

max(4tCK

,6ns)

ACTIVE to ACTIVE command period (1KB

page size)

tRRD

-

max(4t

CK,10n

max(4tCK,1

0ns)

max(4tCK

,7.5ns)

ACTIVE to ACTIVE command period (2KB

page size)

-

s)

Four activate window (1KB page size)

Four activate window (2KB page size)

tFAW

40

50

-

37.5

50

-

30

45

-

ns

tIS(BASE)

DDR3-AC175

tIS(BASE)

DDR3-AC150

tIS(BASE)

DDR3L-AC160

tIS(BASE)

DDR3L-AC135

tIH(BASE)

200

350

215

365

275

285

900

-

125

275

140

290

200

210

780

-

65

-

ps

190

80

Command and Address setup time to CK,

 referenced to Vih(ac) / Vil(ac) levels

205

140

150

620

Command and Address hold time from CK, DDR3-DC100

 referenced to Vih(dc) / Vil(dc) levels

tIH(BASE)

DDR3L-DC90

Control and Address Input pulse width for

each input

tIPW

Calibration Timing

tZQINITmin: max(512tCK, 640ns)

tZQINITmax: -

tZQOPERmin: max(256tCK, 320ns)

tZQOPERmax: -

tZQCSmin: max(64 tCK, 80ns)

tZQCSmax: -

Power-up and RESET calibration time

tZQINIT

tZQOPER

tZQCS

Normal operation Full calibration time

Normal operation Short calibration time

Reset Timing

Exit Reset from CKE HIGH to a valid

command

tXPRmin.: max(5 tCK, tRFC(min) + 10ns)

tXPRmax.: -

tXPR

Self Refresh Timings

Exit Self Refresh to commands not requiring

a locked DLL

tXSmin.: max(5 tCK, tRFC (min) + 10ns)

tXSmax.: -

tXS

Exit Self Refresh to commands requiring a

locked DLL

tXSDLLmin.: tDLLK(min)

tXSDLLmax.: -

tXSDLL

nCK

Minimum CKE low width for Self Refresh

entry to

exit timing

Valid Clock Requirement after Self Refresh

Entry (SRE) or Power-Down Entry (PDE)

Valid Clock Requirement before Self

Refresh Exit (SRX) or Power-Down Exit

(PDX) or Reset Exit

tCKESRmin.: tCKE(min) + 1 tCK

tCKESRmax.: -

tCKESR

tCKSRE

tCKSREmin.: max(5 tCK, 10 ns)

tCKSREmax.: -

tCKSRXmin.: max(5 tCK, 10 ns)

tCKSRXmax.: -

tCKSRX

Version 1.7

04/2015

143

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Power Down Timings

Exit Power Down with DLL on to any valid

command; Exit Precharge Power Down with

DLL frozen to commands not requiring a

locked DLL

max(3t

CK,7.5n

s)

max(3tCK,7.

5ns)

max(3tCK

,6ns)

tXP

-

max(3t

CK,5.62

5ns)

max(3tCK7.

5ns)

max(3tCK

,5.625ns)

CKE minimum pulse width

tCKE

Exit Precharge Power Down with DLL frozen

to commands requiring a locked DLL

tXPDLLmin.: max(10tCK, 24ns)

tXPDLLmax.: -

tXPDLL

tCPDEDmin.: 1

tCPDEDmin.:

Command pass disable delay

tCPDED

tPD

nCK

-

tPDmin.: tCKE(min)

tPDmax.: 9*tREFI

tACTPDENmin.: 1

tACTPDENmax.: -

tPRPDENmin.: 1

tPRPDENmax.: -

tRDPDENmin.: RL+4+1

tRDPDENmax.: -

Power Down Entry to Exit Timing

Timing of ACT command to Power Down

entry

Timing of PRE or PREA command to Power

Down entry

Timing of RD/RDA command to Power

Down entry

Timing of WR command to Power Down

entry

(BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down

entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down

entry (BC4MRS)

Timing of WRA command to Power Down

entry (BC4MRS)

Timing of REF command to Power Down

entry

nCK

tACTPDEN

tPRPDEN

tRDPDEN

tWRPDENmin.: WL + 4 + (tWR /tCK(avg))

tWRPDENmax.: -

tWRPDEN

tWRAPDENmin.: WL+4+WR+1

tWRAPDENmax.: -

tWRPDENmin.: WL + 2 + (tWR /tCK(avg))

tWRPDENmax.: -

tWRAPDENmin.: WL + 2 +WR + 1

tWRAPDENmax.: -

tREFPDENmin.: 1

tREFPDENmax.: -

tMRSPDENmin.: tMOD(min)

tMRSPDENmax.: -

nCK

tWRAPDEN

tWRPDEN

tWRAPDEN

tREFPDEN

tMRSPDEN

nCK

Timing of MRS command to Power Down

entry

ODT Timings

ODT turn on Latency

ODT turn off Latency

ODTLon

ODTLoff

WL-2=CWL+AL-2

nCK

ODT high time without write command or

with write command and BC4

ODTH4min.: 4

ODTH4max.: -

ODTH4

nCK

ODTH8min.: 6

ODTH8max.: -

ODT high time with Write command and BL8 ODTH8

nCK

ns

Asynchronous RTT turn-on delay

tAONPD

2

8.5

2

8.5

2

8.5

(Power-Down with DLL frozen)

Asynchronous RTT turn-off delay

(Power-Down with DLL frozen)

RTT turn-on

RTT_Nom and RTT_WR turn-off time

from ODTLoff reference

RTT dynamic change skew

tAOFPD

2

8.5

400

0.7

2

8.5

300

0.7

2

8.5

250

0.7

ns

tAON

tAOF

tADC

-400

0.3

-300

0.3

-250

0.3

ps

tCK(avg)

Write Leveling Timings

First DQS/ rising edge after

write leveling mode is programmed

DQS/ delay after write leveling mode is

programmed

Write leveling setup time from rising CK, 

crossing to rising DQS,  crossing

Write leveling hold time from rising DQS,

 crossing to rising CK,  crossing

Write leveling output delay

tWLMRD

tWLDQSEN

tWLS

40

25

-

40

25

-

40

25

-

nCK

ps

325

245

195

tWLH

ps

tWLO

tWLOE

0

9

2

0

9

2

0

9

2

ns

Write leveling output error

Version 1.7

04/2015

144

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Timing Parameters for DDR3(L)-1600, DDR3(L)-1866, and DDR3(L)-2133

DDR3(L)-1600

DDR3(L)-1866

DDR3(L)-2133

Parameter

Symbol

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Clock Timing

Minimum Clock Cycle Time (DLL off mode) tCK (DLL_off)

8

-

8

-

8

-

ns

Average Clock Period

Average high pulse width

Average low pulse width

tCK(avg)

tCH(avg)

tCL(avg)

Refer to “Fundamental AC Specifications”

0.47

0.53

0.47

0.53

0.47

0.53

tCK(avg)

Min.: Tck(avg)min + Tjit(per)min

Max.: Tck(avg)max + Tjit(per)max

Absolute Clock Period

tCK(abs)

Absolute clock HIGH pulse width

Absolute clock LOW pulse width

Clock Period Jitter

tCH(abs)

tCL(abs)

JIT(per)

0.43

-70

-

70

60

0.43

-60

-

60

50

0.43

-50

-

50

40

tCK(avg)

ps

Clock Period Jitter during DLL locking period JIT(per, lck)

-60

-50

-40

ps

Cycle to Cycle Period Jitter

Cycle to Cycle Period Jitter during DLL

locking period

Duty Cycle Jitter

Cumulative error across n = 2, 14 . . . 49, 50

cycles

tJIT(cc)

140

120

100

80

JIT(cc, lck)

tJIT(duty)

tERR(nper)

-

ps

tERR(nper) min = (1 + 0.68ln(n)) * tJIT(per)min

tERR (nper) max = (1 + 0.68ln(n)) * tJIT (per)max

Data Timing

DQS,  to DQ skew, per group, per

access

tDQSQ

-

100

-

85

-

75

ps

DQ output hold time from DQS, 

DQ low-impedance time from CK, 

DQ high impedance time from CK, 

tQH

tLZ(DQ)

tHZ(DQ)

0.38

-450

-

0.38

-390

-

0.38

-360

-

tCK(avg)

225

195

180

ps

tDS(base)

DDR3-1600(AC

175)

DDR3-1866/21

33(AC150)

tDS(base)

DDR3-1600(AC

150)

-

ps

Data setup time to DQS,  referenced to

10

68

53

Vih(ac) / Vil(ac) levels

DDR3-1866/21

33(AC135)

tDS(base)

DDR3L-1600(AC1

35) ,SR=1V/ns

DDR3L-1866(AC1

30),SR=2V/ns

tDH(base)

DC100

25

45

-

70

-

ps

tDH(base)

Data hold time from DQS,  referenced

to

Vih(dc) / Vil(dc) levels

DC90

DDR3L-1600(SR

=1V/ns)

55

-

75

-

ps

DDR3L-1866(SR

=2V/ns)

DQ and DM Input pulse width for each input tDIPW

Data Strobe Timing

360

320

280

DQS, differential READ Preamble

DQS,  differential READ Postamble

DQS,  differential output high time

DQS,  differential output low time

DQS,  differential WRITE Preamble

DQS,  differential WRITE Postamble

DQS,  rising edge output access time

from rising CK, 

tRPRE

tRPST

tQSH

tQSL

tWPRE

tWPST

0.9

0.3

0.4

0.9

0.3

Note 19

Note 11

0.9

0.3

0.4

0.9

0.3

Note 19

Note 11

0.9

0.3

0.4

0.9

0.3

Note 19 tCK(avg)

Note 11 tCK(avg)

-

tCK(avg)

tDQSCK

-225

225

-195

195

-180

180

ps

DQS and  low-impedance time

(Referenced from RL – 1)

DQS and  high-impedance time

tLZ(DQS)

tHZ(DQS)

-450

-

225

-390

-

195

-360

-

180

ps

Version 1.7

04/2015

145

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

(Referenced from RL + BL/2)

DQS,  differential input low pulse width tDQSL

DQS,  differential input high pulse width tDQSH

DQS,  rising edge to CK,  rising edge tDQSS

0.45

-0.27

0.55

0.27

0.45

-0.27

0.55

0.27

0.45

-0.27

0.55

0.27

tCK(avg)

DQS,  falling edge setup time to

CK,  rising edge

DQS,  falling edge hold time from

CK,  rising edge

tDSS

0.18

-

0.18

-

0.18

-

tCK(avg)

tDSH

Command and Address Timing

DLL locking time

tDLLK

tRTP

512

-

512

-

512

-

nCK

Internal READ Command to

PRECHARGE Command delay

tRTPmin.: max(4tCK, 7.5ns)

tRTPmax.: -

Delay from start of internal write

transaction to internal read command

WRITE recovery time

tWTRmin.: max(4tCK, 7.5ns)

tWTRmax.: -

tWTR

tWR

tMRD

15

4

-

15

4

-

15

4

-

ns

Mode Register Set command cycle time

nCK

tMODmin.: max(12tCK, 15ns)

tMODmax.:

Mode Register Set command update delay tMOD

ACT to internal read or write delay time

PRE command period

ACT to ACT or REF command period

tRCD

tRP

tRC

Refer to “Fundamental AC Specifications”

ACTIVE to PRECHARGE command period tRAS

A to A command delay

Auto precharge write recovery + precharge

time

tCCD

4

-

4

-

4

-

nCK

tDAL(MIN)

tMPRR

WR + roundup(tRP / tCK(avg))

Multi-Purpose Register Recovery Time

1

-

1

-

1

-

max(4tCK,

6ns)

max(4tCK

,5ns)

max(4tCK

,5ns)

ACTIVE to ACTIVE command period (1KB

page size)

tRRD

-

max(4tCK,

max(4tCK

ACTIVE to ACTIVE command period (2KB

page size)

-

7.5ns)

30

,6ns)

27

,6ns)

25

Four activate window (1KB page size)

Four activate window (2KB page size)

tFAW

-

ns

40

35

tIS(BASE)

DDR3-1600(AC

175)

DDR3-1866/21

33(AC150)

tIS(BASE)

DDR3-1600(AC

150)

45

-

ps

170

150

135

DDR3-1866/21

33(AC125)

tIS(BASE)

DDR3L

(AC160)

tIS(BASE)

DDR3L

(AC135)

tIS(BASE)

DDR3L

(AC125)

tIH(BASE)

DDR3

Command and Address setup time to CK,

 referenced to Vih(ac) / Vil(ac) levels

60

185

-

ps

65

150

100

-

120

95

DC100

Command and Address hold time from CK,

 referenced to Vih(dc) / Vil(dc) levels

tIH(BASE)

DDR3L

130

560

-

110

535

-

ps

DC90

Control and Address Input pulse width for

each input

tIPW

470

Calibration Timing

tZQINITmin: max(512tCK, 640ns)

tZQINITmax: -

Power-up and RESET calibration time

tZQINIT

tZQOPERmin: max(256tCK, 320ns)

tZQOPERmax: -

Normal operation Full calibration time

tZQOPER

Version 1.7

04/2015

146

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

tZQCSmin: max(64 tCK, 80ns)

tZQCSmax: -

Normal operation Short calibration time

tZQCS

tXPR

Reset Timing

Exit Reset from CKE HIGH to a valid

command

tXPRmin.: max(5 tCK, tRFC(min) + 10ns)

tXPRmax.: -

Self Refresh Timings

Exit Self Refresh to commands not requiring

a locked DLL

tXSmin.: max(5 tCK, tRFC (min) + 10ns)

tXSmax.: -

tXS

Exit Self Refresh to commands requiring a

locked DLL

tXSDLLmin.: tDLLK(min)

tXSDLLmax.: -

tXSDLL

nCK

Minimum CKE low width for Self Refresh

entry to

exit timing

Valid Clock Requirement after Self Refresh

Entry (SRE) or Power-Down Entry (PDE)

tCKESRmin.: tCKE(min) + 1 tCK

tCKESRmax.: -

tCKESR

tCKSRE

tCKSREmin.: max(5 tCK, 10 ns)

tCKSREmax.: -

Valid Clock Requirement before Self

Refresh Exit (SRX) or Power-Down Exit

(PDX) or Reset Exit

tCKSRXmin.: max(5 tCK, 10 ns)

tCKSRXmax.: -

tCKSRX

Power Down Timings

Exit Power Down with DLL on to any valid

command; Exit Precharge Power Down with

DLL frozen to commands not requiring a

locked DLL

max(3tCK,

6ns)

max(3tCK

,6ns)

max(3tCK

,6ns)

tXP

-

max(3tCK

5ns)

max(3tCK

,5ns)

max(3tCK

,5ns)

CKE minimum pulse width

tCKE

Exit Precharge Power Down with DLL frozen

to commands requiring a locked DLL

tXPDLLmin.: max(10tCK, 24ns)

tXPDLLmax.: -

tXPDLL

tCPDEDmin.: 1

tCPDEDmin.:

Command pass disable delay

tCPDED

tPD

nCK

-

tPDmin.: tCKE(min)

tPDmax.: 9*tREFI

tACTPDENmin.: 1

tACTPDENmax.: -

tPRPDENmin.: 1

tPRPDENmax.: -

tRDPDENmin.: RL+4+1

tRDPDENmax.: -

Power Down Entry to Exit Timing

Timing of ACT command to Power Down

entry

Timing of PRE or PREA command to Power

Down entry

Timing of RD/RDA command to Power

Down entry

Timing of WR command to Power Down

entry

(BL8OTF, BL8MRS, BC4OTF)

Timing of WRA command to Power Down

entry (BL8OTF, BL8MRS, BC4OTF)

Timing of WR command to Power Down

entry (BC4MRS)

Timing of WRA command to Power Down

entry (BC4MRS)

Timing of REF command to Power Down

entry

nCK

tACTPDEN

tPRPDEN

tRDPDEN

tWRPDENmin.: WL + 4 + (tWR /tCK(avg))

tWRPDENmax.: -

tWRPDEN

tWRAPDENmin.: WL+4+WR+1

tWRAPDENmax.: -

tWRPDENmin.: WL + 2 + (tWR /tCK(avg))

tWRPDENmax.: -

tWRAPDENmin.: WL + 2 +WR + 1

tWRAPDENmax.: -

tREFPDENmin.: 1

tREFPDENmax.: -

tMRSPDENmin.: tMOD(min)

tMRSPDENmax.: -

nCK

tWRAPDEN

tWRPDEN

tWRAPDEN

tREFPDEN

tMRSPDEN

nCK

Timing of MRS command to Power Down

entry

ODT Timings

ODT turn on Latency

ODT turn off Latency

ODTLon

ODTLoff

WL-2=CWL+AL-2

nCK

ODT high time without write command or

with write command and BC4

ODTH4min.: 4

ODTH4max.: -

ODTH4

nCK

ODTH8min.: 6

ODTH8max.: -

ODT high time with Write command and BL8 ODTH8

nCK

ns

Asynchronous RTT turn-on delay

tAONPD

2

8.5

2

8.5

2

8.5

(Power-Down with DLL frozen)

Asynchronous RTT turn-off delay

(Power-Down with DLL frozen)

RTT turn-on

tAOFPD

2

8.5

2

8.5

2

8.5

ns

ps

tAON

-225

225

-195

195

-180

180

Version 1.7

04/2015

147

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

RTT_Nom and RTT_WR turn-off time

tAOF

0.3

0.7

0.3

0.7

0.3

0.7

tCK(avg)

from ODTLoff reference

RTT dynamic change skew

tADC

Write Leveling Timings

First DQS/ rising edge after

write leveling mode is programmed

DQS/ delay after write leveling mode is

programmed

Write leveling setup time from rising CK, 

crossing to rising DQS,  crossing

Write leveling hold time from rising DQS,

 crossing to rising CK,  crossing

Write leveling output delay

tWLMRD

tWLDQSEN

tWLS

40

25

-

40

25

-

40

25

-

nCK

ps

165

140

125

tWLH

ps

tWLO

tWLOE

0

7.5

2

0

7.5

2

0

7.5

2

ns

Write leveling output error

Jitter Notes

Note 1

Unit “Tck(avg)” represents the actual Tck(avg) of the input clock under operation. Unit “Nck” represents one clock cycle of

the input clock, counting the actual clock edges. Ex) Tmrd=4 [Nck] means; if one Mode Register Set command is regis-

tered at Tm, anther Mode Register Set command may be registered at Tm+4, even if (Tm+4-Tm) is 4 x Tck(avg) +

Terr(4per), min.

Note 2

These parameters are measured from a command/address signal (CKE, , RA, A, WE, ODT, BA0, A0, A1, etc)

transition edge to its respective clock signal (CK/) crossing. The spec values are not affected by the amount of clock

jitter applied (i.e. Tjit(per), Tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the

command/address. That is, these parameters should be met whether clock jitter is present or not.

Note 3

These parameters are measured from a data strobe signal (DQS(L/U), LU)) crossing to its respective clock signal

(CK, ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. Tjit(per), Tjit(cc), etc), as

these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or

not.

Note 4

These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective

data strobe signal (DQS(L/U), LU) crossing.

Note 5

For these parameters, the DDR3(L) SDRAM device supports tnPARAM [Nck] = RU{Tparam[ns] / tCK(avg)[ns]}, which is

in clock cycles, assuming all input clock jitter specifications are satisfied.

Note 6

When the device is operated with input clock jitter, this parameter needs to be derated by the actual Terr(mper), act of

the input clock, where 2 <= m <=12. (Output derating is relative to the SDRAM input clock.)

Note 7

When the device is operated with input clock jitter, this parameter needs to be derated by the actual Tjit(per),act of the

input clock. (Output deratings are relative to the SDRAM input clock.)

Version 1.7

04/2015

148

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Timing Parameter Notes

1. Actual value dependent upon measurement level definitions which are TBD.

2. Commands requiring a locked DLL are: READ ( and RAP) are synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register.

5. Value must be rouned-up to next higher integer value.

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, t_REFi

.

7. For definition of RTT-on time t_AONSee “Timing Parameters”.

8. For definition of RTT-off time t_AOFSee “Timing Parameters”.

9. t_WRis defined in ns, for calculation of t_WRPDENit is necessary to round up t_WR/t_CKto the next integer.

10. WR in clock cycles are programmed in MR0.

11. The maximum read postamble is bounded by t_DQSCK(min) plus t_QSH(min) on the left side and t_HZ(DQS)max on the right side.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this

parameter needs to be derated by TBD.

13. Value is only valid for RON34.

14. Single ended signal parameter.

15. t_REFidepends on T_OPER

.

16. t_IS(base) and t_IH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate. Note for

DQ and DM signals, V_REF(DC)=Vref_DQ(DC). For input only pins except RESET, Vref(DC)=Vref_CA(DC).

17. t_DS(base) and t_DH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for

DQ and DM signals, V_REF(DC)=Vref_DQ(DC). For input only pins except RESET, Vref(DC)=Vref_CA(DC).

18. Start of internal write transaction is defined as follows:

For BL8 (fixed by MRS and on-the-fly): Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL.

For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.

19. The maximum preamble is bound by t_LZ(DQS) max on the left side and t_DQSCK(max) on the right side.

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in

progress, but power-down IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once t_REFPDEN(min) is satisfied, there are cases

where additional time such as t_XPDLL(min) is also required.

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

Version 1.7

04/2015

149

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

23. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64

Nck for all speed bins assuming the maximum sensitivities specified in the “Output Driver Voltage and Temperature Sensitivity”

and “ODT Voltage and Temperature Sensitivity” tables. The appropriate interval between ZQCS commands can be determined

from these tables and other application-specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate)

drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula:

ZQCorrection / [(Tsens x Tdriftrate) + (Vsens x Vdriftrate)] where Tsens = max(dRTTdT, dRONdTM) and Vsens =

max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if Tsens = 1.5%/C, Vsens = 0.15%/Mv, Tdriftrate = 1 C/sec and Vdriftrate = 15Mv/sec, then the interval between

ZQCS commands is calculated as 0.5 / [(1.5x1)+(0.15x15)] = 0.133 ~ 128ms

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. t_CH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. t_CL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The t_IS(base) AC150 specifications are adjusted from the t_IS(base) specification by adding an additional 100ps of derating to

accommodate for the lower altemate threshold of 150Mv and another 25ps to account for the earlier reference point [(175Mv –

150Mv) / 1V/ns].

Version 1.7

04/2015

150

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Address / Command Setup, Hold, and Derating

For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base)

and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.

Example: tIS (total setup time) = tIS(base) + delta tIS

Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the first

crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line

between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal

from the ac level to dc level is used for derating value.

Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the

first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line

between shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the

nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal

from the dc level to Vref(dc) level is used for derating value. For a valid transition the input signal has to remain

above/below VIH/IL(ac) for some time tVAC. Although for slow slew rates the total setup time might be negative (i.e. a valid

input signal will not have reached VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to

complete the transition and reach VIH/IL(ac).

ADD/CMD Setup and Hold Base-Values for 1V/ns

Grade

Symbol

Reference

VIH/L(ac)

VIH/L(dc)

VIH/L(ac)

800

200

350

-

1066

125

275

-

1333

65

1600

45

1866

-

2133

Unit

ps

Notes

tIS(base) AC175

tIS(base) AC150

tIS(base) AC135

tIS(base) AC125

tIH(base) DC100

tIS(base) AC160

tIS(base) AC135

tIS(base) AC125

tIH(base) DC90

-

1

190

-

170

-

60

135

95

-

ps

DDR3

65

ps

1

-

150

100

-

ps

1

275

215

365

-

200

140

290

-

140

80

120

60

ps

1

ps

1

205

-

185

-

65

-

ps

1,2

1,3

1

DDR3L

150

110

-

ps

285

210

150

130

-

ps

NOTE 1 (AC/DC referenced for 1 V/ns Address/Command slew rate and 2 V/ns differential CK- slew rate)

NOTE 2 The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125 ps for

DDR3L-800/1066 or 100 ps for DDR3L-1333/1600 of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to

account for the earlier reference point [(160 mV - 135 mV) / 1 V/ns].

NOTE 3 The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75 ps for DDR3L-1866

of derating to accommodate for the lower alternate threshold of 135 mV and another 10 ps to account for the earlier reference point [(135 mV -

125 mV) / 1 V/ns].

Version 1.7

04/2015

151

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Derating values DDR3L-800/1066/1333/1600 tIS/tIH - AC/DC based AC160 Threshold

DDR3L AC160 Threshold -> VIH(ACAC)=VREF(DC)+160 mV, VIL(AC)=VREF(DC)-160 mV

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

2

80

53

45

30

80

53

45

30

80

53

45

30

88

61

53

38

96

69

61

46

104

77

69

54

112

85

79

64

120

93

95

80

1.5

1

0

8

16

24

32

34

40

50

CMD/ADD

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-1

-3

-1

-3

-1

-3

7

5

15

13

11

8

13

9

23

21

19

16

4

21

17

11

4

31

29

27

24

12

-8

31

27

21

14

4

39

37

35

32

20

0

47

43

37

30

20

5

-8

1

-5

-13

-20

-30

-45

-5

-13

-20

-30

-45

-5

-13

-20

-30

-45

3

-5

3

-8

0

-12

-22

-37

-4

-20

-40

-20

-40

-20

-40

-12

-32

-4

-14

-29

-6

-24

-16

-21

-11

Derating values DDR3L-800/1066/1333/1600 tIS/tIH - AC/DC based AC135 Threshold

DDR3L Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135 mV, VIL(AC)=VREF(DC)-135 mV

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

2

68

45

30

68

45

30

68

45

30

76

53

38

84

61

46

92

69

54

100

77

79

64

108

85

95

80

1.5

1

0

8

16

24

32

34

40

50

CMD/ADD

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

2

3

-3

2

3

-3

2

3

-3

10

11

14

17

13

6

5

18

19

22

25

21

14

13

9

26

27

30

33

29

22

21

17

11

4

34

35

38

41

37

30

31

27

21

14

4

42

43

46

49

45

38

47

43

37

30

20

5

-8

1

6

-13

-20

-30

-45

6

-13

-20

-30

-45

6

-13

-20

-30

-45

-5

3

9

-12

-22

-37

-4

5

-14

-29

-6

-3

-21

-11

Version 1.7

04/2015

152

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Derating values DDR3L-1866 tIS/tIH - AC/DC based AC125 Threshold

DDR3L Alternate AC125 Threshold -> VIH(AC)=VREF(DC)+125 mV, VIL(AC)=VREF(DC)-125 mV

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

2

63

42

45

30

63

42

45

30

63

42

45

30

71

50

53

38

79

58

61

46

87

66

69

54

95

74

79

64

103

82

95

80

1.5

1

0

8

16

24

32

34

40

50

CMD/ADD

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

3

-3

3

-3

3

-3

11

14

18

24

23

21

5

19

22

26

32

31

29

13

9

27

30

34

40

39

37

21

17

11

-4

35

38

42

48

47

45

31

27

21

14

4

43

46

50

56

55

53

47

43

37

30

20

5

6

-8

6

-8

6

-8

1

10

16

15

13

-13

-20

-30

-45

10

16

15

13

-13

-20

-30

-45

10

16

15

13

-13

-20

-30

-45

-5

3

-12

-22

-37

4

-14

-29

-6

-21

-11

Derating values DDR3-800/1066/1333/1600 tIS/tIH - AC/DC based AC175 Threshold

DDR3 AC175 Threshold -> VIH(ac)=VREF(dc)+175mV, VIL(ac)=VREF(dc)-175mV

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

2

88

59

50

34

88

59

50

34

88

59

50

34

96

67

58

42

104

75

66

50

112

83

74

58

120

91

84

68

128

99

100

84

1.5

1

0

8

16

24

32

34

40

50

CMD/ADD

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-2

-4

-2

-4

-2

-4

6

2

4

14

10

5

12

6

22

18

13

7

20

14

8

30

26

21

15

-2

30

24

18

8

38

34

29

23

5

46

40

34

24

10

-10

-6

-10

-16

-26

-40

-60

-6

-10

-16

-26

-40

-60

-6

-10

-16

-26

-40

-60

-2

-11

-17

-35

-62

-11

-17

-35

-62

-11

-17

-35

-62

-3

-8

0

-9

-18

-32

-52

-1

-10

-24

-44

-2

-27

-54

-19

-46

-11

-38

-16

-36

-6

-30

-26

-22

Version 1.7

04/2015

153

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Derating values DDR3-800/1066/1333/1600 tIS/tIH - AC/DC based AC150 Threshold

DDR3 Alternate AC150 Threshold -> VIH(ac)=VREF(dc)+150mV, VIL(ac)=VREF(dc)-150mV

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH

2

75

50

34

75

50

34

75

50

34

83

58

42

91

66

50

99

74

58

107

82

84

68

115

90

100

84

1.5

1

0

8

16

24

32

34

40

50

CMD/ADD

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

0

-4

0

-4

0

-4

8

4

16

15

6

12

6

24

23

14

-1

20

14

8

32

31

22

7

30

24

18

8

40

39

30

15

46

40

34

24

10

-10

-16

-26

-40

-60

-10

-16

-26

-40

-60

-10

-16

-26

-40

-60

-2

0

8

-8

0

-1

7

-18

-32

-52

-10

-24

-44

-2

-10

-25

-10

-25

-10

-25

-2

-17

-16

-36

-6

-9

-26

Derating values DDR3-1866/2133 tIS/tIH - AC/DC based AC135 Threshold

DDR3 Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS

△tIH

2

68

45

50

34

68

45

50

34

68

45

50

34

76

53

58

42

84

61

66

50

92

69

74

58

100

77

84

68

108

85

100

84

1.5

1

0

8

16

24

32

34

40

50

CMD/ADD

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

2

3

-4

2

3

-4

2

3

-4

10

11

14

17

13

6

4

18

19

22

25

21

14

12

6

26

27

30

33

29

22

20

14

8

34

35

38

41

37

30

24

18

8

42

43

46

49

45

38

46

40

34

24

10

-10

-16

-26

-40

-60

-10

-16

-26

-40

-60

-10

-16

-26

-40

-60

-2

6

-8

0

9

-18

-32

-52

-10

-24

-44

-2

5

-16

-36

-6

-3

-26

Version 1.7

04/2015

154

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Derating values DDR3-1866/2133 tIS/tIH - AC/DC based AC125 Threshold

DDR3 Alternate AC125 Threshold -> VIH(ac)=VREF(dc)+125mV, VIL(ac)=VREF(dc)-125mV

CK,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS △tIH △tIS

△tIH

2

63

42

50

34

63

42

50

34

63

42

50

34

71

50

58

42

79

58

66

50

87

66

74

58

95

74

84

68

103

82

100

84

1.5

1

0

8

16

24

32

34

40

50

CMD/ADD

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

4

-4

4

-4

4

-4

12

14

19

24

23

21

4

20

22

27

32

31

29

12

6

28

30

35

40

39

37

20

14

8

36

38

43

48

47

45

30

24

18

8

44

46

51

56

55

53

46

40

34

24

10

-10

6

-10

-16

-26

-40

-60

6

-10

-16

-26

-40

-60

6

-10

-16

-26

-40

-60

-2

11

16

15

13

11

16

15

13

11

16

15

13

-8

0

-18

-32

-52

-10

-24

-44

-2

-16

-36

-6

-26

Version 1.7

04/2015

155

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Required time t_VACabove VIH(AC) {below VIL(AC)} for ADD/CMD transition

Slew

Rate

[V/ns]

> 2.0

2.0

DDR3

800/1066/1333/1600

175mV [ps] 150mV[ps] 135mV [ps] 125mV [ps]

DDR3L

800/1066/1333/1600

1866/2133

1866

Unit

160 mV [ps] 135 mV [ps] 135 mV [ps] 125 mV [ps]

75

57

175

170

167

130

113

93

168

145

100

85

173

152

110

96

200

173

120

102

80

213

190

145

130

111

87

200

178

133

118

99

205

184

143

129

111

89

ps

50

1.5

38

1.0

34

0.9

29

66

79

0.8

22

66

42

56

51

75

0.7

note

30

10

27

13

55

43

59

0.6

note

Note

10

Note

18

0.5

10

18

<0.5

NOTE Rising input signal shall become equal to or greater than VIH(ac) level and falling input signal shall become equal to or less

than VIL(ac) level.

Version 1.7

04/2015

156

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Data Setup, Hold, and Slew Rate De-rating

For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base)

and tDH(base) value to the delta tDS and delta tDH derating value respectively.

Example: tDS (total setup time) = tDS(base) + delta tDS

Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and the

first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the nominal slew rate line

between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the

nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the tangent line to the actual signal

from the ac level to dc level is used for derating value.

Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the

first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last

crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal slew rate line

between shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is earlier than the

nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent line to the actual signal

from the dc level to Vref(dc) level is used for derating value.

For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.

Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac)

at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).

For slew rates in between the values listed in the following tables, the derating values may be obtained by linear

interpolation. These values are typically not subject to production test. They are verified by design and characterization.

Derating values DDR3L-800/1066 tDS/tDH - AC/DC based AC160 Threshold

DDR3L AC160 Threshold -> VIH(AC)=VREF(DC)+160mV, VIL(AC)=VREF(DC)-160mV

DQS,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

2

80

53

45

30

80

53

45

30

80

53

45

30

-

1.5

61

38

1

0

8

16

-

DQ

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-

-1

-

-3

-

-1

-3

-

-3

-8

-

7

5

3

-

5

1

-5

-

15

13

11

8

13

9

23

21

19

16

4

21

17

11

4

-

29

27

24

12

-8

27

21

14

4

-

3

35

32

20

0

37

30

20

5

-

-4

-

-6

-

-11

NOTE1: Cell contents shaded in gray are defined as ‘not supported’.

Version 1.7

04/2015

157

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Derating values DDR3L- 800/1066/1333/1600 tDS/tDH - AC/DC based AC135/ Threshold

DDR3L Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV

DQS,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

2

45

68

30

45

68

30

45

-

1.5

30

53

38

-

1

0

8

16

-

DQ

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-

2

-

-3

-

2

3

-

-3

-8

-

10

11

14

-

5

1

-5

-

18

19

22

25

-

13

9

26

27

30

33

29

-

21

17

11

4

-

35

38

41

37

30

27

21

14

4

-

3

46

49

45

38

37

30

20

5

-

-4

-

-6

-

-11

NOTE1: Cell contents shaded in gray are defined as ‘not supported’.

Derating values DDR3L- 1866 tDS/tDH - AC/DC based AC130 Threshold

DDR3L Alternate AC130 Threshold -> VIH(AC)=VREF(DC)+130mV, VIL(AC)=VREF(DC)-130mV

DQS,  Differential Slew Rate

8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

4

33 23 33 23 33 23

-

3.5 28 19 28 19 28 19 28 19

3

22 15 22 15 22 15 22 15 22 15

-

2.5

-

13

-

9

-

13

0

9

0

13

0

9

0

13

0

9

0

13

9

2

0

-

DQ

Slew

rate

1.5

1

-

-22 -15 -22 -15 -22 -15 -22 -15 -14 -7

-

-65 -45 -65 -45 -65 -45 -57 -37 -49 -29

0.9

0.8

0.7

0.6

0.5

0.4

-

-62 -48 -62 -48 -54 -40 -46 -32 -38 -24

V/ns

-

-61 -53 -53 -45 -45 -37 -37 -29 -29 -19

-

-49 -50 -41 -42 -33 -34 -25 -24 -17 -8

-

-37 -49 -29 -41 -21 -31 -13 -15

-

-31 -51 -23 -41 -15 -25

-28 -56 -20 -40

-

NOTE1: Cell contents shaded in gray are defined as ‘not supported’.

Version 1.7

04/2015

158

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Derating values DDR3- 800/1066 tDS/tDH - AC/DC based AC175 Threshold

DDR3 AC175 Threshold

DQS,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

2

50

59

88

34

50

59

88

34

50

59

-

1.5

34

67

42

-

1

0

8

16

-

DQ

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-

-2

-

-4

-

-2

-6

-

-4

6

2

-3

-

4

-2

-8

-

14

10

5

12

6

22

18

13

7

20

14

8

-

-10

26

21

15

-2

24

18

8

-

0

29

23

5

34

24

10

-10

-

-1

-

-10

-

-2

-16

-

-11

-

-6

-

-30

-26

-22

NOTE1: Cell contents shaded in gray are defined as ‘not supported’.

Derating values DDR3- 800/1066/1333/1600 tDS/tDH - AC/DC based AC150 Threshold

DDR3 AC150 Threshold

DQS,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

2

50

75

34

50

75

34

50

-

1.5

34

58

42

-

1

0

8

16

-

DQ

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-

0

-

-4

-

0

-

-4

8

-

4

-2

-8

-

16

15

-

12

6

24

23

14

-

20

14

8

-

-10

32

31

22

7

24

18

8

-

0

40

39

30

15

34

24

10

-10

-

-10

-

-2

-16

-

-6

-

-26

NOTE1: Cell contents shaded in gray are defined as ‘not supported’.

Version 1.7

04/2015

159

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Derating values DDR3- 1866/2133 tDS/tDH - AC/DC based AC135 Threshold

DDR3

Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV

Alternate DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV

DQS,  Differential Slew Rate

8.0 V/ns 7.0 V/ns 6.0 V/ns 5.0 V/ns

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

34 25 34 25 34 25

-

4

29 21 29 21 29 21 29

23 17 23 17 23 17 23

21

17

10

-

3.5

3

23

14

17

10

-

14 10 14 10 14

14

10

2.5

DQ

Slew

rate

-

0

-

2

-

-23 -17 -23 -17 -23 -17 -23 -17 -15 -9

-

1.5

1

-

-68 -50 -68 -50 -68 -50 -60 -42 -52 -34

-

-66 -54 -66 -54 -58 -46 -50 -38 -42 -30

0.9

0.8

0.7

0.6

0.5

0.4

-

-64 -60 -56 -52 -48 -44 -40 -36 -32 -26

V/ns

-

-53 -59 -45 -51 -37 -43 -29 -33 -21 -17

-

-43 -61 -35 -53 -27 -43 -19 -27

-

-39 -66 -31 -56 -23 -40

-38 -76 -30 -60

-

NOTE1: Cell contents shaded in gray are defined as ‘not supported’.

Derating values DDR3- 800/1066/1333/1600 tDS/tDH - AC/DC based AC135 Threshold

DDR3

Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV

Alternate DC100 Threshold -> VIH(dc)=VREF(dc)+100mV, VIL(dc)=VREF(dc)-100mV

DQS,  Differential Slew Rate

4.0 V/ns

3.0 V/ns

2.0 V/ns

1.8 V/ns

1.6 V/ns

1.4 V/ns

1.2 V/ns

1.0 V/ns

△tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH △tDS △tDH

2

68

45

50

34

68

45

50

34

68

45

50

34

-

1.5

53

42

1

0

8

16

-

DQ

Slew rate

V/ns

0.9

0.8

0.7

0.6

0.5

0.4

-

2

-

-4

-

2

3

-

-4

10

11

14

-

4

-2

-8

-

18

19

22

25

-

12

6

26

27

30

33

29

-

20

14

8

-

-10

35

38

41

37

30

24

18

8

-

0

46

49

45

38

34

24

10

-10

-

-10

-

-2

-16

-

-6

-

-26

NOTE1: Cell contents shaded in gray are defined as ‘not supported’.

Version 1.7

04/2015

160

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Required time t_VACabove VIH(AC) {below VIL(AC)} for DQ transition

DDR3

DDR3L

Slew

Rate

800/1066/

1333/1600

Unit

800/1066

1866

2133

800/1066

1866

1333/1600 1333/1600

[V/ns]

175mV [ps] 150mV[ps] 135mV [ps] 135mV [ps] 135 mV [ps] 160 mV [ps] 135 mV [ps] 130 mV [ps]

75

57

105

80

113

90

93

70

25

Note

-

73

165

138

85

113

90

95

73

30

16

Note

-

ps

> 2.0

2.0

73

50

1.5

38

30

45

5

45

1.0

34

13

30

Note

67

30

0.9

29

Note

11

Note

45

11

0.8

Note

-

16

Note

0.7

-

Note

-

0.6

-

0.5

-

<0.5

NOTE Rising input signal shall become equal to or greater than VIH(ac) level and falling input signal shall become equal to or less than

VIL(ac) level.

Version 1.7

04/2015

161

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

Revision History

Version

1.0

Page

Modified

Description

Released

03/2012

07/2012

10/2012

12/2012

01/2013

02/2013

03/2013

05/2013

-

Preliminary Revision

Official Revision

1.0

-

1.0

-

Add IT grade parts (Industry Temperature) IDDs.

Re-move speed 1066 and 1333 Spec

Voltage SPEC modified

1.0

-

1.0

-

1.0

-

Modified MR2 Function

1.0

-

Add RS (Reduced Standaby) Part Numbers

Modified Part Numbers

1.0

-

1.0

-

Add tRFC SPEC and Automobile Part Numbers

Renew the first page

P1

1. Remove ‘on page xxx’

All

-

2. Follow NTC’s data center to change the Revision Rule

P3

Ordering Information Add Part Number ‘NT5CB256M16CP-DIH’.

Special Type Option

Part Number Naming

P4

1. Add H = Automotive Grade 2

Rule

2. Modify A = Automotive 3 (was: A = Automotive)

Fundamental AC

Specifications

Package Outline

Drawing

1. Make all options follow JEDEC standards.

2. Add 800, 1066 and 1333 specifications.

1. Add side view of package to POD

2. Redraw the ballout

P5-11

P13-14

P24,27,30,32

MR0,1,2,3

Redraw the MR functions

1.1

06/2013

1. Follow JEDEC specifications

Absolute Maximum DC

Ratings

 VDD: -0.4V ~ 1.8V (was: -0.4V ~ 1.975V)

 VDDQ: -0.4V ~ 1.8V (was: -0.4V ~ 1.975V)

 Vin,Vout: -0.4V ~ 1.8V (was: -0.4V ~ 1.975V)

P89

P90

Temperature Spec

All

1. Automatic Grade 3: -40 to 85 (was: -40 to 95)

1. Make all specifications follow JEDEC specifications

2. Add DDR3(L) 800, 1066 and 1333 specifications

P92-123

P124-136

P137-143

IDD specifications

Timing specifications

1. Add IDD test conditions

1. Make all specifications follow JEDEC specifications

2. Add DDR3(L) 800, 1066 and 1333 specifications

1. Make all specifications follow JEDEC specifications

2. Add DDR3(L) 800, 1066 and 1333 specifications

P146-156

Derating table

P14

96 ballout

MR

1. Update POD spec to 12mm (was: 11.2mm caused by typo)

1. Add notes below the MR tables

P24,27,30,32

1. Automotive Grade 3: -40 ~ 95 (was: -40~85)

2. Add Automotive Grade 2 Spec on page 90.

P1,P90

Temperature spec

1.2

06/2013

P147-150,

152-155

tIS/tIH/tDS/tDH Derating

table

1. Add DC conditions

1. Correct the typo in 1^stparagraph: tDS(base) and tDH(base), was: tDH(base) and

tDH(base)

P152

P1

Data Setup,Hold

-

1. Renew.

1. Divide the table. Put Core Timing on page 2 and Operating Frequency on

P130-135

P2.133-138

P4

Fundamental AC Spec.

Ordering Info

1. Package: TFBGA (was: WBGA)

Package Outline

Drawing

1. Ball descriptions (was: Pin descriptions)

2. Add seating plane, wiring bonding molding height and top view

1. Ball descriptions (was: Pin descriptions)

2. Add Note 2 to the table.

P6-7

1.3

08/2013

P8-9

All

Ball descriptions

-

1. Format adjustment

1. in supporting temperature range(was: and does not exceed +95°C)

Extended Temperature

Usage

P44

P62

2. removed: Table 14 summarizes the two extended temperature options and Table

15 summarizes how the two extended temperature options relate to one another.

Self Refresh Operation 1. ZQCALfunction requirements [TBD]

Version 1.7

04/2015

162

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

P117

P1

tAON

-

1. Add tAON diagram.

1. Write Leveling :Add Note 7

2. Density and Addressing: Add tREFI

Add: DQ0 is the prime DQ in a low byte lane of x4/x8/x16 configuration and DQ8 is

the prime DQ in a high byte lane of x16 configuration for write leveling.

Emphasize Write Leveling only supports prime DQ’s feedback.

1. A separated feedback mechanism should be able for each byte lane. The low byte

lane’s prime DQ, DQ0, carries the leveling feedback to the controller across the

DRAM configurations x4/x8 whereas DQ0 indicates the lower diff_DQS

(diff_LDQS) to clock relationship..The high byte lane’s prime DQ, DQ8, provides

the feedback of the upper diff_DQS (diff_UDQS) to clock relationship.

2. Timing details of Write leveling sequence: Add (For Information. Only Support prime

DQ)

P9

DQ Description

Write Leveling

1.4

09/2013

P41-P43

P124

All

IDD specifications

-

Add 2133 IDD specs.

Format adjusted and realigned.

1. Add DDR3L-1866 part number and specifications.

2. Update IDD specification.

1.5

1.6

P2,4,123,124,137

P1,4

DDR3L-1866

12/2013

04/2014

Voltage backward

compatible

1. Temperature Range: Add part number’s code

2. NOTE 4: Enhance the statement of voltage backward compatible.

P19

P45, P123, 124

P5

CAS Latency

Self refresh

Correct the description: bit A2, A4~A6 (was: bit A9~A11)

Emphasize the difference among the grades about Self refresh temperature range

Part Numbering Guide Simplify part numbering guide.

1.7

04/2015

P88

Temperature Range Revise the note description of the table.

Version 1.7

04/2015

163

DDR3(L) 4Gb SDRAM

NT5CB(C)512M8CN / NT5CB(C)256M16CP

http://www.nanya.com/

Version 1.7

04/2015

164


型号：	NT5CC256M16CN-FLH
厂家：	Nanya Technology Corporation.
描述：	Commercial, Industrial and Automotive DDR3(L) 4Gb SDRAM 动态存储器双倍数据速率
文件：	总164页 (文件大小：7336K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

NT5CC256M16CN-FLH [NANYA]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E