MX68GL1G0F [Macronix]
SINGLE VOLTAGE 3V ONLY FLASH MEMORY;
| 型号： | MX68GL1G0F |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | SINGLE VOLTAGE 3V ONLY FLASH MEMORY |
| 文件： | 总71页 (文件大小：1050K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX68GL1G0F
MX68GL1G0F
DATASHEET
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MX68GL1G0F
Contents
1. FEATURES ........................................................................................................................................................ 5
2. PIN CONFIGURATION ...................................................................................................................................... 6
3. PIN DESCRIPTION............................................................................................................................................ 7
4. BLOCK DIAGRAM............................................................................................................................................. 8
5. BLOCK DIAGRAM DESCRIPTION................................................................................................................... 9
6. BLOCK STRUCTURE...................................................................................................................................... 10
Table 1. SECTOR ARCHITECTURE ..................................................................................................10
7. BUS OPERATION.............................................................................................................................................11
Table 2. BUS OPERATION-1.............................................................................................................. 11
Table 3. BUS OPERATION-2..............................................................................................................12
8. FUNCTIONAL OPERATION DESCRIPTION .................................................................................................. 13
8-1. READ OPERATION............................................................................................................................13
8-2. PAGE READ .......................................................................................................................................13
8-3. WRITE OPERATION ..........................................................................................................................13
8-4. WRITE BUFFER PROGRAMMING OPERATION..............................................................................13
8-5. DEVICE RESET..................................................................................................................................14
8-6. STANDBY MODE ...............................................................................................................................14
8-7. OUTPUT DISABLE.............................................................................................................................14
8-8. BYTE/WORD SELECTION.................................................................................................................15
8-9. HARDWARE WRITE PROTECT ........................................................................................................15
8-10. ACCELERATED PROGRAMMING OPERATION ..............................................................................15
8-11. SECTOR PROTECT OPERATION.....................................................................................................15
8-12. AUTOMATIC SELECT BUS OPERATIONS .......................................................................................15
8-13. SECTOR LOCK STATUS VERIFICATION..........................................................................................15
8-14. READ SILICON ID MANUFACTURER CODE....................................................................................16
8-15. READ INDICATOR BIT (Q7) FOR SECURITY SECTOR...................................................................16
8-16. INHERENT DATA PROTECTION.......................................................................................................16
8-17. COMMAND COMPLETION................................................................................................................16
8-18. LOW VCC WRITE INHIBIT.................................................................................................................16
8-19. WRITE PULSE "GLITCH" PROTECTION ..........................................................................................16
8-20. LOGICAL INHIBIT...............................................................................................................................16
8-21. POWER-UP SEQUENCE...................................................................................................................17
8-22. POWER-UP WRITE INHIBIT..............................................................................................................17
8-23. POWER SUPPLY DECOUPLING.......................................................................................................17
9. COMMAND OPERATIONS.............................................................................................................................. 18
9-1. READING THE MEMORY ARRAY .....................................................................................................18
9-2. AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY.............................................................18
9-3. ERASING THE MEMORY ARRAY......................................................................................................19
9-4. SECTOR ERASE................................................................................................................................19
9-5. CHIP ERASE .....................................................................................................................................20
9-6. ERASE SUSPEND/RESUME.............................................................................................................21
9-7. SECTOR ERASE RESUME ...............................................................................................................21
9-8. PROGRAM SUSPEND/RESUME.......................................................................................................22
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9-9. PROGRAM RESUME.........................................................................................................................22
9-10. BUFFER WRITE ABORT....................................................................................................................22
9-11. AUTOMATIC SELECT OPERATIONS................................................................................................23
9-12. AUTOMATIC SELECT COMMAND SEQUENCE...............................................................................23
9-13. READ MANUFACTURER ID OR DEVICE ID.....................................................................................23
9-14. RESET ...............................................................................................................................................24
9-15. Advanced Sector Protection/Un-protection.........................................................................................25
Figure 1. Advance Sector Protection/Unprotection SPB Program Algorithm ......................................25
9-15-1. Lock Register..........................................................................................................................26
Figure 2. Lock Register Program Algorithm ........................................................................................26
9-15-2. Solid Protection Mode ............................................................................................................27
9-15-3. Temporary Un-protect Solid write Protect Bits (USPB)...........................................................28
Figure 3. SPB Program Algorithm.......................................................................................................28
9-15-4. Solid Protection Bit Lock Bit ...................................................................................................29
9-15-5. Password Protection Method..................................................................................................29
Table 4. Sector Protection Status........................................................................................................30
9-16. SECURITY SECTOR FLASH MEMORY REGION.............................................................................31
9-17. FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY.
............................................................................................................................................................31
9-18. CUSTOMER LOCKABLE: SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE ...
FACTORY...........................................................................................................................................31
Table 5. COMMAND DEFINITIONS....................................................................................................32
10. COMMON FLASH MEMORY INTERFACE (CFI) MODE .............................................................................. 35
Table 6. CFI mode: Identification Data Values ....................................................................................35
Table 7. CFI mode: System Interface Data Values .............................................................................35
Table 8. CFI mode: Device Geometry Data Values.............................................................................36
Table 9. CFI mode: Primary Vendor-Specific Extended Query Data Values.......................................37
11. ELECTRICAL CHARACTERISTICS.............................................................................................................. 38
11-1. ABSOLUTE MAXIMUM STRESS RATINGS ......................................................................................38
11-2. OPERATING TEMPERATURE AND VOLTAGE .................................................................................38
Figure 4. Maximum Negative Overshoot Waveform ...........................................................................38
Figure 5. Maximum Positive Overshoot Waveform.............................................................................38
Table 10. DC CHARACTERISTICS ....................................................................................................39
Figure 6. SWITCHING TEST CIRCUITS ............................................................................................40
Figure 7. SWITCHING TEST WAVEFORMS.....................................................................................40
Table 11. AC CHARACTERISTICS.....................................................................................................41
12. WRITE COMMAND OPERATION.................................................................................................................. 43
Figure 8. COMMAND WRITE OPERATION .......................................................................................43
13. READ/RESET OPERATION .......................................................................................................................... 44
Figure 9. READ TIMING WAVEFORMS .............................................................................................44
Table 12. AC CHARACTERISTICS-RESET#......................................................................................45
Figure 10. RESET# TIMING WAVEFORM.........................................................................................45
14. ERASE/PROGRAM OPERATION ................................................................................................................. 46
Figure 11. AUTOMATIC CHIP ERASE TIMING WAVEFORM.............................................................46
Figure 12. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART..................................................47
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Figure 13. AUTOMATIC SECTOR ERASE TIMING WAVEFORM......................................................48
Figure 14. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART ...........................................49
Figure 15. ERASE SUSPEND/RESUME FLOWCHART ....................................................................50
Figure 16. AUTOMATIC PROGRAM TIMING WAVEFORMS.............................................................51
Figure 17. ACCELERATED PROGRAM TIMING DIAGRAM..............................................................51
Figure 18. CE# CONTROLLED WRITE TIMING WAVEFORM ..........................................................52
Figure 19. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART ...........................................53
15. SILICON ID READ OPERATION................................................................................................................... 54
Figure 20. SILICON ID READ TIMING WAVEFORM..........................................................................54
16. WRITE OPERATION STATUS....................................................................................................................... 55
Figure 21. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)..........55
Figure 22. STATUS POLLING FOR PROGRAM/ERASE ...................................................................56
Figure 23. STATUS POLLING FOR WRITE BUFFER PROGRAM.....................................................57
Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)...............58
Figure 25. TOGGLE BIT ALGORITHM ...............................................................................................59
17. PAGE READ OPERATION ............................................................................................................................ 60
Figure 26. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte
mode to word mode) ...........................................................................................................................60
Figure 27. PAGE READ TIMING WAVEFORM...................................................................................61
18. DEEP POWER DOWN MODE OPERATION................................................................................................. 62
Table 13. AC CHARACTERISTICS - Deep Power Down Mode..........................................................62
Figure 28. DEEP POWER DOWN MODE WAVEFORM ....................................................................62
19. WRITE BUFFER PROGRAM OPERATION .................................................................................................. 63
Figure 29. WRITE BUFFER PROGRAM FLOWCHART.....................................................................63
20. RECOMMENDED OPERATING CONDITIONS............................................................................................. 64
Figure 30. AC Timing at Device Power-Up..........................................................................................64
21. ERASE AND PROGRAMMING PERFORMANCE........................................................................................ 65
22. DATA RETENTION ........................................................................................................................................ 65
23. LATCH-UP CHARACTERISTICS.................................................................................................................. 65
24. PIN CAPACITANCE....................................................................................................................................... 65
25. ORDERING INFORMATION.......................................................................................................................... 66
26. PART NAME DESCRIPTION......................................................................................................................... 67
27. PACKAGE INFORMATION............................................................................................................................ 68
28. REVISION HISTORY ..................................................................................................................................... 70
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MX68GL1G0F
SINGLE VOLTAGE 3V ONLY FLASH MEMORY
1. FEATURES
GENERAL FEATURES
• 2.7 to 3.6 volt for read, erase, and program operations
• Byte/Word mode switchable
- 134,217,728 x 8 / 67,108,864 x 16
• 64KW/128KB uniform sector architecture
- 1024 equal sectors
• 16-byte/8-word page read buffer
• 64-byte/32-word write buffer
• Extra 128-word sector for security
- Features factory locked and identifiable, and customer lockable
• Advanced sector protection function (Solid and Password Protect)
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Fast access time:
- MX68GL1G0F H/L: 110ns (VCC=2.7~3.6V)
- MX68GL1G0F U/D: 120ns (VCC=2.7~3.6V, V I/O=1.65 to VCC)
- Page access time:
- MX68GL1G0F H/L: 25ns
- MX68GL1G0F U/D: 30ns
- Fast program time: 10us/word
- Fast erase time: 0.5s/sector
• Low Power Consumption
- Low active read current: 10mA (typical) at 5MHz
- Low standby current: 60uA (typical)
• Minimum 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability
PACKAGE
• 56-Pin TSOP
• 64-Ball LFBGA (11mm x 13mm)
• All devices are RoHS Compliant and Halogen-free
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2. PIN CONFIGURATION
56 TSOP
A24
A23
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A25
A22
A15
A14
A13
A12
A11
2
A16
3
BYTE#
GND
Q15/A-1
Q7
4
5
6
7
Q14
Q6
A10
A9
8
9
Q13
Q5
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
A6
Q0
A5
OE#
GND
CE#
A0
A4
A3
A2
A1
NC
NC
V
I/O
NC
64 LFBGA
A23
A24
A25
NC
A22
GND
NC
8
VIO
A15
A11
Q15/
A-1
A13
A9
A12
A8
A14
A10
A16
Q7
BYTE#
Q14
GND
7
6
Q13
VCC
Q11
Q9
Q6
RES-
ET#
5
WE#
A21
A18
A6
A19
A20
A5
Q5
Q2
Q0
Q12
Q10
Q8
Q4
Q3
Q1
RY/
BY#
WP#/
ACC
4
3
A17
A7
A3
NC
A4
A2
A1
A0
CE#
VIO
OE#
NC
GND
2
1
NC
NC
NC
NC
NC
A
B
C
D
E
F
G
H
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MX68GL1G0F
LOGIC SYMBOL
3. PIN DESCRIPTION
SYMBOL PIN NAME
26
A0~A25 Address Input
16 or 8
A0-A25
Q0-Q15
(A-1)
Q0~Q14 Data Inputs/Outputs
Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode)
CE#
WE#
OE#
Chip Enable Input
Write Enable Input
Output Enable Input
CE#
RESET# Hardware Reset Pin, Active Low
OE#
Hardware Write Protect/Programming
Acceleration input
WP#/ACC*
WE#
RY/BY# Ready/Busy Output
RESET#
WP#/ACC
BYTE#
VI/O
RY/BY#
BYTE# Selects 8 bits or 16 bits mode
VCC
GND
NC
+3.0V single power supply
Device Ground
Not Connected
VI/O
Power Supply for Input/Output
Notes:
1. WP#/ACC has internal pull up.
2. VI/O voltage must tight with VCC for MX68GL1G0F H/L.
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4. BLOCK DIAGRAM
CE#
OE#
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
WE#
RESET#
BYTE#
WP#/ACC
MACHINE
(WSM)
LOGIC
STATE
FLASH
ARRAY
ADDRESS
LATCH
REGISTER
ARRAY
A0-AM
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
AM: MSB address
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5. BLOCK DIAGRAM DESCRIPTION
The "BLOCK DIAGRAM" illustrates a simplified architecture of this device. Each block in the block diagram rep-
resents one or more circuit modules in the real chip used to access, erase, program, and read the memory array.
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC.
It creates internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND
BUFFER" to latch the external address pins A0-AM. The internal addresses are output from this block to the
main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH ARRAY".
The X-DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the
flash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively
through the Y-PASS GATES. SENSE AMPLIFIERS are used to read out the contents of the flash memory, while
the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O
BUFFER" controls the input and output on the Q0-Q15/A-1 pads. During read operation, the I/O BUFFER re-
ceives data from SENSE AMPLIFIERS and drives the output pads accordingly. In the last cycle of program com-
mand, the I/O BUFFER transmits the data on Q0-Q15/A-1 to "PROGRAM DATA LATCH", which controls the high
power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user input
pattern.
The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary
high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module com-
prises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and
"COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-Q15/A-1
is latched in the COMMAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE
REGISTER receives the command and records the current state of the device. The WSM implements the in-
ternal algorithms for program or erase according to the current command state by controlling each block in the
block diagram.
ARRAY ARCHITECTURE
The main flash memory array can be organized as Byte mode (x8) or Word mode (x16). The details of the ad-
dress ranges and the corresponding sector addresses are shown in Table 1 .
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6. BLOCK STRUCTURE
Table 1. SECTOR ARCHITECTURE
Sector Size
Sector Address
A25-A16
Address Range
(x16)
Sector
Kbytes
128
Kwords
64
SA0
SA1
SA2
0000000000xxxx
0000000001xxxx
0000000010xxxx
0000000h-000FFFFh
0010000h-001FFFFh
0020000h-002FFFFh
128
64
128
64
:
:
:
:
:
:
:
:
:
:
128
64
SA1023
1111111111xxxx
3FF0000h-3FFFFFFh
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7. BUS OPERATION
Table 2. BUS OPERATION-1
Byte#
Data
RE-
Mode Select
SET#
Address
(Note4)
Vil
Vih
WP#/
ACC
CE# WE# OE#
I/O
Data (I/O)
Q15~Q8
Q7~Q0
Device Reset
Standby Mode
L
X
X
X
X
X
X
X
HighZ
HighZ
HighZ
HighZ
L/H
H
Vcc ± Vcc±
0.3V
HighZ
HighZ
HighZ
0.3V
Output Disable
Read Mode
H
L
H
H
L
H
L
X
HighZ
DOUT
DIN
HighZ
DOUT
DIN
L/H
L/H
H
H
H
L
L
L
AIN
AIN
AIN
Q8-Q14=
HighZ,
Q15=A-1
Write
H
H
Note1,2
Vhv
Accelerate Program
L
DIN
DIN
Notes:
1. The first or last sector was protected if WP#/ACC=Vil.
2. When WP#/ACC = Vih, the protection conditions of the outmost sector depends on previous protection condi-
tions. Refer to the advanced protect feature.
3. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector pro-
tection, or data polling algorithm.
4. In Word Mode (Byte#=Vih), the addresses are AM to A0, AM: MSB of address.
In Byte Mode (Byte#=Vil), the addresses are AM to A-1 (Q15), AM: MSB of address.
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Table 3. BUS OPERATION-2
Control Input
CE# WE# OE#
AM A11
to
A12 A10
A8
A5 A3
Item
to A9 to A6 to
to A1 A0 Q7 ~ Q0 Q15 ~ Q8
A4 A2
A7
01h or
00h
(Note 1)
Sector Lock Status
Verification
L
L
H
H
L
L
SA
X
X
X
Vhv
Vhv
X
L
L
X
X
L
L
H
L
L
L
X
X
Read Silicon ID
Manufacturer
Code
X
C2H
Read Silicon ID
Cycle 1
22H(Word),
XXH(Byte)
22H(Word),
XXH(Byte)
L
L
L
H
H
H
L
L
L
X
X
X
X
X
X
Vhv
Vhv
Vhv
X
X
X
L
L
L
X
X
X
L
H
H
L
H
H
H
L
7EH
28H
01H
Cycle 2
22H(Word),
XXH(Byte)
Cycle 3
H
Notes:
1. Sector unprotected code:00h. Sector protected code:01h.
2. Factory locked code:
WP# protects high address sector: 99h.
WP# protects low address sector: 89h
Factory unlocked code: WP# protects high address sector: 19h.
WP# protects low address sector: 09h
3. AM: MSB of address.
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8. FUNCTIONAL OPERATION DESCRIPTION
8-1. READ OPERATION
To perform a read operation, the system addresses the desired memory array or status register location by pro-
viding its address on the address pins and simultaneously enabling the chip by driving CE# & OE# LOW, and
WE# HIGH. After the Tce and Toe timing requirements have been met, the system can read the contents of the
addressed location by reading the Data (I/O) pins. If either the CE# or OE# is held HIGH, the outputs will remain
tri-stated and no data will appear on the output pins.
8-2. PAGE READ
This device offered high performance page read. Page size is 16 bytes or 8 words. The higher address Amax ~
A3 select the certain page, while A2~A0 for word mode, A2~A-1 for byte mode select the particular word or byte
in a page. The page access time is Taa or Tce, following by Tpa for the rest of the page read time. When CE#
toggles, access time is Taa or Tce. Page mode can be turned on by keeping "page-read address" constant and
changing the "intra-read page" addresses.
8-3. WRITE OPERATION
To perform a write operation, the system provides the desired address on the address pins, enables the chip by
asserting CE# LOW, and disables the Data (I/O) pins by holding OE# HIGH. The system then places data to be
written on the Data (I/O) pins and pulses WE# LOW. The device captures the address information on the falling
edge of WE# and the data on the rising edge of WE#. To see an example, please refer to the timing diagram in
"Figure 8. COMMAND WRITE OPERATION". The system is not allowed to write invalid commands (commands
not defined in this datasheet) to the device. Writing an invalid command may put the device in an undefined
state.
8-4. WRITE BUFFER PROGRAMMING OPERATION
Programs 64bytes/32words in a programming operation. To trigger the Write Buffer Programming, start by the
first two unlock cycles, then third cycle writes the Write Buffer Load command at the destined programming Sec-
tor Address. The forth cycle writes the "word locations subtract one" number.
Following above operations, system starts to write the mingling of address and data. After the programming of
the first address or data, the "write-buffer-page" is selected. The following data should be within the above men-
tioned page.
The "write-buffer-page" is selected by choosing address Amax-A5.
"Write-Buffer-Page" address has to be the same for all address/ data write into the write buffer. If not, operation
will ABORT.
To program the content of the write buffer page this command must be followed by a write to buffer Program con-
firm command.
The operation of write-buffer can be suspended or resumed by the standard commands, once the write buffer
programming operation is finished, it’ll return to normal READ mode.
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FUNCTIONAL OPERATION DESCRIPTION (cont'd)
WRITE BUFFER PROGRAMMING OPERATION (cont'd)
ABORT will be executed for the Write Buffer Programming Sequence if following condition occurs:
•
•
•
The value loaded is bigger than the page buffer size during "Number of Locations to Program"
Address written in a sector is not the same as the one assigned during the Write-Buffer-Load command.
Address/ Data pair written to a different write-buffer-page than the one assigned by the "Starting Address"
during the "write buffer data loading" operation.
•
Writing not "Confirm Command" after the assigned number of "data load" cycles.
At Write Buffer Abort mode, the status register will be Q1=1, Q7=DATA# (last address written), Q6=toggle.
A Write-to-Buffer-Abort Reset command sequence has to be written to reset the device for the next operation.
Write buffer programming can be conducted in any sequence. However the CFI functions, autoselect, Secured
Silicon sector are not functional when program operation is in progress. Multiple write buffer programming opera-
tions on the same write buffer address range without intervening erases is available. Any bit in a write buffer ad-
dress range can’t be programmed from 0 back to 1.
8-5. DEVICE RESET
Driving the RESET# pin LOW for a period of Trp or more will return the device to Read mode. If the device is in
the middle of a program or erase operation, the reset operation will take at most a period of Tready1 before the
device returns to Read mode. Until the device does returns to Read mode, the RY/BY# pin will remain Low (Busy
Status).
When the RESET# pin is held at GND±0.3V, the device only consumes standby (Isbr) current. However, the de-
vice draws larger current if the RESET# pin is held at a voltage greater than GND+0.3V and less than or equal to
Vil.
It is recommended to tie the system reset signal to the RESET# pin of the flash memory. This allows the device
to be reset with the system and puts it in a state where the system can immediately begin reading boot code
from it.
8-6. STANDBY MODE
The device enters Standby mode whenever the RESET# and CE# pins are both held High except in the embed-
ded mode. While in this mode, WE# and OE# will be ignored, all Data Output pins will be in a high impedance
state, and the device will draw minimal (Isb) current.
8-7. OUTPUT DISABLE
While in active mode (RESET# HIGH and CE# LOW), the OE# pin controls the state of the output pins. If OE# is
held HIGH, all Data (I/O) pins will remain tri-stated. If held LOW, the Byte or Word Data (I/O) pins will drive data.
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FUNCTIONAL OPERATION DESCRIPTION (cont'd)
8-8. BYTE/WORD SELECTION
The BYTE# input pin is used to select the organization of the array data and how the data is input/output on the
Data (I/O) pins. If the BYTE# pin is held HIGH, Word mode will be selected and all 16 data lines (Q0 to Q15) will
be active.
If BYTE# is forced LOW, Byte mode will be active and only data lines Q0 to Q7 will be active. Data lines Q8 to
Q14 will remain in a high impedance state and Q15 becomes the A-1 address input pin.
8-9. HARDWARE WRITE PROTECT
By driving the WP#/ACC pin LOW. The highest or lowest was protected from all erase/program operations. If
WP#/ACC is held HIGH (Vih to VCC), these sectors revert to their previously protected/unprotected status.
8-10. ACCELERATED PROGRAMMING OPERATION
By applying high voltage (Vhv) to the WP#/ACC pin, the device will enter the Accelerated Programming mode.
This mode permits the system to skip the normal command unlock sequences and program byte/word locations
directly. During accelerated programming, the current drawn from the WP#/ACC pin is no more than ICP1.
8-11. SECTOR PROTECT OPERATION
The device provides user programmable protection operations for selected sectors. Please refer to Table 1 which
show all Sector assignments.
During the protection operation, the sector address of any sector may be used to specify the Sector being pro-
tected.
8-12. AUTOMATIC SELECT BUS OPERATIONS
The following five bus operations require A9 to be raised to Vhv. Please see AUTOMATIC SELECT COMMAND
SEQUENCE in the COMMAND OPERATIONS section for details of equivalent command operations that do not
require the use of Vhv.
8-13. SECTOR LOCK STATUS VERIFICATION
To determine the protected state of any sector using bus operations, the system performs a READ OPERATION
with A9 raised to Vhv, the sector address applied to address pins A25 to A16, address pins A6, A3, A2 & A0 held
LOW, and address pin A1 held HIGH. If data bit Q0 is LOW, the sector is not protected, and if Q0 is HIGH, the
sector is protected.
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FUNCTIONAL OPERATION DESCRIPTION (cont'd)
8-14. READ SILICON ID MANUFACTURER CODE
To determine the Silicon ID Manufacturer Code, the system performs a READ OPERATION with A9 raised to
Vhv and address pins A6, A3, A2, A1, & A0 held LOW. The Macronix ID code of C2h should be present on data
bits Q7 to Q0.
8-15. READ INDICATOR BIT (Q7) FOR SECURITY SECTOR
To determine if the Security Sector has been locked at the factory, the system performs a READ OPERATION
with A9 raised to Vhv, address pin A6, A3 & A2 held LOW, and address pins A1 & A0 held HIGH. If the Security
Sector has been locked at the factory, the code 99h(H)/89h(L) will be present on data bits Q7 to Q0. Otherwise,
the factory unlocked code of 19h(H)/09h(L) will be present.
8-16. INHERENT DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to Read mode during
power up. Additionally, the following design features protect the device from unintended data corruption.
8-17. COMMAND COMPLETION
Only after the successful completion of the specified command sets will the device begin its erase or program
operation. The failure in observing valid command sets will result in the memory returning to read mode.
8-18. LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from
spuriously being altered during power-up, power-down, or temporary power interruptions. The device
automatically resets itself when Vcc is lower than VLKO and write cycles are ignored until Vcc is greater than
VLKO. The system must provide proper signals on control pins after Vcc rises above VLKO to avoid unintentional
program or erase operations.
8-19. WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
8-20. LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at
Vih, WE# at Vih, or OE# at Vil.
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FUNCTIONAL OPERATION DESCRIPTION (cont'd)
8-21. POWER-UP SEQUENCE
Upon power up, the device is placed in Read mode. Furthermore, program or erase operation will begin only
after successful completion of specified command sequences.
8-22. POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on
the rising edge of WE#.
8-23. POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
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9. COMMAND OPERATIONS
9-1. READING THE MEMORY ARRAY
Read mode is the default state after power up or after a reset operation. To perform a read operation, please re-
fer to READ OPERATION in the BUS OPERATIONS section above at Table 2 and Table 3.
If the device receives an Erase Suspend command while in the Sector Erase state, the erase operation will
pause (after a time delay not exceeding 20us) and the device will enter Erase-Suspended Read mode. While in
the Erase-Suspended Read mode, data can be programmed or read from any sector not being erased. Reading
from addresses within sector (s) being erased will only return the contents of the status register, which is in fact
how the current status of the device can be determined.
If a program command is issued to any inactive (not currently being erased) sector during Erase-Suspended
Read mode, the device will perform the program operation and automatically return to Erase-Suspended Read
mode after the program operation completes successfully.
While in Erase-Suspended Read mode, an Erase Resume command must be issued by the system to reactivate
the erase operation. The erase operation will resume from where is was suspended and will continue until it
completes successfully or another Erase Suspend command is received.
After the memory device completes an embedded operation (automatic Chip Erase, Sector Erase, or Program)
successfully, it will automatically return to Read mode and data can be read from any address in the array. If the
embedded operation fails to complete, as indicated by status register bit Q5 (exceeds time limit flag) going HIGH
during the operations, the system must perform a reset operation to return the device to Read mode.
There are several states that require a reset operation to return to Read mode:
1. A program or erase failure--indicated by status register bit Q5 going HIGH during the operation. Failures dur-
ing either of these states will prevent the device from automatically returning to Read mode.
2. The device is in Auto Select mode or CFI mode. These two states remain active until they are terminated by a
reset operation.
In the two situations above, if a reset operation (either hardware reset or software reset command) is not per-
formed, the device will not return to Read mode and the system will not be able to read array data.
9-2. AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY
The device provides the user the ability to program the memory array in Byte mode or Word mode. As long as
the users enters the correct cycle defined in the Table 5 (including 2 unlock cycles and the A0H program com-
mand), any byte or word data provided on the data lines by the system will automatically be programmed into the
array at the specified location.
After the program command sequence has been executed, the internal write state machine (WSM) automatically
executes the algorithms and timings necessary for programming and verification, which includes generating suit-
able program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do
not pass verification or have low margins. The internal controller protects cells that do pass verification and mar-
gin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells
continue to be programmed.
With the internal WSM automatically controlling the programming process, the user only needs to enter the pro-
gram command and data once.
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COMMAND OPERATIONS (cont'd)
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY (cont'd)
Programming will only change the bit status from "1" to "0". It is not possible to change the bit status from "0" to
"1" by programming. This can only be done by an erase operation. Furthermore, the internal write verification
only checks and detects errors in cases where a "1" is not successfully programmed to "0".
Any commands written to the device during programming will be ignored except hardware reset or program sus-
pend. Hardware reset will terminate the program operation after a period of time no more than 10us. When the
embedded program algorithm is complete or the program operation is terminated by a hardware reset, the de-
vice will return to Read mode. Program suspend ready, the device will enter program suspend read mode.
After the embedded program operation has begun, the user can check for completion by reading the following
bits in the status register:
Status
Q7*1
Q7#
Q7#
Q6*1
Q5
0
Q1
0
RY/BY# (Note)
In progress
Toggling
Toggling
0
0
Exceed time limit
1
N/A
Note: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
9-3. ERASING THE MEMORY ARRAY
There are two types of erase operations performed on the memory array -- Sector Erase and Chip Erase. In
the Sector Erase operation, one or more selected sectors may be erased simultaneously. In the Chip Erase
operation, the complete memory array is erased except for any protected sectors. More details of the protected
sectors are explained in section 5.
9-4. SECTOR ERASE
The sector erase operation is used to clear data within a sector by returning all of its memory locations to the
"1" state. It requires six command cycles to initiate the erase operation. The first two cycles are "unlock cycles",
the third is a configuration cycle, the fourth and fifth are also "unlock cycles", and the sixth cycle is the Sector
Erase command. After the sector erase command sequence has been issued, an internal 50us time-out counter
is started. Until this counter reaches zero, additional sector addresses and Sector Erase commands may be
issued thus allowing multiple sectors to be selected and erased simultaneously. After the 50us time-out counter
has expired, no new commands will be accepted and the embedded sector erase operation will begin. Note that
the 50us timer-out counter is restarted after every erase command sequence. If the user enters any command
other than Sector Erase or Erase Suspend during the time-out period, the erase operation will abort and the
device will return to Read mode.
After the embedded sector erase operation begins, all commands except Erase Suspend will be ignored. The
only way to interrupt the operation is with an Erase Suspend command or with a hardware reset. The hardware
reset will completely abort the operation and return the device to Read mode.
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COMMAND OPERATIONS (cont'd)
SECTOR ERASE (cont'd)
The system can determine the status of the embedded sector erase operation by the following methods:
Status
Q7
0
Q6
Q5
0
Q3*1
0
Q2
RY/BY#*2
Time-out period
In progress
Toggling
Toggling
Toggling
Toggling
Toggling
Toggling
0
0
0
0
0
1
Exceeded time limit
0
1
1
Note:
1. The Q3 status bit is the 50us time-out indicator. When Q3=0, the 50us time-out counter has not yet reached
zero and a new Sector Erase command may be issued to specify the address of another sector to be erased.
When Q3=1, the 50us time-out counter has expired and the Sector Erase operation has already begun. Erase
Suspend is the only valid command that may be issued once the embedded erase operation is underway.
2. RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor.
3. When an attempt is made to erase only protected sector (s), the erase operation will abort thus preventing any
data changes in the protected sector (s). Q7 will output "0" and Q6 will toggle briefly (100us or less) before
aborting and returning the device to Read mode. If unprotected sectors are also specified, however, they will
be erased normally and the protected sector (s) will remain unchanged.
4. Q2 is a localized indicator showing a specified sector is undergoing erase operation or not. Q2 toggles when
user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase
suspend mode).
9-5. CHIP ERASE
The Chip Erase operation is used erase all the data within the memory array. All memory cells containing a "0"
will be returned to the erased state of "1". This operation requires 6 write cycles to initiate the action. The first
two cycles are "unlock" cycles, the third is a configuration cycle, the fourth and fifth are also "unlock" cycles, and
the sixth cycle initiates the chip erase operation.
During the chip erase operation, no other software commands will be accepted, but if a hardware reset is re-
ceived or the working voltage is too low, that chip erase will be terminated. After Chip Erase, the chip will auto-
matically return to Read mode.
The system can determine the status of the embedded chip erase operation by the following methods:
Status
Q7
0
Q6
Q5
0
Q2
RY/BY#*1
In progress
Toggling
Toggling
Toggling
Toggling
0
0
Exceed time limit
0
1
*1: RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor.
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COMMAND OPERATIONS (cont'd)
9-6. ERASE SUSPEND/RESUME
After beginning a sector erase operation, Erase Suspend is the only valid command that may be issued. If sys-
tem issues an Erase Suspend command during the 50us time-out period following a Sector Erase command, the
time-out period will terminate immediately and the device will enter Erase-Suspended Read mode. If the system
issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter
Erase-Suspended Read mode until 20us time has elapsed. The system can determine if the device has entered
the Erase-Suspended Read mode through Q6, Q7, and RY/BY#.
After the device has entered Erase-Suspended Read mode, the system can read or program any sector (s) ex-
cept those being erased by the suspended erase operation. Reading any sector being erased or programmed
will return the contents of the status register. Whenever a suspend command is issued, user must issue a re-
sume command and check Q6 toggle bit status, before issue another erase command. The system can use the
status register bits shown in the following table to determine the current state of the device:
Status
Q7
1
Q6
No toggle
Data
Q5
Q3
Q2
Q1 RY/BY#
Erase suspend read in erase suspended sector
Erase suspend read in non-erase suspended sector
Erase suspend program in non-erase suspended sector
0
N/A toggle N/A
1
1
0
Data
Q7#
Data Data Data Data
N/A N/A N/A
Toggle
0
When the device has suspended erasing, user can execute the command sets, such as read silicon ID, sector
protect verify, program, CFI query and erase resume.
After the device has entered Erase-Suspended Read Mode, Sector Erase, Chip Erase and Program Suspend
commands are forbidden.
9-7. SECTOR ERASE RESUME
The sector Erase Resume command is valid only when the device is in Erase-Suspended Read mode. After
erase resumes, the user can issue another Ease Suspend command, but there should be a 400us interval be-
tween Ease Resume and the next Erase Suspend command.
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COMMAND OPERATIONS (cont'd)
9-8. PROGRAM SUSPEND/RESUME
After beginning a program operation, Program Suspend is the only valid command that may be issued. The sys-
tem can determine if the device has entered the Program-Suspended Read mode through Q6 and RY/BY#.
After the device has entered Program-Suspended mode, the system can read any sector (s) except those be-
ing programmed by the suspended program operation. Reading the sector being program suspended is invalid.
Whenever a suspend command is issued, user must issue a resume command and check Q6 toggle bit status,
before issue another program command. The system can use the status register bits shown in the following table
to determine the current state of the device:
Status
Q7
Q6
Q5
Q3
Q2
Q1 RY/BY#
Program suspend read in program suspended sector
Invalid
1
Program suspend read in non-program suspended
sector
Data Data Data Data Data Data
1
When the device has Program suspended, user can execute read array, auto-select, read CFI, read security sili-
con. Program and Erase Suspend commands are forbidden after the device entered Program-Suspend mode.
9-9. PROGRAM RESUME
The Program Resume command is valid only when the device is in Program-Suspended mode. After program
resumes, the user can issue another Program Suspend command, but there should be a 5us interval between
Program Resume and the next Program Suspend command.
9-10. BUFFER WRITE ABORT
Q1 is the indicator of Buffer Write Abort. When Q1=1, the device will abort from buffer write and go back to read
status register shown as following table:
Status
Q7
Q6
Q5
0
Q3
N/A
N/A
N/A
Q2
N/A
N/A
N/A
Q1
0
RY/BY#
Buffer Write Busy
Buffer Write Abort
Buffer Write Exceeded Time Limit
Q7#
Q7#
Q7#
Toggle
Toggle
Toggle
0
0
0
0
1
1
0
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COMMAND OPERATIONS (cont'd)
9-11. AUTOMATIC SELECT OPERATIONS
When the device is in Read mode, Program Suspended mode, Erase-Suspended Read mode, or CFI mode, the
user can issue the Automatic Select command shown in Table 5 (two unlock cycles followed by the Automatic
Select command 90h) to enter Automatic Select mode. After entering Automatic Select mode, the user can query
the Manufacturer ID, Device ID, Security Sector locked status, or Sector protected status multiple times without
issuing a new Automatic Select command.
While In Automatic Select mode, issuing a Reset command (F0h) will return the device to Read mode (or Ease-
Suspended Read mode if Erase-Suspend was active) or Program Suspended Read mode if Program Suspend
was active.
Another way to enter Automatic Select mode is to use one of the bus operations shown in Table 2 BUS OPERA-
TION. After the high voltage (Vhv) is removed from the A9 pin, the device will automatically return to Read mode
or Erase-Suspended Read mode.
9-12. AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured
silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles.
The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle,
and user can read at any address any number of times without entering another command sequence. The Reset
command is necessary to exit the Automatic Select mode and back to read array.
After entering automatic select mode, no other commands are allowed except the reset command.
9-13. READ MANUFACTURER ID OR DEVICE ID
The Manufacturer ID (identification) is a unique hexadecimal number assigned to each manufacturer by the JE-
DEC committee. Each company has its own manufacturer ID, which is different from the ID of all other compa-
nies. The number assigned to Macronix is C2h.
After entering Automatic Select mode, performing a read operation with A1 & A0 held LOW will cause the device
to output the Manufacturer ID on the Data I/O (Q7 to Q0) pins.
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COMMAND OPERATIONS (cont'd)
9-14. RESET
In the following situations, executing reset command will reset device back to Read mode:
• Among erase command sequence (before the full command set is completed)
• Sector erase time-out period
• Erase fail (while Q5 is high)
• Among program command sequence (before the full command set is completed, erase-suspended program
included)
• Program fail (while Q5 is high, and erase-suspended program fail is included)
• Auto-select mode
• CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset
device back to read array mode. While the device is in Auto-Select mode or CFI mode, user must issue reset
command to reset device back to read array mode.
When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig-
nore reset command.
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9-15. Advanced Sector Protection/Un-protection
There are two ways to implement software Advanced Sector Protection on this device: Password method or
Solid methods. Through these two protection methods, user can disable or enable the programming or erasing
operation to any individual sector or the whole chip. The figure below helps to describe an overview of these
methods.
The device is default to the Solid mode. All sectors are default as unprotected when shipped from factory.
The detailed algorithm of advance sector protection is shown as follows:
Figure 1. Advance Sector Protection/Unprotection SPB Program Algorithm
Start
To choose
protection mode
set lock register bit
(Q1/Q2)
Q1=0
Q2=0
Solid Protection Mode
Password Protection Mode
Set 64 bit Password
SPBLK = 0
Set
SPB Lock bit locked
SPB Lock Bit
All SPBs can not changeable
SPBLK = 1
SPB Lock bit Unlocked
All SPBs are changeable
Dynamic write Protect bit
(DPB)
Temporary Unprotect
SPB bit (USPB)
Solid write Protect bit (SPB)
Sector Array
DPB=0 sector protect
SPB=0 sector protect
USPB=0 SPB bit is disabled
USPB=1 SPB bit is enabled
DPB=1 sector unprotect
SPB=1 sector unprotect
DPB 0
DPB 1
SA 0
SA 1
SPB 0
SPB 1
USPB 0
USPB 1
DPB 2
SA 2
SPB 2
USPB 2
:
:
:
:
:
:
:
:
DPB N-1
DPB N
SA N-1
SA N
SPB N-1
SPB N
USPB N-1
USPB N
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9-15-1. Lock Register
User can choose the sector protecting method via setting Lock Register bits as Q1 and Q2. Lock Register is a
16-bit one-time programmable register. Once programming either Q1 or Q2, they will be locked in that mode and
the others will be disabled permanently. Q1 and Q2 can not be programmed at the same time, otherwise the
device will abort the operation.
If users select Password Protection mode, the password setting is required. Users can set password by issuing
password program command.
Lock Register bits
Q15-Q3
Q2
Q1
Q0
Password Protection Mode
Lock Bit
Solid Protection Mode
Lock Bit
Secured Silicon Sector
Protection Bit
Don't care
Please refer to the command for Lock Register command set about how to read and program the Lock Register
bits.
Figure 2. Lock Register Program Algorithm
START
Write Data AAH, Address 555H
Lock register command set Entry
Write Data 55H, Address 2AAH
Write Data 40H, Address 555H
Write Data A0H,
Address don’t care
Lock register data program
Write Program Data,
Address don’t care
Data # Polling Algorithm
YES
Done
NO
Pass
NO
Q5 = 1
YES
Exit Lock Register
command
Fail
Reset command
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9-15-2. Solid Protection Mode
Solid write Protection Bits (SPB)
The Solid write Protection bits (SPB) are nonvolatile bit with the same endurances as the Flash memory. Each
SPB is assigned to each sector individually. The SPB is preprogrammed, and verified prior to erasure are
managed by the device, so system monitoring is not necessary.
When SPB is set to “0”, the associated sector may be protected, preventing any program or erase operation on
this sector. Whether the sector is protected depends also upon the value of the USPB, as described elsewhere.
The SPB bits are set individually by SPB program command. However, it cannot be cleared individually. Issuing
the All SPB Erase command will erase all SPB in the same time. During SPB programming period, the read and
write operations are disabled for normal sector until exiting this mode.
To unprotect a protected sector, the SPB lock bit must be cleared first by using a hardware reset or a power-up
cycle. After the SPB lock bit is cleared, the SPB status can be changed to the desired settings. To lock the Solid
Protection Bits after the modification has finished, the SPB Lock Bit must be set once again.
To verify the state of the SPB for a given sector, issuing a SPB Status Read Command to the device is required.
Refer to the flow chart for details in Figure 3.
Dynamic write Protection Bits (DPB)
The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from
being unintentionally changed, and is easy to disable.
All Dynamic write Protection bit (DPB) can be modified individually. DPBs protect the unprotected sectors with
their SPBs cleared. To modify the DPB status by issuing the DPB Set (programmed to “0”) or DPB Clear (erased
to “1”) commands, and place each sector in the protected or unprotected state seperately. After the DPB Clear
command is issued (erased to “1”), the sector may be modified depending on the SPB state of that sector.
The DPBs are default to be erased to “1” when first shipped from factory.
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9-15-3. Temporary Un-protect Solid write Protect Bits (USPB)
Temporary Un-protect Solid write Protect Bits are volatile. They are unique for each sector and can be
individually modified. Software can temporarily unprotect write protect sectors despite of SPB's property when
DPBs are cleared. While the USPB is set (to “0”), the corresponding sector's SPB property is masked.
Notes:
1. Upon power up, the USPBs are cleared (all “1”). The USPBs can be set (to “0”) or cleared (to “1”) as often as
needed. The hardware reset will reset USPB/DPB to their default values.
2. To change the protected sector status of solid write protect bit, users don't need to clear all SPBs. The users
can just implement software to set corresponding USPB to "0", in which the corresponding DPB status is
cleared too. Consequently, the original solid write protect status of protected sectors can be temporarily
changed.
Figure 3. SPB Program Algorithm
SPB command
set entry
Program SPB
Read Q7~Q0
Twice
NO
Q6 Toggle ?
YES
NO
Q5 = 1 ?
Wait 500 µs
YES
Read Q7~Q0
Twice
Read Q7~Q0
Twice
NO
Q6 Toggle ?
YES
Q0=
'1' (Erase)
'0' (Program)
NO
YES
Program Fail
Write Reset CMD
Pass
SPB command
set Exit
Note: SPB program/erase status polling flowchart: check Q6 toggle, when Q6 stop toggle, the read status is 00H
/01H (00H for program/ 01H for erase), otherwise, the status is “fail” and “exit”.
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9-15-4. Solid Protection Bit Lock Bit
The Solid Protection Bit Lock Bit (SPBLK) is assigned to control all SPB status. It is an unique and volatile. When
SPBLK=0 (set), all SPBs are locked and can not be changed. When SPBLK=1 (cleared), all SPBs are allowed to
be changed.
There is no software command sequence requested to unlock this bit, unless the device is in the password
protection mode. To clear the SPB Lock Bit, just execute a hardware reset or a power-up cycle. In order to
prevent modification, the SPB Lock Bit must be set (SPBLK=0) after all SPBs are set to desired status.
9-15-5. Password Protection Method
The security level of Password Protection Method is higher than the Solid protection mode. The 64 bit password
is requested before modifying SPB lock bit status. When device is under password protection mode, the SPB
lock bit is set as “0”, after a power-up cycle or Reset Command.
A correct password is required for password Unlock command to unlock the SPB lock bit. Await 2us is necessary
to unlock the device after a valid password is given. After that, the SPB bits are allowed to be changed. The
Password Unlock command is issued slower than 2 μs every time, to prevent hacker from trying all the 64-bit
password combinations.
There are a few steps to start password protection mode:
(1).Set a 64-bit password for verification before entering the password protection mode. This verification is only
allowed in password programming.
(2).Set the Password Protection Mode Lock Bit to”0” to activate the password protection mode.
Once the password protection mode lock bit is programmed, the programmed Q2 bit can not be erased any more
and the device will remain permanently in password protection mode. The previous set 64-bit password can not
be retrieved or programmed. All the commands to the password-protected address will also be disabled.
All the combinations of the 64-bit password can be used as a password, and programming the password does
not require special address. The password is defaulted to be all “1” when shipped from the factory. Under
password program command, only "0" can be programmed. In order to prevent access, the Password Mode
Locking Bit must be set after the Password is programmed and verified. To set the Password Mode Lock Bit will
prevent this 64-bits password to be read on the data bus. Any modification is impossible then, and the password
can not be checked anymore after the Password Mode Lock Bit is set.
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MX68GL1G0F
Table 4. Sector Protection Status
Protection Bit Status
Sector Status
DPB
clear
clear
clear
clear
set
SPB
clear
clear
set
USPB
clear
set
Unprotect
Unprotect
Protect
clear
set
set
Unprotect
Protect
clear
clear
set
clear
set
set
Protect
set
clear
set
Protect
set
set
Protect
Notes: If SPBLK is set, SPB will be unchangeable.
If SPBLK is cleared, SPB will be changeable.
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9-16. SECURITY SECTOR FLASH MEMORY REGION
The Security Sector region is an extra OTP memory space of 128 words in length. The security sector can be
locked upon shipping from factory, or it can be locked by customer after shipping. Customer can issue Security
Sector Factory Protect Verify and/or Security Sector Protect Verify to query the lock status of the device. After
enter Security Sector region, it is forbidden to enter Lock Register, DPB, SPB, SPB lock region.
In factory-locked device, security sector region is protected when shipped from factory and the security silicon
sector indicator bit is set to "1". In customer lockable device, security sector region is unprotected when shipped
from factory and the security silicon indicator bit is set to "0".
9-17. FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY
In a factory locked device, the Security Sector is permanently locked before shipping from the factory. The de-
vice will have a 16-byte (8-word) ESN in the security region. The ESN occupies addresses 00000h to 0000Fh in
byte mode or 00000h to 00007h in word mode.
Secured Silicon Sector
Address Range
Express Flash
Factory Locked
Standard Factory Locked
Customer Lockable
ESN or Determined by
Customer
Determined by Customer
0000000h-0000007h
0000008h-000007Fh
ESN
Determined by Customer
Unavailable
9-18. CUSTOMER LOCKABLE: SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE
FACTORY
When the security feature is not required, the security region can act as an extra memory space.
Security silicon sector can also be protected by two methods. Note that once the security silicon sector is pro-
tected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered.
After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a pow-
er cycle, or issue a hardware reset to return the device to read normal array mode.
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Table 5. COMMAND DEFINITIONS
Automatic Select
Security
Sector
Region
Exit Security
Comm-
and
Read Reset
Mode Mode
Factory Protect Sector Protect Verify
Sector
Silicon ID
Device ID
Verify
Word Byte Word Byte
Addr Addr XXX 555 AAA 555 AAA
Word
555
AA
2AA
55
555
90
Byte
AAA
AA
555
55
Word
555
AA
2AA
55
Byte
AAA
AA
555
55
Word Byte Word Byte
555 AAA 555 AAA
1st Bus
Cycle
Data Data
Addr
Data
Addr
Data
F0
AA
2AA 555 2AA 555
55 55 55 55
555 AAA 555 AAA
90 90 90 90
AA
AA
AA
AA
2AA 555 2AA 555
55 55 55 55
555 AAA 555 AAA
88 88 90 90
AA
AA
AA
2nd Bus
Cycle
AAA
90
555
90
AAA
90
3rd Bus
Cycle
(Sector) (Sector)
Addr
Data
X00 X00 X01 X02
C2h C2h ID1 ID1
X03
X06
XXX XXX
00 00
X02
X04
4th Bus
Cycle
99/19(H)
89/09(L)
00/01
00/01
Addr
Data
Addr
Data
X0E X1C
ID2 ID2
X0F X1E
ID3 ID3
5th Bus
Cycle
6th Bus
Cycle
Write to
Buffer
Program
Write to
Buffer
Program
Write to
Buffer
Program
Program/ Program/
Erase Erase
Suspend Resume
Sector
Erase
Program
Chip Erase
CFI Read
Comm-
and
Abort Reset confirm
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
Addr 555 AAA 555 AAA 555 AAA SA SA 555 AAA 555 AAA 55 AA xxx xxx xxx xxx
1st Bus
Cycle
Data AA AA AA AA AA AA 29
Addr 2AA 555 2AA 555 2AA 555
29
AA AA AA AA 98 98 B0 B0 30
2AA 555 2AA 555
30
2nd Bus
Cycle
Data 55
Addr 555 AAA SA SA 555 AAA
Data A0 A0 25 25 F0 F0
55
55
55
55
55
55
555 AAA 555 AAA
80 80 80 80
55 55 55
3rd Bus
Cycle
Addr Addr Addr SA SA
Data Data Data N-1 N-1
555 AAA 555 AAA
AA AA AA AA
2AA 555 2AA 555
4th Bus
Cycle
Addr
Data
WA WA
WD WD
5th Bus
Cycle
55
55 55 55
Sec- Sec-
tor tor
10 30 30
Addr
Data
WBL WBL
WD WD
555 AAA
6th Bus
Cycle
10
WA= Write Address
WD= Write Data
SA= Sector Address
N-1= Word Count
WBL= Write Buffer Location
PWD= Password
PWDn=Password word 0, word 1, word n
ID1/ID2/ID3: Refer to Table 3 for detail ID.
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MX68GL1G0F
Deep Power Down
Password Protection
Password
Password
Command Set
Entry
Command
Password
Program
Password
Read
Password
Unlock
Enter
Exit
Command Set
Exit
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
Addr 555
AAA XXX XXX
555
AA
2AA
55
555
60
AAA XXX XXX
AA A0 A0 PWD0 PWD0 25
555 PWA PWA X01 X01 00
PWD PWD PWD1 PWD1 03
X02 X02 X00
X00
X00
00
00
25
00
03
X00
XXX XXX
90 90
XXX XXX
00 00
1st Bus
Cycle
Data AA
Addr 2AA
AA
555
55
AB
AB
2nd Bus
Cycle
Data
55
55
AAA
60
Addr XXX XXX
Data B9
Addr
3rd Bus
Cycle
B9
PWD2 PWD2 PWD0 PWD0
X03 X03 X01 X01
PWD3 PWD3 PWD1 PWD1
X04 X02 X02
PWD4 PWD2 PWD2
X05 X03 X03
PWD5 PWD3 PWD3
X06 00 X04
PWD6 29 PWD4
4th Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
5th Bus
Cycle
6th Bus
Cycle
7th Bus
Cycle
X07
PWD7
X05
PWD5
X06
PWD6
X07
PWD7
00
29
8th Bus
Cycle
9th Bus
Cycle
10th Bus
Cycle
11th Bus
Cycle
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MX68GL1G0F
Lock Register
Global Non-Volatile
Lock register
Command
Set Entry
Lock register
Command Command
Set Exit Set Entry
SPB
Command
SPB
Program
All SPB
Erase
SPB Status
Read
Program
Read
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
Addr 555 AAA XXX XXX XXX XXX XXX XXX 555 AAA XXX XXX XXX XXX SA SA
1st Bus
Cycle
Data
Addr 2AA 555 XXX XXX
Data 55 55 Data Data
Addr 555 AAA
AA
AA
A0
A0 DATA DATA 90
XXX XXX 2AA 555 SA SA
00 00 55 55 00 00
555 AAA
C0 C0
90
AA
AA
A0
A0
80
00
30
80 00/01 00/01
00
30
2nd Bus
Cycle
3rd Bus
Cycle
Data
Addr
Data
40
40
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Global Non-
Volatile
Global Volatile Freeze
SPB Lock SPB Lock
Volatile
SPB
Command
Set Exit
SPB Lock
Command
Set Entry
SPB Lock
Command Command DPB Set DPB Clear
Set Exit Set Entry
DPB
Command
Set
Status Read
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
Addr XXX XXX 555 AAA XXX XXX XXX XXX XXX XXX 555 AAA XXX XXX XXX XXX
Data 90 90 AA AA A0 A0 00/01 00/01 90 90 AA AA A0 A0 A0 A0
Addr XXX XXX 2AA 555 XXX XXX XXX XXX 2AA 555 SA SA SA SA
00 00 55 55 00 00 01 01
555 AAA
E0 E0
1st Bus
Cycle
2nd Bus
Cycle
Data 00
Addr
Data
00
55
55
00
00
555 AAA
50
3rd Bus
Cycle
50
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Volatile
Command
DPB Status DPB Command
Read
Set Exit
Word
SA
Byte
SA
Word Byte
Addr
XXX
XXX
1st Bus
Cycle
Data 00/01 00/01
90
XXX
00
90
XXX
00
Addr
Data
Addr
Data
Addr
Data
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Notes:
* It is not recommended to adopt any other code not in the command definition table which will potentially enter
the hidden mode.
* For the SPB Lock and DPB Status Read "00" means lock (protect), "01" means unlock (unprotect).
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MX68GL1G0F
10. COMMON FLASH MEMORY INTERFACE (CFI) MODE
QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE
The device features CFI mode. Host system can retrieve the operating characteristics, structure and vendor-
specified information such as identifying information, memory size, byte/word configuration, operating voltages
and timing information of this device by CFI mode. If the system writes the CFI Query command "98h", to ad-
dress "55h"/"AAh" (depending on Word/Byte mode), the device will enter the CFI Query Mode, any time the de-
vice is ready to read array data. The system can read CFI information at the addresses given in Table 6 ~ Table 9.
Once user enters CFI query mode, user can issue reset command to exit CFI mode and return to read array
mode. The CFI unused area is reserved by Macronix.
(Note 1)
Table 6. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
10
11
12
13
14
15
16
17
18
19
1A
20
22
24
26
28
2A
2C
2E
30
32
34
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Note 1. Query data are always presented on the lowest data output Q7~Q0 only, Q8~Q15 are "0".
Table 7. CFI mode: System Interface Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
Vcc supply minimum program/erase voltage
Vcc supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n us
Typical timeout for maximum-size buffer write, 2n us (00h, not
1B
1C
1D
1E
1F
36
38
3A
3C
3E
0027
0036
0000
0000
0003
20
40
0006
support)
Typical timeout per individual block erase, 2n ms
Typical timeout for full chip erase, 2n ms (00h, not support)
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times typical
Maximum timeout for chip erase, 2n times typical (00h, not
21
22
23
24
25
42
44
46
48
4A
0009
0018
0003
0005
0003
26
4C
0002
support)
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MX68GL1G0F
Table 8. CFI mode: Device Geometry Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
Device size = 2n in number of bytes (1B=1Gb)
Flash device interface description (02=asynchronous x8/x16)
27
28
4E
001B
50
52
54
56
58
5A
5C
5E
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
0002
0000
0006
0000
0001
00FF
0003
0000
0002
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
29
2A
2B
2C
2D
Maximum number of bytes in buffer write = 2n (00h, not support)
Number of erase regions within device (01h:uniform, 02h:boot)
Index for Erase Bank Area 1:
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256 bytes
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4
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MX68GL1G0F
Table 9. CFI mode: Primary Vendor-Specific Extended Query Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
40
41
42
43
44
45
46
47
48
49
4A
4B
80
82
84
86
88
8A
8C
8E
90
92
94
96
0050
0052
0049
0031
0033
0014
0002
0001
0000
0008
0000
0000
Query - Primary extended table, unique ASCII string, PRI
Major version number, ASCII
Minor version number, ASCII
Unlock recognizes address (0= recognize, 1= don't recognize)
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/Chip unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode (0=not supported)
Page mode (0=not supported, 01 = 4 word page, 02 = 8 word
page)
4C
98
0002
Minimum ACC(acceleration) supply (0= not supported), [D7:D4]
for volt, [D3:D0] for 100mV
Maximum ACC(acceleration) supply (0= not supported), [D7:D4]
for volt, [D3:D0] for 100mV
4D
4E
9A
9C
0095
00A5
WP# Protection
04=Uniform sectors bottom WP# protect
05=Uniform sectors top WP# protect
0004/
0005
4F
50
9E
A0
Program Suspend (0=not supported, 1=supported)
0001
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11. ELECTRICAL CHARACTERISTICS
11-1. ABSOLUTE MAXIMUM STRESS RATINGS
Storage Temperature
VCC
-65°C to +150°C
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to +10.5V
-0.5V to Vcc +0.5V
200 mA
VI/O
Voltage Range
A9 , WP#/ACC
The other pins.
Output Short Circuit Current (less than one second)
11-2. OPERATING TEMPERATURE AND VOLTAGE
Industrial (I) Grade Surrounding Temperature (T )
range
A
-40°C to +85°C
+2.7V to 3.6V
+3.0V to 3.6V
+1.65V to 3.6V
Full VCC
Regulated VCC
range
range
Supply Voltages
VCC
VI/O
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot GND to -2.0V and Vcc to +2.0V for periods up to 20ns, see
below Figure.
Figure 5. Maximum Positive Overshoot Waveform
Figure 4. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
GND
Vcc + 2.0V
GND - 2.0V
Vcc
20ns
20ns
20ns
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Table 10. DC CHARACTERISTICS
Symbol Description
Min.
Typ.
Max.
Remark
Iilk
Iilk9
Iolk
Input Leak
A9 Leak
±8.0uA
140uA A9=10.5V
±1.0uA
Output Leak
CE#=Vil, OE#=Vih,
5mA
10mA
15mA
15mA
20mA
30mA
Vcc=Vccmax;
f=1MHz,
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=5MHz,
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=10MHz
Icr1
Icr2
Read Current
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=10MHz
4mA
8mA
10mA
20mA
VCC Page Read Current
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=33MHz
Iio
VIO non-active current
Write Current
0.2mA
14mA
10mA
30mA
Icw
CE#=Vil, OE#=Vih
Vcc=Vcc max, other
pin disable
Isb
Standby Current
Reset Current
60uA
60uA
200uA
Vcc=Vccmax,
200uA RESET# enable,
Isbr
other pin disable
Isbs
Idpd
Sleep Mode Current *1
60uA
4uA
200uA
40uA
Vcc deep power down current
Accelerated Pgm Current, WP#/Acc pin
(Word/Byte)
Accelerated Pgm Current, Vcc pin,
(Word/Byte)
Icp1
Icp2
1.5mA
14mA
4mA
CE#=Vil, OE#=Vih
CE#=Vil, OE#=Vih
28mA
Vil
Input Low Voltage
Input High Voltage
-0.1V
0.3xVI/O
Vih
0.7xVI/O
VI/O+0.3V
Very High Voltage for Auto Select/
Accelerated Program
Vhv
9.5V
10.5V
0.45V
Vol
Voh
Vlko
Output Low Voltage
Iol=100uA
Ouput High Voltage
0.85xVI/O
Ioh=-100uA
Low Vcc Lock-out voltage *2
2.1V
2.4V
Note:
1. Sleep mode enables the lower power when address remain stable for taa+30ns.
2. Not 100% tested.
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MX68GL1G0F
Figure 6. SWITCHING TEST CIRCUITS
3.3V
2.7KΩ
DEVICE UNDER
TEST
CL
6.2KΩ
Test Condition
Output Load Capacitance, CL : 1TTL gate, 30pF
Rise/Fall Times : 5ns
Input Pulse levels :0.0 ~ VI/O
In/Out reference levels :0.5VI/O
Figure 7. SWITCHING TEST WAVEFORMS
VI/O
VI/O / 2
VI/O / 2
Test Points
0.0V
INPUT
OUTPUT
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Table 11. AC CHARACTERISTICS
Symbol Description
VCC=2.7V~3.6V
Unit
Min. Typ. Max.
VI/O=VCC
110
120
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Taa Valid data output after address
Tpa Page access time
VI/O=1.65 toVCC
VI/O=VCC
VI/O=1.65 toVCC
VI/O=VCC
30
110
120
25
Tce Valid data output after CE# low
Toe Valid data output after OE# low
VI/O=1.65 toVCC
VI/O=VCC
VI/O=1.65 toVCC
30
Tdf
Data output floating after OE# high or CE# high
20
Tsrw Latency between read and write operation (Note)
35
0
Toh Output hold time from the earliest rising edge of address, CE#, OE#
VI/O=VCC
110
120
110
120
110
120
0
Trc
Read period time
VI/O=1.65 toVCC
VI/O=VCC
Twc Write period time
VI/O=1.65 toVCC
VI/O=VCC
Tcwc Command write period time
Tas Address setup time
VI/O=1.65 toVCC
Taso Address setup time to OE# low during toggle bit polling
Tah Address hold time
15
45
0
Taht Address hold time from CE# or OE# high during toggle bit polling
Tds Data setup time
30
0
Tdh Data hold time
Tvcs Vcc setup time
500
0
Tcs
Chip enable Setup time
Tch Chip enable hold time
0
Toes Output enable setup time
0
Read
0
Toeh Output enable hold time
Toggle & Data# Polling 10
Tws WE# setup time
Twh WE# hold time
0
0
Tcepw CE# pulse width
Tcepwh CE# pulse width high
Twp WE# pulse width
Twph WE# pulse width high
35
30
35
30
VI/O=VCC
110
120
Tbusy Program/Erase active time by RY/BY#
VI/O=1.65 toVCC
Tghwl Read recover time before write
Tghel Read recover time before write
0
0
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MX68GL1G0F
VCC=2.7V~3.6V
Unit
Symbol Description
Min. Typ. Max.
Byte
10
10
10
0.5
us
us
Twhwh1 Program operation
Word
Twhwh1 Acc program operation (Word/Byte)
Twhwh2 Sector erase operation
us
3.5
50
sec
us
Tbal Sector add hold time
Trdp Release from deep power down mode
200
us
Note : Not 100% tested.
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12. WRITE COMMAND OPERATION
Figure 8. COMMAND WRITE OPERATION
Tcwc
Vih
CE#
Vil
Tch
Tcs
Vih
WE#
Vil
Toes
Twph
Twp
Vih
Vil
OE#
Vih
Vil
Addresses
VA
Tah
Tas
Tdh
Tds
Vih
Vil
Data
DIN
VA: Valid Address
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13. READ/RESET OPERATION
Figure 9. READ TIMING WAVEFORMS
Tce
Vih
CE#
Vil
Vih
WE#
Vil
Toeh
Tdf
Toe
Vih
OE#
Vil
Toh
Taa
Trc
Vih
ADD Valid
Addresses
Vil
Tsrw
HIGH Z
HIGH Z
Voh
Vol
Outputs
DATA Valid
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Table 12. AC CHARACTERISTICS-RESET#
Item Description
Setup Speed
Unit
us
Trp1 RESET# Pulse Width (During Automatic Algorithms)
Trp2 RESET# Pulse Width (NOT During Automatic Algorithms)
MIN
MIN
MIN
MIN
MIN
MAX
MAX
10
500
200
0
ns
Trh
RESET# High Time Before Read
ns
Trb1 RY/BY# Recovery Time (to CE#, OE# go low)
ns
Trb2 RY/BY# Recovery Time (to WE# go low)
50
ns
Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write
Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write
20
us
500
ns
Figure 10. RESET# TIMING WAVEFORM
Trb1
CE#, OE#
Trb2
WE#
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
Trh
RY/BY#
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
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14. ERASE/PROGRAM OPERATION
Figure 11. AUTOMATIC CHIP ERASE TIMING WAVEFORM
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycle
Read Status
Tah
Twc
Tas
VA
VA
2AAh
555h
Address
Tds
Tdh
In
Complete
Progress
55h
10h
Data
Tbusy
Trb
RY/BY#
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MX68GL1G0F
Figure 12. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
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Figure 13. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Tas
Sector
Sector
Sector
VA
VA
2AAh
Address
Address 0
Address 1
Address n
Tah
Tds Tdh
In
Progress
Complete
55h
30h
30h
30h
Data
Tbusy
Trb
RY/BY#
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Figure 14. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Last Sector
to Erase
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh
YES
Auto Sector Erase Completed
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Figure 15. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
ERASE SUSPEND
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
Continue Erase
ERASE RESUME
Another
NO
Erase Suspend ?
YES
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Figure 16. AUTOMATIC PROGRAM TIMING WAVEFORMS
CE#
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Tas
Last 2 Read Status Cycle
Tah
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
Trb
RY/BY#
Figure 17. ACCELERATED PROGRAM TIMING DIAGRAM
Vcc (min)
Vcc
GND
Tvcs
(9.5V ~ 10.5V)
Vhv
WP#/ACC
Vil or Vih
Vil or Vih
250ns
250ns
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Figure 18. CE# CONTROLLED WRITE TIMING WAVEFORM
WE#
Tcepw
Twh
Tws
Twhwh1 or Twhwh2
CE#
OE#
Tcepwh
Tghwl
Tah
Tas
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
RY/BY#
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Figure 19. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
No
Read Again Data:
Program Data?
YES
No
Last Word to be
Programed
YES
Auto Program Completed
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15. SILICON ID READ OPERATION
Figure 20. SILICON ID READ TIMING WAVEFORM
VCC
3V
Vhv
ADD
A9
Vih
Vil
Vih
Vil
ADD
A0
Taa
Taa
Taa
Taa
Vih
Vil
A1
A2
Vih
Vil
Vih
Vil
ADD
Disable
Enable
CE#
Tce
Vih
Vil
WE#
Toe
Vih
Vil
OE#
Tdf
Toh
Toh
Toh
Toh
Vih
Vil
DATA
Q15~Q0
DATA OUT
Manufacturer ID
DATA OUT
DATA OUT
DATA OUT
Device ID
Cycle 1
Device ID
Cycle 2
Device ID
Cycle 3
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16. WRITE OPERATION STATUS
Figure 21. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
VA
VA
Address
Taa
Toh
High Z
High Z
Complement
Complement
Status Data
True
True
Valid Data
Valid Data
Q7
Q6~Q0
Status Data
Tbusy
RY/BY#
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Figure 22. STATUS POLLING FOR PROGRAM/ERASE
Start
Read Data at valid address
(Note 1)
No
Q7 = Data# ?
Yes
No
Q5 = 1 ?
Yes
Read Data at valid address
(Note 1)
No
Q7 = Data# ?
(Note 2)
Yes
Fail
Pass
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2. Q7 may change simultaneously with Q5, so even Q5=1, Q7 should be reverify.
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Figure 23. STATUS POLLING FOR WRITE BUFFER PROGRAM
Start
Read Data at last write
address (Note 1)
No
Q7 = Data# ?
Yes
Q1=1 ?
Yes
Only for write
buffer program
No
No
Q5=1 ?
Read Data at last write
address (Note 1)
Yes
Read Data at last write
address (Note 1)
No
Q7 = Data# ?
(Note 2)
No
Q7 = Data# ?
(Note 2)
Yes
Write Buffer Abort
Yes
Fail
Pass
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2. Q7 may change simultaneously with Q5, so even Q5=1, Q7 should be reverify.
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Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
OE#
Toe
Toeh
Tdf
Taht
Taso
Trc
VA
VA
VA
VA
Address
Taa
Toh
Valid Status
(second read)
Valid Status
(first read)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
Tbusy
RY/BY#
VA : Valid Address
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Figure 25. TOGGLE BIT ALGORITHM
Start
Read Data Twice
(Note 1)
No
Q6 Toggle ?
Yes
No
Q5 = 1 ?
Yes
Read Data Twice
(Note 1, 2)
No
Q6 Toggle ?
Yes
Fail
Pass
Notes:
1. Toggle bit Q7-Q0 should be read twice to check if it is toggling.
2. While Q5=1, the toggle bit (Q6) may stop toggling. Therefore, the system should be read again.
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17. PAGE READ OPERATION
AC CHARACTERISTICS
WORD/BYTE CONFIGURATION (BYTE#)
Test
Parameter Description
All Speed Options
Unit
Setup
Max.
Max.
Min.
Telfl/Telfh CE# to BYTE# from L/H
5
ns
ns
ns
Tflqz
BYTE# from L to Output Hiz
30
90
Tfhqv
BYTE# from H to Output Active
Figure 26. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to
word mode)
CE#
OE#
Telfh
BYTE#
DOUT
(Q0-Q7)
DOUT
(Q0-Q14)
Q14~Q0
Q15/A-1
DOUT
(Q15)
VA
Tfhqv
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Figure 27. PAGE READ TIMING WAVEFORM
Amax:A3
VALID ADD
2'nd ADD
Tpa
3'rd ADD
Tpa
Data 2
(A-1),A0,A1,A2
DATA
1'st ADD
Taa
Data 1
Data 3
Toe
Tce
OE#
CE#
Note: CE#, OE# are enable.
Page size is 8 words in Word mode, 16 bytes in Byte mode.
Address are A2~A0 for Word mode, A2~A-1 for Byte mode.
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18. DEEP POWER DOWN MODE OPERATION
Table 13. AC CHARACTERISTICS - Deep Power Down Mode
Item
Typ.
100us
10us
Max.
200us
20us
WEB high to release from deep power down mode
WEB high to deep power down mode
tRDP
tDP
Figure 28. DEEP POWER DOWN MODE WAVEFORM
CEB
WEB
tDP
tRDP
ADD
XX
55
2AA
XX (don't care)
DATA
AA
55
B9
AB
Standby mode
Standby mode
Deep power down mode
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19. WRITE BUFFER PROGRAM OPERATION
Figure 29. WRITE BUFFER PROGRAM FLOWCHART
Addr=555h
Data=AAh,
Write CMD:
Write CMD:
Write CMD:
Write CMD:
Addr=2AA
h
Data=55h,
Addr=SA
Data=29h,
Write CMD:
Addr=SA
Data=25h,
tus
Polling Sta
Addr=SA
Data=PWC,
Yes
Pass
No
Write CMD:
Data=PGM_data, Addr
Return to read Mode
=PGM_addr
?
-1
No
PWC=PWC
Fail
Write a different sector
address to cause Abort
Yes
Want to Abort
No
Yes
Yes
r Abort
Write Buffe
No
Yes
PWC =0?
No
d page
SA: Sector Address of to be Programme
m Word Count
CMD
Write Abort reset CMD
to return to read Mode
Write reset
to return to read Mode
PWC: Progra
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20. RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure 30 is recommended for the supply voltages and the control signals at device pow-
er-up (e.g. VCC and CE# ramp up simultaneously). If the timing in the figure is ignored, the device may not oper-
ate correctly.
Figure 30. AC Timing at Device Power-Up
VCC(min)
VCC
GND
Tvr
Tvcs
VI/O(min)
GND
VI/O
Tvios
Tvr
Tf
Tce
Tr
Vih
Vil
CE#
WE#
OE#
Vih
Vil
Tf
Toe
Tr
Vih
Vil
Taa
Tr or Tf
Tr or Tf
Vih
Vil
Valid
Address
ADDRESS
Voh
Vol
High Z
Valid
Ouput
DATA
Vih
Vil
WP#/ACC
Symbol
Parameter
VCC Rise Time
Input Signal Rise Time
Input Signal Fall Time
VCC Setup Time
VI/O Setup Time
Min.
20
Max.
500000
20
Unit
us/V
us/V
us/V
us
Tvr
Tr
Tf
Tvcs
Tvios
20
500
500
us
Notes:
1. VI/O<VCC+200mV.
2. Not test 100%.
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21. ERASE AND PROGRAMMING PERFORMANCE
Parameter
Limits
Units
Min.
Typ. (1)
Max. (2)
Chip Erase Time
400
1000
sec
sec
sec
us
Sector Erase Time
Chip Programming Time
Word Program Time
Total Write Buffer Time
ACC Total Write Buffer Time
Erase/Program Cycles
Notes:
0.5
320
10
3.5
1400
180
70
140
us
70
us
100,000
Cycles
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC. Programming specifica-
tions assume checkboard data pattern.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
3. Erase/Program cycles comply with JEDEC JESD-47 & JESD 22-A117 standard.
4. Exclude 00h program before erase operation.
22. DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
55˚C
20
years
23. LATCH-UP CHARACTERISTICS
Min.
-1.0V
Max.
10.5V
Input Voltage voltage difference with GND on WP#/ACC and A9 pins
Input Voltage voltage difference with GND on all normal pins input
Vcc Current
-1.0V
1.5Vcc
+100mA
-100mA
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
24. PIN CAPACITANCE
Parameter Symbol
Parameter Description
Control Pin Capacitance
Output Capacitance
Input Capacitance
Test Set
VIN=0
Typ.
15
Max.
Unit
pF
CIN2
COUT
CIN
70
24
30
VOUT=0
VIN=0
17
pF
20
pF
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25. ORDERING INFORMATION
PART NO.
ACCESS TIME (ns)
PACKAGE
64 LFBGA
Remark
MX68GL1G0FHXFI-11G
MX68GL1G0FLXFI-11G
MX68GL1G0FHT2I-11G
MX68GL1G0FLT2I-11G
MX68GL1G0FUXFI-12G *
MX68GL1G0FDXFI-12G *
MX68GL1G0FUT2I-12G *
MX68GL1G0FDT2I-12G *
110
110
110
110
120
120
120
120
64 LFBGA
56 Pin TSOP
56 Pin TSOP
64 LFBGA
64 LFBGA
56 Pin TSOP
56 Pin TSOP
* Advance Information
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26. PART NAME DESCRIPTION
68
F
T2
11
G
GL 1G0
MX
H
I
OPTION:
G: RoHS Compliant & Halogen-free
SPEED:
11: 110ns
12: 120ns
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
T2: 56-TSOP
XF: LFBGA (11mm x 13mm)
PRODUCT TYPE (Protection when WP#=VIL):
H: VI/O=VCC=2.7 to 3.6V, Highest Address Sector Protected, uniform sector
L: VI/O=VCC=2.7 to 3.6V, Lowest Address Sector Protected, uniform sector
U: VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Highest Address Sector Protected, uniform sector
D: VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Lowest Address Sector Protected, uniform sector
REVISION:
F
DENSITY & MODE:
1G0: 1Gb x8/x16 Architecture
TYPE:
GL: 3V Page Mode
DEVICE:
68: Stack Die Flash
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27. PACKAGE INFORMATION
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28. REVISION HISTORY
Revision No. Description
Page
Date
0.01
1. Changed title from Advanced Information to Preliminary
P5
MAY/09/2012
2. Added MX68GL1G0F U/D function
3. Added MX68GL1G0F U/D ORDERING INFORMATION
and PART NAME DESCRIPTION
P5,7,38~41
P65,66
4. Modified Figure 18. CE# Controlled Write Timing Waveform
5. Added VI/O Setup Time
P52
P63
1.0
Removed "Preliminary" from Feature page.
P5
JUL/27/2012
1.1
1. Added Word/Byte Configuration (BYTE#) & Figure 26
2. Modified "Figure 27. PAGE READ TIMING WAVEFORM"
3. Modified Icr2
P60
P61
P39
FEB/01/2013
4. Modified Chip Programming Time (typ.) from 400sec to 800sec P65
5. Added Total Write Buffer Time (max.) 360us
6. Added ACC Total Write Buffer Time (max.) 360us
P65
P65
1.2
1.3
1. Advanced Sector Protection/Un-protection description updated P25~30
AUG/12/2013
2. Modified Word/Byte Configuration (BYTE#) table
P60
3. Modified Erase And Programming Performance table
P65
1. Updated parameters for DC Characteristics.
2. Updated Erase and Programming Performance.
3. Content correction
P5,39
P5,42,65
P25~30
OCT/30/2013
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Except for customized products which have been expressly identified in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2011~2013. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,
NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,
Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names
and brands of third party referred thereto (if any) are for identification purposes only.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
71
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