MX66C256TI-70 [Macronix]
Very Low Power 32k x 8 CMOS SRAM; 超低功耗的32k ×8 CMOS SRAM
| 型号： | MX66C256TI-70 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Very Low Power 32k x 8 CMOS SRAM |
| 文件： | 总9页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX66C256
Very Low Power 32k x 8 CMOS SRAM
DESCRIPTION
FEATURES
The MX66C256 is a high performance, very low power
CMOS Static Random Access Memory organized as
32,768 words by 8 bits and operates at 5.0V supply
voltage.
Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 0.4uA and maximum
access time of 70ns and 100 ns in 5V operation.
Easy memory expansion is provided by an active LOW
chip enable(CE), and active LOW output enable (OE)
and three-state output drivers.
The MX66C256 has an automatic power down feature,
reducing the power consumption significantly when chip
is deselected.
The MX66C256 is available in the JEDEC standard 28
pin 330mil Plastic SOP, and 8mmx13.4mm TSOP
(normal type).
Vcc operation voltage : 5.0V
Very low power consumption :
50 mA (Max.) write current
40 mA (Max.) read current
0.4uA (Typ.) CMOS standby current
High speed access time :
- 70
70ns (Max.)
- 100
100ns (Max.)
Input levels are CMOS-compatible
Automatic power down when chip is deselected
Three state outputs
Fully static operation
Data retention supply voltage as low as 2.0V
Easy expansion with CE and OE options
PIN CONFIGURATIONS
BLOCK DIAGRAM
A14
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
2
3
A6
4
A5
A5
A6
5
A9
A4
6
A11
OE
A7
A3
7
Address
Memory Array
512 x 512
A12
A14
A13
A8
A9
18
512
A2
Row
8
28-SOP
A10
CE
Input
A1
9
Decoder
A0
Buffer
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
GND
A11
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
Column I/O
8
Write Driver
Sense Amp
8
8
Data
Output
Buffer
64
Column Decoder
12
OE
A11
A9
1
2
3
4
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A8
CE
WE
OE
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
5
6
7
8
Control
Address Input Buffer
28-TSOP
Vdd
Gnd
A4 A3 A2 A1 A0 A10
9
10
11
12
13
14
A1
A2
P/N DS0035
Rev. 1.1, Jan., 2000
1
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
PIN DESCRIPTIONS
A0-A14 Address Input
These 15 address input select one of the 32768 x 8-bit words
in the RAM
CE Chip Enable Input
CE is active LOW . Chip enable must be active to read from
or write to the device. If chip enable is not active, the device
is deselected and is in a standby power mode. The DQ pins will
be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and
write operations. With the chip selected, when WE is HIGH
and OE is LOW, output data will be present on the DQ pins;
when WE is LOW, the data present on the DQ pins will be
written into the selected memory location.
WE Write Enable Input
OE Output Enable Input
The output enable input is active LOW. If the output enable
is active while the chip is selected and the write enable is
inactive, data will be present on the DQ pins and they will
be enabled. The DQ pins will be in the high impedance
state when OE is inactive.
DQ0 - DQ7 Data Input/Output Ports
These 8 bi-directional ports are used to read data from or
write data into the RAM.
Vcc
Power Supply
GND
Ground
TRUTH TABLE
MODE
Not Selected
Output Disabled
Read
WE
X
CE
H
OE
X
I/O Operation
High Z
Vcc Current
ICCSB, ICCSB1
H
L
H
High Z
ICC
ICC
ICC
H
L
L
DOUT
Write
L
L
X
DIN
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
PARAMETER
RATING
UNITS
V
RANGE
AMBIEN TEMPERATURE
Vcc
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +7.0
0O C to + 70O
-40O C to + 85O
C
4.5 ~ 5.5V
4.5 ~ 5.5V
COMMERCIAL
INDUSTRIAL
TBIAS
TSTG
PT
Temperature Under Bias -40 to +125
OC
OC
W
C
Storage Temperature
Power Dissipation
DC Output Current
-60 to +150
1.0
20
CAPACITANCE(1) (TA = 25O C, f = 1.0 MHz)
IOUT
mA
SYMBOL
CONDITIONS MAX. UNIT
PARAMETER
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
CIN
Input Capacitance
V
IN = 0V
6
8
pF
pF
Input/Output
Capacitance
CDQ
V
I/O = 0V
1. This parameter is guaranteed and not tested.
maximum rating conditions for extended periods may affect reliability.
P/N DS0035
Rev. 1.1, Jan., 2000
2
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
DC ELECTRICAL CHARACTERISTICS ( T
= 0o to + 70oC )
A
PARAMETER
TYP.(1)
UNITS
PARAMETER
TEST CONDITIONS
MIN.
MAX.
NAME
Guaranteed Input Low
V
IL
-0.5
0.3VCC
V
Voltage(2)
Guaranteed Input High
Voltage(2)
Input Leakage Current
V
IH
0.7VCC
VCC+0.2
1
V
IIL
Vcc = Max, VIN = 0V to Vcc
uA
Vcc = Max, CE = VIH, or OE = VIH
,
IOL
Output Leakage Current
1
uA
V
I/O = 0V to Vcc
V
V
OL
Output Low Voltage
Output High Voltage
Vcc = 5.0V, IOL = 2mA
0.4
V
V
OH
Vcc = 5.0V, IOH = -1mA
2.4
CE=VIL, IDQ=0mA, F=Fmax(3)
CE=VIL, IDQ=0mA, F=1MHZ
Vcc = 5.0V
Vcc = 5.0V
Vcc = 5.0V
Vcc = 5.0V
50
40
1
mA
mA
Operating Power Supply
Current
I
CC
Standby Power Supply
Current
Power Down Supply
Current
CE = VIH, IDQ = 0mA,
ICCSB
mA
uA
CE ³ Vcc-0.2V,
0.4
3
ICCSB1
V
IN
Vcc - 0.2V or VIN 0.2V
³
£
1. Typical characteristics are at T
A
= 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. FMAX = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( T
= 0oC to + 70oC )
A
TYP.(1)
SYMBOL
PARAMETER
MIN.
MAX. UNITS
TEST CONDITIONS
CE Vcc - 0.2V,
VDR
Vcc for Data Retention
2.0
³
V
VIN Vcc - 0.2V or VIN 0.2V
³
£
Data Retention Current
CE Vcc -0.2V,
³
0.20
uA
0.01
ICCDR
tCDR
tR
VIN Vcc - 0.2V or VIN 0.2V
³
£
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 2.0V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
V
DR ³ 2.0V
VCC
VCC
Vcc
CE
t
R
t
CDR
CE ³ Vcc - 0.2V
VIH
VIH
P/N DS0035
Rev. 1.1, Jan., 2000
3
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output
5.0/V0V
WAVEFORM
INPUTS
OUTPUTS
5ns
MUST BE
STEADY
MUST BE
STEADY
2.5V
Timing Reference Level
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
AC TEST LOADS AND WAVEFORMS
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
1923 W
1923 W
5.0V
5.0V
FROM L TO H
OUTPUT
OUTPUT
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
100PF
5PF
ANY CHANGE
PERMITTED
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
W
1020W
1020
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
¡¨OFF ¡¨STATE
THEVENIN EQUIVALENT
667 W
OUTPUT
10%
1.73V
ALL INPUT PULSES
VCC
GND
10%
90% 90%
®
®
¬
¬ 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS (over the operating range)
READ CYCLE
JEDEC
PARAMETER
NAME
DESCRIPTION
UNIT
MX66C256-70
MX66C256-10
PARAMETER
NAME
MIN.
TYP. MAX. MIN. TYP. MAX.
tAVAX
tAVQV
tELQV
tGLQV
tELQX
tGLQX
tEHQZ
tGHQZ
tAZQX
tRC
tAA
70
Read Cycle Time
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
50
100
100
50
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Output Disable to Output Address Change
10
10
0
10
10
0
35
30
35
30
0
0
10
10
1. Typical characteristics are at Vcc = 5.0V, T
= 25oC.
A
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
P/N DS0035
Rev. 1.1, Jan., 2000
4
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
READ CYCLE2 (1,3,4)
CE
t ACS
(5)
CHZ
t
(5)
t
CLZ
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
t ACS
t
t
OHZ
(1,5)
CHZ
(5)
CLZ
t
D OUT
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL
.
3. Address valid prior to or coincident with CE transition low .
4. OE = VIL
.
±
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
P/N DS0035
Rev. 1.1, Jan., 2000
5
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
AC ELECTRICAL CHARACTERISTICS (over the operating range)
WRITE CYCLE
JEDEC
PARAMETER
NAME
DESCRIPTION
MX66C256-70
MIN. TYP.
UNIT
PARAMETER
NAME
MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
Write Cycle Time
70
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set up Time
Address Valid to End of Write
Write Pulse Width
70
50
0
Write Recovery Time
(CE , WE)
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
30
30
40
0
tOHZ
tOW
Output Disable to Output in High Z
End of Write to Output Active
0
5
1. Typical characteristics are at Vcc = 5.0V, T
= 25oC.
A
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
(3)
t
WR
OE
(11)
t
CW
(5)
CE
t
AW
t
WP
(2)
WE
t
AS
(4,10)
OHZ
t
D OUT
t
DH
t
DW
D IN
P/N DS0035
Rev. 1.1, Jan., 2000
6
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
WRITE CYCLE2 (1,6)
t
WC
ADDRESS
CE
(11)
CW
t
(5)
t
AW
t
WP
(2)
t
DH
WE
t AS
(4,10)
t WHZ
(7)
(8)
D OUT
t
DW
(8)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE active
and WE low. All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of
write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the
WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals
of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1b.
±
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
P/N DS0035
Rev. 1.1, Jan., 2000
7
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
ORDERING INFORMATION
SPEED
(ns)
ORDERING
PART NUMBER
PACKAGE
TYPE
TEMPERATURE
RANGE
70
0O C to + 70O
0O C to + 70O
-40O C to + 85O
-40O C to + 85O
0O C to + 70O
0O C to + 70O
-40O C to + 85O
-40O C to + 85O
C
C
MX66C256MC- 70
MX66C256MC-10
MX66C256MI- 70
MX66C256MI-10
MX66C256TC- 70
MX66C256TC- 10
MX66C256TI- 70
MX66C256TI-10
SOP-28PIN
SOP-28PIN
SOP-28PIN
SOP-28PIN
100
70
C
C
100
70
C
TSOP-28PIN
TSOP-28PIN
TSOP-28PIN
TSOP-28PIN
100
70
C
C
C
100
n PACKAGE DIMENSIONS
P/N DS0035
Rev. 1.1, Jan., 2000
8
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
MX66C256
n PACKAGE DIMENSIONS (continued)
P/N DS0035
Rev. 1.1, Jan., 2000
9
Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131
Tel (408)453-8088 Fax (408)451-0876 www.macronix.com
相关型号：
MX66L51235FXDI-10G
3V, 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO® (SERIAL MULTI I/O) FLASH MEMORY
Macronix
©2020 ICPDF网 联系我们和版权申明