MX26C1000BTI-10 [Macronix]
1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM; 1M - BIT [ 128K ×8 ] CMOS多时间可编程EPROM
| 型号： | MX26C1000BTI-10 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 1M-BIT [128K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM |
| 文件： | 总23页 (文件大小：987K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
MX26C1000B
1M-BIT[128Kx8]CMOS
MULTIPLE-TIME-PROGRAMMABLE-EPROM
FEATURES
• 128Kx 8 organization
• 50 minimum erase/program cycles
• Chip erase time: 1 (typ.)
• Chip program time: 6.25 (typ.)
• Single +5V power supply
• +12Vprogrammingvoltage
• Fast access time:90/100/120/150 ns
• Totally static operation
• Completely TTL compatible
• Operatingcurrent:30mA
• Standby current: 100uA
• Typical fast programming cycle duration 10us/byte
• Package type:
- 32 pin plastic DIP
- 32 pin PLCC
- 32 pin TSOP
- 32 pin SOP
GENERAL DESCRIPTION
The MX26C1000B is a 5V only, 1M-bit, MTP EPROMTM
(Multiple Time Programmable Read Only Memory). It is
organized as 128K words by 8 bits per word, operates
fromasingle+5volt supply,hasastaticstandby mode,
and features fast single address location programming.
AllprogrammingsignalsareTTLlevels,requiringasingle
pulse. It is design to be programmed and erased by an
EPROM programmer or on-board. The MX26C1000B
supportsaintelligentfastprogrammingalgorithmwhich
can result in programming time of less than one minute.
This MTP EPROMTM is packaged in industry standard
32pindual-in-linepackages,32leadPLCC,32leadSOP
and 32 lead TSOP packages.
PIN CONFIGURATIONS
32 PDIP/SOP
32PLCC
VCC
WE
NC
A14
A13
A8
VPP
A16
A15
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
4
1
32
30
29
3
A14
A13
A8
5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
4
5
A6
6
A9
A5
7
A9
A11
OE
A10
CE
Q7
A4
8
A11
OE
A10
CE
Q7
9
25
MX26C1000B
A3
9
A2
10
11
12
13
14
15
16
A1
A0
Q6
Q0
13
21
Q5
Q1
14
17
20
Q4
Q2
Q3
GND
32 TSOP
PIN DESCRIPTION
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
SYMBOL
A0~A16
Q0~Q7
CE
PIN NAME
Address Input
2
A8
3
A13
A14
NC
4
5
DataInput/Output
Chip Enable Input
6
WE
VCC
VPP
A16
A15
A12
A7
7
8
MX26C1000B
9
OE
Output Enable Input
Write Enable Input
ProgramSupplyVoltage
NoInternalConnection
Power Supply Pin (+5V)
GroundPin
10
11
12
13
14
15
16
WE
VPP
A6
A1
A5
A2
NC
A4
A3
VCC
GND
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1
MX26C1000B
BLOCK DIAGRAM
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
CE
OE
WE
MACHINE
(WSM)
LOGIC
STATE
MX26C1000B
FLASH
ADDRESS
LATCH
REGISTER
ARRAY
ARRAY
A0-A16
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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MX26C1000B
Theset-upProgramcommand(40H)istheonlycommand
thatrequiresatwosequenceresetcycle.ThefirstReset
commandisinterpretedasprogramdata.However,FFH
dataisconsiderednulldataduringprogrammingoperations
(memory cells are only programmed from logica "1" to
"0". The second Reset command safely aborts the
programming operation and resets the device to the
Readmode.
FUNCTIONAL DESCRIPTION
When the MX26C1000B is delivered, or it is erased, the
chip has all 1000K bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C1000B through the
procedure of programming.
ERASE ALGORITHM
This detailed information is for your reference. It may
prove esier to always issue the Reset command two
consecutivetimes.Thiseliminatestheneedtodetermine
if you are in the set-up Program state or not.
The MX26C1000B do not required preprogramming
beforeaneraseoperation.Theerasealgorithmisaclose
loop flow to simultaneously erase all bits in the entire
array. Erase operation starts with the initial erase
operation. Erase verification begins at address 0000H
by reading data FFH from each byte. If any byte fails
to erase. the entire chip is reerased. to a maximum for
30 pulse counts of 100ms duration for each pulse. The
maximum cumulative erase time is 3s. However. the
deviceisusuallyerasedinnomorethan3pulses. Erase
verification time can be reduced by storing the address
of the last byte that failed. Following the next erase
operation verification may start at the stored address
location. JEDEC standard erase algorithm can also be
used. But erase time will increase by performing the
unnecessarypreprogramming.
SET-UP PROGRAM/PROGRAM
A three-step sequence of commands is required to
performacompleteprogramoperation:SetUpProgram-
Program-ProgramVerify.Thedeviceisbulkerasedand
bytebybyteprogramming.Thecommand40Hiswritten
to the command register to initiate Set Up Program
operation. Address and data to be programmed into the
byte are provided on the second WE pulse. Addresses
arelatchedonthefallingedgeoftheWEpulse, dataare
latched on the rising edge of the WE pulse. Program
operation begins on the rising edge of the second WE
pulse, and terminate of the next rising edge of the WE
pulse. Refer to AC Characteristics and Waveforms for
specific timing parameters.
PROGRAM ALGORITHM
The device is programmed byte by byte. A maximum
of 25 pulses. each of 10us duration is allowed for each
byte being programmed. The byte may be programmed
sequentially or by random. After each program pulse,
a program verify is done to determine if the byte has
been successfully programmed.
COMMAND REGISTER
When high voltage is applied to VPP the command
registerisenabled.Read,write,standby,outputdisable
modes are available. The read, erase, erase verify,
program,programverifyandDeviceIDareaccessedvia
the command register. Standard microprocessor write
timingsareusedtoinputacommandtotheregister.This
register serves as the input to an internal state machine
which controls the operation mode of the device. An
internal latch is used for write cycles, addresses and
dataforprogramminganderaseoperations.
Programming then proceeds to the next desired byte
location. JEDEC standard program algorithms can be
used.
RESET
The Reset command initializes the MTP EPROMTM
devicetotheReadmode.Inaddition,italsoprovidesthe
user with a safe method to abort any device operation
(includingprogramorerase).TheResetcommandmust
bewrittentwoconsecutivetimesaftertheset-upProgram
command (40H). This will safely abort any previous
operation and initialize the device to the Read mode.
NO INTEGRATED STOP TIMER FOR ERASE
Leading industry flash technology requires a stop timer
built into the flash chip to prevent the memory cells from
going into depletion due to over erase. The 1 Mbit MTP
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MX26C1000B
EPROMTM is built on an innovative cell concept in which
over erasing the memory cell is impossible.
force 12.0 ±0.5 V on address line A9 of the device.
Two identifier bytes may then be sequenced from the
device outputs by toggling address line A0 from VIL to
VIH. All other address lines must be held at VIL during
auto identify mode.
DATA WRITE PROTECTION
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C1000B, these two identifier bytes are given
intheModeSelectTable. Allidentifiersformanufacturer
and device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
The design of the device protects against accidental
erasure or programming. The internal state machine is
automaticallyresettothereadmodeonpower-up.Using
control register architecture, alteration of memory can
only occur after completion of proper command
sequences.ThecommandregisterisonlyactivewhenV
PP isathighvoltage.whenVPP =VPPL ,thedevicedefaults
to the Read Mode. Robust design features prevent
inadvertentwritecyclesresultingfromVCC power-upand
power-downtransitionsorsystemnoise.Toavoidinitiation
ofwritecycleduringVCC power-up,awritecycleislocked
outforVCC lessthan4V.Thetwo-commandprogramand
erase write sequence to the command register provide
additional software protection against spurious data
changes.
READ MODE
The MX26C1000B has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
datatotheoutputpins, independentofdeviceselection.
Assuming that addresses are stable, address access
time(tACC)isequaltothedelayfromCEtooutput(tCE).
DataisavailableattheoutputstOEafterthefallingedge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
PROGRAM VERIFY MODE
Verificationshouldbeperformedontheprogrammedbits
to determine that they were correctly programmed.
Verification should be performed with OE and CE, at
VIL, WE at VIH, and VPP at its programming voltage.
STANDBY MODE
The MX26C1000B has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ±0.3 V.
The MX26C1000B also has a TTL-standby mode which
reduces the maximum VCC current to 1.5 mA. It is
placed in TTL-standby when CE is at VIH. When in
standby mode, the outputs are in a high-impedance
state, independent of the OE input.
ERASE VERIFY MODE
Verification should be performed on the erased chip to
determine that the whole chip(all bits) was correctly
erased. Verification should be performed with OE and
CE at VIL, WE at VIH, and VCC = 5V, VPP = 12.5V
AUTO IDENTIFY MODE
SYSTEM CONSIDERATIONS
Theautoidentifymodeallowsthereadingoutofabinary
code from MTP EPROM that will identify its
manufacturer and device type. This mode is intended
for use by programming equipment for the purpose of
automatically matching the device to be programmed
with its corresponding programming algorithm. This
modeisfunctionalinthe25°C±5°Cambienttemperature
range that is required when programming the
MX26C1000B.
During the switch between active and standby
conditions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The magnitude
of these transient current peaks is dependent on the
outputcapacitanceloadingofthedevice. Ataminimum,
a0.1uFceramiccapacitor(highfrequency,lowinherent
inductance) should be used on each device between
VCCandGNDtominimizetransienteffects. Inaddition,
to overcome the voltage drop caused by the inductive
Toactivatethismode,theprogrammingequipmentmust
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MX26C1000B
effects of the printed circuit board traces on EPROM
arrays, a 4.7 uF bulk electrolytic capacitor should be
used between VCC and GND for each of the eight
devices. The location of the capacitor should be close
to where the power supply is connected to the array.
OUTPUT DISABLE
Output is disabled when OE is at logre high. When in
outputdisabledallcircuitryisenabled.Excepttheoutput
pins are in a high impedance state(TRI-ATATE).
Table 1: BUS OPERATIONS
Mode
VPP(1)
A0
A0
X
A9
A9
X
CE
VIL
VIL
VIH
OE
VIL
VIH
X
WE
VIH
VIH
X
Q0~Q7
Read
VPPL
VPPL
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
Data Out
Tri-State
Tri-State
Data=C2H
Data=CFH
DataOut(3)
Tri-State
Tri-State
Data Inb
READ-ONLY
MODE
OutputDisable
Standby
X
X
ManufacturerIdentification
Device Identification
Read
VIL
VID(2) VIL
VIL
VIL
VIL
VIH
X
VIH
VIH
VIH
VIH
X
VIH VID(2) VIL
A0
X
A9
X
VIL
VIL
VIH
VIL
COMMAND
MODE
OutputDisable
Standby(4)
X
X(5)
A9
Program
A0
VIH
VIL
Note:
1. Refer to DC Characteristics. When VPP=VPPL memory contents can be read but not written or erased.
2. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
3. Read operations with VPP=VPPH may access array data or the intelligent identifier codes.
4. With VPP at high voltage the standby current equals ICC+IPP(standby).
5. Refer to Table 2 for vaild data-in during a write operation.
6. X can be VIL or VIH.
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MX26C1000B
erase operation. The two-step command prevents
accidental alteration to memory array. Erase operation
startswiththerisingedgeoftheWE pulseandterminates
with the rising edge of the next WE pulse, which in this
case is the erase verify command.
COMMAND MODE
The 1 Mbit MTP EPROMTM is in Command mode when
highvoltageVPPH isappliedtotheVPP pin.Inthisstatethe
available functions are Read, Program, Program Verify,
Erase and Erase Verify. Reset are selected by writing
commandstotheinputregister.Datafromtheregisterare
input to the state machine. The output from the state
machine determines the function of the device. The
command register serves as a latch to store data for
executing commands. It does not occupy address- able
memory location. Standard microprocessor write timing
is used. Table 2 defines the register commands. The
commandregisteriswrittenbybringingWEtoalogic-low
Level(VIL),whileCEislow.Addressesarelatchedonthe
fallingedgeofWE,whiledataislatchedontherisingedge
of the WE pulse.
ERASE VERIFY
Eacheraseoperationisfollowedbyaneraseverify. The
commandA0Hiswrittenintothecommandregister.The
address of the bytes to be verified is supplied with the
command. The address is latched on the falling edge of
the WE pulse. A reading FFH is returned to confirm all
bits in the byte are erased. This sequence of Set Up
Erase- Erase continues for each address until FFH is
returned. This indicates the entire memory array is
erasedandcompletestheoperation.Eraseverifyoperation
starts at address 0000H and ends at the last address.
Maximum erase pulse duration for the 1Mbit MTP
EPROMTM is100mswithamaximum30pulses.Referto
AC Characteristics and Waveforms for specific timing
parameters.
StandbyandOutputdisablefunctionsarethesameasin
Read Mode, controlled by CE and OE. If the device is
deselected during erasure, programming, or erase/
programverification,thedevicedrawsactivecurrentuntil
theoperationsterminate.
READ COMMAND
To read memory content, write 00H into the command
register while high voltage is applied to
VPP pin(VPP =VPPH).Microprocessorreadcycleretrieves
the data . The device remains enable for read until the
data in the command register are altered. The device is
defaultinreadmodewhenpowerup.Thisistoensureno
accidentalalterationofthememoryoccursduringpower
transition. Refer to AC Read Characteristics and
Waveforms for specific timing parameters.
SET UP ERASE/ERASE
Preprogram operation is not required prior to the erase
operation. A sequence of commands is required to
performacompleteeraseoperation:setuperase,erase,
and erase verify. High voltage is applied to the V PP pin
(VPP=VPPH).Thecommand20Hiswrittentothecommand
register to initiate the set-up erase mode.
ERASE OPERATION
The same command, 20H, is again written to the
command register. This second command starts bulk
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MX26C1000B
PROGRAMMING ALGORITHM FLOW CHART
Start
Programming
Apply V
PPH
PLSCNT=0
Write Set-up Program CMD
Write Program Cmd(A/D)
Time Out 10us
Write Program Verify Cmd
Time out 6us
Read Data From Device
NO
NO
Verify Data ?
YES
Inc PLSNT=25 ?
YES
NO
Last Address ?
Increment Address
YES
Write Read CMD
Apply V
PPL
Apply V
PPL
Programming
Completed
Programming
Error
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MX26C1000B
ERASE ALGORITHM FLOW CHART
Start
Erasure
Apply V
PPH
Address=00H
PLSCNT=0
Write Set-up Erase and
Erase Cmd
Time Out 100ms
Write Erase Verify Cmd
Time out 6us
Read Data From Device
NO
NO
Data=FFH ?
YES
Inc PLSNT=30 ?
YES
NO
Last Address ?
Increment Address
YES
Write Read CMD
Apply V
PPL
Apply V
PPL
Erasure
Completed
Erasure
Error
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MX26C1000B
SWITCHING TEST CIRCUITS
DEVICE
UNDER
TEST
1.8K ohm
+5V
DIODES = IN3064
OR EQUIVALENT
CL
6.2K ohm
CL = 100 pF including jig capacitance
SWITCHING TEST WAVEFORMS
2.0V
0.8V
2.0V
TEST POINTS
AC driving levels
0.8V
OUTPUT
INPUT
AC TESTING: AC driving levels are 2.4V/0.4V for commercial grade.
Input pulse rise and fall times are equal to or less than 10ns.
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MX26C1000B
NOTICE:
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended period may
affect reliability.
RATING
VALUE
AmbientOperatingTemperature -40oCto85oC
StorageTemperature
Applied Input Voltage
AppliedOutputVoltage
VCC to Ground Potential
A9 & VPP
-65oCto125oC
-0.5V to 7.0V
-0.5V to VCC + 0.5V
-0.5V to 7.0V
NOTICE:
-0.5V to 13.5V
Specifications contained within the following tables are
subject to change.
DC/AC OPERATING CONDITION FOR READ OPERATION
MX26C1000B
-90
-100
-120
-150
OperatingTemperature Industrial
Vcc Power Supply
-40°C to 85°C
5V ±10%
-40°Cto85°C
5V ±10%
-40°Cto85°C
5V ±10%
-40°Cto85°C
5V ±10%
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
CIN
PARAMETER
TYP.
8
MAX.
12
UNIT
pF
CONDITIONS
InputCapacitance
OutputCapacitance
VPP Capacitance
VIN = 0V
COUT
CVPP
8
12
pF
VOUT = 0V
VPP = 0V
18
25
pF
DC CHARACTERISTICS TA = -45°C ~ 85°C, VCC=5V±10%
SYMBOL PARAMETER
MIN.
-0.3
2.0
MAX.
UNIT CONDITIONS
VIL
Input Low Voltage
0.8
VCC + 0.5
0.4
V
V
VIH
Input High Voltage
VOL
VOH
ICC1
ISB
OutputLowVoltage
V
IOL = 2.1mA, VCC=VCC MIN
OutputHighVoltage
2.4
V
IOH = -0.4mA
VCC Active Current
30
100
1.5
100
30
mA
uA
mA
uA
mA
CE = VIL, OE=VIH, f=5MHz
CE=VCC+0.2V, VCC=VCC MAX
CE=VIH, VCC=VCC MAX
CE = OE = VIL, VPP = 5.5V
CE=WE=VIL, OE=VIH
VCCStandbyCurrent(CMOS)
VCCStandbyCurrent(TTL)
VPPReadCurrent
ISB
IPP
IPP2
VPP Supply Current
(Program/Erase)
ILI
InputLeakageCurrent
OutputLeakageCurrent
Fast Programming Supply Voltage
FastProgrammingVoltage
-10
-10
10
10
uA
uA
V
VIN = 0 to 5.5V
ILO
VOUT = 0 to 5.5V
VCC1
VPP1
6.0
6.5
13.0
12.5
V
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MX26C1000B
AC RAED CHARACTERISTICS OVER OPERATING RANGE WITH VPP=VCC
Symbol
Jeded STD
tAVAV TRC
tELQV TCE
Parameter
90
100
120
150
Unit
ns
MIN MAX MIN MAX MIN MAX MIN MAX
Read Cycle Time
CE Access Time
90
0
100
0
120
0
150
0
90
90
40
100
100
45
120
120
50
150 ns
150 ns
tAVQV TACC Address Access Time
0
0
0
0
tGLQV TOE
tELQX TLZ
tEHQZ TDF
OE Access Time
0
0
0
0
65
50
50
0
ns
ns
ns
ns
ns
CE to Output in Low Z(Note 1)
0
0
0
0
Chip Disable to Output in High Z(Note 2) 0
30
30
0
0
35
35
0
0
35
35
0
0
tGLQX TOLZ OE to Output in Low Z (Note 1)
0
0
0
0
0
tGHQZ TDF
tAXQX TOH
Output Disable to Output in High Z
0
0
0
(Note1)
Output Hold from Address, CE or OE,
change
ns
tWHGL TWHGL Write Recovery Time Before Read
6
6
6
6
us
us
tVCS TVCS VCC Setup Time to Valid Read (Note 2)
50
50
50
50
Note:
1. Sampled: not 100% tested.
2. Guaranteed by design. not tested.
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MX26C1000B
AC CHARACTERISTICS - WRITE/ERASE/PROGRAM OPERATIONS
Symbol
JEDED
Parameter
90
100
120
150
Unit
STD
MIN MAX MIN MAX MIN MAX MIN MAX
tAVAV
tAVWL
tWLAX
tDVWH
tWHDX
tWHGL
tGHWL
tELWL
TWC Write Cycle Time (Note 3)
TAS Address Setup Time
90
0
100
0
120
0
150
0
ns
ns
ns
ns
ns
us
us
ns
ns
ns
ns
us
TAH Address Hold Time
40
40
10
6
40
40
10
6
40
40
10
6
40
40
10
6
TDS Data Setup Time
TDH Data Hold Time
TWR Write Recovery Time Before Read
TDES Read Recovery Time Before Write
0
0
0
0
tCS
tCH
tWP
CE Setup Time Before Write
CE Hold Time
0
0
0
0
tWHEH
tWLWH
tWHWL
tWHWH1
0
0
0
0
Write Pulse Width
50
20
10
50
20
10
50
20
10
50
20
10
tWPH Write Pulse Width High
DurationofProgrammingOperation
(Note2)
tWHWH2
tVPEL
DurationofEraseOperation(Note2)
VPP Setup Time to Chip Enable Low
(Note3)
100
1
100
1
100
1
100
1
ms
us
tVCS
VCC Setup Time to Chip Enable Low
(Note3)
50
50
50
50
us
tVPPR
tVPPF
VPP Rise Time (Note 3) 90% VPPH
VPP Fall Time (Note 3) 10% VPPH
500
500
500
500
500
500
500
500
ns
ns
Note:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to
AC Characteristics for Read Only Operations.
2. Maximum pulse widths not required because the on-chip program/erase circuitry will terminate the pulse widths
internally on the device.
3. Not 100% tested.
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MX26C1000B
Table 2: Command Definitions
Command
Bus
First Bus Cycle
Second Bus Cycle
Cycles.
Req
1
Operation
Write
Address1 Data2
Operation
Address1
Data2
ReadMemory
SetupErase/Erase
Erase Verify
X
X
00H
20H
A0H
40H
C0H
FFH
2
Write
Write
Read
Write
Read
Write
X
X
20H
EVD
PD
2
Write
EA
X
SetupProgram/Program
ProgramVerify
Reset
2
Write
PA
X
2
Write
X
PVD
FFH
2
Write
X
X
1 EA=Erase Address: address of memory location to be read during erase verify.
PA=Program Address: address of memory location to be Programmed.
Address are latched on the falling edge of the WE pulse.
2 EVD=Erase Verify Data: data read from location EA during erase verify.
PD=Program Data: data to be programmed at location PA. Data is latched on the rising edge of WE.
PVD=Program Verify Data: data read from location PA during program verify. PA is latched on the Program
command.
REV. 0.6, OCT. 04, 2001
P/N: PM0767
13
MX26C1000B
AC WAVEFORMS FOR READ OPERATIONS
Outputs
enabled
Device and
Address Selection
Data Valid
Power-Up Standby
Standby Power-Up
Address
Addresses Stable
tAVAV(tRC)
CE
OE
tEHQZ(tDF)
tGHQZ(tDF)
tWHGL
tGLQV(tOE)
tELQV(tCE)
WE
tAXQX(tOH)
tGLQX(tOLZ)
tELQX(tLZ)
High Z
High Z
tVCS
Data
Output Valid
tAVQV(tACC)
5.0V
0V
VCC
REV. 0.6, OCT. 04, 2001
P/N: PM0767
14
MX26C1000B
AC WAVEFORMS FOR ERASE OPERATIONS
Program Command
Latch Program Address
Programming
Power-Up
Standby
Verify
Command
Programming Standby
and Data
Setup Program
Verification
Power-Down
Addresses
tWLAX(tAH)
tAVAV(tWC)
tAVWL(tAS)
tAVAV(tRC)
tAVWL(tAS)
CE
OE
tEHQZ(tDF)
tGHQZ(tDF)
tELWL(tCS)
tWHEH(tCH)
tWHWH1
tWHGL
tGHWL(tDES)
tWHWL(tWPH)
tWLWH(tWP)
tDVWH(tDS)
tGLQV(tOE)
tAXQX(tOH)
WE
tGLQX(tOLZ)
tWHDX(tDH)
DATA
IN=40h
DATA
IN=PD
DATA
IN=C0h
VALID DATA
OUT
tELQX(tLZ)
Data
tVCS
tELQV(tCE)
5V
VCC
VPP
tVPEL
0V
VPPH
VPPL
REV. 0.6, OCT. 04, 2001
P/N: PM0767
15
MX26C1000B
AC WAVEFORMS FOR PROGRAMMING OPERATIONS
Program Command
Power-Up
Standby
Latch Address
and Data
Verify
Command
Programming Standby
Programming
Setup Program
Verification
Power-Down
Addresses
tWLAX(tAH)
tAVAV(tWC)
tAVWL(tAS)
tAVAV(tRC)
tAVWL(tAS)
CE
OE
tEHQZ(tDF)
tGHQZ(tDF)
tELWL(tCS)
tWHEH(tCH)
tWHWH1
tWHGL
tGHWL(tDES)
tWHWL(tWPH)
tWLWH(tWP)
tDVWH(tDS)
tGLQV(tOE)
tAXQX(tOH)
WE
tGLQX(tOLZ)
tWHDX(tDH)
DATA
IN=20h
DATA
IN=20h
DATA
IN=C0h
VALID DATA
OUT
tELQX(tLZ)
tELQV(tCE)
Data
tVCS
5V
VCC
VPP
tVPEL
0V
VPPH
VPPL
REV. 0.6, OCT. 04, 2001
P/N: PM0767
16
MX26C1000B
ORDERING INFORMATION
PLASTICPACKAGE
PART NO.
ACCESS TIME(ns)
OPERATING
STANDBY
OPERATING
TEMPERATURE
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
PACKAGE
Current MAX.(mA)
Current MAX.(uA)
100
MX26C1000BPC-90
MX26C1000BQC-90
MX26C1000BMC-90
MX26C1000BTC-90
MX26C1000BPC-10
MX26C1000BQC-10
MX26C1000BMC-10
MX26C1000BTC-10
MX26C1000BPC-12
MX26C1000BQC-12
MX26C1000BMC-12
MX26C1000BTC-12
MX26C1000BPC-15
MX26C1000BQC-15
MX26C1000BMC-15
MX26C1000BTC-15
MX26C1000BPI-90
MX26C1000BQI-90
MX26C1000BMI-90
MX26C1000BTI-90
MX26C1000BPI-10
MX26C1000BQI-10
MX26C1000BMI-10
MX26C1000BTI-10
MX26C1000BPI-12
MX26C1000BQI-12
MX26C1000BMI-12
MX26C1000BTI-12
MX26C1000BPI-15
MX26C1000BQI-15
MX26C1000BMI-15
MX26C1000BTI-15
90
90
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
32 Pin DIP
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
90
100
90
100
100
100
100
100
120
120
120
120
150
150
150
150
90
100
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
100
100
100
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
100
100
100
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
100
100
100
90
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
90
100
90
100
100
100
100
100
120
120
120
120
150
150
150
150
100
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
100
100
100
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
100
100
100
100
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
100
100
REV. 0.6, OCT. 04, 2001
P/N: PM0767
17
MX26C1000B
PACKAGE INFORMATION
32-PIN PLASTIC DIP(600 mil)
REV. 0.6, OCT. 04, 2001
P/N: PM0767
18
MX26C1000B
32-PINPLASTICLEADEDCHIPCARRIER(PLCC)
REV. 0.6, OCT. 04, 2001
P/N: PM0767
19
MX26C1000B
32-PIN PLASTIC TSOP
REV. 0.6, OCT. 04, 2001
P/N: PM0767
20
MX26C1000B
32-PIN PLASTIC SOP (450 mil)
REV. 0.6, OCT. 04, 2001
P/N: PM0767
21
MX26C1000B
REVISION HISTORY
RevisionNo. Description
Page
All
Date
DEC/11/2000
0.1
ChangetitlefromMX26C1000AtoMX26C1000B
To add erase/program cycle
P1
0.2
0.3
Change Device ID code from 30H to CEH
To added 32SOP/TSOP types package and access time 150ns
Modify device ID old CEH-->New CFH
P5
DEC/28/2000
P1,11,12,17,18 MAR/27/2001
P5
Modify read ID method
P4,5,6,13
P10
P10
P10
P18~21
P1
Modify erase/program cycle from 100ns to 50ns
Modify VCC Standby Current(TTL) from 1mA to 1.5mA
To added VCC1 & VPP1 to DC Characteristics Table
Modify Package Information
To added chip erase time / chip program time
Modify Package Information
0.4
0.5
0.6
APR/23/2001
JUL/04/2001
OCT/04/2001
P18~21
P15
Modify the Programming Operations Timing Waveforms
REV. 0.6, OCT. 04, 2001
P/N: PM0767
22
MX26C1000B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
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FAX:+65-348-8096
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FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
23
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