MX23L6412TC-20 [Macronix]
SEQUENTIAL 64M-BIT MASK ROM; 序贯64M - BIT掩膜ROM![MX23L6412TC-20](http://pdffile.icpdf.com/pdf1/p00118/img/icpdf/MX23L6412TC-20_647006_icpdf.jpg)
型号: | MX23L6412TC-20 |
厂家: | ![]() |
描述: | SEQUENTIAL 64M-BIT MASK ROM |
文件: | 总8页 (文件大小:195K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MX23L6412
SEQUENTIAL64M-BITMASKROM
FEATURES
• Bitorganization
• Current
- 4M x 16 (word mode only)
-256words/page
-Operating:25mA(max.)
- Address input:2mA(max.)
-Standby:20uA(max.)
• Supply voltage
- 3.0V~3.6V
- Total 16K pages
• Sequential access at 200ns cycle time in a page
• Asynchronous chip enable input (ALEH, ALEL)
• Access time
• Package
- Read latency time: 950ns
- Read cycle time: 200ns
- RD access time: 150ns
- 32 pin TSOP
ORDER INFORMATION
Part No.
Read CycleTime
Package
MX23L6412TC-20
200ns
32 pin TSOP
GENERAL DESCRIPTION
are not used internally. As for low 16 bit address, A1~A8
are through 8 bit address counter, A9~A15 are through 7
bit address register, and A0 are not used internally. High
address input must be done before low address input,
and both address inputs are needed for page change or
address change in a same page. After address inputs,
CE goes high at ALEH falling edge and RD doesn't toggle,
the ROM is in stand-by mode.
The product is a 64M bits (4M x 16) mask ROM
composed of 16K pages, and each consists of 256 words
memory cell array. This mask ROM has a 16 bit address
input / data output bus (AD0~AD15), two address latch
enable pins (high : ALEH, low : ALEL), a read strobe
(RD).
There are 3 modes, Stand-by mode, Active mode, and
Address input mode. Stand-by mode is a non-operating
state, and has the smallest current dissipation. Active
mode is an operating state, and data output is possible.
Address input mode is a state of address input.
After ROM turned into Active mode from Address input
mode, it takes tL time to read. In a page, sequential
read access is possible at tCYC cycle time. Sequential
read operation (increment of internal address counter) is
done at every falling edge of RD. At the end of a page,
internal address counter raps around to the beginning of
the page.
Address input is through AD bus when ALEL is high.
The high and low 16 bit addresses are latched at
ALEH’sand ALEL falling edges. As for high 16 bit ad-
dress, A0~A6 are through 7 bit address register, A7~A15
P/N:PM0652
REV. 1.5, MAR. 11, 2003
1
MX23L6412
PIN CONFIGURATION
32TSOP
PIN DESCRIPTION
Symbol
AD0~AD15
ALEH
ALEL
CE
Pin Function
NC
CE
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
Address Input / Data Output
Address Latch Enable High
Address Latch Enable Low
Chip Enable Input
2
RD
VSS
AD12
AD13
AD14
AD15
NC
3
VCC
AD11
AD10
AD9
AD8
NC
4
5
6
7
8
MX23L6412
NC
9
NC
RD
Read Strobe Input
Power Supply Pin
AD0
AD1
AD2
AD3
VCC
ALEL
NC
10
11
12
13
14
15
16
AD7
AD6
AD5
AD4
VSS
ALEH
NC
VCC
VSS
Ground Pin
NC
No Connection
TRUTH TABLE
Mode
Operation
CE
ALEH
ALEL
RD
X
AD Bus
Address Input
Address Input
Active
High address input
Low address input
Internally active
Data read
L
H
H
H
L
Address input
Address input
Floating
X
X
X
X
L
X
L
H
L
Active
L
L
Data output
Floating
Stand-by
Stand-by *
H-->L
L
X
Note: Please see "standby mode" timing diagram.
BLOCK DIAGRAM
RD
ALEH
ALEL
Enable
CE
Reg.
CE
AD0
AD1
AD2
AD3
AD4
AD5
Address
Register
Memory Cell Array
256 words/ Page
AD6
AD7
AD8
AD9
Address
Register
AD10
AD11
AD12
AD13
AD14
AD15
Column Decoder
Latch x 16
Address
Presettable
Counter
Enable
Clock
P/N:PM0652
REV. 1.5, MAR. 11, 2003
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MX23L6412
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Ratings
Voltage on any Pin Relative to VSS
Ambient OperatingTemperature
Storage Temperature
-0.5V to 4.6V
0°C to 70°C
-55°C to 125°C
Topr
Tstg
DC CHARACTERISTICS (Ta = 0° C~70°C, VCC = 3.3V±10%)
Item
Symbol MIN.
MAX.
-
Conditions
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
Address Input Current
VOH
VOL
VIH
VIL
2.0V
-
IOH = -0.4mA
IOL = 2mA
0.4V
2.0V
-0.5V
-10uA
-10uA
-
VCC+0.5V
0.8V
ILI
10uA
10uA
25mA
2mA
VIN = 0V to 3.6V
ILO
VOUT = 0V to 3.6V
ICC1
ICC2
Cycle = 200ns,VIN =VIH orVIL, active mode
Cycle = 100ns, VIN = VIH or VIL, address
input mode
-
Standby Current (CMOS)
ISTB
-
20uA
Cycle = 200ns, VIN = VCC±0.3V or
0V±0.3V,stand-by mode
Input Capacitance
Output Capacitance
CIN
-
-
12pF
12pF
Ta = 25° C, f = 5MHz, VIN = 0V
Ta = 25° C, f = 5MHz, VOUT = 0V
COUT
AC CHARACTERISTICS (Ta = 0°C~70°C, VCC = 3.3V±10%)
Item
Symbol
tALES
tALED
tAS
MIN.
70ns
70ns
30ns
0
MAX.
Conditions
ALEL SetupTime
ALE Delay Time
Address SetupTime
Address HoldTime
Read LatencyTime
Read CycleTime
CE Setup Time
CE Hold Time
tAH
tL
950ns
200ns
50ns
0ns
tCYC
tCES
tCEH
tRD
RD Access Time
RD HighTime
150ns
40ns
tRDH
tOH
50ns
0
Output HoldTime
Output Float Time
ReleaseTime
tDF
tR
0
P/N:PM0652
REV. 1.5, MAR. 11, 2003
3
MX23L6412
TIMING DIAGRAM
Address Input Mode and Active Mode
Address Input Mode
Active Mode
ALEH
tALES
tCES
tL
tALED
ALEL
tCYC
CE
RD
tCEH
tR
tRDH
tOH
tAS
tAH
tRD
AD[0:15]
A H
A L
D0
D1
AH
DN
tDF
Standby Mode
Active Mode
CE Latch
Standby Mode
(1)
tALED
ALEL
ALEH
tALES
tCEH
CE
tCES
Active Mode
CE Latch
Standby Mode
(2)
ALEL
(Low)
tALES
ALEH
CE
P/N:PM0652
REV. 1.5, MAR. 11, 2003
4
MX23L6412
AC Test Conditions
2.4V
0.4V
2.4V
0.4V
TEST POINTS
TEST POINTS
INPUT
2.0V
0.8V
2.0V
0.8V
OUTPUT
* Input Rise and Fall Times : <10ns
* Output Load : 1TTL+100pF (without active current loading)
P/N:PM0652
REV. 1.5, MAR. 11, 2003
5
MX23L6412
PACKAGE INFORMATION
P/N:PM0652
REV. 1.5, MAR. 11, 2003
6
MX23L6412
REVISION HISTORY
REVISION
1.1
1.2
DESCRIPTION
PAGE
P3
P1,3
P5
DATE
JUL/26/1999
OCT/13/2000
To revise the CE setup time tCES as 50ns(min.) instead of 30ns
Modify Access time--Read latency time:1000ns--->950
Add Package Information
1.3
1.4
1.5
Change Standby Current:500uA(max.)--->20uA(max.)
Add Standby ModeTiming Diagram
To modify Package Information
P1,3
P2,4
P6
AUG/17/2001
FEB/20/2002
MAR/11/2003
P/N:PM0652
REV. 1.5, MAR. 11, 2003
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MX23L6412
MACRONIX INTERNATIONALCO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
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FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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