ADC-208AMM-QL-C [MURATA]
A/D Converter, 8-Bit, 1 Func, CMOS, CDIP24;
| 型号： | ADC-208AMM-QL-C |
| 厂家： | 
muRata |
| 描述： | A/D Converter, 8-Bit, 1 Func, CMOS, CDIP24 CD |
| 文件： | 总4页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
PRODUCT OVERVIEW
The ADC-208A utilizes an advanced VLSI 1.2
micron CMOS in providing 20MHz sampling rates
at 8-bits. The flexibility of the design architecture
and process delivers latch-up free operation
without external components and operation over
the full military range.
The ADC-208A is mechanically and electri-
cally equivalent to the ADC-208 Series, with the
exception of the OVERFLOW (pin 13) and ENABLE
(pins 11 and 12) functions. These functions are not
offered on the ADC-208A.
INPUT/OUTPUT CONNECTIONS
FUNCTION Pin
FEATURES
Pin
1
FUNCTION
BIT 8 (LSB)
BIT 7
■
8-bit flash A/D converter
24
23
22
21
20
19
18
17
16
15
14
13
VDD
CLOCK INPUT
–REFERENCE
ANA/DIG GND (VSS)
ANALOG INPUT
REF MIDPOINT
ANALOG INPUT
ANA/DIG GND (VSS)
+REFERENCE
VDD
2
■
20MHz sampling rate
BIT 6
3
■
10MHz full-power bandwidth
BIT 5
4
■
Sample-hold not required
REF 1/4 FS
VDD
5
6
■
Low power CMOS
REF 3/4 FS
BIT 4
7
■
+5Vdc operation
8
■
1.2 Micron CMOS
BIT 3
9
BIT 2
10
11
12
■
8-Bit latched outputs
N.C.
BIT 1 (MSB)
N.C.
■
Surface-mount version
N.C.
■
No missing codes
02
01
02
CLOCK
GENERATOR
CLOCK
2
01
ANALOG INPUT
+REFERENCE
5,7
9
R2
D
G
Q
BIT 1
BIT 2
BIT 3
14
D
R
G
Q
1:
D
G
Q
Q
15
16
¾ REFERENCE
18
D
G
Q
D
G
R
D
G
1:
1:
R2
R2
256 to
7 ENCODER
MIDPOINT
REFERENCE
6
Q
D
G
Q
Q
17
21
BIT 4
BIT 5
BIT 6
¼ REFERENCE
20
R2
D
G
D
G
Q
22
D
G
Q
Q
R
R2
– REFERENCE
3
D
G
23 BIT 7
D
G
+VDD
Q
PINS 1, 10, 19 +5V
DIGITAL GND
ANALOG GND
BIT 8
(LSB)
24
PINS 4-8
Figure 1. ADC-208A Block Diagram
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
09 Mar 2012 ADC-208A.B03 Page 1 of 4
®
®
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
ABSOLUTE MAXIMUM RATINGS
PERFORMANCE
MIN.
TYP.
MAX.
UNITS
Int. Linearity @ +25°C
(ref. unadjusted)
End-point
PARAMETERS
LIMITS
–0.5 to +7
–0.5 to +5.5
–0.5 to (+VDD +0.5)
–0.5 to (+VDD +0.5)
–0.5 to +5.5
UNITS
—
—
2
1.6
2.6
1.9
LSB
LSB
Power Supply Voltage (VDD Pin 1, 10, 19)
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
(short circuit protected to ground)
Lead Temperature (10 sec. max.)
Storage Temperature
Volts
Volts
Volts
Volts
Volts
Best-fit Line
Int. Linearity Over Temp.
(ref. unadjusted)
End-point
—
—
—
2.3
1.8
1
2.6
2.0
2
LSB
LSB
LSB
Best-fit Line
Zero-Scale Offset
(Code "0" to "1" transition)
Gain Error
Differential Gain ➂
Differential Phase ➂
degrees
Aperture Delay
Aperture Jitter
Harmonic Distortion
(8MHz second order harm.)
Ref. bandwidth
+300 max.
–65 to +150
°C
°C
—
—
—
1.5
2
1.1
3
—
—
LSB
%
FUNCTIONAL SPECIFICATIONS
(Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V,
–REFERENCE = ground, unless noted)
—
—
8
50
—
—
ns
ps
ANALOG INPUT
MIN.
TYP.
MAX.
UNITS
Single-Ended, Non-Isolated
Input Range DC - 20MHz
Analog Input Capacitance
(static - Pin 5 to 7)
(dynamic - Pin 5 to 7)
Reference Ladder Resistance
Reference Input (Note 5)
–40
–46
10
—
—
dB
0
–
+5.0
Volts
(See tech note 5)
Power Supply Rejection
No Missing Codes
—
—
MHz
–
–
–
–0.5
20
64
500
–
–
–
–
pF
pF
Ohms
Volts
0.02
0.05 %FSR/%Vs
Over the operating temperature range
POWER REQUIREMENTS
+3.0 +5.0
VDD +0.5
Power Supply Range (+VDD)
+5.5
Volts
DIGITAL INPUTS
Power Supply Current
+25°C
+85°C
–40°C
+125°C
–55°C
Power Dissipation
+25°C
+85°C
–40°C
+125°C
–55°C
Logic Levels
Logic "1"
Logic "0"
Logic Loading
Logic Loading "1"
Logic Loading "0"
Clock Low Pulse Width
—
—
—
—
—
+45
+40
+50
+40
+50
+65
+60
+70
+60
+70
mA
mA
mA
mA
mA
3.2
—
—
—
—
0.8
Volts
Volts
—
—
15
+1
+1
25
+5
+5
—
µA
µA
nSec
—
—
—
—
—
225
200
250
200
250
325
300
350
300
350
mW
mW
mW
mW
mW
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading
2.4
—
4.5
—
5.0
0.4
Volts
Volts
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range, Case:
MC/LC Versions
MC-C/LC-C Versions
ME/LE Versions
ME-C/LE-C Versions
MM/LM/QL Versions
MM-C/LM-C/QL-C Versions
Logic Loading "1"
Logic Loading "0"
Output Data Valid Delay From
Rising Clock Edge
99% probability
100% probability
+25°C
–55°C to +125°C
Data Output Resolution
Data Coding
4
4
—
—
—
—
mA
mA
0
0
-40
-40
–55
–55
—
—
—
—
—
—
+70
+70
+85
+85
+125
+125
°C
°C
°C
°C
°C
°C
5
10
15
nSec
5
—
8
10
—
—
25
40
—
nSec
nSec
Bits
Storage Temp. Range
Package Type
–65
—
+150
°C
Straight binary
DIP 24-pin ceramic DIP
LCC 24-pin ceramic LCC
PERFORMANCE
Sampling Rate ➁
Full Power Bandwidth
Diff. Linearity @ +25°C
(See tech note 7)
Code Transitions
15
10
20
—
—
—
MSPS
MHz
Footnotes:
➀ Maximum input impedance is a function of clock frequency.
➁ At full-power input.
➂ For 10-step, 40 IRE NTSC ramp test.
—
—
0.5
0.25
1.0
—
LSB
LSB
Center of Codes
Diff. Linearity Over Temp.
Code Transitions
Center of Codes
—
—
0.5
0.25
1.0
—
LSB
LSB
Int. Linearity @ +25°C
(See tech note 4)(ref. adjusted)
End-point
—
—
—
—
1/2
1/2
LSB
LSB
Best-fit Line
Int. Linearity Over Temp.
(ref. adjusted)
Best-fit Line
—
1/2
1
LSB
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
09 Mar 2012 ADC-208A.B03 Page 2 of 4
®
®
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
Table 1. ADC-208A Output Code
TECHNICAL NOTES
1. The Reference ladder is floating with respect to VDD and may be referenced anywhere
within the specified limits. AC modulation of the reference voltage may also be utilized; contact
DATEL for further information.
ANALOG
INPUT
CODE
DATA
1234
DATA 5678 DECIMAL
HEX
2. Clock Pulse Width – To improve performance when input signals may exceed Nyquist
bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of
the clock pulse is 15nSec wide. Reducing the sampling time period minimizes the amount the
input voltage slews and prevents the comparators from saturating.
0.00V
+0.02V
+1.28V
+2.54V
+2.56V
+2.58V
+3.84V
+5.10V
Zero 0000
+1 LSB
0000
0000
0100
0111
1000
1000
1100
1111
0000
0001
0000
1111
0000
0001
0000
1111
0
00
01
40
7F
80
81
C0
FF
1
3. A full-scale input produces all "1" on the data outputs.
+¼ FS
64
4. DATEL uses the conservative definitions when specifying Intergal Linearity (end-point) and
Differential Linearity (code transition). The specifications using the less conservative definition
have also been provided as a comparative specification for products specified this way.
5. The process that is used to fabricate the ADC-208A eliminates the latchup phenomena
that has plagued CMOS devices in the past. These converters do not require external protec-
tion diodes.
6. For clock rates less than 100kHz, there may be some degradation in offset and differential
nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing
the time spent in the sample mode).
7. Connect the converter appropriately; a typical connection circuit is shown in Figure 2.
Then apply an appropriate clock input.The reference input should be held to 0.1% accuracy
or better. Do not use the +5V power supply as a reference without precision regulation and
high-frequency decoupling capacitors.
+½ FS-ILSB
+½ FS
127
128
129
192
255
+½ FS+ILSB
+¾ FS
+FS
Note: Values shown here are for a +5.12Vdc reference. Scale other refereces proportion-
ally. (+REF=+5.12V, –REF=GND, ¼, ½, and ¾ References FS=No Connection)
8. Zero Adjustment - Adjusting the voltage at –REFERENCE (pin 3) adjusts the offset or zero
of the device. Pin 3 can be tied to GROUND for operation without adjustments
9. Full Scale Adjustment - Adjusting the voltage at +REFERENCE (pin 9) adjusts the gain of
the device. Pin 9 can be tied directly to a +5V reference for operation without adjustment.
10. Integral Nonlinearity Adjustments - Provision is made for optional adjustment of Integral
Nonlinearity through access of the reference's ¼, ½, and ¾ full scale points. For example, the
REF. MIDPOINT (pin 6) can be tied to a precision voltage halfway between +REFERENCE
and –REFERENCE. Pins 6, 18 and 20 should be bypassed to GROUND through 0.1µF
capacitors for operation without INL adjustments
+15
0.01μF
+5V
0.1μF
+
B8
B7
B6
B5
B4
B3
B2
B1
24 (LSB)
4.7μF
23
22
CLOCK 2
VIN 5,7
20MHz CLOCK
21
12
17
10:
11
5
16
HA-5033
10
15
14 (MSB)
20
HP2811
R¼
R¾
4.7μF
–15
18
0.1μF
+15V
+15V
+
1-N
2
3
2
6
5
1
LM324
1+N
REF. D2
4
1-N
9
10k:
8
+
LM324
1+N
0.1μF
4.7μF
10
+
0.1μF
2k:
4.7μF
1k:
0.1μF
1.5k:
1-N
6
5
7
LM324
1+N
1k:
1.5k:
1k:
+
0.1μF
4.7μF
0.1μF
12
13
1-N
14
LM324
1+N
0.1μF
+
0.1μF
4.7μF
2k:
Figure 2. ADC-208A Typical Connection Diagram
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
09 Mar 2012 ADC-208A.B03 Page 3 of 4
®
®
ADC-208A
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
MECHNICAL DIMENSIONS
ADC-208A DIP
ADC-208A LCC
0.250 0.005
(6.35)
1.250
(31.7)
0.050
(1.27)
Pin 9
DATEL
0.400 SQ.
+0.010, –0.005
(10.16)
0.500
(12.7)
0.610
(15.5)
ADC-208A
Pin 21
Pin 1
PIN 1
IDENTIFIER
0.020 0.005
(0.50)
0.090 Max.
(2.28)
0.190
(4.9)
0.38
(9.7)
0.190
(4.9)
0.050
(1.3)
0.020
(0.5)
0.100
(2.5)
ORDERING INFORMATION
AUTO ZERO
SAMPLE
AUTO ZERO
01
SAMPLE
AUTO ZERO
01
SAMPLE
N+2
N
N+1
MODEL
TEMP. RANGE
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PACKAGE
01
02
02
02
ADC-208AMC
ADC-208AMC-C
ADC-208AME
ADC-208AME-C
ADC-208AMM
ADC-208AMM-C
ADC-208ALC
ADC-208ALC-C
ADC-208ALE
ADC-208ALE-C
ADC-208ALM
ADC-208ALM-C
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
Non-RoHS
RoHS
N+1 DATA
N DATA
Non-RoHS
RoHS
40nSec max.
40nSec max.
–55°C to +125°C ➀ 24-pin DIP
–55°C to +125°C ➁ 24-pin DIP
Non-RoHS
RoHS
Figure 3 Timing Diagram
0°C to +70°C
24-pin LCC
24-pin LCC
24-pin LCC
24-pin LCC
24-pin LCC
24-pin LCC
Non-RoHS
RoHS
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
Non-RoHS
RoHS
Non-RoHS
RoHS
➀ The ADC-208AMM-QL replaces the ADC-208MM-QL and includes DATEL
QL High-Reliability Screening.
➁ The ADC-208ALM-QL replaces the ADC-208LM-C.
DATEL
. makes no representation that the use of its products in the circuits described herein, or the use of other
technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not
imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change
without notice.
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
ITAR and ISO 9001/14001 REGISTERED
www.datel.com • e-mail: help@datel.com
09 Mar 2012 ADC-208A.B03 Page 4 of 4
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